Semiconductor package

Abstract

A semiconductor package includes: a semiconductor substrate including a device region and an edge region; a first redistribution layer located on a lower surface of the semiconductor substrate; a second redistribution layer located on an upper surface of the semiconductor substrate; a through-hole vertically penetrating the semiconductor substrate in the edge region to electrically connect the first redistribution layer and the second redistribution layer; and a circuit layer located between the lower surface of the semiconductor substrate and the first redistribution layer. The circuit layer may include: circuit elements located on the lower surface of the semiconductor substrate; a circuit wiring pattern electrically connected to the circuit elements and the first redistribution layer; and an inter-device dielectric layer substantially surrounding the circuit elements and the circuit wiring pattern, wherein the circuit elements and the circuit wiring pattern are disposed in the device region rather than in the edge region.

Description

Semiconductor Package [Cross - Reference to Related Applications] This U.S. non - provisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10 - 2022 - 0130895, filed on October 12, 2022, with the Korean Intellectual Property Office, the subject matter of which is hereby incorporated by reference in its entirety. The inventive concept is generally related to a semiconductor package and a method of manufacturing the same. With the continuous development of various semiconductor technologies, semiconductor chips have gradually become more compact. However, more functions have been integrated into contemporary and emerging semiconductor chips. Therefore, semiconductor chips must provide a large number of input / output (I / O) pads on a relatively small area. Various semiconductor packages provide practical accessibility and functional utilization for corresponding semiconductor chips. In a typical semiconductor package, one or more semiconductor chips are mounted (e.g., electrically connected and / or mechanically assembled) on a substrate (e.g., a printed circuit board) using wires and / or conductive bumps. Various studies have been conducted to improve the structural stability and electrical utility of semiconductor packages. Regrettably, as the sizes of contemporary and emerging semiconductor chips continue to decrease, it is difficult to attach, process, and test solder balls. In addition, problems have arisen in obtaining diverse mounting boards according to the sizes of corresponding semiconductor chips. Embodiments of the inventive concept provide a compact semiconductor package exhibiting improved thermal radiation properties, increased integration, and improved electrical properties. According to some embodiments of the inventive concept, a semiconductor package may include: a first semiconductor substrate having a device region and an edge region; a first semiconductor element located on the device region, wherein the first semiconductor element is formed on an active surface of the first semiconductor substrate; a first circuit layer disposed on the active surface of the first semiconductor substrate; a first redistribution layer disposed on the first circuit layer; and a plurality of first vias located on the edge region, wherein the first vias vertically penetrate the first semiconductor substrate and the first circuit layer and are connected to the first redistribution layer. The first circuit layer may include: a first device interlayer dielectric layer covering the active surface of the first semiconductor substrate; and a first circuit wiring pattern located on the device region, wherein the first circuit wiring pattern is disposed in the first device interlayer dielectric layer and is connected to the first semiconductor element. The first circuit wiring pattern and the first vias may be electrically connected via the first redistribution layer. The first vias may be configured to extend along a lateral surface of the first semiconductor substrate and be spaced apart from each other in at least two rows in a direction from the device region toward the lateral surface of the first semiconductor substrate. According to some embodiments of the inventive concept, a semiconductor package may include: a first semiconductor die including a first silicon substrate, first semiconductor elements formed on an active surface of the first silicon substrate, and a first circuit layer disposed on the active surface of the first silicon substrate; a first redistribution layer disposed on the active surface of the first semiconductor die and coupled to the first circuit layer; a second redistribution layer disposed on a non-active surface of the first semiconductor die; a first via vertically penetrating the first semiconductor die and connecting the first redistribution layer and the second redistribution layer to each other; and a plurality of pads disposed on the first redistribution layer. The first circuit layer may include: a first device interlayer dielectric layer covering the active surface of the first silicon substrate; and a first circuit wiring pattern disposed in the first device interlayer dielectric layer. The first via may be spaced apart from the first circuit wiring pattern. According to some embodiments of the inventive concept, a semiconductor package may include: a package substrate; and a chip package mounted on the package substrate. The chip package may include: a semiconductor die including a silicon substrate and a circuit wiring pattern on the silicon substrate, the silicon substrate having semiconductor elements formed on an active surface of the silicon substrate, and the circuit wiring pattern being connected to the semiconductor elements; a first redistribution layer disposed on a first surface of the semiconductor die, the first surface being oriented toward the package substrate; a second redistribution layer disposed on a second surface of the semiconductor die, the second surface being opposite the first surface; and a plurality of vias vertically penetrating the semiconductor die and connecting the first redistribution layer and the second redistribution layer to each other. The vias may be positioned between the circuit wiring pattern and a lateral surface of the silicon substrate. A distance from the lateral surface of the silicon substrate to a conductive pattern of the first redistribution layer may be less than a distance from the lateral surface of the silicon substrate to the circuit wiring pattern. Throughout the written description and the drawings, like reference numerals and marks are used to denote the same or similar elements, components, features, and / or method steps. Throughout the written description, certain geometric terms may be used to emphasize the relative relationships between elements, components, and / or features of certain embodiments of the inventive concept. Those of ordinary skill in the art will recognize that such geometric terms are relative in nature, arbitrary in descriptive relationships, and / or aspect-specific to the illustrated embodiments. Geometric terms may include, for example: height / width; vertical / horizontal; top / bottom; higher / lower; nearer / farther; thicker / thinner; close to / far from; above / below; under / over; upper / lower; center / sides; surrounding; overlying / underlying, etc. Certain embodiments of the inventive concept or related aspects thereof may be described relative to a presumed geometric orientation described by a first direction D1 (e.g., a first horizontal direction), a second direction D2 (e.g., a second horizontal direction) intersecting the first direction D1, and a third direction D3 (e.g., a vertical direction) substantially orthogonal to the first direction D1 and the second direction D2. FIG. 1 is a cross-sectional view showing a semiconductor package 10 according to an embodiment of the present invention concept; FIG. 2 is an enlarged cross-sectional view further partially showing the semiconductor package 10 of FIG. 1; FIGS. 3, 4, and 5 are respective plan views showing semiconductor packages 10A, 10B, and 10C according to embodiments of the present invention concept; and FIG. 6 is a cross-sectional view showing a semiconductor package 11 according to an embodiment of the present invention concept. Referring to FIGS. 1 and 2, the semiconductor package 10 may include a semiconductor wafer 100, wherein the semiconductor wafer 100 includes a semiconductor substrate 110 and a circuit layer 120. In some embodiments, the semiconductor substrate 110 may have a width 'w' (e.g., a dimension measured in a first horizontal direction D1) between about 3 mm and about 50 mm (see, e.g., FIG. 5). Thus, assuming the semiconductor substrate 110 has a square shape, its area may be between about 9 square millimeters and about 2,500 square millimeters. The semiconductor substrate 110 may include at least one semiconductor material, such as, for example, single crystal silicon (Si). The semiconductor substrate 110 may be conceptually and / or functionally divided into a device region DR and an edge region ER. Referring to FIGS. 3, 4, and 5, the device region DR may be centrally disposed, and the edge region ER may be disposed at least partially around the periphery of the device region DR. That is, differently configured edge regions ER may substantially surround (or enclose) the centrally disposed edge region DR (compare, e.g., FIGS. 3, 4, and 5). In such a configuration, the edge region ER may be horizontally disposed (e.g., in a first horizontal direction D1 and a second horizontal direction D2) between the device region DR of the semiconductor substrate 110 and the respective outer edges. The device region DR may be a region where one or more semiconductor elements (e.g., the semiconductor wafer 100) may be disposed on the semiconductor substrate 110. In contrast, the edge region ER may be understood as a region where no semiconductor elements are disposed. In various embodiments, the ratio between a first area occupied (or designated for) by the device region DR and a second area occupied (or designated for) by the edge region ER may be between about 5:95 and about 95:5. Referring to FIG. 2, the semiconductor substrate 110 may include a first (or lower) surface 110a and an opposite second (or upper) surface 110b. In some embodiments, the first surface 110a of the semiconductor substrate 110 may be a front surface and the second surface 110b of the semiconductor substrate 110 may be a back surface. Here, the term "front surface" indicates a surface that typically includes various wirings, interconnects, pads, passive elements, and / or active elements. Further in this regard, one or more of the first surface 110a and the second surface 110b may be an active surface or a non-active surface. As shown in FIG. 2, for example, the semiconductor wafer 100 may include a circuit layer 120 located on its first surface 110a, where the circuit layer 120 may differently include circuit elements 122 and circuit wiring patterns 124. Here, the circuit elements 122 of FIG. 2 may include various active and / or passive elements, such as one or more different types of transistors, resistors, capacitors, etc. The circuit wiring patterns 124 may include one or more wirings, interconnections, pads, vias, etc. that can be used to differently interconnect the components of the circuit elements 122. Relative to the circuit elements 122, one or more transistors TR may each include a source and a drain located on a lower portion of the semiconductor substrate 110, a gate electrode located on the first surface 110a of the semiconductor substrate 110, and a gate dielectric layer inserted between the semiconductor substrate 110 and the gate electrode. In some embodiments, the circuit elements 122 may include multiple transistors TR and / or one or more logic circuits. When placed in the device region DR on the first surface 110a, the circuit elements 122 may include shallow device isolation patterns, logic units, and / or memory units. The circuit elements 122 will generally not be placed on the edge region ER of the semiconductor substrate 110. The first surface 110a of the semiconductor substrate 110 may be substantially covered by a device interlayer dielectric layer 126. On the device region DR, the device interlayer dielectric layer 126 may substantially surround the circuit elements 122 and the associated circuit writing patterns 124. In some embodiments, the device interlayer dielectric layer 126 may completely surround the circuit elements 122 and may substantially surround the circuit wiring elements 124, except for selectively exposed portions (e.g., the selected lower surface of the circuit wiring element 124 exposed through the lower surface of the device interlayer dielectric layer 126). In some embodiments, the device interlayer dielectric layer 126 may extend under the semiconductor substrate 110 and may include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). Alternatively or additionally, the device interlayer dielectric layer 126 may include a low-k dielectric material. The device interlayer dielectric layer 126 may have a single-layer structure or a multi-layer structure. For example, the device interlayer dielectric layer 126 may be a multi-layer structure that substantially surrounds multiple wiring layers, where an etch stop layer may be inserted between adjacent dielectric layers associated with the device interlayer dielectric layer 126. For example, the etch stop layer may be disposed on the lower surface of each dielectric layer and may include at least one of silicon oxide (SiO), silicon oxynitride (SiON), and silicon carbonitride (SiCN). As noted above, the device interlayer dielectric layer 126 may substantially surround the circuit wiring pattern 124. The circuit wiring pattern 124 does not extend into the edge region ER. Thus, the circuit layer 120 may only include the device interlayer dielectric layer 126 in the device region DR, such that the circuit layer 120 may include the device interlayer dielectric layer 126, the circuit elements 122, and the circuit wiring pattern 124. As shown in FIG. 2, the circuit wiring pattern 124 may differently include wiring patterns, such as horizontally extending connections and / or vertically extending connections. One or more portions of the circuit wiring pattern 124 (e.g., portion 124a in FIG. 2) may be selectively exposed via the device interlayer dielectric layer 126. For example, the exposed wiring portion 124a may be a lower portion of the circuit wiring pattern 124 exposed via the device interlayer dielectric layer 126. Thus, in some embodiments, the exposed wiring portion 124a may have a lower surface coplanar with the lower surface of the device interlayer dielectric layer 126. The circuit wiring pattern 124 may be differently configured between the upper surface and the lower surface of the device interlayer dielectric layer 126. As shown in FIG. 2, the semiconductor substrate 110 may include the circuit wiring pattern 124 configured differently, where the circuit wiring pattern 124 may include at least, for example, copper (Cu) and tungsten (W). The connection contacts provided by the circuit wiring pattern 124 may be used to connect the circuit elements 122 and / or the semiconductor substrate 110. For example, various connection contacts may vertically penetrate the device interlayer dielectric layer 126 to connect one or more source electrodes, drain electrodes, and gate electrodes of the transistor TR or connect to various components associated with the circuit elements 122. Such connection contacts may include, for example, tungsten (W). Thus, the circuit layer 120 may include the circuit elements 122 (configured differently), the device interlayer dielectric layer 126, and the circuit wiring pattern 124. The semiconductor wafer 100 may further include one or more vias 130 disposed on the edge region ER. The vias 130 may be individual conductive patterns forming vertical connection paths. The vias 130 may vertically penetrate the semiconductor substrate 110 and the device interlayer dielectric layer 126. The vias 130 may be exposed on the lower surface of the device interlayer dielectric layer 126 and / or the upper surface of the semiconductor substrate 110. The vias 130 may be disposed on the edge region ER of the semiconductor substrate 110, rather than on the device region DR. Each of the vias 130 may have an elliptical cross-sectional shape and have a diameter 'd' between about 0.001 mm and about 1 mm (see, for example, FIG. 3). Each of the vias 130 may have an aspect ratio between about 0.5 and about 10. The vias 130 may include at least one of, for example, copper (Cu), aluminum (Al), gold (Au), silver (Ag), tin (Sn), carbon (C), cobalt (Co), manganese (Mn), and lead (Pb). Since the vias 130 are disposed on the edge region ER, the vias are horizontally spaced apart from the device region DR (e.g., in the first horizontal direction D1 or the second horizontal direction D2). Thus, the vias 130 are horizontally spaced apart from the circuit wiring pattern 124 such that the vias 130 are not directly connected to the circuit wiring pattern 124. Additionally, in this configuration, the vias 130 are closer to the outer edge of the semiconductor substrate 110 than the circuit wiring pattern 124. Accordingly, the distance from the outer edge of the semiconductor substrate 110 to the vias 130 is less than the distance from the outer edge of the semiconductor substrate 110 to the circuit wiring pattern 124. In some embodiments, the vias 130 may be arranged in a configuration including at least two rows extending along at least one side of the edge region ER. For example, as depicted in FIG. 3, the vias 130 may be disposed on two opposite sides of the edge region. Alternatively, as depicted in FIG. 4, the vias 130 may be disposed on all four sides of the edge region ER. The spatial pitch 'g' between adjacent vias 130 may be between about 0.001 mm and about 1 mm (see, e.g., FIG. 3). And in some embodiments, the number of vias 130 disposed relative to the semiconductor wafer 100 may range from 1 to 10,000. Referring to FIG. 5, the vias 130 need not be disposed along all sides of the edge region ER, nor need they completely occupy a side. For example, one or more additional components 140 may be disposed on at least one side of the edge region ER (e.g., horizontally spaced apart). Thus, the additional components 140 may be horizontally spaced apart from the device region DR and the circuit wiring pattern 124. Accordingly, the additional components 140 are not directly connected to the circuit wiring pattern 124. The additional components 140 may be closer to the outer edge of the semiconductor substrate 110 than the circuit wiring pattern 124. Here, the additional components 140 may alternatively include passive components such as resistors or capacitors. As an example, the additional component 140 may include a resistor that vertically penetrates the semiconductor substrate 110 and the circuit layer 120. As another example, the additional component 140 may include a cylindrical capacitor that vertically penetrates the semiconductor substrate 110 and the circuit layer 120. In some embodiments, the additional components 140 may electrically connect a portion of the first redistribution layer 200 disposed on the upper surface of the semiconductor wafer 100 to a portion of the second redistribution layer 300 disposed on the lower surface of the semiconductor wafer 100. The first redistribution layer 200 can be disposed on the first surface 110a of the semiconductor substrate 110. For example, the first redistribution layer 200 can cover the circuit layer 120. The first redistribution layer 200 can cover both the device region DR and the edge region ER. The first redistribution layer 200 can include one or more first wiring layers, where the first wiring layers are vertically stacked on top of each other. Each of the first wiring layers can include a first redistribution dielectric layer 210 and a first redistribution conductive pattern 220 located in the first redistribution dielectric layer 210. When multiple first wiring layers are provided, the first redistribution conductive pattern 220 of one first wiring layer can be electrically connected to the first redistribution conductive pattern 220 of another first wiring layer adjacent to the said one first wiring layer. The first redistribution dielectric layer 210 can include, for example, a dielectric polymer or a photo-imageable dielectric (PID), where the photo-imageable dielectric can include at least one of the following: photosensitive polyimide (PI), polybenzoxazole (PBO), phenolic polymer, and benzocyclobutene polymer. Alternatively, the first redistribution dielectric layer 210 can include a dielectric material such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and / or a dielectric polymer. The first redistribution conductive pattern 220 can be disposed on the first redistribution dielectric layer 210. The first redistribution conductive pattern 220 can horizontally extend on the first redistribution dielectric layer 210. The first redistribution conductive pattern 220 can be a component for redistribution in the first wiring layer. The first redistribution conductive pattern 220 can be disposed on both the device region DR and the edge region ER. At least a portion of the first redistribution conductive pattern 220 can be closer to the outer edge of the semiconductor substrate 110 than the circuit wiring pattern 124. For example, the distance from the outer edge of the semiconductor substrate 110 to the first redistribution conductive pattern 220 can be less than the distance from the outer edge of the semiconductor substrate 110 to the circuit wiring pattern 124. The first redistribution conductive pattern 220 can allow the electrical connection of the circuit wiring pattern 124 to extend from the device region DR to the edge region ER. The first redistribution conductive pattern 220 can include a conductive material such as, for example, copper (Cu) and aluminum (Al). The first redistribution conductive pattern 220 can have an embedded structure. For example, the first redistribution conductive pattern 220 can have a head portion and a tail portion integrally connected as a single element. The head portion and the tail portion of the first redistribution conductive pattern 220 can have an inverted T-shaped cross-section. The head portion of the first rewiring conductive pattern 220 may be a pad or a wire component that allows the circuit in the first rewiring layer 200 to horizontally expand. The head portion may be disposed on the lower surface of the first rewiring dielectric layer 210. For example, the head portion may protrude from the lower surface of the first rewiring dielectric layer 210. The first rewiring conductive pattern 220 of the lowermost one of the first wiring layers may be exposed on the lower surface of the first rewiring dielectric layer 210. The lower surface of the first rewiring conductive pattern 220 of the lowermost first wiring layer may have a lower surface coplanar with the lower surface of the first rewiring dielectric layer 210. The tail portion of the first rewiring conductive pattern 220 may be a via component for vertical connection of the circuit in the first rewiring layer 200. The tail portion may be coupled to another first wiring layer overlying the tail portion. For example, the tail portion of one first rewiring conductive pattern 220 may extend from the upper surface of the head portion of the one first rewiring conductive pattern 220 and may penetrate the first rewiring dielectric layer 210 to be coupled to the head portion of another first rewiring conductive pattern 220 included in another first wiring layer overlying the tail portion of the one first rewiring conductive pattern 220. The tail portion of the first rewiring conductive pattern 220 included in the uppermost one of the first wiring layers may penetrate the first rewiring dielectric layer 210 to be coupled to the semiconductor wafer 100. For example, the first rewiring conductive pattern 220 of the uppermost first wiring layer may be coupled to the exposed wiring portion 124a on the device region DR and may be coupled to the via 130 on the edge region ER. The via 130, the circuit element 122 of the semiconductor wafer 100, and the circuit wiring pattern 124 may be electrically connected to each other via the first rewiring layer 200. The second rewiring layer 300 may be disposed on the second surface 110b of the semiconductor substrate 110. For example, the second rewiring layer 300 may cover the second surface 110b of the semiconductor substrate 110. The second rewiring layer 300 may cover both the device region DR and the edge region ER. The second rewiring layer 300 may include one or more vertically stacked second wiring layers. Each of the second wiring layers may include a second rewiring dielectric layer 310 and a second rewiring conductive pattern 320 located in the second rewiring dielectric layer 310. When multiple second wiring layers are provided, the second rewiring conductive pattern 320 of one second wiring layer may be electrically connected to the second rewiring conductive pattern 320 of another second wiring layer adjacent to the one second wiring layer. The second redistribution dielectric layer 310 may include a dielectric polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric may include at least one of, for example, photosensitive polyimide (PI), polybenzoxazole (PBO), phenol polymer, and benzocyclobutene polymer. Alternatively, the second redistribution dielectric layer 310 may include a dielectric material such as, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and / or a dielectric polymer. The second redistribution conductive pattern 320 may be disposed on the second redistribution dielectric layer 310. The second redistribution conductive pattern 320 may horizontally extend on the second redistribution dielectric layer 310. The second redistribution conductive pattern 320 may be a component for redistribution in the second wiring layer. The second redistribution conductive pattern 320 may include a conductive material such as copper (Cu) and aluminum (Al). The second redistribution conductive pattern 320 may have an embedded structure. For example, the second redistribution conductive pattern 320 may have a head portion and a tail portion integrally connected as a single unitary piece. The head portion and the tail portion of the second redistribution conductive pattern 320 may have a T-shaped cross-section. The head portion of the second redistribution conductive pattern 320 may be a pad or a wire component that allows the lines in the second redistribution layer 300 to horizontally expand. The head portion may be disposed on the upper surface of the second redistribution dielectric layer 310. For example, the head portion may protrude from the upper surface of the second redistribution dielectric layer 310. The second redistribution conductive pattern 320 of the uppermost one of the second wiring layers may be exposed via the upper surface of the second redistribution dielectric layer 310. The second redistribution conductive pattern 320 of the uppermost second wiring layer may be coplanar with the upper surface of the second redistribution dielectric layer 310. A semiconductor package, a semiconductor wafer, or an electronic component may be individually mounted on the second redistribution conductive pattern 320 of the uppermost second wiring layer. The tail portion of the second rewiring conductive pattern 320 can be a via component for vertical connection of the circuits in the second rewiring layer 300. The tail portion can be coupled to another second wiring layer underlying the tail portion. For example, the tail portion of a second rewiring conductive pattern 320 can extend from the lower surface of a second rewiring conductive pattern 320 and can penetrate the second rewiring dielectric layer 310 to be coupled to the head portion of the second rewiring conductive pattern of another second wiring layer underlying the tail portion of the said second rewiring conductive pattern 320. The tail portion of the second rewiring conductive pattern 320 included in the lowermost one of the second wiring layers can penetrate the second rewiring dielectric layer 310 to be coupled to the via 130. For example, the second rewiring conductive pattern 320 of the lowermost second wiring layer can be coupled to the via 130 on the edge region ER. The second rewiring layer 300 can be electrically connected to the circuit wiring pattern 124 and the circuit element 122 of the semiconductor wafer 100 via the via 130 and the first rewiring layer 200. The distance from the lower surface of the first rewiring layer 200 to the upper surface of the second rewiring layer 300 can be between about 0.03 mm and about 1 mm. In some embodiments, the first rewiring layer 200 and the second rewiring layer 300 can be disposed on the lower surface and the upper surface of the semiconductor wafer 100 respectively. In this configuration, the first rewiring layer 200 and the second rewiring layer 300 are not interconnected by using connection members disposed on one side of the semiconductor wafer 100 in the device region DR, but instead are interconnected by using vias 130 that directly penetrate the edge region ER of the semiconductor wafer 100. This allows the semiconductor wafer 100 to occupy a relatively small area. In addition, since the first rewiring layer 200 and the second rewiring layer 300 are connected by using vias 130, there is no need for a molding member to cover (e.g., isolate and / or protect) separately provided connection members. Therefore, the thermal energy (hereinafter referred to as "heat") generated by the semiconductor wafer 100 can be more easily discharged from the semiconductor package 10. That is, the process of discharging the heat generated by the semiconductor wafer 100 will not be thermally hindered by the heat insulating property of the molding member, but instead, the heat can be effectively discharged from the side surface, the upper surface, and the lower surface of the semiconductor wafer 100. This ability improves the overall heat radiation property of the semiconductor package 10. As pointed out above, the perforations 130 are not provided in the device region DR that includes the circuit elements 122 and the circuit wiring pattern 124 associated with the semiconductor wafer 100. Therefore, an increase in both the degree of freedom in the layout related to the circuit elements 122 and the degree of freedom in the layout related to the circuit wiring pattern 124 and the degree of freedom in interconnection can be achieved. This extended degree of freedom in the layout and interconnection of the circuit elements 122 and the circuit wiring pattern 124 enables further integration of the semiconductor package 10. And thus, a more compact semiconductor package with increased integration and improved overall electrical properties can be provided. Referring to FIG. 6, the semiconductor package 11 according to an embodiment of the inventive concept may further include one or more components providing external coupling of the semiconductor package 11. For example, as shown in FIG. 6, a substrate protection layer 410 may be additionally disposed on the lower surface of the first redistribution layer 200 to substantially cover the first redistribution dielectric layer 210 and the first redistribution conductive pattern 220. The substrate protection layer 410 may include at least one of the following: high density plasma (HDP) oxide, undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), silicon nitride (SiN), silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon carbonitride (SiCN). The substrate protection layer 410 may be implemented as a single-layer structure or a multi-layer structure. One or more external pads 420 may be disposed on the lower surface of the substrate protection layer 410. The external pads 420 may be disposed on at least one of the device region DR and the edge region ER. Thus, while the circuit elements 122 and the circuit wiring pattern 124 of the semiconductor substrate 110 may be provided only in the device region DR, in some embodiments, the external pads 420 may be provided in both the device region DR and the edge region ER. The outermost of the external pads 420 may be disposed closer to the outer edge of the semiconductor substrate 110 than the circuit wiring pattern 124. In some embodiments, the external pads 420 may penetrate the substrate protection layer 410 to be firmly connected to the first redistribution conductive pattern 220 of the first redistribution layer 200. The external pads 420 may serve as pads for coupling external terminals 430. For example, the external pads 420 may correspond to under-bump metals for bonding the external terminals 430. External terminals 430 may be respectively and correspondingly disposed on the lower surface of the external terminals 430. The external terminals 430 may be implemented as solder balls and / or solder bumps. And based on a given type of the external terminals 430, the semiconductor package 11 may comply with conventional understanding practices associated with a ball grid array (BGA), a fine ball-grid array (FBGA), or a land grid array (LGA). FIG. 7 is a cross-sectional view showing a semiconductor package 12 according to an embodiment of the inventive concept, and FIG. 8 is an enlarged cross-sectional view further partially showing the semiconductor package 12 of FIG. 7. Here, FIGS. 7 and 8 may be compared with FIGS. 1 and 2, and only the substantial differences will be described. It is noted that the semiconductor package 12 of FIGS. 7 and 8 does not include the second rewiring layer 300 of the semiconductor package 10 of FIGS. 1 and 2. Accordingly, the respective upper surfaces of the vias 130 and the second surface 110b of the semiconductor substrate 110 may be exposed. This configuration allows for the selective mounting thereon of another semiconductor package, another semiconductor chip, or various components and / or assemblies. FIG. 9 is a cross-sectional view showing a semiconductor package 13 according to an embodiment of the inventive concept, and FIG. 10 is an enlarged cross-sectional view further partially showing the semiconductor package 13 of FIG. 9. Referring to FIGS. 9 and 10, the semiconductor package 13 may include a plurality of first semiconductor packages P1 and second semiconductor packages P2 stacked vertically. Here, in some embodiments, the first package P1 may be substantially similar to the semiconductor package 11 of FIG. 6. That is, the first package P1 may include: a semiconductor wafer 100, a first redistribution layer 200 on the lower surface of the semiconductor wafer 100, a second redistribution layer 300 on the upper surface of the semiconductor wafer 100, and a substrate protection layer 410, an external pad 420, and an external terminal 430 disposed below the first redistribution layer 200. As described above, the semiconductor wafer 100 may include: a semiconductor substrate 110; circuit elements 122 on the active surface 110a (e.g., the first surface 100a) in the device region DR; a circuit wiring pattern 124 connected to the circuit elements 122 in the device region DR; a device interlayer dielectric layer 126 covering the circuit wiring pattern 124 and the circuit elements 122 on the active surface 110a of the semiconductor substrate 110; and vias 130 penetrating the semiconductor substrate 110 and the device interlayer dielectric layer 126 to connect the first redistribution layer 200 and the second redistribution layer 300 in the edge region ER of the semiconductor substrate 110. The second redistribution conductive pattern 320 may include an exposed portion 322 on the upper surface of the second redistribution layer 300, and the portion 322 corresponds to the upper pad 322 on which the second package P2 may be mounted. Here, the upper pads 322 may each have a width between about 0.5 microns and about 20 microns and be separated by a spacing between about 0.5 microns and about 20 microns. Alternatively, the first package P1 may be substantially similar to the semiconductor packages 10 of FIGS. 1 and 2. That is, the first package P1 may not include any of the substrate protection layer 410, the external pad 420, and the external terminal 430 below the first redistribution layer 200. Alternatively, the first package P1 may be substantially similar to the semiconductor packages 12 of FIGS. 7 and 8. That is, the first package P1 may omit the second redistribution layer 300 from the second surface 110b of the semiconductor substrate 110. In this case, the upper portion of the via 130 may be exposed through the upper surface of the semiconductor substrate 110, and the exposed upper portion of the via 130 may respectively correspond to the pads on which the second package P2 may be mounted. In the context of the semiconductor package 13 of FIGS. 9 and 10, the second package P2 may be substantially similar to the semiconductor package 10 of FIGS. 1 and 2. That is, the second package P2 may include a semiconductor wafer 100, a first redistribution layer 200 located on the lower surface of the semiconductor wafer 100, and a second redistribution layer 300 located on the upper surface of the semiconductor wafer 100. As described above, the semiconductor wafer 100 may include: a semiconductor substrate 110; circuit elements 122 formed on the active surface 110a in the device region DR; a circuit wiring pattern 124 connected to the circuit elements 122 in the device region DR; a device interlayer dielectric layer 126 substantially covering the circuit wiring pattern 124 and the circuit elements 122 on the active surface 110a of the semiconductor substrate 110; and vias 130 penetrating the semiconductor substrate 110 and the device interlayer dielectric layer 126 to connect the first redistribution layer 200 and the second redistribution layer 300 in the edge region ER. Here, the first redistribution conductive pattern 220 may include portions 222 located on the lower surface of the first redistribution layer 200, where the portions 222 of the first redistribution conductive pattern 220 respectively correspond to the lower pads 222 on which the second package P2 can be mounted. Also here, the lower pads 222 may have a width between about 0.5 micrometers and about 20 micrometers and may be separated by a spacing between about 0.5 micrometers and about 20 micrometers. The second package P2 may be mounted differently on the first package P1 such that the upper pads 322 of the second redistribution layer 300 of the first package P1 are vertically aligned with the lower pads 222 of the first redistribution layer 200 of the second package P2. Once proper alignment is achieved, the first package P1 and the second package P2 may be placed in contact for bonding. Thus, at the interface between the first package P1 and the second package P2, the second redistribution dielectric layer 310 of the second redistribution layer 300 in the first package P1 may be bonded to the first redistribution dielectric layer 210 of the first redistribution layer 200 in the second package P2. In this case, the bonding of the second redistribution dielectric layer 310 and the first redistribution dielectric layer 210 may constitute a hybrid bond of oxides, nitrides, and / or oxynitrides. In this regard, the term "hybrid bond" indicates a bonding method in which two or more components of the same type (e.g., oxides, nitrides, metals, etc.) are at least partially merged at their interface. For example, the second redistribution dielectric layer 310 and the first redistribution dielectric layer 210 are bonded together, thereby forming a continuous invisible boundary between the second redistribution dielectric layer 310 and the first redistribution dielectric layer 210. Thus, assuming the second redistribution dielectric layer 310 and the first redistribution dielectric layer 210 are formed of the same material, there will be no distinguishable interface between the second redistribution dielectric layer 310 and the first redistribution dielectric layer 210. However, those of ordinary skill in the art will understand that hybrid bonding is only one of several methods available for effectively mounting (e.g., electrically connecting and / or mechanically assembling) the second package P2 on the first package P1. In some embodiments, one or more conductive interfaces between the first package P1 and the second package P2 (e.g., the upper pads 322 of the second redistribution layer 300 in the first package P1 and the lower pads 222 of the first redistribution layer 200 in the second package P2) can be used to effectively mount the second package P2 on the first package P1. For example, assuming the foregoing configuration, the upper pads 322 and the lower pads 222 can be subjected to an intermetallic hybrid bond. Thus, the upper pads 322 and the lower pads 222 having the same material can be joined together without distinguishable material boundaries. FIG. 11 is a cross-sectional view showing a semiconductor package 14 according to an embodiment of the inventive concept. Referring to FIG. 11, the first package P1 can be substantially similar to the semiconductor package 11 of FIG. 6. That is, the first package P1 can include: a semiconductor wafer 100, a first redistribution layer 200 on the lower surface of the semiconductor wafer 100, a second redistribution layer 300 on the upper surface of the semiconductor wafer 100, wherein a substrate protection layer 410, external pads 420, and external terminals 430 are disposed below the first redistribution layer 200. The semiconductor wafer 100 can include: a semiconductor substrate 110; circuit elements 122 on the active surface 110a in the device region DR; circuit wiring patterns 124 connected to the circuit elements 122 in the device region DR; a device interlayer dielectric layer 126 substantially covering the circuit wiring patterns 124 and the circuit elements 122 on the active surface 110a of the semiconductor substrate 110; and vias 130 penetrating the semiconductor substrate 110 and the device interlayer dielectric layer 126 to connect the first redistribution layer 200 and the second redistribution layer 300 in the edge region ER. The second redistribution conductive pattern 320 can have a portion 322 exposed via the upper surface of the second redistribution layer 300, and the portion 322 of the second redistribution conductive pattern 320 can correspond to the upper pad 322 on which the second package P2 can be mounted. The second package P2 can also be substantially similar to the semiconductor package 11 of FIG. 6. Thus, the second package P2 can be mounted on the first package P1. For example, the second package P2 can be placed on the first package P1 such that the upper pads 322 of the second redistribution layer 300 of the first package P1 are vertically aligned with the external pads 420 of the second package P2. Here, the first package P1 and the second package P2 can be vertically spaced apart from each other. Once properly aligned, the first package P1 and the second package P2 can be connected to each other using, for example, a hybrid bonding method. For example, the external terminals 430 of the second package P2 can be inserted between the upper pads 322 of the first package P1 and the external pads 420 of the second package P2. The external terminals 430 can connect the upper pads 322 of the first package P1 to the external pads 420 of the second package P2. An underfill member (not shown) can be disposed between the first package P1 and the second package P2, and when filling the space between the first package P1 and the second package P2, the underfill member can substantially surround the external terminals 430. FIGS. 9 and 10 show a semiconductor package 13, in which the first package P1 and the second package P2 of similar size and configuration are vertically aligned and vertically stacked on top of each other. In contrast, FIGS. 12 and 13 are respective cross-sectional views showing semiconductor packages 15 and 16 according to embodiments of the concepts of the present invention, in which at least two stacked packages do not have the same size and configuration and are not vertically aligned. Referring to FIG. 12, the semiconductor package 15 includes a package substrate 510, such as a printed circuit board (PCB) having a signal pattern (not shown) on its upper surface. The package substrate 510 may further include substrate terminals 520 (e.g., solder balls, conductive bumps, or conductive pads). In some embodiments, the substrate terminals 520 can be configured as a ball grid array (BGA), a fine ball grid array (FBGA), or a land grid array (LGA). The first (or lower) package P1 in the semiconductor package 15 can be substantially similar to the semiconductor package 11 of FIG. 6 and can be mounted on the package substrate 510 using, for example, flip chip mounting technology. The external terminals 430 associated with the first package P1 can be respectively connected to the signal patterns provided on the upper surface of the package substrate 510. The semiconductor package 15 may further include conductive pillars 540 horizontally disposed adjacent to at least one side of the first package P1 on the package substrate 510. Thus, the conductive pillars 540 may be horizontally spaced apart from the side surfaces of the first package P1. Each of the conductive pillars 540 may have a columnar shape extending in a direction substantially perpendicular to the upper surface of the package substrate 510. The conductive pillars 540 may be differently connected to the signal patterns of the package substrate 510. In some embodiments, the respective upper surfaces of the conductive pillars 540 may be disposed at the same level as the upper surface of the first package P1. (In this context, the term "level" indicates a distance typically measured in a third (or vertical) direction relative to any arbitrarily selected reference (e.g., a horizontal surface or point, such as the upper surface of the package substrate 510).) The conductive pillars 540 may include at least one metal material such as copper (Cu) and tungsten (W). Although not shown, each of the conductive pillars 540 may include seed layers differently disposed on the bottom surface and / or side surfaces. The second package P2 may be disposed on the upper surfaces of the first package P1 and the conductive pillars 540. The second package P2 may be substantially the same as the semiconductor package 10 of FIGS. 1 and 2. Thus, the second package P2 may be disposed on the second redistribution layer 300 of the first package P1. However, here, the second package P2 and the first package P1 may be disposed in an offset stacked structure. For example, the first package P1 and the second package P2 may be horizontally offset in at least one of a first horizontal direction D1 and a second horizontal direction D2 such that the upper surfaces of the first package P1 and the second package P2 form a stepped structure. Thus, a first portion of the second package P2 may overlap the first package P1, while a second portion of the second package P2 may horizontally extend (or protrude) beyond the side surface of the first package P1. Since the second package P2 may be at least partially mounted on the upper surface of the first package P1 and also on the upper surfaces of the conductive pillars 540, the lower surface of the second package P2 may be substantially parallel to the upper surface of the package substrate 510. At least some of the upper pads 322 of the second redistribution layer 300 of the first package P1 may be vertically aligned with the lower pads 222 of the first redistribution layer 200 of the second package P2. In this way, the first package P1 and the conductive pillars 540 may be in contact with the second package P2. Once properly contacted and placed, the first package P1 and the second package P2 can be joined together using, for example, a hybrid bonding method. Thus, at the respective interfaces between the first package P1 and the second package P2, the upper pads 322 of the second redistribution layer 300 of the first package P1 can be joined to the lower pads 222 of the first redistribution layer 200 of the second package P2. In this regard, the upper pads 322 of the first package P1 can be at least partially merged with the lower pads 222 of the second package P2 using, for example, an intermetallic hybrid bonding method. The conductive pillars 540 can also be connected to the second package P2. For example, the upper surfaces of the conductive pillars 540 can be placed in contact with the lower pads 222 of the first redistribution layer 200 included in the second package P2 respectively and then joined using, for example, an intermetallic hybrid bonding method. Alternatively, the conductive pillars 540 can be connected to the lower pads 222 of the second package P2 via connection terminals (e.g., solder balls) respectively. Thus, the second package P2 can be electrically connected to the package substrate 510 via the conductive pillars 540 or via the first redistribution layer 200, vias 130, and the second redistribution layer 300 of the first package P1. And since the second package P2 is connected to the package substrate 510 not only via the conductive pillars 540 but also via the first package P1, the total number of the conductive pillars 540 required for mounting the second package P2 can be reduced, thereby enabling the reduction of the overall size of the semiconductor package 15. In addition, a molding layer 530 (e.g., a dielectric polymer such as an epoxy molding compound (EMC)) can be provided on the package substrate 510 to cover the exposed portions of the package substrate 510 and substantially surround the conductive pillars 540, the first package P1, and the second package P2. Thus, in some embodiments, the molding layer 530 can cover the side surfaces and the upper surfaces of each of the first package P1 and the second package P2. Alternatively, the molding layer 530 can expose the upper surface of the second package P2. On one side of the first package P1, the molding layer 530 can fill the space between the package substrate 510 and the second package P2. The molding layer 530 can substantially surround the conductive pillars 540 between the package substrate 510 and the second package P2. In some embodiments, a plurality of second packages P2 can be horizontally placed and vertically stacked on the first package P1. For example, FIG. 13 is a cross-sectional view showing a semiconductor package 16 that includes a plurality of (e.g., first and second) second packages P2 arranged in a horizontal (or lateral) offset stacked structure on the top of the first package P1. In this regard, a first one in the second package P2 can be stacked on the first package P1 and horizontally offset in one direction, and a second one in the second package P2 can be stacked on the first package P1 and horizontally offset in another direction. Thus, the first one in the second package P2 can extend beyond one side surface of the first package P1 and the second one in the second package P2 can extend beyond another side surface of the first package P1 opposite to the one side surface. The semiconductor package 16 can include a package substrate 510 and conductive pillars 540. However, here, the conductive pillars 540 can be horizontally disposed on either side (or both sides) of the first package P1. For example, a first group of conductive pillars 540 can be disposed on one side of the first package P1 and can be used to electrically connect the package substrate 510 to the first one in the second package P2. Additionally, a second group of conductive pillars 540 can be disposed on the other side of the first package P1 opposite to the one side and can be used to electrically connect the package substrate 510 to the second one in the second package P2. Also here, a molding layer 530 can be provided on the package substrate 510 to substantially surround the conductive pillars 540, the first package P1, and the second package P2. Thus, the molding layer 530 can fill the space between the package substrate 510 and the second package P2 and surround the conductive pillars 540 between the package substrate 510 and the second package P2. FIG. 14 is a cross-sectional view showing a semiconductor package 17 according to an embodiment of the concept of the present invention. Referring to FIG. 14, the package substrate 510 and the substrate terminals 520 can be provided as described above. However, a plurality of first packages P1 can be disposed on the upper surface of the package substrate 510 instead of the vertically stacked packages (package P1, package P2) described in FIGS. 12 and 13. Each of the first packages P1 can be substantially similar to the semiconductor package 11 of FIG. 6. The first packages P1 can be horizontally spaced apart from each other on the package substrate 510 and respectively mounted on the package substrate 510 using, for example, a flip-chip mounting method. Here, the respective external terminals 430 of each first package P1 can be electrically connected to the signal patterns on the package substrate 510. FIGS. 15A to 20A are related cross-sectional views showing a method of manufacturing a semiconductor package according to an embodiment of the concept of the present invention in one example. Referring to FIGS. 15A and 15B, a wafer is provided and can be used as a base for the semiconductor substrate 110. Circuit elements 122 can then be formed on the front surface 110a of the semiconductor substrate 110. For example, transistors (TR) can be formed by forming source and drain electrodes on the upper portion of the semiconductor substrate 110 and forming a gate dielectric layer and a gate electrode between the source and drain electrodes. As described above, regardless of the specific configuration, the circuit elements 122 will be formed on the device region DR of the semiconductor substrate 110. The device interlayer dielectric layer 126 and the circuit wiring pattern 124 may also be formed on the semiconductor substrate 110. For example, at least one dielectric material may be deposited on the front surface 110a of the semiconductor substrate 110 to form a lower portion of the device interlayer dielectric layer 126. Contact points may be formed to penetrate the lower portion of the device interlayer dielectric layer 126 to connect to the semiconductor substrate 110, and the circuit wiring pattern 124 may be formed in the lower portion of the device interlayer dielectric layer 126. The circuit wiring pattern 124 may be formed in the device region DR, rather than on the edge region ER. At least one dielectric material may be deposited on the lower portion of the device interlayer dielectric layer 126 to form an upper portion of the device interlayer dielectric layer 126. Contact points may be formed to penetrate the device interlayer dielectric layer 126 to connect differently from the circuit wiring pattern 124. Therefore, the circuit layer 120 may include the circuit element 122, the circuit wiring pattern 124, and the device interlayer dielectric layer 126. Referring to FIGS. 16A and 16B, the vias 130 may be formed to vertically penetrate the device interlayer dielectric layer 126. For example, in the edge region ER, through-holes may be selectively formed in the device interlayer dielectric layer 126, and the through-holes may then be filled with at least one conductive material to form the vias 130. Here, the vias 130 are formed in the edge region ER, rather than in the device region DR. The through-holes may not completely penetrate the device interlayer dielectric layer 126. For example, the vias 130 may be exposed via the upper surface (or the first surface) 110a of the semiconductor substrate 110, and may not be exposed on the opposite rear surface 110b (or the second surface) of the semiconductor substrate 110. Referring to FIGS. 17A and 17B, the first redistribution layer 200 may be formed on the circuit layer 120. For example, a dielectric layer may be formed on the lower surface of the circuit layer 120, the dielectric layer may be patterned to form the first redistribution dielectric layer 210, a dielectric layer may be formed on the first redistribution dielectric layer 210, and a conductive layer may be patterned to form the first redistribution conductive pattern 220, and as a result, one first wiring layer may be formed. The formation of the first wiring layer may be repeated to form the first redistribution layer 200. The first redistribution conductive pattern 220 of the lowermost one in the first wiring layer may correspond to the lower pad of the first redistribution layer 200. Referring to FIGS. 18A and 18B, the semiconductor substrate 110 may be disposed on the carrier substrate 910. The carrier substrate 910 may be a dielectric substrate including glass or polymer, or may be a conductive substrate including metal. An adhesive member (such as a tape) may be disposed on the upper surface of the carrier substrate 910. The semiconductor substrate 110 may be attached to the carrier substrate 910 to allow the first redistribution layer 200 to face the carrier substrate 910. A thinning process (e.g., a chemical mechanical polishing (CMP) process) can now be performed on the semiconductor substrate 110. The thinning process can be performed on the back surface 110b of the semiconductor substrate 110 to remove a portion at the back surface 110b of the semiconductor substrate 110. After the thinning process, the upper surface of the via 130 can be exposed. However, in some embodiments, the thinning process can also remove the upper portion of the via 130. Referring to FIGS. 19A and 19B, the second wiring layer 300 can be formed on the semiconductor substrate 110. For example, a dielectric layer can be formed on the back surface 110b of the semiconductor substrate 110, the dielectric can be patterned to form the second wiring dielectric layer 310, a conductive layer can be formed on the second wiring dielectric layer 310, and the conductive can be patterned to form the second wiring conductive pattern 320, and as a result, a second wiring layer can be formed. The formation of the second wiring layer can be repeatedly performed to form the second wiring layer 300. In some embodiments, the formation of the second wiring layer 300 can be omitted (see, for example, the embodiment shown in FIG. 7). Thereafter, the carrier substrate 910 can be removed from the first wiring layer 200 to expose the lower surface of the first wiring layer 200. In this regard, the bonding member can be physically or chemically removed from the carrier substrate 910. Referring to FIGS. 20A and 20B, the substrate protection layer 410 can be formed on the lower surface of the first wiring layer 200. For example, the substrate protection layer 410 can be formed by coating or depositing a dielectric material on the lower surface of the first wiring layer 200. The substrate protection layer 410 can include at least one of the following: high density plasma (HDP) oxide, undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), silicon nitride (SiN), silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon carbonitride (SiCN). The substrate protection layer 410 can be patterned to expose the lower pad of the first wiring layer 200 or the first wiring conductive pattern 220 of the lowermost first wiring layer included in the first wiring layer 200. A conductive layer can be formed on the substrate protection layer 410, and the conductive layer can be patterned to form the external pad 420. The external pad 420 can be coupled to the lower pad of the first wiring layer 200. The external terminal 430 can be disposed on the first wiring layer 200. The external terminal 430 can be disposed on the lower surface of the external pad 420. Certain semiconductor packages in accordance with embodiments of the present inventive concept include a first redistribution layer and a second redistribution layer disposed on an upper surface and a lower surface of a semiconductor wafer, respectively. The first redistribution layer and the second redistribution layer may be electrically connected using vias that penetrate a body of the semiconductor wafer in an edge region substantially surrounding a device region. In view of this configuration, the resulting semiconductor package may have a more compact size occupying a smaller area. Since the first redistribution layer and the second redistribution layer can be connected in the foregoing manner, connection members conventionally used to connect upper and lower conductive elements are not required to be molded members. Thus, in view of the absence of the inherent thermal insulation effect associated with conventionally provided molded members, heat generated by operation of the semiconductor wafer can be easily dissipated. And as another result, semiconductor packages in accordance with embodiments of the present inventive concept exhibit improved thermal radiation properties. Since the vias are only disposed in the indicated edge regions of semiconductor packages in accordance with embodiments of the present inventive concept, such semiconductor packages enjoy relative layout freedom and / or interconnection freedom. Thus, various circuit elements and associated circuit wiring patterns can be designed to increase overall integration and / or avoid design faults (e.g., short circuit electrical connections). Accordingly, a more compact size semiconductor package exhibiting increased integration and improved electrical properties can be provided. Although the present inventive concept has been described with respect to certain of its embodiments, those of ordinary skill in the art will understand that changes in form and detail may be made without departing from the scope of the present inventive concept as defined by the appended claims. 10, 10A, 10B, 10C, 11, 12, 13, 14, 15, 16, 17: Semiconductor package 100: Semiconductor wafer 110: Semiconductor substrate 110a: First surface 110b: Second surface 120: Circuit layer 122: Circuit element 124: Circuit wiring pattern 124a: Portion 126: Device interlayer dielectric layer 130: Via 140: Additional element 200: First redistribution layer 210: First redistribution dielectric layer 220: First redistribution conductive pattern 222: Lower pad 300: Second redistribution layer 310: Second redistribution dielectric layer 320: Second redistribution conductive pattern 322: Upper pad 410: Substrate protective layer 420: External pad 430: External terminal 510: Package substrate 520: Substrate terminal 530: Molded layer 540: Conductive pillar 910: Carrier substrate d: Diameter D1: First direction D2: Second direction D3: Third direction DR: Device region ER: Edge region g: Spatial interval P1: First semiconductor package P2: Second semiconductor package TR: Transistor w: Width After considering the following detailed description and the accompanying drawings, the advantages, benefits, and features of the inventive concept, as well as the manufacturing and use thereof, will be clearly understood. In the accompanying drawings: FIG. 1 is a cross-sectional view of a semiconductor package 10 showing an embodiment according to the inventive concept. FIG. 2 is an enlarged cross-sectional view further partially showing the semiconductor package 10 of FIG. 1. FIGS. 3, 4, and 5 are respective plan (or top) views of semiconductor packages 10A, 10B, and 10C showing embodiments according to the inventive concept. FIGS. 6 and 7 are respective cross-sectional views of semiconductor packages 11 and 12 showing embodiments according to the inventive concept. FIG. 8 is an enlarged cross-sectional view further partially showing the semiconductor package 12 of FIG. 7. FIG. 9 is a cross-sectional view of a semiconductor package 13 showing an embodiment according to the inventive concept. FIG. 10 is an enlarged cross-sectional view further partially showing the semiconductor package 13 of FIG. 9. FIGS. 11, 12, 13, and 14 are respective cross-sectional views of various semiconductor packages showing embodiments according to the inventive concept. FIGS. 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, and 20B (hereinafter collectively referred to as "FIGS. 15A to 20B") are various related cross-sectional views showing a method of manufacturing a semiconductor package according to an embodiment of the inventive concept in one example. 10: Semiconductor package 100: Semiconductor wafer 110: Semiconductor substrate 120: Circuit layer 130: Via 200: First redistribution layer 210: First redistribution dielectric layer 220: First redistribution conductive pattern 300: Second redistribution layer 310: Second redistribution dielectric layer 320: Second redistribution conductive pattern D1: First direction D2: Second direction D3: Third direction DR: Device region ER: Edge region TR: Transistor

Claims

1. A semiconductor package, comprising: A first semiconductor substrate has an active surface, the active surface comprising a device region and an edge region; A first semiconductor element, located on the device region of the active surface, wherein the first semiconductor element includes a transistor formed on the device region of the active surface of the first semiconductor substrate; a first circuit layer disposed on the device region and the edge region of the active surface of the first semiconductor substrate; a first redistribution layer disposed on the first circuit layer; and a plurality of first vias located on the edge region, wherein the first vias vertically penetrate the first semiconductor substrate and the first circuit layer and are connected to the first redistribution layer, wherein the first circuit layer includes: a first inter-device dielectric layer covering the active surface of the first semiconductor substrate; and a first circuit wiring pattern located on the device region, wherein the first circuit wiring pattern is disposed in the first inter-device dielectric layer and connected to the first semiconductor element, wherein the first circuit wiring pattern and the first vias are electrically connected via the first redistribution layer, and wherein the first vias are configured to extend along a lateral surface of the first semiconductor substrate and be spaced apart from each other in at least two rows in a direction from the device region toward the lateral surface of the first semiconductor substrate.

2. The semiconductor package as claimed in claim 1, wherein, when viewed in a plan view, the first through-hole is spaced apart from the first circuit wiring pattern in a direction from the device region toward the edge region.

3. The semiconductor package as claimed in claim 1, wherein the first circuit wiring pattern is not disposed on the edge region.

4. The semiconductor package as claimed in claim 1, wherein the first through-hole vertically penetrates the first semiconductor substrate and the first device interlayer dielectric layer.

5. The semiconductor package of claim 1, wherein the ratio between the first region of the device region and the second region of the edge region is in the range of about 5:95 to about 95:

5.

6. The semiconductor package of claim 1, further comprising a second rewiring layer disposed on a non-active surface of the first semiconductor substrate, wherein the first via connects the first rewiring layer and the second rewiring layer to each other.

7. The semiconductor package of claim 1 further includes a plurality of pads disposed on the first redistribution layer, wherein at least one of the pads is positioned on the edge region.

8. A semiconductor package, comprising: A first semiconductor wafer includes a first silicon substrate, a first semiconductor element formed on an active surface of the first silicon substrate, and a first circuit layer disposed on the active surface of the first silicon substrate, wherein the first semiconductor element includes a transistor formed on the active surface of the first silicon substrate; and a first redistribution layer disposed on the active surface of the first semiconductor wafer and coupled to the first circuit layer. A second wiring layer is disposed on the non-active surface of the first semiconductor wafer; a first via vertically penetrates the first semiconductor wafer and connects the first wiring layer and the second wiring layer to each other, wherein the first via vertically penetrates the first silicon substrate and the first circuit layer; and a plurality of pads are disposed on the first wiring layer, wherein the first circuit layer includes: a first inter-device dielectric layer covering the active surface of the first silicon substrate; and a first circuit wiring pattern disposed in the first inter-device dielectric layer, wherein the first via is spaced apart from the first circuit wiring pattern.

9. The semiconductor package of claim 8, wherein the first silicon substrate includes a device region thereon on which the first semiconductor element is disposed and an edge region surrounding the device region, the first circuit wiring pattern is disposed on the device region, and the first via is disposed on the edge region.

10. The semiconductor package as claimed in claim 9, wherein the first circuit wiring pattern is not disposed on the edge region.

11. The semiconductor package of claim 9, wherein at least one of the pads is positioned on the edge region.

12. The semiconductor package of claim 8, wherein the first circuit wiring pattern and the first via are electrically connected via the first rewiring layer.

13. The semiconductor package of claim 8, wherein the first through-hole vertically penetrates the first silicon substrate and the first device interlayer dielectric layer.

14. The semiconductor package of claim 8, wherein a plurality of the first through-holes are provided, and the width of the first through-holes and the spacing between the first through-holes are in the range of about 0.001 mm to about 1 mm.

15. The semiconductor package as described in claim 8, further comprising: A second semiconductor wafer is mounted on the second redistribution layer, wherein the second semiconductor wafer includes a second silicon substrate, a second semiconductor element formed on an active surface of the second silicon substrate, and a second circuit layer disposed on the active surface of the second silicon substrate; a third redistribution layer is disposed on the active surface of the second semiconductor wafer and coupled to the second circuit layer; a fourth redistribution layer is disposed on a non-active surface of the second semiconductor wafer; and a second through-hole vertically penetrates the second semiconductor wafer and connects the third redistribution layer and the fourth redistribution layer to each other.

16. The semiconductor package of claim 15, wherein the second overlay layer and the third overlay layer are in contact with each other, and wherein the first conductive pattern of the second overlay layer and the second conductive pattern of the third overlay layer are directly coupled to each other.

17. The semiconductor package of claim 15, wherein the third wiring layer is mounted on the second wiring layer by means of a plurality of die terminals disposed between the second wiring layer and the third wiring layer.

18. The semiconductor package of claim 15, wherein the second silicon substrate is vertically aligned with the first silicon substrate, or the second silicon substrate is offset from the silicon substrate in a direction parallel to the top surface of the first silicon substrate.

19. The semiconductor package as described in claim 8, further comprising: The encapsulation substrate is mounted on the first wiring layer via a plurality of connection terminals disposed on the pad; And a third semiconductor wafer, located on the packaging substrate and horizontally spaced apart from the first semiconductor wafer.

20. A semiconductor package, comprising: Packaging substrate; and a wafer package mounted on the package substrate, wherein the wafer package includes: a semiconductor wafer including a silicon substrate and a circuit wiring pattern located on the silicon substrate, the silicon substrate having semiconductor elements formed on an active surface of the silicon substrate, and the circuit wiring pattern being connected to the semiconductor elements, wherein the semiconductor elements include transistors formed on the active surface of the silicon substrate; and a first redistribution layer disposed on a first surface of the semiconductor wafer, the first surface being oriented toward the package substrate; A second wiring layer is disposed on a second surface of the semiconductor wafer, the second surface being opposite to the first surface; And a plurality of vias vertically penetrating the semiconductor wafer and connecting the first and second superwiring layers to each other, wherein the vias vertically penetrate the silicon substrate, wherein the vias are located between the circuit wiring pattern and the outer surface of the silicon substrate, and wherein the distance from the outer surface of the silicon substrate to the conductive pattern of the first superwiring layer is less than the distance from the outer surface of the silicon substrate to the circuit wiring pattern.

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