Image analysis system and image analysis method

Abstract

This disclosure provides an image analysis system and an image analysis method. The image analysis system includes an input device, a storage device, and a processing device. The input device is configured to receive circuit layout image information for manufacturing a printed circuit board. The storage device is configured to access preset standard information. The processing device is electrically connected to the input device and the storage device, wherein the processing device is configured to generate at least one feature information based on the circuit layout image information, and the processing device is configured to compare the at least one feature information with the preset standard information to generate feasibility analysis information.

Description

Technical Field

[0001] The present invention relates to printed circuit board manufacturing technology, and more particularly to an image analysis system and an image analysis method. Prior Art

[0002] Electronic design automation (EDA) refers to a design method that uses computer-aided design software to complete the design process of electronic components (such as printed circuit boards, integrated circuits, etc.). Among them, design for manufacturability (DFM) is an important step in EDA. Specifically, the purpose of DFM is to evaluate the circuit layout parameters according to some design specifications (or design standards) to ensure that the product design can proceed smoothly during the actual manufacturing process. In this way, manufacturing problems can be reduced, production costs can be lowered, and the quality and reliability of the product can be improved. In order to make the results of DFM more accurate and meet the user's needs, it is necessary to develop an analysis system and an analysis method that can accurately judge the circuit layout parameters or design parameters. Summary of the Invention

[0003] In some embodiments, an image analysis system is provided. The image analysis system includes an input device, a storage device, and a processing device. The input device is configured to receive circuit layout image information for manufacturing a printed circuit board. The storage device is configured to access preset standard information. The processing device is electrically connected to the input device and the storage device, wherein the processing device is configured to generate at least one characteristic information according to the circuit layout image information, and the processing device is configured to compare at least one characteristic information with the preset standard information to generate a feasibility analysis information.

[0004] In some embodiments, an analysis method is provided. The image analysis method includes: receiving, by an input device, circuit layout image information for manufacturing a printed circuit board; generating, by a processing device, at least one characteristic information according to the circuit layout image information; comparing, by the processing device, at least one characteristic information with a preset standard information stored in a storage device to generate a feasibility analysis information.

[0005] The image analysis system and method disclosed herein can be applied to the Design for Manufacturing (DFM) analysis of printed circuit boards. By analyzing the image information of the circuit layout of printed circuit boards through images, it is possible to effectively avoid design errors before actually manufacturing printed circuit boards, thereby avoiding manufacturing cost losses caused by subsequent defect repair or scrapping of defective products. To make the features and advantages of the present disclosure more obvious and understandable, various embodiments are specifically given below and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0006] Through the following detailed description in conjunction with the accompanying drawings, the viewpoints of the embodiments of the present disclosure can be better understood. It should be noted that, according to industrial standard conventions, some features may not be drawn to scale. In fact, for the sake of clear description, the sizes of different components may be increased or decreased. FIG. 1 is a block diagram of an image display analysis system according to some embodiments of the present disclosure; FIG. 2 is a flowchart of an image display analysis method according to some embodiments of the present disclosure; FIG. 3 is a cross-sectional schematic diagram showing a circuit pattern according to some embodiments of the present disclosure; FIG. 4 is a top view schematic diagram showing a circuit pattern according to some embodiments of the present disclosure; FIGS. 5A and 5B are perspective schematic diagrams showing a circuit pattern according to some embodiments of the present disclosure, respectively; FIGS. 6A and 6B are top view schematic diagrams showing gaskets according to some embodiments of the present disclosure, respectively; FIG. 7 is a top view schematic diagram showing a heat dissipation copper bar according to some embodiments of the present disclosure; FIG. 8A is a top view schematic diagram showing a via according to some embodiments of the present disclosure; and FIGS. 8B and 8C are cross-sectional and top view schematic diagrams showing a via according to some other embodiments of the present disclosure, respectively. Embodiments

[0007] The following disclosure provides many different embodiments or examples for implementing the provided analysis system and analysis method. Specific examples of each component and its configuration are described below to simplify the embodiments of this disclosure, and of course, they are not used to limit this disclosure. For example, when it is mentioned in the description that the first component is formed on the second component, it may include embodiments where the first component and the second component are in direct contact, or it may also include embodiments where additional components are formed between the first component and the second component, such that the first component and the second component are not in direct contact. In addition, this disclosure may repeat element symbols and / or characters in different embodiments or examples. Such repetition is for the sake of brevity and clarity, rather than to indicate the relationship between the different embodiments and / or examples discussed.

[0008] The directional terms mentioned in this article, such as "up", "down", "left", "right" and their similar terms, are with reference to the directions of the drawings. Therefore, the directional terms used are for illustration rather than to limit this disclosure.

[0009] In some embodiments of this disclosure, terms related to setting and connection, such as "set", "connected" and their similar terms, unless specifically defined, may refer to two components in direct contact, or may also refer to two components not in direct contact, where there are additional components located between these two structures. Terms related to setting and connection may also include cases where both structures are movable, or both structures are fixed.

[0010] In addition, the "first", "second" and their similar terms mentioned in this specification or claims are used to name different components or to distinguish different embodiments or scopes, rather than to limit the upper or lower limits of the number of components, nor to limit the manufacturing order or setting order of the components.

[0011] Hereinafter, "about", "substantially" or their similar terms mean within 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of a given numerical value or numerical range. The given quantity is an approximate quantity, that is, even without specifically stating "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0012] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that such terms, if defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0013] In the prior art, the layout of a printed circuit board (PCB) is usually carried out by engineering drawing software. Specifically, the layout needs to meet design specifications such as electrical rules, routing rules, surface mount technology rules (SMT rules), mask rules, manufacture rules, etc., to ensure that a printed circuit board that meets the expectations and is reliable can be actually manufactured.

[0014] For this reason, this disclosure provides an image analysis system and an image analysis method, which can automatically determine the manufacturing feasibility of the layout according to a preset standard or a custom standard, thereby effectively solving the above problems. It is worth mentioning that although some design specifications in the layout are mentioned above, this disclosure is not limited thereto. In other embodiments, the image analysis system and the image analysis method of this disclosure can analyze the layout according to any design specifications recognized by one of ordinary skill in the art to which this disclosure pertains.

[0015] Referring to FIG. 1, which is a block diagram showing an image analysis system according to some embodiments of this disclosure. As shown in the figure, the image analysis system 1 includes an input device 10, a storage device 11, a processing device 12, and an output device 13. In some embodiments, the image analysis system 1 and each device therein can be individually or integrally installed in a terminal device, a computer device, and / or a server in the form of a combination of software programs and physical circuits, and after being read and / or enabled, perform a manufacturing feasibility analysis on the layout information for producing a printed circuit board.

[0016] The input device 10 is configured to receive line layout image information for manufacturing printed circuit boards. In some embodiments, the line layout image information may be presented as a digital file of engineering drawing software (e.g., a CAM file), and the line layout image information may be a two-dimensional design drawing or a three-dimensional design drawing. In some embodiments, the line layout image information may include schematics and their parameters of substrates, circuit patterns, pads, vias, combinations thereof, and other electronic components. For example, the parameters of the substrate include substrate length, substrate width, substrate thickness, substrate shape, substrate material, combinations thereof, or other suitable parameters, but the present disclosure is not limited thereto. For example, the parameters of the circuit pattern include upper line width, lower line width, line height, line pitch, conductor material, combinations thereof, or other suitable parameters, but the present disclosure is not limited thereto. For example, the parameters of the pad include pad size, pad material, combinations thereof, or other suitable parameters, but the present disclosure is not limited thereto.

[0017] In some embodiments, the input device 10 may also be configured to receive preset standard information or customized standard information. Among them, the preset standard information may include parameter thresholds corresponding to one or more of the design specifications such as electrical rules, wiring rules, surface mount technology rules, solder mask / soldering rules, manufacturing rules, etching rules, etc. For example, the preset standard information may include line bending angle standard information, pad pitch standard information, copper spokes standard information, via standard information, pin standard information, line size standard information, line position standard information, combinations thereof, or other suitable standard information. These standard information will be used to compare whether the line layout image information complies with the design specifications such as those mentioned above. When the line layout image information does not conform to the standard information, it means that some of the parameters of the line layout exceed the parameter thresholds, such that there may be a risk of insufficient manufacturing feasibility for the said part.

[0018] In addition, in order to meet the design requirements of different products (e.g., higher electrical requirements or specific structures), the preset standard information may also be adjusted to generate customized standard information. Similarly, the customized information may include line bending angle customized information, pad pitch customized information, copper spokes customized information, via shape customized information, pin customized information, line size customized information, line position customized information, combinations thereof, or other suitable customized information.

[0019] In some embodiments, the input device 10 may be or may include a device for receiving digital image files, such as a connector, a communication port, etc. Alternatively, the input device 10 may be or may include a device for reading digital image files, such as a card reader, etc. In some embodiments, the input device 10 may further include an alphanumeric keyboard and a pointing device (e.g., a cursor control device), a photographing device, a microphone, or a similar device for receiving voice commands, etc., but the present disclosure is not limited thereto.

[0020] The storage device 11 is configured to access preset standard information, custom standard information, and circuit layout image information. In some embodiments, the storage device 11 may include a compact disc read-only memory (CD-ROM), a hard disk drive, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc., but the present disclosure is not limited thereto. Examples of memory may include a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, etc., but the present disclosure is not limited thereto.

[0021] The processing device 12 is electrically connected to the input device 10 and the storage device 11, and the processing device 12 is configured to generate at least one piece of feature information according to the circuit layout image information. Specifically, the processing device 12 is configured to compare at least one piece of feature information with preset standard information, or is configured to compare at least one piece of feature information with customized standard information. Herein, the term "feature information" refers to the patterns and their parameters of substrates, circuit patterns, pads, or other electronic components in the circuit layout image information, but the present disclosure is not limited thereto. For example, the processing device 12 can extract the upper line width, lower line width, line height, and line pitch of the circuit pattern in the circuit layout image information to generate feature information. Then, the processing device 12 determines whether these feature information conform to the corresponding parameters in the preset standard information. When the upper line width of the circuit pattern does not conform to the upper line width threshold value in the preset standard information, it indicates that the circuit pattern may have a risk of insufficient manufacturing feasibility. For example, an over-etching result may occur in the subsequent etching process. The specific operations of the comparison process for manufacturing feasibility will be further described in the analysis method below, and only the possible configurations and functions of each device are described herein.

[0022] In some embodiments, the processing device 12 may include electronic components such as a processor, a computer-readable medium, and a memory to execute a computer program to implement the functions described above. Among them, examples of the processor may include a central processing unit (CPU), a multi-core CPU, a graphics processing unit (GPU), etc., but the present disclosure is not limited thereto. Examples of the computer-readable medium may include a compact disc read-only memory (CD-ROM), a hard disk drive, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc., but the present disclosure is not limited thereto. Examples of the memory may include a dynamic random access memory, a static random access memory, a flash memory, etc., but the present disclosure is not limited thereto. It is worth mentioning that the term "computer program" as used herein refers to an application program stored in a computer-readable medium, which can be read into the memory for the processor to process. In some embodiments, the application program can be written in any combination of one or more programming languages. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, or similar languages, and include traditional procedural programming languages such as the C programming language or similar programming languages.

[0023] The output device 13 is electrically connected to the processing device 12 and is configured to display the feasibility analysis information according to the comparison result of the processing device 12. In some embodiments, the output device 13 displays an image or output data generated by the electronic components. For example, the output device 13 may be or may include a printer, a display, a speaker, or a similar output device, where the display is such as a cathode ray tube (CRT), a liquid crystal display (LCD), etc. It is worth mentioning that in some embodiments, the image analysis system 1 may not have the output device 13. In these embodiments, the feasibility analysis information obtained by the image analysis system 1 can be read by other devices outside the image analysis system 1, such as the terminal device of the manufacturing system, etc.

[0024] Referring to FIG. 2 together, which is a flowchart showing an image analysis method according to some embodiments of the present disclosure. As shown in the figure, the analysis method includes steps S10 to S16. In step S10, a line layout image information for manufacturing a printed circuit board is received by the input device 10. In some embodiments, the line layout image information may be a digital image file that has been drawn by other drawing devices. Alternatively, an instruction may also be input by the input device 10 to directly generate the line layout image information in the terminal device, computer device, and / or server where the image analysis system of the present disclosure is located, and edit the line layout image information. In step S12, at least one feature information is generated by the processing device 12 according to the line layout image information. In step S14, the processing device 12 compares at least one feature information with the preset standard information stored in the storage device. In step S16, the output device 13 displays the feasibility analysis information according to the comparison result of the processing device 12. Among them, the feasibility analysis information may be presented in the form of a chart, a design drawing, or a text description, but the present disclosure is not limited thereto. It is worth mentioning that in some embodiments, the image analysis system 1 may not have the output device 13. Therefore, in these embodiments, step S16 may be omitted.

[0025] In some embodiments, the processing device 12 may generate at least one feature information according to the full version image of the line layout image, or may also generate at least one feature information according to the partial image of the line layout image, but the present disclosure is not limited thereto.

[0026] In some embodiments, the processing device 12 may be an AI artificial intelligence device, and use AI artificial intelligence to perform the processing of steps S12 and S14, but the present disclosure is not limited thereto.

[0027] To more clearly understand steps S12 and S14, the operations of extracting feature information and comparing feature information with preset standard information are described below with reference to FIGS. 3 to 8C together. It is worth mentioning that the manufacturing feasibility analysis operations described below are only some embodiments of the present disclosure, which are only used to make the present disclosure easier to understand, but are not intended to limit the present disclosure. In other embodiments, different feature information may be extracted for the manufacturing feasibility analysis operation.

[0028] As shown in FIG. 3, which is a schematic cross-sectional view showing a circuit pattern according to some embodiments of the present disclosure. In some embodiments, the processing device 12 extracts feature information of the circuit pattern C provided on the substrate S at a specific position (e.g., the cross-section shown in FIG. 3). For example, the feature information may include line information, which defines values such as the upper line width W1, the lower line width W2, the sidewall width W3, the line height H, and the top-view sidewall width d1. On the other hand, the preset standard information correspondingly includes line standard information, and the line standard information defines values such as the upper line width threshold, the lower line width threshold, the sidewall width threshold, the line height threshold, and the top-view sidewall width threshold. In this case, step S12 may further include: comparing, by the processing device 12, the line information with the line standard information. In some embodiments, electrical rules define the electrical requirements of the circuit pattern, and the line information affects the electrical performance of the line. Therefore, when the above parameters are lower than the threshold (e.g., the upper line width W1 is lower than the upper line width threshold), the processing device 12 may determine that the manufacturing feasibility is insufficient according to the electrical rules. In some embodiments, the electrical rules may be calculation methods specified in relevant standards such as IPC issued by the International Electronics Industries Association, such as IPC-2221, IPC-2222, IPC-2223, IPC-2224, IPC-2225, IPC-2226, IPC-2227, etc., but the present disclosure is not limited thereto.

[0029] As shown in FIG. 4, which is a top-view schematic view showing a circuit pattern according to some embodiments of the present disclosure. In some embodiments, the line information further defines the line pitch d2, and the line standard information defines the line pitch threshold. In this case, step S12 may further include: comparing, by the processing device 12, the line information with the line standard information. In some embodiments, clearance rules define that the distance between two adjacent conductors in the circuit pattern shall not be less than a certain value to avoid interference between electrical signals or to avoid a short circuit between two lines. Therefore, when the line pitch d2 is lower than the line pitch threshold, the processing device 12 may determine that the manufacturing feasibility is insufficient according to the clearance rules.

[0030] As shown in FIG. 4, in some embodiments, the feature information may further include line position information, and the preset standard information correspondingly includes line position standard information. In this case, step S12 may further include: comparing, by the processing device 12, the line position information with the line position standard information. In some embodiments, the safety spacing rule defines that the spacing d3 between the conductor in the circuit pattern and the periphery of the substrate shall not be lower than a certain value to avoid forming an electrical short circuit along the sidewall of the substrate between two conductors located in different layers. Therefore, when the spacing d3 between the conductor and the periphery of the substrate is lower than the threshold, the processing device 12 may determine that the manufacturing feasibility is insufficient according to the safety spacing rule.

[0031] As shown in FIGS. 5A and 5B, which are respectively three-dimensional schematic diagrams showing a circuit pattern according to some embodiments of the present disclosure. In some embodiments, the processing device 12 extracts the feature information of the circuit pattern C provided on the substrate S. For example, the feature information may include line bending angle information, and the preset standard information correspondingly includes line bending angle standard information. As shown in FIG. 5A, for example, the line bending angle information defines the bending angle θ1 of the circuit pattern C1 in the area A1, and defines the bending angles θ20 and θ21 of the circuit pattern C2 in the area A2. Among them, the bending angle θ1 is less than 90 degrees, the bending angle θ20 is equal to 90 degrees, and the bending angle θ21 is greater than 90 degrees. In this case, step S12 may further include: comparing, by the processing device 12, the line bending angle information with the line bending angle standard information. In some embodiments, the routing corners rules define that the bending angle of the circuit pattern shall not be less than a right angle (i.e., an acute angle) to avoid the etching solution of the subsequent etching process getting into the corners of the circuit pattern and forming an acid trap. Therefore, the processing device 12 may determine that the manufacturing feasibility of the circuit pattern C1 in the area A1 is insufficient according to the routing corners rules, and determine that the circuit pattern C2 in the area A2 has manufacturing feasibility.

[0032] Similarly, as shown in FIG. 5B, the line bending angle information defines the bending angle θ3 of the circuit pattern C3 in the area A3, and defines the bending angles θ40 and θ41 of the circuit pattern C4 in the area A4. Among them, the bending angle θ3 is less than 90 degrees, the bending angle θ40 is equal to 90 degrees, and the bending angle θ41 is greater than 90 degrees. In this case, step S12 may further include: comparing, by the processing device 12, the line bending angle information with the line bending angle standard information. Further, the processing device 12 may determine that the manufacturing feasibility of the circuit pattern C3 in the area A3 is insufficient according to the routing corners rules, and determine that the circuit pattern C4 in the area A4 has manufacturing feasibility.

[0033] As shown in FIGS. 6A and 6B, which are respectively top schematic views of a gasket according to some embodiments of the present disclosure. In some embodiments, the feature information may include gasket spacing information, and the preset standard information correspondingly includes gasket spacing standard information. As shown in FIG. 6A, for example, the gasket spacing information defines the gasket spacing d4 between two adjacent gaskets P, and the line standard information defines a gasket spacing threshold. In this case, step S12 may further include: comparing, by the processing device 12, the gasket spacing information with the gasket spacing standard information. In some embodiments, the safety spacing rule defines that the spacing d4 between two adjacent gaskets shall not be lower than a certain value to prevent the gasket P from drifting during subsequent processes such as reflow soldering and generating an antenna effect (floating copper / solder mask silvers antennas) with other gaskets P (as shown in area A5 of FIG. 6B), or to prevent the gasket P from drifting during subsequent processes such as reflow soldering and causing an electrical short circuit with other gaskets P (as shown in area A6 of FIG. 6B). Therefore, when the gasket spacing d4 is lower than the gasket spacing threshold, the processing device 12 may determine that the manufacturing feasibility is insufficient according to the safety spacing rule.

[0034] As shown in FIG. 7, which is a top schematic view of a heat dissipation copper bar according to some embodiments of the present disclosure. In some embodiments, the feature information may further include heat dissipation copper bar information, and the preset standard information correspondingly includes heat dissipation copper bar standard information. For example, the heat dissipation copper bar information defines the number of heat dissipation copper bars CS, and the heat dissipation copper bar standard information defines a threshold value for the number of heat dissipation copper bars. In this case, step S12 may further include: comparing, by the processing device 12, the heat dissipation copper bar information with the heat dissipation copper bar standard information. In some embodiments, the heat dissipation copper bars CS are used to provide sufficient heat capacity (or heat storage) during the soldering process to avoid instability or insufficient heat storage (starved thermal) during the soldering process. Therefore, when the number of heat dissipation copper bars CS exceeds (for example, is lower than) the threshold value for the number of heat dissipation copper bars, the processing device 12 may determine that the manufacturing feasibility is insufficient.

[0035] As shown in FIGS. 8A to 8C, where FIG. 8A is a top schematic view showing a via hole according to some embodiments of the present disclosure, and FIGS. 8B and 8C are respectively a cross-sectional schematic view and a top schematic view showing a via hole according to some other embodiments of the present disclosure. In some embodiments, the feature information may include via hole information, and the preset standard information correspondingly includes via hole standard information. In some embodiments, the via hole V is an interconnect component for electrical connection, which includes a conductive layer V1 horizontally extending on the surface of the substrate S and vertically extending on the side wall of the through hole, and includes a conductive filling material V2 vertically extending in the through hole (as shown in FIG. 8B). In a top view perspective, the via hole information defines the distance d5 between the center CC1 of the conductive layer V1 and the center CC2 of the conductive filling material V2 (as shown in FIG. 8C), and the via hole standard information defines a distance threshold. In this case, step S12 may further include: comparing the via hole information with the via hole standard information by the processing device 12. In some embodiments, the routing via style defines that the distance d5 between the center CC1 of the conductive layer V1 and the center CC2 of the conductive filling material V2 shall not exceed a certain value to avoid the electrical properties of the via hole V not meeting the design specifications. Therefore, when the distance d5 between the center CC1 of the conductive layer V1 and the center CC2 of the conductive filling material V2 exceeds the distance threshold, the processing device 12 may determine that the manufacturing feasibility is insufficient according to the routing via style rule.

[0036] In some embodiments, the feature information may further include pin information, and the preset standard information includes pin standard information. For example, the pin information defines the number of clearance pads, and the pin standard information defines a number threshold of the clearance pads. In this case, step S12 may further include: comparing the pin information with the pin standard information by the processing device 12. In some embodiments, if there is no clearance pad provided between the pin and the substrate in the circuit layout, the pin will be directly connected to the voltage plane, resulting in a functional failure. Therefore, when the pin information does not define enough clearance pads at the position of the pin, the processing device 12 may determine that the manufacturing feasibility is insufficient.

[0037] In the above, some possible embodiments of the feature information have been provided, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various design specifications that the circuit layout of the printed circuit board needs to comply with can be used as the feature information to determine the manufacturing feasibility. For example, the design specifications may further include short-circuit rules, SMD to corner rules, and other suitable rules, but the present disclosure is not limited thereto.

[0038] In some embodiments, step S14 may also be replaced by the following steps. The replacement steps are as follows: The processing device 12 compares at least one piece of feature information with the customized standard information stored in the storage device. In some cases, although the printed circuit board already complies with common design specifications, it may not meet the requirements of the product design. Therefore, the image analysis system and the image analysis method disclosed herein can also cause the processing device 12 to compare the feature information with the customized standard information according to the requirements of the product design. Among them, the customized standard information can define various parameters similar to those mentioned above, but the disclosure is not limited thereto.

[0039] In some embodiments, the image analysis system disclosed herein can analyze the circuit layout design before the etching process and give modification suggestions, reducing the possibility that the product has defects after etching and even cannot be repaired, but the disclosure is not limited thereto.

[0040] In summary, by analyzing the circuit layout image information of the printed circuit board in this case, it is possible to effectively avoid design errors before actually manufacturing the printed circuit board, thereby avoiding the manufacturing cost losses caused by subsequent defect repair or defective product scrapping.

[0041] The above outlines several embodiments so that those of ordinary skill in the art can better understand the viewpoints of the embodiments disclosed herein. Those of ordinary skill in the art should understand that other processes and structures can be designed or modified based on the embodiments disclosed herein to achieve the same purposes and / or advantages as the embodiments introduced herein. Those of ordinary skill in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the disclosure.

[0042] 1: Image analysis system 10: Input device 11: Storage device 12: Processing device 13: Output device A1: Area A2: Area A3: Area A4: Area A5: Area A6: Area C: Circuit pattern C1: Circuit pattern C2: Circuit pattern C3: Circuit pattern C4: Circuit pattern CC1: Center of circle CC2: Center of circle CS: Heat dissipation copper bar d1: Depth d2: Line pitch d3: Spacing d4: Spacer spacing d5: Spacing H: Line height P: Spacer S: Substrate S10 - S16: Steps V: Via V1: Conductive layer V2: Conductive filling material W1: Upper line width W2: Lower line width W3: Side line length θ1: Bending angle θ20: Bending angle θ21: Bending angle θ3: Bending angle θ40: Bending angle θ41: Bending angle

Claims

1. An image analysis system comprising: an input device configured to receive circuit layout image information for manufacturing a printed circuit board; a storage device configured to access preset standard information; and a processing device electrically connected to the input device and the storage device, wherein the processing device is configured to generate at least one feature information based on a full-page image of the circuit layout image information, and the processing device is configured to compare the at least one feature information with the preset standard information to generate feasibility analysis information, wherein the at least one feature information includes geometric layout features of the printed circuit board, wherein the feasibility analysis information relates to an etching process or a soldering process of the printed circuit board, wherein the combination of the at least one feature information and the preset standard information satisfies at least one of the following (A) to (E): (A) the at least one feature information includes a spacer spacing information, and the preset standard information includes a spacer spacing standard information; (B) the at least one feature information includes a heat sink copper strip information, and the preset standard information includes a heat sink copper strip standard information. (C) The at least one feature information includes a via information, and the preset standard information includes a via standard information. (D) The at least one feature information includes a pin information, and the preset standard information includes a pin standard information. (E) The at least one feature information includes a line position information, and the preset standard information includes a line position standard information.

2. The image analysis system of claim 1, wherein the combination of the at least one feature information and the preset standard information satisfies at least one of the following (F) to (G): (F) the at least one feature information includes a line information and the preset standard information includes a line standard information; (G) the at least one feature information includes a line curvature angle information and the preset standard information includes a line curvature angle standard information.

3. The image analysis system of claim 1, wherein the input device is further configured to receive a custom standard information, and the processing device is further configured to compare at least one feature information with the custom standard information, thereby generating the feasibility analysis information.

4. The image analysis system of claim 1, wherein the image analysis system analyzes the circuit layout design of the printed circuit board prior to the etching process.

5. The image analysis system of claim 1, wherein the processing device generates the feasibility analysis information in accordance with relevant electrical specifications such as IPC published by the International Electron Devices Association when comparing the at least one feature information with the preset standard information.

6. The image analysis system of claim 1 further includes an output device electrically connected to the processing device, the output device being configured to output the feasibility analysis information to an external device or display the feasibility analysis information.

7. An image analysis method comprising the following steps: receiving, via an input device, circuit layout image information for producing a printed circuit board; generating, via a processing device, at least one feature information based on a full-page image of the circuit layout image information; and generating, via the processing device, a feasibility analysis information by comparing the at least one feature information with preset standard information stored in a storage device, wherein the at least one feature information includes geometric layout features of the printed circuit board, wherein the feasibility analysis information relates to an etching process or soldering process of the printed circuit board, wherein the combination of the at least one feature information and the preset standard information satisfies at least one of the following (A) to (G): (A) the at least one feature information includes circuit information, and the preset standard information includes circuit standard information; (B) the at least one feature information includes circuit bending angle information, and the preset standard information includes circuit bending angle standard information; (C) the at least one feature information includes spacer spacing information, and the preset standard information includes spacer spacing standard information. (D) The at least one feature information includes a heat dissipation copper strip information, and the preset standard information includes a heat dissipation copper strip standard information. (E) The at least one feature information includes a via information, and the preset standard information includes a via standard information. (F) The at least one feature information includes a pin information, and the preset standard information includes a pin standard information. (G) The at least one feature information includes a line location information, and the preset standard information includes a line location standard information.

8. The image analysis method of claim 7 further includes the following steps: receiving a custom standard information via the input device; and comparing at least one feature information with the custom standard information via the processing device to generate the feasibility analysis information.

9. The image analysis method of claim 7, wherein the feasibility analysis information generated by the processing device is for the circuit layout design before the etching process of the printed circuit board.

10. The image analysis method of claim 7, wherein when the processing device compares the at least one feature information with the preset standard information, the feasibility analysis information generated according to the relevant electrical specifications of the IPC published by the International Electron Industries Connection Association further includes the following steps: outputting the feasibility analysis information to an external device or displaying the feasibility analysis information by means of an output device.

11. The image analysis method of claim 7 further includes the following steps: outputting the feasibility analysis information to an external device or displaying the feasibility analysis information via an output device.

Images