Semiconductor structures and methods for forming the same

Abstract

A self-aligned gate isolation / dicing technique is provided for a multi-gate device. An exemplary multi-gate device includes a first gate having a gate stack surrounding a semiconductor layer. The first gate is disposed between a first gate isolation wall and a second gate isolation wall. The gate stack has a gate dielectric and a gate electrode, and the gate stack has a first sidewall and a second sidewall, the first sidewall being formed by the gate dielectric and the gate electrode. A gate end cap is disposed on the first sidewall. A gate shield is disposed on the gate stack, and a portion of the gate dielectric is disposed between the gate electrode and the gate shield. A gate contact is disposed on the first gate. The gate contact extends on the first gate isolation wall and connects the first gate to a second gate.

Description

Technical Field

[0001] The present invention relates to a structure and a method for forming the same, and more particularly to a semiconductor structure and a method for forming the same. Prior Art

[0002] Multi-gate devices have been introduced to improve gate control and can increase gate-channel coupling, reduce off-state current, mitigate short-channel effects (SCEs), or a combination thereof. One such multi-gate device is a gate-all-around (GAA) device, which includes a gate structure that extends partially or completely around the channel region, providing access to the channel region on at least two sides. GAA devices allow for significant scaling of integrated circuit (IC) technology while maintaining gate control and reducing SCEs, while seamlessly integrating with conventional IC manufacturing flows. However, as GAA device scaling continues, non-self-aligned gate-cutting techniques are often implemented to isolate the gates of different GAA devices from each other, such as the first gate of a first GAA transistor from the second gate of a second GAA transistor. This hinders the dense packaging of devices / semiconductor components required at advanced IC technology nodes. Therefore, while existing GAA devices and their fabrication methods are generally adequate for their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0003] Some embodiments of the present invention provide a semiconductor structure comprising: a semiconductor layer; a first isolation component and a second isolation component; a first gate isolation wall and a second gate isolation wall, wherein the first gate isolation wall is disposed on the first isolation component and the second gate isolation wall is disposed on the second isolation component; a first gate disposed between the first gate isolation wall and the second gate isolation wall, wherein the first gate comprises: a gate stack surrounding the semiconductor layer, wherein the gate stack has a gate dielectric and a gate electrode, the gate stack having a first sidewall and a second sidewall, wherein the first sidewall is formed by the gate dielectric and the gate electrode, and a gate end cap disposed on the first sidewall; a gate cover disposed on the gate stack, wherein a portion of the gate dielectric is disposed between the gate electrode and the gate cover; and a gate contact disposed on the first gate, wherein the gate contact extends over the first gate isolation wall and connects the first gate to the second gate.

[0004] Some other embodiments of the present invention provide a semiconductor structure comprising: a semiconductor layer; a first isolation member and a second isolation member; a first gate isolation wall and a second gate isolation wall, wherein the first gate isolation wall is disposed on the first isolation member and the second gate isolation wall is disposed on the second isolation member; a first gate disposed between the first gate isolation wall and the second gate isolation wall, wherein the first gate comprises: a gate stack surrounding the semiconductor layer, wherein the gate stack has a gate dielectric and a gate electrode, the gate stack having a first sidewall and a second sidewall, wherein the gate stack The first sidewall of the gate stack is formed by a gate dielectric, the second sidewall of the gate stack is formed by a gate electrode, and the first sidewall of the gate stack is in physical contact with the first gate isolation wall, and a gate end cap is arranged on the second sidewall of the gate stack, wherein the gate end cap is between the gate stack and the second gate isolation wall; a gate cover is arranged on the gate stack, wherein a portion of the gate dielectric is arranged between the gate electrode and the gate cover; and a gate contact is arranged on the first gate, wherein the gate contact extends over the first gate isolation wall and connects the first gate to the second gate.

[0005] Still other embodiments of the present invention provide a method for forming a semiconductor structure, comprising: forming a gate dielectric in a gate opening, wherein the gate dielectric surrounds a first semiconductor layer, a second semiconductor layer, a first gate cap on the first semiconductor layer, and a second gate cap on the second semiconductor layer, and the gate dielectric partially fills a first gap between the first semiconductor layer and the first gate cap and a second gap between the second semiconductor layer and the second gate cap; depositing and etching back a gate electrode material to form a first gate electrode and a second gate electrode in the gate opening, wherein the first gate electrode fills a remaining portion of the first gap between the first semiconductor layer and the first gate cap, and the second gate electrode fills a remaining portion of the second semiconductor layer and the second gate cap. The remaining portion of the second gap between the caps, and the first gate electrode and the first portion of the gate dielectric form a first gate stack having a first sidewall, and the second gate electrode and the second portion of the gate dielectric form a second gate stack having a second sidewall; selectively depositing a first gate end cap on the first sidewall of the first gate stack, and selectively depositing a second gate end cap on the second sidewall of the second gate stack; forming a gate isolation wall in the gate opening, which fills the remaining space between the first gate stack and the second gate stack; and forming a gate contact on the first gate electrode and the second gate electrode, wherein the gate contact is disposed on the gate isolation wall and the gate contact is disposed between the first gate cap and the second gate cap. Simple diagram description

[0006] The following details various aspects of the present disclosure, along with accompanying illustrations. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of elements may be arbitrarily increased or decreased to clearly illustrate the features of the present disclosure. FIG. 1 is a flow chart of a method for fabricating a portion or all of a multi-gate device according to various aspects of the present disclosure. According to various aspects of the present disclosure, Figures 2-15 are partial or full views of a multi-gate device at various stages of fabrication (e.g., associated with the method of Figure 1). According to various aspects of the present disclosure, Figures 16A-16C are cross-sectional views of a portion or the entirety of the multi-gate device of Figure 15. FIG. 17 is a cross-sectional view of a portion or the entirety of a multi-gate device according to various aspects of the present disclosure. According to various aspects of the present disclosure, Figures 18-20 are partial or full views of a multi-gate device at a manufacturing stage of forming a gate cap and its inner spacer (e.g., associated with the method of Figure 1). According to various aspects of the present disclosure, Figures 21-25 are partial or full views of another multi-gate device at various stages of fabrication (e.g., associated with the method of Figure 1). According to various aspects of the present disclosure, Figures 26A-26C are cross-sectional views of a portion or the entirety of the multi-gate device of Figure 25. According to various aspects of the present disclosure, Figures 27-31 are views of a portion or the entirety of another multi-gate device at various stages of fabrication (e.g., related to the method of Figure 1). According to various aspects of the present disclosure, Figures 32A-32C are cross-sectional views of a portion or the entirety of the multi-gate device of Figure 31. FIG. 33 is a flow chart of another method for fabricating a portion or all of a multi-gate device according to various aspects of the present disclosure. According to various aspects of the present disclosure, Figures 34-52 are partial or full views of a multi-gate device at various stages of fabrication (e.g., associated with the method of Figure 33). According to various aspects of the present disclosure, Figures 53A-53C are cross-sectional views of part or all of the multi-gate device of Figure 52. According to various aspects of the present disclosure, FIG. 54 is a cross-sectional view of a portion or the entirety of the multi-gate device of FIG. 52 . According to various aspects of the present disclosure, Figures 55-58 are partial or full views of a multi-gate device at a manufacturing stage of forming a gate cap and its inner spacer (e.g., associated with the method of Figure 33). According to various aspects of the present disclosure, Figures 59-64 are partial views of another multi-gate device at various stages of fabrication (e.g., related to the method of Figure 33). According to various aspects of the present disclosure, Figures 65A-65C are cross-sectional views of part or all of the multi-gate device of Figure 64. According to various aspects of the present disclosure, Figures 66A and 66B are cross-sectional views of a portion or the entirety of the multi-gate device of Figure 64, at a manufacturing stage associated with Figure 61 and a manufacturing stage associated with Figure 64, respectively. According to various aspects of the present disclosure, Figures 67-70 are partial or whole views of another multi-gate device at various stages of manufacture (e.g., related to the method of Figure 33). According to various aspects of the present disclosure, Figures 71A-71C are cross-sectional views of part or all of the multi-gate device of Figure 70. According to various aspects of the present disclosure, FIG. 72 is a partial or full view of the multi-gate device of FIG. 52 , wherein trimming processes such as those associated with FIG. 47 are omitted from its manufacture. According to various aspects of the present disclosure, FIG. 73 is a partial or full view of the multi-gate device of FIG. 64 , wherein trimming processes such as those associated with FIG. 47 are omitted from its manufacture. According to various aspects of the present disclosure, FIG. 74 is a partial or full view of the multi-gate device of FIG. 70 , wherein trimming processes such as those associated with FIG. 47 are omitted from its manufacture. Implementation Method

[0007] The present disclosure generally relates to multi-gate devices, and more particularly to metal gate isolation and cutting techniques for multi-gate devices.

[0008] The following provides many different embodiments or examples for implementing various components of the disclosed embodiments. Specific examples of components and configurations are described below to simplify the disclosed embodiments. These are, of course, merely examples and are not intended to limit the disclosed embodiments. For example, references to forming a first component above or on a second component in the following description may include embodiments in which the first and second components are formed in direct contact, as well as embodiments in which an additional component is formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, spatially relative terms such as "lower," "higher," "horizontally," "vertically," "above," "above," "below," "under," "up," "down," "top," "bottom," and their derivatives (e.g., "horizontally," "downwardly," "upwardly," etc.) may be used to facilitate describing the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the drawings. Furthermore, when the terms "approximately," "approximately," and similar terms are used to describe a number or range of numbers, such terms are intended to encompass values ​​that are within a reasonable range of the number being described. For example, a number or range encompasses a reasonable range that includes the number being described, such as within + / - 10% of the number being described based on known manufacturing tolerances associated with manufacturing components having the features associated with the number. For example, a material layer having a thickness of "approximately 5 nm" may encompass a range of dimensions from 4.5 nm (nanometers) to 5.5 nm, where manufacturing tolerances associated with deposited material layers are known to those skilled in the art to be within a + / - 10% range. Furthermore, the presently disclosed embodiments may repeat reference numerals and / or letters in various examples. This repetition is for the purposes of simplicity and clarity and does not in itself imply a specific relationship between the various embodiments and / or configurations discussed.

[0009] An exemplary non-self-aligned gate cut technique may involve forming a mask layer over a gate stack, wherein the mask layer covers a first portion of the gate stack, covers a second portion of the gate stack, and exposes a third portion of the gate stack through an opening formed in the mask layer. The third portion of the gate stack is disposed between the first portion of the gate stack and the second portion of the gate stack. An etching process is then performed to remove the exposed third portion of the gate stack (including, for example, at least one gate electrode layer and at least one gate dielectric layer), thereby forming a gate cut opening between and separating the first portion of the gate stack and the second portion of the gate stack. A gate isolation structure, such as a dielectric layer (e.g., a silicon nitride layer), may then be formed in the gate cut opening to provide electrical isolation between the first portion of the gate stack and the second portion of the gate stack. The first portion may be located above a first channel layer (i.e., a first active device region) of a first GAA device, and the second portion may be located above a second channel layer (i.e., a second active device region) of a second GAA device.

[0010] The spacing between active device regions (e.g., the first and second channel layers) is often intentionally designed to be larger than necessary to compensate for process variations that occur during non-self-aligned gate sawing techniques. For example, etch loading and / or other loading effects can degrade critical dimension uniformity (CDU) across the wafer, causing the width of the opening in the mask layer and / or the gate saw opening to be larger than the target width at some locations. This can lead to unintended exposure and / or damage to the first channel layer, the second channel layer, the first portion of the gate stack, the second portion of the gate stack, or a combination thereof. In another example, overlay shift caused by the lithography process used to form the mask layer can cause the opening in the mask layer to shift left or right from its intended location, which can also lead to unintended exposure and / or damage to the first channel layer, the second channel layer, the first portion of the gate stack, the second portion of the gate stack, or a combination thereof. The need to increase the spacing between active device regions to adequately compensate for such process variations hinders the dense packing of active device regions required for advanced IC technology nodes, thereby undesirably reducing pattern density. The increased spacing between active device regions also results in a larger gate stack area, which in turn leads to higher parasitic capacitance.

[0011] Therefore, the present disclosure proposes various self-aligned gate cut (isolation) techniques for GAA devices, which allow for smaller spacing between active device regions (and therefore smaller cell heights) than required between active device regions using non-self-aligned gate cut techniques. The self-aligned gate cut techniques described in this disclosure reduce the area of ​​gate consumption in the active device region, which can improve GAA device performance, for example, by reducing capacitance. This disclosure describes details of self-aligned gate isolation and cut techniques for multi-gate devices and the resulting multi-gate devices.

[0012] In some embodiments, a self-aligned gate cut technique includes replacing a top semiconductor layer, such as a dielectric layer, of a semiconductor layer stack in a channel region with a hard mask (also referred to as a gate cap), the dielectric layer comprising silicon, nitrogen, carbon, oxygen, or a combination thereof. The self-aligned gate cut technique also includes removing a second semiconductor layer from the semiconductor layer stack in the channel region, such that the first semiconductor layer and the hard mask are suspended above the substrate. A gate dielectric is formed over the first semiconductor layer and the hard mask; a gate electrode is formed over the gate dielectric, wherein the gate dielectric and the gate electrode are formed to provide a gate stack having a first sidewall and a second sidewall formed by the gate dielectric and the gate electrode; a first dielectric wall is formed along the first sidewall of the gate stack and a second dielectric wall is formed along the second sidewall of the gate stack, wherein the hard mask is disposed between the first dielectric wall and the second dielectric wall; and a gate contact is formed over the first dielectric wall, extending through the hard mask to the gate stack. The first dielectric wall can separate the gate stack from another gate stack in the same cell (e.g., a memory cell), and the gate contact can be connected to the other gate stack. The second dielectric wall can separate the gate stack from another gate stack in a different cell. In some embodiments, before forming the first dielectric wall and the second dielectric sidewall, a gate end cap is formed along the first sidewall and / or the second sidewall of the gate stack.

[0013] In some embodiments, a gate cut technique includes replacing a top semiconductor layer, such as a dielectric layer, of a semiconductor layer stack in the channel region with a hard mask (also referred to as a gate cap), the top semiconductor layer comprising silicon, nitrogen, carbon, oxygen, or a combination thereof. The gate cut technique also includes removing a second semiconductor layer of the semiconductor layer stack in the channel region, such that the first semiconductor layer and the hard mask are suspended above the substrate; forming a gate dielectric over the first semiconductor layer and the hard mask; and forming a gate electrode over the gate dielectric. The gate dielectric and gate electrode are formed to provide a gate stack having a first sidewall and a second sidewall, wherein the first sidewall is formed by the gate dielectric and the second sidewall is formed by the gate electrode. A first gate spacer (e.g., a first dielectric wall) is formed along the first sidewall, and a second gate spacer (e.g., a second dielectric wall) is formed along the second sidewall. The first gate spacer is formed before removing the second semiconductor layer, and the second gate spacer is formed after forming the gate electrode. A gate contact may be formed over the first gate spacer, extending through the hard mask to the gate stack. The first gate spacer can separate the gate stack from another gate stack in the same cell (e.g., a memory cell), and the gate contact can connect to the other gate stack. The second gate spacer can separate the gate stack from another gate stack in a different cell. In some embodiments, a gate end cap is formed along the second sidewall of the gate stack before forming the second gate spacer. In some embodiments, the second gate spacer fills the remaining portion of the gate opening. In some embodiments, a gate cut process is performed to form a gate cut opening, and the second gate spacer is formed in the gate cut opening.

[0014] According to various aspects of the present disclosure, FIG. 1 is a flow chart of a method 100 for fabricating a portion or all of a multi-gate device. At step 105, method 100 includes forming a semiconductor layer stack above a semiconductor substrate. The semiconductor layer stack includes a first semiconductor layer, a second semiconductor layer, and a top semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the top semiconductor layer have different compositions. At steps 110 and 115, method 100 includes forming a dummy gate and gate spacers above a first portion of the semiconductor layer stack and forming source / drain recesses in a second portion of the semiconductor layer stack, respectively. At step 120, method 100 includes replacing the top semiconductor layer of the first portion of the semiconductor layer stack with a gate cap. In some embodiments, a portion of the second semiconductor layer of the first portion of the semiconductor layer stack (e.g., a portion below the gate spacer) may be replaced with an inner spacer. The gate cap may be formed before, after, or simultaneously with the inner spacer. At step 125, method 100 includes forming epitaxial source / drain electrodes in the source / drain recesses. In some embodiments, after forming the epitaxial source / drain at step 125 and before performing a gate replacement process (i.e., replacing the dummy gate with a metal gate) as described in the present disclosure, a dielectric layer, such as an interlayer dielectric layer and / or a contact etch stop layer, is formed.

[0015] At step 130, method 100 includes removing the dummy gate to form a gate opening exposing the first portion of the semiconductor layer stack. The gate opening may also expose the gate cap and / or inner spacer. At step 135, method 100 includes removing the second semiconductor layer of the first portion of the semiconductor layer stack, thereby suspending the first semiconductor layer above the semiconductor substrate (e.g., performing a channel release process at step 135). Removing the second semiconductor layer may further suspend the gate cap above the first semiconductor layer. At step 140, method 100 includes forming a gate dielectric in the gate opening above the first semiconductor layer of the first portion of the semiconductor layer stack. The gate dielectric may surround the first semiconductor layer. The gate dielectric may also surround the gate cap. At steps 145 and 150, method 100 includes forming a gate electrode over the gate dielectric in the gate opening and etching back the gate electrode, respectively. A gate stack including a gate dielectric and a gate electrode may surround the first semiconductor layer, and the sidewalls of the gate stack may be formed from both the gate dielectric and the gate electrode. At step 155, method 100 includes selectively forming a gate end cap in the gate opening. The gate end cap is formed on the sidewalls of the gate stack, is disposed on the gate electrode, and may be disposed on the gate dielectric. The gate stack and the gate end cap form a first gate. At step 160, method 100 includes forming a gate spacer that fills the remaining portion of the gate opening. The gate spacer is located between the first gate and the second gate and may electrically isolate the first gate from the second gate. At step 165, method 100 includes forming a gate contact. The gate contact is disposed on the first gate (e.g., its gate electrode). The gate contact may be disposed on the gate end cap. The gate contact extends above the gate spacer and connects the first gate to the second gate (e.g., its gate electrode). The present disclosure contemplates additional processes. Additional steps may be provided before, during, and after method 100, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of method 100. The following discussion illustrates various embodiments of multi-gate-based integrated circuit devices that may be fabricated according to method 100.

[0016] According to various aspects of the present disclosure, Figures 2-15 are partial or full views of a multi-gate device 200 at various stages of fabrication (e.g., in connection with method 100 in Figure 1). For ease of description and understanding, Figures 9-15 are views of the gate structure of the multi-gate device 200 taken along line G-G' in Figure 8 (and are therefore referred to as gate cross-sectional views). According to various aspects of the present disclosure, Figures 16A, 16B, and 16C are partial or full cross-sectional views of the multi-gate device 200 taken along lines AA, BB, and CC (e.g., y- and x-cross-sectional views), respectively, in Figure 15. Figures 2-15 and 16A-16C have been simplified for clarity and to facilitate a better understanding of the inventive concepts of the present disclosure. Additional features may be added to the multi-gate device 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 200.

[0017] As described in the present disclosure, in Figures 2-15, multi-gate device 200 can be processed to form a first transistor in transistor region 202A, a second transistor in transistor region 202B, and a third transistor in transistor region 202C. In some embodiments, the first transistor, the second transistor, the third transistor, or a combination thereof are n-type transistors. In some embodiments, the first transistor, the second transistor, the third transistor, or a combination thereof are p-type transistors. In some embodiments, transistor regions 202A-202C are processed to provide a first multi-gate device in device region 204A and a second multi-gate device in device region 204B. In some embodiments, the first multi-gate device includes an n-type transistor (e.g., a first transistor formed in transistor region 202A) and a p-type transistor (formed in transistor region 202B), and the second multi-gate device includes an n-type transistor (formed in transistor region 202C) and a p-type transistor (formed in a transistor region adjacent to transistor region 202C), such that device region 204A and device region 204B each include a complementary metal oxide semiconductor (CMOS) transistor.

[0018] Referring to FIG. 2 , a fin fabrication process is performed to form fins extending from a substrate (wafer) 206 , such as fin 208A, fin 208B, and fin 208C (also referred to as fin structures, fin elements, etc.) extending from substrate 206 . Fins 208A-208C extend substantially parallel to one another along the x-direction, having a length in the x-direction, a width in the y-direction, and a height in the z-direction. Fins 208A-208C each include a substrate portion and a semiconductor layer stack portion disposed above the substrate portion. The substrate portion includes a mesa 206 ′ (also referred to as a substrate extension, a fin portion of substrate 206 , a substrate fin portion, an etched substrate portion, etc.). The semiconductor layer stack portion includes a semiconductor layer stack 210 comprising semiconductor layers 215 , 220 , and 225 .

[0019] In the depicted embodiment, substrate 206 comprises silicon. Substrate 206 may alternatively or additionally comprise another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In some embodiments, substrate 206 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. Substrate 206 (including plateaus 206' extending therefrom) may include various doped regions, such as a p-type doped region / p-well in the n-type transistor region and an n-type doped region / n-well in the p-type transistor region. The n-well is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopant, or combinations thereof. The p-well is doped with a p-type dopant, such as boron, indium, other p-type dopant, or combinations thereof. In some embodiments, substrate 206 includes doped regions formed using a combination of p-type and n-type dopants. Various doped regions can be formed directly on and / or in substrate 206, for example, to provide a p-well structure, an n-well structure, a dual-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form the various doped regions.

[0020] Each semiconductor layer stack 210 is disposed above a corresponding plateau 206 ′ of substrate 206 and includes a corresponding semiconductor layer 215, a corresponding semiconductor layer 220, and a corresponding semiconductor layer 225. Semiconductor layers 215 and 220 are stacked vertically (e.g., along the z-direction) in a staggered or alternating configuration from the top surface of substrate 206 . The composition of semiconductor layer 215, semiconductor layer 220, and semiconductor layer 225 differ to achieve etch selectivity and / or different oxidation rates during processing. For example, semiconductor layers 215, 220, and 225 may include different materials, composition atomic percentages, composition weight percentages, thicknesses, other characteristics, or combinations thereof to achieve a desired etch selectivity. In the depicted embodiment, semiconductor layer 220 includes silicon, semiconductor layer 215 includes silicon germanium having a first germanium atomic percentage, and semiconductor layer 225 includes silicon germanium having a second germanium atomic percentage. The second germanium atomic percentage is greater than the first germanium atomic percentage. In some embodiments, the second germanium atomic percentage is from about 30% to about 50%, and the first germanium atomic percentage is from about 15% to about 30%. With such a composition, semiconductor layer 215 can have a first etch rate for the etchant, semiconductor layer 220 can have a second etch rate for the etchant, and semiconductor layer 225 can have a third etch rate for the etchant, where the first etch rate, the second etch rate, and the third etch rate are different. In some embodiments, semiconductor layer 220 includes silicon germanium having a third germanium atomic percentage that is different from the first and second germanium atomic percentages. In such embodiments, the second germanium atomic percentage is the largest, and the topmost layer of fins 208A-208C has the highest germanium atomic percentage. In some embodiments, semiconductor layer 215, semiconductor layer 220, semiconductor layer 225, or a combination thereof includes n-type dopants and / or p-type dopants. For example, semiconductor layer 220 in the n-type transistor region can include p-type dopants, and semiconductor layer 220 in the p-type transistor region can include n-type dopants. The present disclosure contemplates semiconductor layers 215, 220, and 225 having any combination of semiconductor materials, including any semiconductor material disclosed herein, that provides a desired etch selectivity and / or desired performance characteristics (eg, a material that maximizes current flow).

[0021] As described further below, semiconductor layer 220 or portions thereof form the channel region of a transistor in multi-gate device 200. In FIG. 2 , each semiconductor layer stack 210 includes four semiconductor layers 215 and three semiconductor layers 220. The semiconductor layer stack 210 thus includes four semiconductor layer pairs disposed above substrate 206, three of which have corresponding semiconductor layers 215 and corresponding semiconductor layers 220, and one of which has corresponding semiconductor layers 215 and corresponding semiconductor layers 225. After processing, this configuration enables multi-gate device 200 to have three channels. However, in some embodiments, semiconductor layer stack 210 includes more or fewer semiconductor layers, depending on, for example, the number of channels desired for multi-gate device 200 and / or the design requirements of multi-gate device 200. For example, semiconductor layer stack 210 and semiconductor layer 215 can each include two to ten semiconductor layers 220. In the depicted embodiment, semiconductor layer 215 has a thickness t1, semiconductor layer 220 has a thickness t2, and semiconductor layer 225 has a thickness t3. Thickness t1, thickness t2, and thickness t3 may be selected based on manufacturing and / or device performance considerations. For example, thickness t1 may be configured to provide a desired distance (or spacing) between adjacent channels of the transistor (e.g., between semiconductor layers 220), thickness t2 may be configured to provide a desired thickness for the channels of the transistor, and thickness t3 may be configured to provide a gate cap of the desired thickness to protect the channels.

[0022] The fabrication of fins 208A-208C may include forming a semiconductor layer stack precursor over substrate 206 and performing a lithography process and / or an etching process to pattern the semiconductor layer stack precursor and / or substrate 206. In some embodiments, forming the semiconductor layer stack precursor includes epitaxially growing semiconductor layers 215 and semiconductor layers 220 in a staggered and alternating configuration over substrate 206, and then epitaxially growing semiconductor layer 225 over the topmost semiconductor layer 215. For example, a first semiconductor layer 215 is epitaxially grown over substrate 206, a first semiconductor layer 220 is epitaxially grown over a first semiconductor layer 215, a second semiconductor layer 215 is epitaxially grown over a first semiconductor layer 220, and so on, until a desired number of semiconductor layers 215 and semiconductor layers 220 of semiconductor layer stack 210 are provided over substrate 206. Semiconductor layer 225 may then be epitaxially grown over the topmost semiconductor layer 215. The epitaxial growth is performed by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof.

[0023] The lithography process may include forming a resist layer on the semiconductor layer stack precursor (e.g., by spin coating), performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the resist layer is exposed to radiation energy (e.g., ultraviolet (UV) light, deep ultraviolet (DUV) light, or extreme ultraviolet (EUV) light), wherein the mask blocks, transmits, and / or reflects the radiation depending on the mask pattern and / or mask type (e.g., a binary mask, a phase-shift mask, or an EUV mask), such that a pattern is projected onto the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiation, exposed portions of the resist layer undergo a chemical change, and depending on the properties of the resist layer and the properties of the developer used in the development process, exposed (or unexposed) portions of the resist layer are dissolved during the development process. After development, the patterned resist layer includes a resist pattern corresponding to the mask. An etching process uses the patterned resist layer as an etch mask to remove portions of the semiconductor layer stack precursor and / or substrate 206. In some embodiments, a patterned resist layer is formed over a mask layer disposed over a semiconductor layer stack precursor. A first etching process removes portions of the mask layer to form a patterned layer (e.g., a patterned hard mask layer). A second etching process uses the patterned layer as an etching mask to remove portions of the semiconductor layer stack precursor and / or substrate 206. The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a reactive ion etching (RIE) process. After etching, the patterned resist layer can be removed, for example, by a resist stripping process or other suitable process.

[0024] In some embodiments, the fins 208A-208C are formed by a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) SADP process, other double patterning processes, or a combination thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof. This process can also provide fins 208A-208C with corresponding semiconductor layer stacks 210 above corresponding mesas 206', as shown in FIG2 . In some embodiments, directed self-assembly (DSA) technology is performed while patterning the semiconductor layer stack precursor. Furthermore, in some embodiments, the exposure process can implement maskless lithography, electron beam (e-beam) writing, ion beam writing, or a combination thereof to pattern the resistive layer.

[0025] Trench 230 is located between fins 208A-208C, and isolation features 235 are formed in trench 230. Isolation features 235 fill the lower portion of trench 230 and surround portions of fins 208A-208C. The portion of fins 208A-208C that extends from the top surface of isolation features 235 may be referred to as the fin active region. Isolation features 235 electrically isolate active device regions and / or passive device regions. For example, isolation features 235 separate and electrically isolate fin 208A from fin 208B, fin 208B from fin 208C, fin 208A from other device regions / components, and fin 208C from other device regions / components. Isolation features 235 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, etc.), or combinations thereof. Isolation features 235 may have a multilayer structure. For example, isolation feature 235 includes a bulk dielectric (e.g., an oxide layer) over a dielectric liner (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbon nitride, or a combination thereof). In another example, isolation feature 235 includes a bulk dielectric over a doped liner, such as a boron silicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner. The dimensions and / or characteristics of isolation feature 235 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or a combination thereof. In FIG. 2 , isolation feature 235 may be STI.

[0026] Isolation features 235 can be formed by depositing a liner (e.g., a dielectric layer) over the multi-gate device 200 that partially fills the trenches 230, depositing an oxide material over the multi-gate device 200 (e.g., over the liner) that fills the remaining portions of the trenches 230, and performing a planarization process. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed until a planarization stop layer, such as the semiconductor layer 225, is reached and exposed. In some embodiments, the planarization process removes the mask layer, any liner, any oxide material, or a combination thereof, located above and / or on the top surfaces of the fins 208A-208C. The remaining portions of the liner and oxide material form the liner and bulk dielectric of the isolation features 235, respectively. The liner can cover the sidewalls of the trenches 230 (formed by the sidewalls of the fins 208A-208C) and the bottom of the trenches 230 (formed by the substrate 206). The liner layer can be formed by atomic layer deposition (ALD), CVD, physical vapor deposition (PVD), high-density plasma CVD (HDPCVD), MOCVD, RPCVD, PECVD, LPCVD, atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), sub-pressure CVD (SACVD), other suitable methods, or combinations thereof. The oxide material can be formed by flow-based CVD (FCVD), high aspect ratio deposition (HARP) processes, HDPCVD, other suitable processes, or combinations thereof. In some embodiments, an annealing process is performed when forming the isolation features 235.

[0027] Isolation features 235 are then recessed and / or etched back, causing fins 208A-208C to protrude from isolation features 235. In FIG. 2 , isolation features 235 are etched back until they are below the semiconductor layer stack 210. In some embodiments, the height of isolation features 235 along the z-direction is less than the height of plateaus 206' along the z-direction (e.g., relative to the top surface of substrate 206). In some embodiments, the etching process selectively removes isolation features 235 relative to semiconductor layer stack 210. For example, the etching process removes isolation features 235 but does not remove or substantially does not remove semiconductor layer 225, semiconductor layer 220, semiconductor layer 215, and plateaus 206'. An etchant can be selected for the etching process that etches dielectric material (e.g., isolation features 235) at a higher rate than the semiconductor material. The etching process can be a dry etch, a wet etch, another suitable etch process, or a combination thereof. In some embodiments, the etching process removes the mask / patterning layer of fins 208A-208C. In some embodiments, the mask / patterned layer serves as an etch mask during the etching process.

[0028] Referring to FIG. 3 , a dummy gate stack 240 is formed over a portion of the fins 208A-208C. The dummy gate stack 240 partially fills the upper portion of the trench 230 . The dummy gate stack 240 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the fins 208A-208C. For example, the dummy gate stack 240 extends along the y-direction and has a length in the y-direction, a width in the x-direction, and a height in the z-direction. The dummy gate stack 240 is disposed over the channel region (C) and between the source / drain regions (S / D). In the YZ plane, the dummy gate stack 240 is disposed on the top and sidewalls of the fins 208A-208C and covers the channel region of the fins 208A-208C. The dummy gate stack 240 is also disposed over the top of the isolation feature 235 . In the XZ plane, the dummy gate stack 240 is disposed above the top of the channel region of the fins 208A- 208C, and the dummy gate stack 240 is disposed between the source / drain regions of the fins 208A- 208C.

[0029] The dummy gate stack 240 includes a dummy gate dielectric 242, a dummy gate electrode 244, and a hard mask 246 (including, for example, a first mask layer 247 and a second mask layer 248). The dummy gate dielectric 242 includes a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. For example, the dummy gate dielectric 242 is an oxide layer. The dummy gate electrode 244 includes a suitable dummy gate material such as polysilicon. In some embodiments, the dummy gate stack 240 includes other layers such as a cap layer, an interface layer, a diffusion layer, a barrier layer, or a combination thereof. The dummy gate stack 240 is formed by a deposition process, a lithography process, an etching process, other suitable processes, or a combination thereof. For example, the dummy gate stack 240 is formed by depositing a dummy gate dielectric layer over the multi-gate device 200, depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing a hard mask layer over the dummy gate electrode layer, and performing a lithography process and an etching process to pattern the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer. The remaining portions of the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer form a dummy gate dielectric 242, a dummy gate electrode 244, and a hard mask 246, respectively, as depicted. The hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer can be deposited by CVD, PVD, ALD, other suitable deposition processes, or combinations thereof.

[0030] 4 , gate spacers 250 are formed along the sidewalls of the dummy gate stack 240 to form a gate structure 255 (collectively, the dummy gate stack 240 and the gate spacer 250). Fin spacers 256 are formed along the sidewalls of the source / drain regions of the fins 208A-208C. Portions of the fins 208A-208C (i.e., the source / drain regions of the fins 208A-208C not covered by the gate structure 255) are at least partially removed to form source / drain recesses (trench) 260. The gate spacer 250 is disposed adjacent to the dummy gate stack 240, and the fin spacers 256 are disposed adjacent to the semiconductor layer stack 210 in the source / drain regions of the fins 208A-208C before removal. The gate spacers 250 and the fin spacers 256 are formed by any suitable process and include a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable dielectric compositions, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbonitride, or combinations thereof). For example, a spacer layer including silicon and nitrogen (e.g., a silicon nitride layer) is deposited over the multi-gate device 200 and etched to form the gate spacers 250 and the fin spacers 256. In some embodiments, the gate spacers 250 and / or the fin spacers 256 have a multi-layer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon carbide. In some embodiments, the gate spacers 250 and / or the fin spacers 256 include more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. In such an embodiment, each set of spacers may have a different composition.

[0031] In the depicted embodiment, the etching process completely removes the semiconductor layer stack 210 in the source / drain regions of the fins 208A-208C, exposing the mesas 206'. The etching process also removes some, but not all, of the mesas 206', allowing the source / drain recesses 260 to extend below the top surface of the isolation features 235. Each source / drain recess 260 has sidewalls formed by the fin spacer 256 and the isolation features 235 thereunder, sidewalls formed by the remaining portion of the semiconductor layer stack 210 in the channel region of a respective one of the fins 208A-208C, and a bottom formed by the respective mesa 206'. In some embodiments, the etching process removes some, but not all, of the semiconductor layer stack 210, and the source / drain recesses 260 have bottoms formed by either the semiconductor layer 215 or the semiconductor layer 220. In some embodiments, the etching process stops at the mesas 206', and the source / drain recesses 260 do not extend below the isolation features 235. The etching process is dry etching, wet etching, other suitable etching methods, or combinations thereof. In some embodiments, the etching process is a multi-step etching process. In some embodiments, the etching process parameters are configured to selectively etch the semiconductor layer stack 210 while minimally or completely etching (i.e., negligibly etching) the gate structure 255 (i.e., the dummy gate stack 240 and the gate spacer 250), the fin spacer 256, the isolation feature 235, or a combination thereof.

[0032] Referring to Figures 5 and 6 , the process includes forming inner spacers 262 below the gate spacer 250 along the sidewalls of the semiconductor layer 215 and forming a gate cap 264 below the gate structure 255 on the semiconductor layer stack 210 (i.e., below the dummy gate stack 240 and the gate spacer 250). The inner spacers 262 separate the semiconductor layers 220 from each other and from the bottom semiconductor layer 220 to the mesa 206 ′, while the gate cap 264 separates the top semiconductor layer 215 from the gate structure 255. The inner spacers 262 replace the portion of the semiconductor layer 215 below the gate spacer 250, and the gate cap 264 replaces the semiconductor layer 225 below the gate structure 255. The inner spacers 262 have a thickness t4, and the gate cap 264 has a thickness t5. Thickness t5 is greater than thickness t4. In some embodiments, thickness t5 is approximately 3 nm to approximately 15 nm. In some embodiments, thickness t4 is approximately 2.5 nm to approximately 14 nm. In some embodiments, thickness t5 is less than or equal to thickness t4. In some embodiments, thickness t5 is thickness t3 and / or thickness t4 is thickness t1.

[0033] Forming the inner spacer 262 and the gate cap 264 may include a first etching process, a deposition process, and a second etching process. For example, in FIG. 5 , the first etching process selectively etches the semiconductor layer 215 and the semiconductor layer 225 while causing only negligible etching of the semiconductor layer 220, the mesa 206 ′, the isolation feature 235 , the dummy gate stack 240 , the gate spacer 250 , the fin spacer 256 , or a combination thereof. The first etching process is also configured to laterally etch (e.g., along the x-direction and / or y-direction) the semiconductor layer 215 and the semiconductor layer 225 to reduce their lengths along the x-direction. Consequently, the first etching process forms a gap 266 between the semiconductor layer 220 , a gap 268 between the mesa 206 ′ and the semiconductor layer 220 , and a gap 270 between the gate structure 255 and the top semiconductor layer 215 . Gaps 266 and 268 are located below gate spacer 250, allowing semiconductor layer 220 to be suspended below gate spacer 250, separated from the adjacent semiconductor layer 220 by gap 266, and separated from the adjacent plateau 206' by gap 268. In some embodiments, gap 266 extends laterally (e.g., along the x-direction) below dummy gate stack 240. Gap 270 is located below gate spacer 250 and dummy gate stack 240, separating top semiconductor layer 215 from gate structure 255 by gap 270.

[0034] Because semiconductor layer 215 and semiconductor layer 225 have different compositions (e.g., different germanium concentrations), the parameters of the first etching process can be configured to completely remove semiconductor layer 225 and partially remove semiconductor layer 215. For example, the etchant of the first etching process removes semiconductor layer 225 (e.g., SiGe with a germanium atomic concentration of approximately 30% to approximately 50%) at a first etching rate and removes semiconductor layer 215 (e.g., SiGe with a germanium atomic concentration of approximately 15% to approximately 30%) at a second etching rate, where the first etching rate is greater than the second etching rate. In such an example, the ratio of the first etching rate to the second etching rate can be adjusted to simultaneously remove semiconductor layer 225 and semiconductor layer 215, but completely remove semiconductor layer 225 while partially removing semiconductor layer 215. The first etching process is a dry etch, a wet etch, another suitable etch, or a combination thereof. In some embodiments, the first etching process is an anisotropic etch with a horizontal etch rate greater than a vertical etch rate (in some embodiments, the vertical etch rate is equal to zero), such that the anisotropic etch primarily removes material in the horizontal direction, while negligible material removal in the vertical direction.

[0035] In FIG6 , a deposition process forms a spacer layer above the multi-gate device 200. A second etching process selectively etches the spacer layer to form inner spacers 262 filling gaps 266 and 268, and gate caps 264 filling gaps 270. Negligible etching of the semiconductor layer 220, the mesa 206′, the isolation feature 235, the dummy gate stack 240, the gate spacers 250, the fin spacers 256, or a combination thereof is performed. To achieve a desired etch selectivity during the second etching process, the spacer layer (and therefore the inner spacers 262 and gate caps 264) has a different composition than the semiconductor layer 220, the mesa 206′, the isolation feature 235, the dummy gate stack 240, the gate spacers 250, the fin spacers 256, or a combination thereof. In some embodiments, the spacer layer comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable dielectric compositions, or combinations thereof. For example, the spacer layer is a silicon nitride layer, a silicon carbonitride layer, a silicon carbon nitride layer, a silicon oxycarbide layer, or a combination thereof. The second etching process is dry etching, wet etching, other suitable etching methods, or a combination thereof.

[0036] The deposition process may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. The deposition process is configured to fill gaps 266, 268, and 270 with a spacer layer. In some embodiments, a single deposition process is performed to form a spacer layer that fills gaps 266, 268, and 270. In some embodiments, gap 270 is wider than gaps 266 and 268 (e.g., semiconductor layer 225 is thicker than semiconductor layer 215), and gaps 266 and 268 may be filled by a deposition process before gap 270. In such embodiments, a first deposition process may be performed to form a first spacer layer that completely fills gaps 266 and 268 and partially fills gap 270, and a second deposition process may be performed to form a second spacer layer that fills the remaining portion of gap 270. Thus, the inner spacer 262 is formed by the first spacer layer, and the gate cap 264 is formed by the first spacer layer and the second spacer layer. The composition and / or material of the first spacer layer may be the same as or different from the composition and / or material of the second spacer layer. In embodiments where the first spacer layer and the second spacer layer have different compositions and / or materials, the gate cap 264 has a multi-layer structure.

[0037] Referring to FIG. 7 , epitaxial source / drain electrodes are formed in the source / drain recesses 260 . For example, semiconductor material is epitaxially grown from the mesa 206 ′, the semiconductor layer 220 , the semiconductor layer 215 , or a combination thereof, thereby forming epitaxial source / drain electrodes 275A in the transistor region 202A, epitaxial source / drain electrodes 275B in the transistor region 202B, and epitaxial source / drain electrodes 275C in the transistor region 202C. The epitaxial source / drain electrodes 275A-275C fill the respective source / drain recesses 260 and, in the depicted embodiment, have portions located between the respective isolation features 235 , between the respective fin spacers 256 , and above the fin spacers 256 . In FIG. 7 , the epitaxial source / drain electrodes 275A-275C are located below the gate cap 264 . For example, the distance between the top of the epitaxial source / drain 275A-275C and the top of the fin spacer 256 (e.g., along the z-direction) is less than the distance between the gate cap 264 (e.g., its bottom) and the top of the fin spacer 256. In the depicted embodiment, the epitaxial source / drain 275A-275C is also located below the top inner spacer 262. For example, the distance between the top of the epitaxial source / drain 275A-275C and the top of the fin spacer 256 is less than the distance between the top of the top inner spacer 262 and the top of the fin spacer 256. Other configurations of the epitaxial source / drain 275A-275C relative to the gate cap 264 and / or the top inner spacer 262 are also contemplated by the present disclosure.

[0038] The epitaxial growth process can utilize CVD deposition techniques (e.g., RPCVD, LPCVD, VPE, UHV-CVD, or combinations thereof), MBE, other suitable epitaxial growth processes, or combinations thereof. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the composition of the mesa 206', semiconductor layer 220, semiconductor layer 215, or combinations thereof. The epitaxial source / drain electrodes 275A-275C can have the same or different compositions and / or materials, depending on the configuration of their respective transistor regions 202A-202C. The epitaxial source / drain electrodes 275A-275C can be doped with n-type dopants and / or p-type dopants. In some embodiments (e.g., when forming part of an n-type transistor), the epitaxial source / drain 275A-275C comprises silicon, which may be doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof (e.g., Si:C epitaxial source / drain, Si:P epitaxial source / drain, or Si:C:P epitaxial source / drain). In some embodiments (e.g., when forming part of a p-type transistor), the epitaxial source / drain 275A-275C comprises silicon germanium or germanium, which may be doped with boron, other p-type dopants, or a combination thereof (e.g., Si:Ge:B epitaxial source / drain). In some embodiments, the epitaxial source / drain 275A-275C comprises more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may comprise the same or different materials and / or the same or different dopant concentrations. In some embodiments, the epitaxial source / drain electrodes 275A-275C include materials and / or dopants that achieve a desired tensile and / or compressive stress in the channel region of the transistor regions 202A-202C. In some embodiments, the epitaxial source / drain electrodes 275A-275C are doped during deposition (i.e., in situ) by adding impurities to the source material of the epitaxial process. In some embodiments, the epitaxial source / drain electrodes 275A-275C are doped by an ion implantation process after the deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing and / or laser annealing) is performed to activate dopants in the epitaxial source / drain electrodes 275A-275C and / or other source / drain regions (e.g., heavily doped source / drain (HDD) regions and / or lightly doped source / drain (LDD) regions). In some embodiments, the epitaxial source / drain electrodes 275A-275C are formed in separate process sequences. For example, when forming the epitaxial source / drain electrodes for n-type transistors in an n-type transistor region, the p-type transistor region is shielded; and when forming the epitaxial source / drain electrodes for p-type transistors in a p-type transistor region, the n-type transistor region is shielded.

[0039] Referring to FIG. 8 , a dielectric layer 280 is formed over the multi-gate device 200. The dielectric layer 280 is disposed over the epitaxial source / drain electrodes 275A-275C. In the YZ plane, the dielectric layer 280 fills the spaces between the epitaxial source / drain electrodes 275A-275C and the spaces between the fin spacers 256. In the XZ plane, the dielectric layer 280 fills the spaces between the gate structure 255 and adjacent components. For example, the dielectric layer 280 may fill the spaces between the gate spacers 250 of the gate structure 255 and the gate spacers of adjacent gate structures. In some embodiments, forming the dielectric layer 280 includes depositing a contact etch stop layer (CESL) 282, depositing an interlayer dielectric (ILD) layer 284 over the CESL 282, and performing a CMP and / or other planarization process until the dummy gate electrode 244 is reached (exposed). The planarization process can remove the hard mask 246 of the dummy gate stack 240 to expose the underlying dummy gate electrode 244, such as a polysilicon dummy gate electrode. The CESL 282 and the ILD layer 284 are formed by CVD, other suitable methods, or a combination thereof. In some embodiments, the ILD layer 284 is formed by FCVD, HARP, HDPCVD, or a combination thereof.

[0040] ILD layer 284 includes a dielectric material such as silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from TEOS, PSG, BSG, BPSG, FSG, xerogel, aerogel, amorphous carbon fluoride, parylene, BCB-based dielectric materials, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layer 284 includes a low-k dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, ILD layer 284 includes a dielectric material having a dielectric constant less than approximately 2.5 (i.e., an extreme low-k (ELK) dielectric material), such as porous silicon dioxide, silicon carbide, a carbon-doped oxide (e.g., a SiCOH-based material, e.g., having Si-CH bonds), or combinations thereof, each of which is tuned / configured to exhibit a dielectric constant less than approximately 2.5. ILD layer 284 may include a multilayer structure including multiple dielectric materials. CESL 282 may include a different material from ILD layer 284, such as a dielectric material different from the dielectric material of ILD layer 284. For example, when ILD layer 284 includes silicon and oxygen including a low-k dielectric material, CESL 282 may include silicon and nitrogen, such as silicon nitride or silicon oxynitride.

[0041] Referring to Figures 9-13 , a gate replacement process is performed to replace the dummy gate stack 240 with a gate in the transistor regions 202A-202C, and a channel release process is performed to form a suspended channel layer in the channel region of the transistor regions 202A-202C. The gate at least partially surrounds the suspended channel layer. For ease of description and understanding, Figures 9-13 are views of the gate structure 255 taken along line G-G' in Figure 8 (hence referred to as gate cross-sectional views). Referring to Figure 9 , a gate opening 285 is formed in the gate structure 255 by removing the dummy gate electrode 244. For example, an etching process removes the dummy gate electrode 244 selectively relative to the dummy gate dielectric 242, the gate spacer 250, the ILD layer 284, the CESL 282, or a combination thereof. In other words, the etching process removes the dummy gate electrode 244 while removing negligible amounts of the dummy gate dielectric 242, gate spacers 250, ILD layer 284, CESL 282, or a combination thereof. For example, an etchant is selected for the etching process that removes polysilicon (i.e., the dummy gate electrode 244) at a higher rate than the dielectric material (i.e., the dummy gate dielectric 242, gate spacers 250, ILD layer 284, CESL 282, etc.) (i.e., the etchant has a high etch selectivity for polysilicon). In the depicted embodiment, the etching process can completely remove the dummy gate electrode 244 and expose the dummy gate dielectric 242. In some embodiments, the etching process can partially or completely remove the dummy gate dielectric 242. The etching process can be a dry etch, a wet etch, another suitable etch, or a combination thereof. In some embodiments, the etching process includes multiple steps. In some embodiments, during the etching process, the patterned mask layer covers the ILD layer 284 , the CESL 282 , the gate spacer 250 , or a combination thereof, and has an opening therein exposing the dummy gate stack 240 .

[0042] Referring to FIG. 10 , the process includes removing the dummy gate dielectric 242 and performing a channel release process to form a suspended channel layer in the channel region of the transistor regions 202A-202C. For example, the etching process selectively removes the dummy gate dielectric 242 relative to the semiconductor layer stack 210, the gate spacers 250, the ILD layer 284, the CESL 282, or a combination thereof. In other words, the etching process removes the dummy gate dielectric 242 while negligibly removing the semiconductor layer stack 210, the gate spacers 250, the ILD layer 284, the CESL 282, or a combination thereof. For example, an etchant is selected for the etching process that removes the dummy gate dielectric 242 at a higher rate than the semiconductor layer stack 210, the gate spacers 250, the ILD layer 284, the CESL 282, or a combination thereof (i.e., the etchant has a high etch rate for interfacial oxide). The etching process may be a dry etch, a wet etch, another suitable etch, or a combination thereof. In some embodiments, the etching process includes multiple steps. In some embodiments, the patterned mask layer used during the removal of the dummy gate electrode 244 can be used during the removal of the dummy gate dielectric 242 and / or during the channel release process described below.

[0043] In FIG. 10 , the semiconductor layer 215 exposed by the gate opening 285 is selectively removed to form gaps / openings 286, 288, and 290, thereby suspending the semiconductor layer 220 above the plateau 206' in the channel region of the transistor regions 202A-202C. Thus, the gate opening 285 extends between the semiconductor layers 220, between the semiconductor layer 220 and the gate cap 264, and between the semiconductor layer 220 and the plateau 206'. Gap 286 is located between the semiconductor layers 220, gap 288 is located between the semiconductor layer 220 and the plateau 206', and gap 290 is located between the semiconductor layer 220 and the gate cap 264. In the depicted embodiment, each channel region has three suspended semiconductor layers 220, hereinafter referred to as channel layers 220'. The channel layer 220' is vertically stacked along the z-direction and provides three channels respectively, through which current can flow between corresponding epitaxial sources / drains 275A-275C.

[0044] In some embodiments, the etching process selectively removes the semiconductor layer 215 while causing negligible removal of the mesa 206', the semiconductor layer 220, the gate cap 264, the inner spacer 262, the gate spacer 250, the dielectric layer 280, or a combination thereof. For example, an etchant is selected for the etching process that etches silicon germanium (i.e., the semiconductor layer 215) at a higher rate than silicon (i.e., the semiconductor layer 220 and the mesa 206') and the dielectric material (i.e., the gate cap 264, the inner spacer 262, the gate spacer 250, the CESL 282, the ILD layer 284, or a combination thereof) (i.e., the etchant has a high etch selectivity for silicon germanium). The etching process is a dry etch, a wet etch, another suitable etch, or a combination thereof. In some embodiments, prior to performing the etching process, an oxidation process converts the semiconductor layer 215 into a silicon germanium oxide feature, and the etching process removes the silicon germanium oxide feature. In some embodiments, the dummy gate dielectric 242 and the semiconductor layer 215 are removed by different etching processes (e.g., a first etch for removing the dummy gate dielectric 242 and a second etch for removing the semiconductor layer 215). In some embodiments, a single etching process is performed to remove the dummy gate dielectric 242 and the semiconductor layer 215 (e.g., using an etchant that can remove both).

[0045] An etching process can be performed to modify the profile of the channel layer 220' to provide a target size and / or target shape. For example, the etching process can provide the channel layer 220' with a cylindrical profile (e.g., a nanowire), a rectangular profile (e.g., a nanorod), a sheet-shaped profile (e.g., a nanosheet (e.g., a dimension in the XY plane that is substantially larger than the dimensions in the XZ and YZ planes to form a sheet-like structure), or any other suitable shape. In some embodiments, the channel layer 220' has nanometer dimensions and may be referred to individually or collectively as a "nanostructure." In some embodiments, the channel layer 220' has sub-nanometer dimensions and / or other suitable dimensions. In the depicted embodiment, the channel layer 220' has dimensions that are smaller than the dimensions of the inner spacer 262 and / or the gate cap 264. In some embodiments, the width of the channel layer 220' (e.g., along the y-direction) is smaller than the width of the inner spacer 262 and / or the gate cap 264 (e.g., along the y-direction). In some embodiments, the thickness of the channel layer 220 ′ (eg, along the z-direction) is smaller than the thickness of the inner spacer 262 and / or the gate cap 264 (eg, along the z-direction).

[0046] Referring to FIG. 11 , a gate dielectric 302 is formed in and partially fills the gate opening 285 . The gate dielectric 302 also partially fills the gaps 286 , 288 , and 290 . The gate dielectric 302 includes dielectric layers, such as an interfacial layer 304 and a high-k dielectric layer 306 . The interfacial layer 304 and the high-k dielectric layer 306 are disposed on the top surface, bottom surface, and sidewalls of the channel layer 220 ′. For example, the gate dielectric 302 surrounds the channel layer 220 ′. The gate dielectric 302 is also disposed over the mesa 206 ′, the isolation feature 235 , the gate spacer 250 , and the gate cap 264 . For example, the interface layer 304 and the high-k dielectric layer 306 encapsulate the mesa 206 ′, the high-k dielectric layer 306 is disposed on the top surface of the isolation feature 235 , the high-k dielectric layer 306 is disposed on the sidewalls of the gate spacer 250 , and the high-k dielectric layer 306 is disposed on the top surface, bottom surface, and sidewalls of the gate cap 264 (e.g., the high-k dielectric layer 306 surrounds the gate cap 264 ).

[0047] The interfacial layer 304 includes a dielectric material such as SiO2, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. The interfacial layer 304 is formed by thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof. For example, the interfacial layer 304 is formed by a chemical oxidation process in which the channel layer 220' and the mesa 206' are exposed to hydrofluoric acid. In another example, the interfacial layer 304 is formed by a thermal oxidation process in which the channel layer 220' and the mesa 206' are exposed to an oxygen environment and / or an air environment. In some embodiments, the interfacial layer 304 is formed on exposed semiconductor surfaces (e.g., the channel layer 220' and the mesa 206'), but not on exposed dielectric surfaces (e.g., the gate cap 264 and the gate spacer 250). In some embodiments, the interfacial layer 304 is formed after the high-k dielectric layer 306 is formed. For example, after forming the high-k dielectric layer 306, the multi-gate device 200 may be annealed in an oxygen environment and / or a nitrogen environment (eg, nitrous oxide).

[0048] High-k dielectric layer 306 includes a high-k dielectric material, which refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k=approximately 3.9). For example, high-k dielectric layer 306 includes HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, a hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. The high-k dielectric layer 306 is formed by ALD, CVD, PVD, an oxidation-based deposition process, other suitable processes, or combinations thereof. For example, the ALD process conformally deposits the high-k dielectric layer 306 such that the thickness of the high-k dielectric layer 306 is substantially uniform (conforms) across all surfaces within the gate opening 285.

[0049] 12 , a gate electrode 308 is formed over the gate dielectric 302 in the gate opening 285. The gate electrode 308 partially fills the gate opening 285 and fills the gap 286, the gap 288, and the remaining portion of the gap 290. For example, each gate electrode 308 includes a portion 308A that fills the remaining portion of the corresponding gap 290, a portion 308B that fills the remaining portion of the corresponding gap 286, and a portion 308C that fills the remaining portion of the corresponding gap 288. In such an embodiment, the gate electrode 308 is disposed along the top and bottom surfaces of the channel layer 220′, the bottom surface of the gate cap 264, and the top surface of the mesa 206′.

[0050] Gate electrode 308 includes a conductive material such as polysilicon, Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other suitable conductive materials, or combinations thereof. Gate electrode 308 can have a single-layer structure or a multi-layer structure. In some embodiments, portions 308A-308C each include a work function layer and a bulk (or filler) layer. The work function layer is a conductive layer tuned to have a desired work function (e.g., an n-type work function or a p-type work function), and the bulk layer is a conductive layer disposed above the work function layer. In some embodiments, the work function layer includes an n-type work function material such as Ti, Ag, Mn, Zr, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer includes a p-type work function material, such as Ru, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The bulk layer may include Al, W, Cu, Ti, Ta, alloys thereof, or combinations thereof. In some embodiments, portions 308A-308C include a diffusion layer and / or a barrier layer, for example, the bulk layer is disposed on the diffusion / barrier layer.

[0051] Forming gate electrode 308 includes depositing a gate electrode material in gate opening 285 that fills the remaining portions of gaps 286, 288, and 290, and etching back the gate electrode material such that the remaining portions of the gate electrode material form portions 308A-308C. The gate electrode material may partially or completely fill gate opening 285. In some embodiments, the etch back is an etch process that selectively removes the gate electrode material while negligibly removing the high-k dielectric layer 306, CESL 282, ILD layer 284, or a combination thereof. For example, an etchant is selected for the etch process that removes metal material (i.e., gate electrode material, which may form one or more of portions 308A-308C) at a higher rate than dielectric material (i.e., high-k dielectric layer 306, CESL 282, ILD layer 284, or a combination thereof) (i.e., the etchant has a high etch selectivity to the metal material). In some embodiments, after deposition, the gate electrode material is disposed along the top surface, bottom surface, and sidewalls of the channel layer 220' and / or the gate cap 264 (i.e., the gate electrode material surrounds the channel layer 220' and / or the gate cap 264), and the etchback removes the gate electrode material from the sidewalls of the channel layer 220', the sidewalls of the gate cap 264, and the top of the gate cap 264. In such embodiments, the etchback exposes the high-k dielectric layer 306 along the sidewalls of the channel layer 220' and / or the sidewalls and / or top of the gate cap 264. In some embodiments, the etching process is configured to stop upon reaching the high-k dielectric layer 306. In some embodiments, the etching process uses the high-k dielectric layer 306 as an etch stop layer. To minimize and / or prevent removal of gate electrode material filling gaps 286, 288, and 290, the etching process may be an anisotropic etch process in which the vertical etch rate is greater than the horizontal etch rate, such that the anisotropic etch removes material substantially in the vertical direction while negligible material removal in the horizontal direction. In some embodiments, the horizontal etch rate may be zero. The etching process may be dry etching, wet etching, other suitable etching methods, or combinations thereof.

[0052] In FIG. 12 , each transistor region 202A-202C has its own gate stack 320. Each gate stack 320 includes its own gate dielectric 302 and its own gate electrode 308. In the depicted embodiment, the high-k dielectric layer 306 spans the transistor regions 202A-202C, such that the gate stacks 320 of the transistor regions 202A-202C share the high-k dielectric layer 306 (which can extend uninterrupted from the transistor region 202A to the transistor region 202C), but have separate, respective interfacial layers 304 and separate, respective gate electrodes 308. Because the gate electrode material is etched back, each gate stack 320 has sidewalls 322 formed by its respective gate dielectric 302 (e.g., its high-k dielectric layer 306) and its respective gate electrode 308. Furthermore, each gate cap 264 is surrounded by a respective portion of the high-k dielectric layer 306. The gate cap 264 and its corresponding surrounding high-k dielectric layer 306 are collectively referred to as a gate cap structure 323. In some embodiments, as depicted, the gate stack 320 is disposed below the gate cap structure 323, and the gate cap structure 323 extends laterally (e.g., along the y-direction) beyond the sidewalls 322 of the gate stack 320. For example, the gate cap structure 323 has overhangs 324 such that a distance (e.g., along the y-direction) exists between the sidewalls of the gate cap structure 323 and the sidewalls 322 of the gate stack 320. In some embodiments, the gate cap structure 323 and the gate stack 320 can have substantially the same width such that the sidewalls of the gate cap structure 323 are aligned with the sidewalls 322 (e.g., along the z-direction).

[0053] The gate stack 320 is configured to achieve the desired functionality according to the design requirements of the multi-gate device 200. Depending on its configuration, the gate stack 320 may have different layers within the transistor regions 202A-202C. For example, the number, configuration, material, or combination of layers of the gate dielectric 302 and / or gate electrode 308 corresponding to the p-type transistor region may differ from the number, configuration, material, or combination of layers of the gate dielectric 302 and / or gate electrode 308 corresponding to the n-type transistor region. In another example, the number, configuration, material, or combination of layers of the gate dielectric 302 and / or gate electrode 308 corresponding to the first n-type transistor region may differ from the number, configuration, material, or combination of layers of the gate dielectric 302 and / or gate electrode 308 corresponding to the second n-type transistor region. In yet another example, the number, configuration, material, or combination thereof of the gate dielectric 302 and / or gate electrode 308 layers corresponding to the first p-type transistor region may be different from the number, configuration, material, or combination thereof of the gate dielectric 302 and / or gate electrode 308 layers corresponding to the second p-type transistor region. The gate stack 320 may include many other layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof.

[0054] Referring to FIG. 13 , a gate end cap 325 is formed in and partially fills the gate opening 285 . In such an embodiment, a gate 328A is provided in the transistor region 202A, a gate 328B is provided in the transistor region 202B, and a gate 328C is provided in the transistor region 202C. Gates 328A-328C each include a corresponding gate stack 320 (e.g., a corresponding gate dielectric 302 and a corresponding gate electrode 308) and a corresponding gate end cap 325 forming its sidewalls. Gates 328A-328C are also referred to as metal gates and / or high-k / metal gates.

[0055] In the multi-gate device 200, a gate cap 325 covers the sidewalls 322 of the gate stack 320, which is formed by the high-k dielectric layer 306 and the gate electrode 308. For example, the gate cap 325 is disposed on the sidewalls of the portions 308A-308C and is physically and / or electrically connected to one or more of the portions 308A-308C. The gate cap 325 is disposed along the sidewalls of the channel layer 220', with the gate dielectric 302 located between the channel layer 220' and the gate cap 325. The gate cap 325 can extend along the sidewalls of the gate cap structure 323 above the gate electrode 308 and can cover the overhanging portion 324 of the gate cap structure 323. In the depicted embodiment, the gate end cap 325 extends along the bottom and sidewalls of the gate cap 264, for example, forming part of the overhang 324 of the gate cap structure 323, and the high-k dielectric layer 306 is located between the gate cap 264 and the gate end cap 325. The gate end cap 325 can extend along the sidewalls of the plateau 206' below the gate electrode 308, as depicted, and the gate dielectric 302 can be located between the plateau 206' and the gate end cap 325. In some embodiments, the gate end cap 325 does not extend above and / or below the gate electrode 308.

[0056] The gate end cap 325 includes tungsten, ruthenium, molybdenum, or other conductive materials optionally formed on the gate electrode 308, alloys thereof, or combinations thereof. For example, the gate end cap 325 is a tungsten layer. In another example, the gate end cap 325 is a ruthenium layer. In yet another example, the gate end cap 325 is a molybdenum layer. The gate end cap 325 has a width w1 along the sidewalls 322 of the gate stack 320 (e.g., along the y-direction). In some embodiments, the width w1 is approximately 4 nm to approximately 10 nm. The width w1 may be the total thickness of the gate end cap 325. In some embodiments, the gate end cap 325 has a width w2 along the sidewalls of the gate cap structure 323 (e.g., along the y-direction). The width w2 is less than the width w1. In some embodiments, the width of the gate end cap 325 along the sidewalls of the mesa 206 ′ is width w2. In some embodiments, the width of the gate end cap 325 along the sidewalls of the mesa 206 ′ is less than the width w1 and different from the width w2.

[0057] The gate cap 325 is formed by a selective deposition process, such as a deposition process configured to selectively grow the gate cap material from a metal surface. The selective deposition process can limit (or prevent) the gate cap material from growing from a dielectric surface. For example, forming the gate cap 325 includes performing selective CVD or selective ALD, wherein parameters of the selective CVD or selective ALD are adjusted to selectively grow a metal material (e.g., tungsten, ruthenium, molybdenum, or alloys thereof) from the portions 308A-308C. The selective CVD or ALD process can be further adjusted to limit (or prevent) the metal material from growing from the high-k dielectric layer 306, the gate spacer 250, and the dielectric layer 280. In the depicted embodiment, the selective deposition process is performed until the metal material grown from the portions 308A-308C merges to form a gate cap 325 that extends continuously along the sidewalls 322 of the gate stack 320, such that the gate cap 325 connects the portions 308A-308C between the channel layers 220'. Deposition parameters may include deposition precursors (e.g., metal precursors and / or reactants), deposition precursor flow rates, deposition temperature, deposition time, deposition pressure, source power, radio frequency (RF) bias, RF bias power, other suitable deposition parameters, or combinations thereof. In some embodiments, a carrier gas is used to deliver the metal precursors and / or reactants. In some embodiments, multiple CVD cycles or ALD cycles are performed to form the gate end cap 325. In some embodiments, the selective deposition process includes multiple deposition / etch cycles, each of which may include depositing and etching back the metal material.

[0058] Referring to FIG. 14 , the process includes a self-aligned metal gate isolation process (also known as a metal gate cut process) that includes forming gate spacers 330 that fill the remaining portion of the gate opening 285. For example, the gate spacers 330 fill the spaces between the gates 328A-328C, and each gate spacer 330 is disposed between the gate end caps 325 of adjacent gates 328A-328C. The gate spacers 330 may also fill the spaces between the gate caps 264, such that each gate spacer 330 is disposed between adjacent gate cap structures 323. In the depicted embodiment, a high-k dielectric layer 306 is disposed between the gate spacers 330 and the gate caps 264, and between the gate spacers 330 and the isolation features 235. The gate spacers 330 may electrically isolate the gates 328A-328C from each other. For example, gate 328A in transistor region 202A is separated and electrically isolated from gate 328B in transistor region 202B by one of the gate spacers 330, and gate 328B in transistor region 202B is separated and electrically isolated from gate 328C in transistor region 202C by the other of the gate spacers 330. In some embodiments, gate 328A and gate 328C may also be isolated from other active regions (e.g., gates of adjacent transistor regions) by their respective gate spacers 330.

[0059] The gate spacer 330 comprises a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable dielectric compositions, or combinations thereof. For example, the gate spacer 330 comprises silicon nitride, silicon carbide nitride, silicon carbon nitride oxide, silicon oxycarbide, or combinations thereof. In the depicted embodiment, the gate spacer 330 is a silicon nitride wall. In some embodiments, the gate cap 264 serves as a planarization stop during the planarization process, and the composition of the gate spacer 330 may differ from that of the gate cap 264. In the depicted embodiment, the gate spacer 330 is formed of a single layer. In some embodiments, the gate spacer 330 may have a multi-layer structure, such as a bulk dielectric layer on one or more dielectric liners.

[0060] The gate spacer 330 has a width w3 (e.g., along the y-direction). In some embodiments, the width w3 is between approximately 5 nm and approximately 100 nm. The gate spacer 330 can be formed by depositing a dielectric material (e.g., silicon nitride) over the multi-gate device 200, filling the remaining portion of the gate opening 285, and performing a planarization process. A planarization process, such as a CMP, is performed until the gate cap 264 is reached and exposed, leaving the top surface of the gate cap 264 free of the high-k dielectric layer 306. In some embodiments, the gate cap 264 can serve as a planarization stop layer. In some embodiments, the planarization process removes any of the dielectric material, the high-k dielectric layer 306, the ILD layer 284, the CESL 282, the gate spacer 250, or a combination thereof, disposed above and / or on the top surface of the gate cap 264. The remaining portion of the dielectric material forms the gate spacer 330. Because the fabrication of gates 328A-328C includes etching back the gate electrode 308 and the gate end cap 325, the gate spacers 330 may have a T-shaped profile, as depicted. In such an embodiment, the width of the gate spacers 330 between the gate cap structures 323 is greater than the width of the gate spacers 330 between the gate end caps 325. The dielectric material is formed by CVD, FCVD, HDPCVD, MOCVD, RPCVD, PECVD, APCVD, SAVCD, other suitable deposition processes, or combinations thereof.

[0061] The metal gate cutting process is referred to as "self-aligned" because the gate spacers 330 are aligned between the gates 328A-328C without requiring a lithography process after forming the gates 328A-328C. The self-aligned placement of the gate spacers 330 provides electrical isolation between devices in adjacent active regions, such as the transistors formed in the transistor regions 202A-202C. The self-aligned placement of the gate spacers 330 also allows for higher packaging density without negatively impacting the operation of closely spaced devices in high-density ICs. For example, the spacing S between the active regions of the transistor regions 202A-202C and / or the active regions of the device regions 204A and 204B can be smaller (e.g., smaller than about 5 nm to about 10 nm) than the spacing required between adjacent active regions when implementing non-self-aligned metal gate cutting techniques, such as those using lithography to form gate isolation structures between gates. In some embodiments, the spacing S is from about 5 nm to about 100 nm. Smaller spacing between active regions is possible because the described self-aligned metal gate cutting technique does not suffer from the overlay issues associated with non-self-aligned metal gate cutting techniques. Thus, smaller spacing between active regions can be achieved without the risk of unintended damage to the channel layer 220' and / or gates 328A-328C, such as may be caused by process variations inherent in non-self-aligned metal gate cutting techniques. Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

[0062] 15 and 16A-16C , the process may include forming a dielectric layer 340 (e.g., CESL and ILD layers) similar to dielectric layer 280 over the multi-gate device 200 and forming device layer contacts in the dielectric layer 340. The device layer contacts may include metal-to-poly (MP) contacts, such as gate contact 350A and gate contact 350B, and metal-to-device (MD) contacts, such as source / drain contact 355. A gate contact 350A is disposed on top of the gate stack 320 (e.g., portion 308A thereof and gate end cap 325) of gates 328A and 328B. Gate contact 350A is disposed between the gate cap 264 covering gates 328A and 328B, and gate contact 350A is disposed on top of the gate spacer 330 between gates 328A and 328B. A gate contact 350B is disposed on top of the gate stack 320 (e.g., portion 308A thereof and gate end cap 325) of gate 328C. Gate contact 350B is disposed adjacent to the gate cap 264 covering gate 328C, and gate contact 350B is disposed on top of the gate spacer 330 between gate 328C and adjacent device regions and / or device features. Gate contact 350A can physically and / or electrically connect gate 328A and gate 328B, and gate contact 350B can physically and / or electrically connect gate 328C and the gate of an adjacent transistor region. Source / drain contacts 355 are disposed on corresponding epitaxial source / drain electrodes 275B and between corresponding portions of CESL 382.

[0063] Gate contacts 350A and 350B include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, a low-resistance metal composition, alloys thereof, or combinations thereof. In the depicted embodiment, gate contacts 350A and 350B include tungsten, ruthenium, cobalt, alloys thereof, or combinations thereof. For example, gate contacts 350A and / or gate contacts 350B may be tungsten contacts, ruthenium contacts, or cobalt contacts. In some embodiments, gate contacts 350A, 350B, and gate end cap 325 include different materials. In some embodiments, gate contacts 350A, 350B, and gate end cap 325 include the same material. For example, gate end cap 325 may be a tungsten layer, and gate contacts 350A and 350B may be tungsten contacts. In another example, the gate end cap 325 can be a ruthenium layer, and the gate contacts 350A and 350B can be ruthenium contacts. In some embodiments, the gate contacts 350A and / or 350B do not have a barrier. For example, the gate contacts 350A and / or 350B can include metal plugs that physically contact the gate electrode 308, the gate end cap 325, the gate spacer 330, the gate cap 264, the dielectric layer 340, other adjacent dielectric layers, or a combination thereof. In some embodiments, the gate contacts 350A and / or 350B include metal plugs disposed above a diffusion / barrier layer. The diffusion / barrier layer can include a material that promotes adhesion between the metal plug and adjacent dielectric materials (e.g., the dielectric layer 340, the gate cap 264, the gate spacer 330, etc.) and / or a material that prevents diffusion of metal components from the metal plug into the adjacent dielectric material. In some embodiments, the diffusion / barrier layer includes tantalum, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, tantalum carbide, titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, other suitable materials, or combinations thereof. In some embodiments, the diffusion / barrier layer can have a multilayer structure, such as a first sublayer and a second sublayer.

[0064] In some embodiments, forming the gate contact 350 may include forming a patterned mask layer over the dielectric layer 340, wherein the patterned mask layer has a first opening and a second opening. The first opening overlaps a portion of the gate 328A, a portion of the gate 328B, and the gate spacer 330 therebetween, and the second opening overlaps a portion of the gate 328C and the gate spacer 330 adjacent thereto. An etching process using the patterned mask layer as an etching mask may be performed to form the first gate contact opening and the second gate contact opening. The first gate contact opening exposes a portion of the gate 328A, a portion of the gate 328B, and the gate spacer 330 therebetween, and the second gate contact opening exposes a portion of the gate 328C and the gate spacer 330 adjacent thereto. The etching process selectively removes dielectric material (e.g., dielectric layer 340, gate cap 264, high-k dielectric layer 306, gate spacers 330, or a combination thereof) exposed by the first and second openings of the patterned mask layer, while negligibly removing metal material (e.g., gate electrode 308, gate end cap 325, or a combination thereof). In some embodiments, the etching process is configured to stop upon reaching and / or exposing the gate electrode 308 and / or gate end cap 325. The etching process is a dry etch, a wet etch, another suitable etch, or a combination thereof. One or more deposition processes (e.g., CVD, ALD, PVD, etc.) may then be performed to form gate contact material (e.g., one or more conductive layers) over the dielectric layer 340, filling the first and second gate contact openings. CMP and / or other planarization processes may be performed to remove excess gate contact material, such as gate contact material above the top surface of the dielectric layer 340. The remaining portions of the contact material filling the first and second gate contact openings may provide gate contacts 350A and 350B, respectively.

[0065] The source / drain contacts 355 can be formed in a manner similar to the gate contacts 350A and 350B. For example, forming the source / drain contacts 355 can include forming a patterned mask layer over the dielectric layer 340, wherein the patterned mask layer has an opening that overlaps the epitaxial source / drain (e.g., epitaxial source / drain 275B); selectively removing the dielectric material (e.g., dielectric layer 340 and / or dielectric layer 284) exposed by the opening of the patterned mask layer, while negligibly removing the semiconductor material (e.g., epitaxial source / drain 275B), to form a source / drain contact opening that exposes the epitaxial source / drain; depositing one or more source / drain contact materials on the dielectric layer 340 to fill the source / drain contact opening; and performing a planarization process to remove excess source / drain contact material. In some embodiments, a silicide layer is formed over the epitaxial source / drain electrodes 275A-275C. For example, the silicide layer is formed by depositing a metal layer in the source / drain contact openings over the epitaxial source / drain electrodes (e.g., epitaxial source / drain 275B) and heating the multi-gate device 200 to react the composition of the epitaxial source / drain electrodes with the metal composition of the metal layer. In some embodiments, the silicide layer includes a metal composition (e.g., nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof) and the composition of the epitaxial source / drain electrodes 275A-275C (e.g., silicon and / or germanium).

[0066] Dielectric layer 280, dielectric layer 340, MD contacts (e.g., source / drain contacts 355), and MP contacts (e.g., gate contacts 350A and gate contacts 350B) can form part of a multilayer interconnect (MLI) component. The device-layer contacts can electrically and / or physically connect the electrically active regions of multi-gate device 200 (e.g., gates 328A-328C and / or epitaxial source / drain electrodes 275A-275C) to the metallization layers of the MLI device. The MLI component electrically couples various devices (e.g., p-type transistors and / or n-type transistors, resistors, capacitors, inductors, or combinations thereof) and / or components (e.g., gate electrodes and / or epitaxial source / drain electrodes) to enable the various devices and / or components to operate as specified by design requirements. The MLI component includes a combination of dielectric layers and conductive layers (e.g., metal layers) that combine to form various interconnect structures. For example, the conductive layers form vertical interconnects, such as device-level contacts and / or vias, and / or horizontal interconnects, such as conductive lines. The vertical interconnects can connect horizontal interconnects in different levels (or layers) of the MLI component. During operation, the interconnects route signals between devices and / or components of the multi-gate device 200 and / or distribute signals (e.g., clock signals, voltage signals, ground signals, etc.) to the devices and / or components.

[0067] In some embodiments, dielectric layer 280 is the bottommost layer of the MLI component (e.g., dielectric layer 280 is ILD0 and dielectric layer 340 is ILD1). The process can continue to form additional components of the MLI component, such as metallization layers (hierarchies) of the MLI component, such as a first metallization layer (i.e., a metal one (M1) layer and a via zero (V1) layer), a second metallization layer (i.e., a metal two (M2) layer and a via one (V2) layer), ..., to a topmost metallization layer above the first metallization layer (i.e., a metal X (MX) layer and a via X (VX) layer, where X is the total number of metallization layers of the MLI component). Each metallization layer includes a patterned metal line layer and a patterned via layer configured to provide an interconnect structure disposed in an insulating layer. The patterned metal line layer and the patterned metal via layer are formed by any suitable process, including various dual damascene processes, and include any suitable materials and / or layers.

[0068] In Figures 15 and 16A-16C, multi-gate device 200 includes transistors. For example, transistors in transistor region 202A include corresponding channel layers 220', epitaxial source / drain electrodes 275A, and gate electrodes 328A; transistors in transistor region 202B include corresponding channel layers 220', epitaxial source / drain electrodes 275B, and gate electrodes 328B; and transistors in transistor region 202C include corresponding channel layers 220', epitaxial source / drain electrodes 275C, and gate electrodes 328C. The transistors in transistor regions 202A and 202B are electrically connected via gate contacts 350A, which physically and / or electrically connect gate electrodes 328A and 328B. The transistors in transistor region 202C can be electrically connected to another transistor and / or device via gate contacts 350B. The gate spacers 330 separate and isolate the transistors in the transistor regions 202A- 202C, such as the gates 328A- 328C thereof, and the gates 328A- 328C are each disposed between corresponding gate spacers 330 .

[0069] Each gate (e.g., gate 328B) is disposed along the x-direction between a corresponding epitaxial source / drain (e.g., epitaxial source / drain 275B), and an inner spacer 262 is disposed between each gate and its corresponding epitaxial source / drain. Furthermore, each gate (e.g., gate 328B) is bonded to a corresponding channel layer (e.g., channel layer 220' in transistor region 202B), and the channel layer extends along the x-direction between the corresponding epitaxial source / drain (e.g., epitaxial source / drain 275B). Each gate (e.g., gate 328B) surrounds its corresponding channel layer. In the YZ plane, each gate has a gate dielectric surrounding its corresponding channel layer (e.g., gate dielectric 302 of gate 328B), gate electrodes disposed along the top and bottom of its respective channel layer (e.g., gate electrode 308 of gate 328B), and a gate end cap (e.g., gate end cap 325 of gate 328B) along the sidewalls of its respective channel layer, the sidewalls of its respective gate electrode, and the sidewalls of its respective gate dielectric. In the XZ plane, each gate has a high-k dielectric layer surrounding the gate dielectric of its respective gate electrode (e.g., high-k dielectric layer 306 of gate 328B), and an interfacial layer disposed between the high-k dielectric layer and its corresponding channel layer (e.g., interfacial layer 304 of gate 328B). In addition, each gate (e.g., gate 328B) has a gate cap (e.g., gate cap 264) disposed thereon, wherein the gate cap is disposed above the top of the corresponding gate electrode (e.g., portion 308A of gate 328B) and between the respective gate end caps. Portions of the gate dielectric (e.g., high-k dielectric layer 306 of gate 328B) wrap around the corners of the gate cap, are disposed between the gate cap and the top of the corresponding gate electrode, are disposed between the gate cap and the corresponding gate end cap, and are disposed between the gate cap and the corresponding gate spacer 330.

[0070] Each gate 328A-328C has a sidewall S1 and a sidewall S2 formed by a corresponding gate endcap 325. In such an embodiment, the two sidewalls 322 of each gate stack 320 are separated from the corresponding gate spacer 330 by the corresponding gate endcap 325. Gate contacts 350A and 350B extend over the sidewall S1 of the gates 328A-328C and physically contact the gate endcaps 325, with each gate spacer 330 disposed between a corresponding pair of gate endcaps 325. In the depicted embodiment, the sidewalls S1 and S2 are generally straight, and the gate endcaps 325 have a rectangular profile / shape. In some embodiments, as shown in FIG. 17 , the sidewalls S1 and S2 are wavy, and the gate endcaps 325 have a scalloped profile / shape. In such an embodiment, the gate endcap 325 has a curved segment that intersects the gate spacer 330. Due to deposition / growth variations in the selective deposition process, different sidewall profiles, such as wavy sidewalls, may occur.

[0071] In Figures 2-15 and 16A-16C, gate cap 264 is formed simultaneously with inner spacer 262. For example, gate cap 264 and inner spacer 262 are formed by selectively etching semiconductor layer 225 and semiconductor layer 215 to form gaps 266, 268, and 270 (Figure 5); depositing one or more dielectric layers to fill gaps 266, 268, and 270 (Figure 6); and selectively etching the one or more dielectric layers so that the remaining portions of the one or more dielectric layers form gate cap 264 and inner spacer 262 (Figure 6). In some embodiments, gate cap 264 can be formed before or after inner spacer 262. For example, instead of forming gate cap 264 and inner spacer 262 as depicted and described with reference to Figures 5 and 6, gate cap 264 can be formed before inner spacer 262, as depicted and described with reference to Figures 18-21.

[0072] According to various aspects of the present disclosure, Figures 18-21 are partial views of the multi-gate device 200 at various stages of fabrication associated with forming the gate cap 264 and the inner spacer 262. In such an embodiment, the multi-gate device 200 has already undergone the processes associated with Figures 2-4 (Figure 18), the multi-gate device 200 has undergone processes to form the gate cap 264 (Figures 18 and 19), the multi-gate device 200 has undergone processes to form the inner spacer 262 (Figures 20 and 21), and the multi-gate device 200 may undergo the processes associated with Figures 7-15 after forming the gate cap 264 and the inner spacer 262. The process may include selectively etching the semiconductor layer 225 to form a gap 270 ( FIG. 18 ); depositing one or more dielectric layers on the multi-gate device 200 to fill the gap 270 ( FIG. 19 ); and selectively etching the one or more dielectric layers so that the remaining portions of the one or more dielectric layers form a gate cap 264 ( FIG. 19 ). Subsequently, the process may include selectively etching the semiconductor layer 215 to form gaps 266 and 268 ( FIG. 20 ); depositing one or more dielectric layers on the multi-gate device 200 to fill the gaps 266 and 268 ( FIG. 21 ); and selectively etching the one or more dielectric layers so that the remaining portions of the one or more dielectric layers form an inner spacer 262 ( FIG. 21 ). In some embodiments, the composition of the gate cap 264 is different from the composition of the inner spacer 262. In some embodiments, the processes associated with Figures 20 and 21 may be performed before the processes associated with Figures 18 and 19 to form the gate cap 264 after the inner spacer 262. In such embodiments, the multi-gate device 200 includes the semiconductor layer 225 when the inner spacer 262 is formed, and the inner spacer 262 when the gate cap 264 is formed. For clarity, Figures 18-21 have been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to the multi-gate device 200 of Figures 18-21, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 200 of Figures 18-21.

[0073] In Figures 2-15 and 16A-16C, the gate end cap 325 forms two sidewalls of the gates 328A-328C in a y-sectional view (e.g., in the YZ plane). In some embodiments, the gate end cap 325 may form one sidewall of the gates 328A-328C in a y-sectional view, rather than two, as depicted and described with reference to Figures 22-25. According to various aspects of the present disclosure, Figures 22-25 are partial views of a multi-gate device 400 at various stages of fabrication (e.g., stages associated with method 100 of Figure 1). According to various aspects of the present disclosure, Figures 26A, 26B, and 26C are partial or full cross-sectional views (e.g., y-sectional and x-sectional views) of the multi-gate device 400, respectively, along lines AA, BB, and CC of Figure 25. The fabrication of the multi-gate device 400 is similar in many respects to the fabrication of the multi-gate device 200. For example, in FIG. 22 , a multi-gate device 400 has undergone the processes associated with FIGS. 2-12 to form a gate stack 320 having sidewalls 322 in the transistor regions 202A-202C. The gate stack 320 is located around the corresponding channel layer 220′ and between the corresponding epitaxial source / drain electrodes 275A-275C. In FIG. 22-25 , instead of forming gate end caps 325 on both sidewalls 322 of the gate stack 320, the process may include forming a patterned mask layer 829 over the multi-gate device 400 that covers some sidewalls 322 while exposing other sidewalls 322 of the gate stack 320 ( FIG. 22 ); and forming the gate end caps 325 on the exposed sidewalls 322 of the gate stack 320 in a manner similar to that described above with reference to FIG. 13 (e.g., to allow for merging) ( FIG. 23 ). The patterned mask layer 829 ( FIG. 24 ) is selectively removed by any suitable process. Gate spacers 330 are formed between gates 328A-328C, filling the remaining portions of gate openings 285 ( FIG. 24 ), in a manner similar to that described above with reference to FIG. 14 . Gate contacts, such as gate contacts 350A and gate contacts 350B, are formed to gates 328A-328C ( FIG. 25 ) in a manner similar to that described above with reference to FIG. 15 . For clarity, FIG. 22-25 and FIG. 26A-26C have been simplified to facilitate a better understanding of the concepts disclosed herein. Additional features may be added to the multi-gate device 400 , and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 400 .

[0074] In FIG. 22 , a patterned mask layer 829 covers one sidewall 322 of each gate stack 320 , leaving each gate stack 320 with an exposed sidewall 322. In FIG. 23 , a corresponding gate endcap 325 is selectively formed on the exposed sidewall 322. Thus, in FIG. 25 and FIG. 26A-26C , each gate 328A-328C has a sidewall S9 formed by its respective gate stack 320 and a sidewall S10 formed by its respective gate endcap 325. In such an embodiment, one sidewall 322 of each gate stack 320 physically contacts its respective gate endcap 325, while the other sidewall 322 of each gate stack 320 is separated from the corresponding gate spacer 330 by the respective gate endcap 325. In the depicted embodiment, the sidewall S10 is substantially straight, such as described with reference to FIG. 15 and FIG. 16A-16C . The gate endcap 325 has a rectangular profile / shape. In some embodiments, the sidewall S10 is corrugated, such as depicted and described with reference to FIG. 17 , and the gate end cap 325 has a scalloped profile / shape.

[0075] Furthermore, in the multi-gate device 400, the gate contacts 350A and 350B extend over the sidewalls S9 of the gates 328A-328C (i.e., the sidewalls 322 of the gate stack 320 that physically contact the gate spacers 330) and do not extend over and / or physically contact the gate end caps 325. The gate contact 350A is disposed on top of the gate electrodes 308 (e.g., portion 308A thereof) of the gates 328A and 328B, the gate contact 350A is disposed on top of the gate spacer 330 between the gates 328A and 328B, the gate contact 350A is disposed between the gate caps 264, the gate caps 264 covering the tops of the gate electrodes 308 of the gates 328A and 328B, and the high-k dielectric layer 306 is disposed between the gate caps 264 and the tops of the gate electrodes 308.

[0076] In some embodiments, the process is configured to form the gate end cap 325 on the gate stack 320 and on the opposite sidewalls as depicted, such that the gate end cap 325 is instead formed on the sidewall 322 of the gate stack 320, with the gate contacts 350A and 350B extending thereover. In such embodiments, the gate contacts 350A and 350B extend over and / or physically contact the gate end cap 325, the gate spacer 330 between the transistor regions 202A and 202B is separated from the sidewall 322 of the gate stack 320 of gates 328A and 328B by the gate end cap 325, and the gate spacer 330 between the transistor regions 202B and 202C physically contacts the sidewall 322 of the gate stack 320 of gates 328B and 328C.

[0077] In Figures 2-15 and 16A-16C, the gate end caps 325 also extend continuously along the sidewalls of the gate stack 320. In some embodiments, one or both of the gate end caps 325 may be segmented, such as depicted and described with reference to Figures 27-31. According to various aspects of the present disclosure, Figures 27-31 are partial views of a multi-gate device 500 at various stages of fabrication (e.g., in connection with method 100 of Figure 1). According to various aspects of the present disclosure, Figures 32A, 32B, and 32C are partial or full cross-sectional views (e.g., y- and x-sectional views) of the multi-gate device 500, respectively, taken along lines AA, BB, and CC of Figure 31. The fabrication of the multi-gate device 500 is similar in many respects to the fabrication of the multi-gate device 200. For example, in FIG. 27 , the multi-gate device 500 has undergone the processes associated with FIG. 2-12 to form gate stacks 320 having sidewalls 322 in the transistor regions 202A-202C. The gate stacks 320 are located around the corresponding channel layer 220′ and between the corresponding epitaxial source / drain electrodes 275A-275C. In FIG. 27-31 , instead of forming gate endcaps 325 on both sidewalls 322 of the gate stacks 320, the multi-gate device 500 is processed to provide gates 328A-328C having segmented gate endcaps 325-1 and unsegmented gate endcaps 325-2. The process may include performing a first selective deposition process to selectively form gate end cap segments 325A-325C (collectively referred to as segmented gate end caps 325-1) on sidewalls 322 of the gate stack 320 (e.g., on sidewalls of portions 308A-308C of the gate electrode) ( FIG. 27 ); forming a patterned mask layer 510 over the multi-gate device 500, which covers some sidewalls 322 of the gate stack 320 and the segmented gate end caps 325-1 thereon while exposing other sidewalls 322 of the gate stack 320 and the segmented gate end caps 325-1 thereon ( FIG. 28 ); performing a second selective deposition process to merge the exposed sidewalls 322 of the gate stack 320 and the segmented gate end caps 325-1 thereon ( FIG. 29 ); The exposed gate end cap segments 325A-325C are formed to form an unsegmented gate end cap 325-2 on the exposed sidewalls 322 of the gate stack 320 ( FIG. 29 ); the patterned mask layer 510 is selectively removed by any suitable process ( FIG. 30 ); gate spacers 330 are formed between the gates 328A-328C, filling the remaining portion of the gate opening 285 ( FIG. 30 ), in a manner similar to that described with reference to FIG. 14 ; and gate contacts, such as gate contact 350A and gate contact 350B, are formed to the gates 328A-328C ( FIG. 31 ), in a manner similar to that described with reference to FIG. 15 . For clarity, FIG. 27-31 and FIG. 32A-32C have been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to the multi-gate device 500, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 500.

[0078] In FIG. 27 , a first selective deposition process ( FIG. 27 ) is configured to selectively form and / or grow gate cap material from metal surfaces. The first selective deposition process can limit (or prevent) the formation and / or growth of gate cap material from dielectric surfaces, such as high-k dielectric layer 306 , gate spacer 250 , and dielectric layer 280 . The first selective deposition process can be selective CVD or selective ALD, with parameters adjusted to selectively form a metal material (e.g., tungsten, ruthenium, molybdenum, alloys thereof, or combinations thereof) on the sidewalls of portions 308A-308C. The parameters of the first selective deposition process can be adjusted to partially cover the sidewalls of portions 308A-308C with the corresponding metal material without merging, such that the corresponding material portions provide gate cap segments 325A-325C having a width w4 (e.g., along the y-direction). In some embodiments, width w4 is approximately 4 nm to approximately 10 nm. In some embodiments, such as depicted, the first selective deposition process is performed until the corresponding metal material portion extends laterally above the gate dielectric portion of sidewall 322 (e.g., the portion formed by high-k dielectric layer 306). The top metal material portion (e.g., formed on the sidewall of portion 308A) can extend laterally above the sidewall of gate cap structure 323. The bottom metal material portion (e.g., formed on the sidewall of portion 308C) can extend laterally above the sidewall of mesa 206'. In some embodiments, the corresponding metal material portion does not extend laterally above the gate dielectric portion of sidewall 322. In some embodiments, the corresponding metal material portion partially covers the sidewalls of portions 308A-308C, but does not completely cover the sidewalls of portions 308A-308C, as depicted.

[0079] In FIG. 29 , a second selective deposition process is configured to selectively form and / or grow gate cap material from metal surfaces. The second selective deposition process can limit (or prevent) the formation and / or growth of gate cap material from dielectric surfaces, such as the high-k dielectric layer 306 , the gate spacer 250 , and the dielectric layer 280 . The second selective deposition process can be a selective CVD or selective ALD process, with parameters adjusted to selectively form a metal material (e.g., tungsten, ruthenium, molybdenum, alloys thereof, or combinations thereof) on the gate cap segments 325A- 325C. The second selective deposition process can be performed until the metal material formed on and / or grown from the gate cap segments 325A- 325C merges to form an unsegmented gate cap 325-2 that extends continuously along the sidewalls 322 of the gate stack 320 . Gate end cap 325-2 connects portions 308A-308C between channel layer 220' on one side of gate stack 320. Gate end cap 325-2 has a width w5 (e.g., along the y-direction) that is greater than width w4. In some embodiments, width w5 is approximately 4 nm to approximately 10 nm. In some embodiments, an etch-back process may be performed to reduce width w5 so that width w5 is approximately width w4.

[0080] In FIG. 28 , a patterned mask layer 510 covers one sidewall 322 of each gate stack 320 (and the gate endcap segments 325A-325C thereon), leaving each gate stack 320 with an exposed sidewall 322 and the gate endcap segments 325A-325C thereon. These segments merge during the second selective deposition process to form the corresponding gate endcap 325-2 in FIG. Therefore, in FIG. 31 and FIG. 32A-32C , each gate 328A-328C has a sidewall S5 and a sidewall S6. Sidewall S5 is formed by the corresponding segmented gate endcap 325-1 and its corresponding gate stack 320 (specifically, its high-k dielectric layer 306). Sidewall S6 is formed by the corresponding unsegmented gate endcap 325-2. In such an embodiment, the gate dielectric portion of one sidewall 322 of each gate stack 320 (e.g., formed by its high-k dielectric layer 306) physically contacts the corresponding gate spacer 330, while the gate electrode portion of one sidewall 322 of each gate stack 320 (e.g., formed by its gate electrode 308) is separated from the corresponding gate spacer 330 by the corresponding segmented gate endcap 325-1. Furthermore, the other sidewall 322 of each gate stack 320 is separated from the corresponding gate spacer 330 by the corresponding gate endcap 325-2. In some embodiments, the gate spacers 330 can fill the space between the gate endcap segments 325A-325C, such that portions of the gate spacers 330 are located between adjacent gate endcap segments 325A-325C. In the depicted embodiment, the sidewall S6 is generally straight, such as described with reference to FIGS. 15 and 16A-16C, and the gate endcap 325-2 has a rectangular profile / shape. Furthermore, the gate end cap segments 325A-325C have substantially straight sidewalls, resulting in the gate end cap segments 325A-325C and / or the gate end cap 325-1 having a rectangular profile / shape. In some embodiments, the sidewall S6 is wavy, such as depicted and described with reference to FIG. 17 , and the gate end cap 325-2 has a scalloped profile / shape. In some embodiments, the gate end cap segments 325A-325C have curved sidewalls that intersect the gate spacer 330, resulting in the gate end cap segments 325A-325C and / or the gate end cap 325-1 having a scalloped profile / shape.

[0081] In Figures 31 and 32A-32C, gates 328A-328C have a π-gate (pi-gate) portion formed by portions 308A-308C and gate end cap segments 325A-325C. For example, gate 328A has a π-gate portion formed by its corresponding portion 308A and its corresponding gate end cap segment 325A, a π-gate portion formed by its corresponding portion 308B and its corresponding gate end cap segment 325B, and a π-gate portion formed by its corresponding portion 308C and its corresponding gate end cap segment 325C. Gate end cap segments 325A-325C can extend laterally from the sidewalls of the channel layer 220' by a distance d1 (e.g., along the y-direction) and vertically by a distance d2 (e.g., along the z-direction) to overlap the sidewalls of the channel layer 220'. Distance d1 is located between the sidewalls of the channel layer 220' and the surfaces of the gate endcap segments 325A-325C forming the sidewalls S5 (and / or between the sidewalls of the channel layer 220' and the sidewalls of the gate spacers 330). Distance d2 is located between the top (or bottom) of the channel layer 220' and the ends of the gate endcap segments 325A-325C. In some embodiments, distance d1 is approximately 1 nm to approximately 6 nm. In some embodiments, distance d2 is approximately 0.1 nm to approximately 2.5 nm. The first selective deposition process can be adjusted to achieve a desired lateral extension and / or desired vertical extension of the π gate portion (specifically, its gate endcap segments 325A-325C) relative to the channel layer 220'. The π gate portion can improve short channel effect (SCE) control of the transistors in the transistor regions 202A-202C and / or the multi-gate device 400.

[0082] In Figures 31 and 32A-32C, gate contacts 350A and 350B extend over sidewalls S5 of gates 328A-328C. In such embodiments, gate contacts 350A and 350B extend over and / or physically contact gate end cap 325-1 (specifically, gate end cap segment 325A thereof) on one sidewall of gate stack 320. The gate contact 350A is disposed on top of the electrodes 308 (e.g., portion 308A thereof) of the gates 328A and 328B, the gate contact 350A is disposed on top of the gate spacer 330 between the gates 328A and 328B, the gate contact 350A is disposed between the gate caps 264 covering the tops of the gate electrodes 308 of the gates 328A and 328B, and the high-k dielectric layer 306 is disposed between the gate caps 264 and the tops of the gate electrodes 308. A gate contact 350B is disposed on top of the gate electrode 308 (e.g., portion 308A thereof) of the gate 328C. The gate contact 350B is disposed on top of the gate spacer 330 between the gate 328C and another device region / feature. The gate contact 350B is disposed adjacent to the gate cap structure 323 (e.g., the gate cap 264 and the high-k dielectric layer 306) covering the top of the gate electrode 308 of the gate 328C, and the high-k dielectric layer 306 is disposed between the gate cap 264 and the top of the gate electrode 308 of the gate 328C.

[0083] In some embodiments, compared to what is shown, the process is configured to form the gate end cap 325-1 and the gate end cap 325-2 on opposite sidewalls of the gate stack 320, such that the gate end cap 325-2 is instead formed on the sidewall 322 of the gate stack 320, with the gate contact 350A and the gate contact 350B extending thereon. In such embodiments, gate contacts 350A and 350B extend over and / or physically contact gate cap 325-2, gate spacers 330 between transistor regions 220A and 220B are separated from sidewalls 322 of gate stacks 320 for gates 328A and 328B by gate cap 325-2, and gate spacers 330 between transistor regions 220B and 220C physically contact gate dielectric portions of sidewalls 322 of gate stacks 320 for gates 328B and 328C. In some embodiments, gate cap segment 325A is configured to partially cover sidewalls of portion 308A in a manner that provides spacing between gate cap segment 325A and gate contacts (e.g., gate contacts 350A and / or gate contacts 350B). In such an embodiment, the gate spacer 330 may fill the space between the gate end cap segment 325A and the gate contact.

[0084] Patterned mask layer 829 ( FIG. 22 ) and patterned mask layer 510 ( FIG. 28 ) may include any suitable patterning material and be formed by any suitable process. In some embodiments, patterned mask layer 829 and / or patterned mask layer 510 may be formed by: depositing a hard mask material (e.g., silicon nitride) over multi-gate device 400; forming a patterned layer over the hard mask material (e.g., by a lithography process and / or an etching process), wherein the patterned layer has openings exposing portions of the hard mask material; selectively removing the exposed portions of the hard mask material; and selectively removing the patterned layer. The remaining portions of the hard mask material form a patterned hard mask layer (e.g., a patterned silicon nitride layer), such as patterned mask layer 829 and / or patterned mask layer 510. In some embodiments, the composition of the patterned mask layer 829 and / or the patterned mask layer 510 is configured to limit and / or prevent growth thereon during the selective deposition process used to form the gate end cap. In some embodiments, the composition of the patterned mask layer 829 and / or the patterned mask layer 510 is different from the composition of the high-k dielectric layer 306 and the composition of the gate end caps (e.g., gate end cap 325, gate end cap 325-1, gate end cap 325-2, etc.) to facilitate selective removal of the patterned mask layer 829 and / or the patterned mask layer 510 relative to the high-k dielectric layer 306 and the gate end cap. In other words, the composition can be configured to ensure minimal or no removal of the high-k dielectric layer 306 and / or the gate end cap when the patterned mask layer is removed.

[0085] Referring to FIG. 33 , FIG. 33 is a flow chart of a method 600 for fabricating a portion or all of a multi-gate device, according to various aspects of the present disclosure. At step 605 , method 600 includes forming a semiconductor layer stack above a semiconductor substrate. The semiconductor layer stack includes a first semiconductor layer, a second semiconductor layer, and a top semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the top semiconductor layer have different compositions. At step 610 , method 600 includes forming a dummy gate and a gate spacer above a first portion of the semiconductor layer stack. The dummy gate may include a dummy gate electrode layer and a dummy gate dielectric layer. At step 615 , method 600 includes forming a source / drain recess in a second portion of the semiconductor layer stack. At step 620 , method 600 includes replacing the top semiconductor layer of the first portion of the semiconductor layer stack with a gate cap. In some embodiments, a portion of the second semiconductor layer of the first portion of the semiconductor layer stack (e.g., a portion below the gate spacer) may be replaced with an inner spacer. The gate cap may be formed before, after, or simultaneously with the inner spacer. At step 625, method 600 includes forming epitaxial source / drain electrodes in the source / drain trenches. In some embodiments, after forming the epitaxial source / drain electrodes, and before performing a gate replacement process (i.e., replacing the dummy gates with metal gates), a dielectric layer (e.g., an interlayer dielectric layer and / or a contact etch stop layer) is formed, as described herein.

[0086] At step 630, method 600 includes removing the dummy gate electrode layer of the dummy gate, which may expose the dummy gate dielectric layer of the dummy gate and / or a first portion of the semiconductor layer stack. The gate opening may also expose the gate cap and / or inner spacer. At step 635, method 600 includes forming a first gate spacer in the gate opening in the intra-cell region. The intra-cell region may be located between adjacent gates that will be electrically connected to each other, such as gates of the same device, the same device region, the same cell (e.g., a logic cell or a memory cell), or a combination thereof. The first gate spacer partially fills the gate opening. At step 640, method 600 includes optionally trimming the dummy gate dielectric layer. At step 645, method 600 includes removing the second semiconductor layer of the first portion of the semiconductor layer stack, thereby suspending the first semiconductor layer above the semiconductor substrate (e.g., performing a channel release process at step 645). Removing the second semiconductor layer may further suspend the gate cap above the first semiconductor layer. At step 650, method 600 includes forming a gate dielectric in a gate opening above a first semiconductor layer in a first portion of the semiconductor layer stack. The gate dielectric may surround the first semiconductor layer. The gate dielectric may also surround a gate cap. The gate dielectric partially fills the gate opening. In some embodiments, a dummy gate dielectric layer and / or a portion thereof (e.g., after trimming) may form a portion of the gate dielectric.

[0087] Method 600 then includes filling the remaining portion of the gate opening by either process A (which includes steps 655A, 660A, and 665A) or process B (which includes steps 655B, 658, 660B, and 665B). In process A, at step 655A, method 600 includes forming a gate electrode on the gate dielectric that partially fills the gate opening. Step 655A may include depositing a gate electrode layer that fills the remaining portion of the gate opening, then etching back the gate electrode layer, which reopens a portion of the gate opening. A gate stack including a gate dielectric and a gate electrode may surround the first semiconductor layer, and the sidewalls of the gate stack may be formed by both the gate dielectric and the gate electrode. At step 660A, method 600 includes selectively forming a gate cap in the gate opening. The gate cap is formed on the sidewalls of the gate stack, is disposed on the gate electrode, and may be disposed on the gate dielectric. The gate stack and gate end cap form a first gate. At step 665A, method 600 includes forming a second gate spacer in a boundary region that fills the remaining portion of the gate opening. The boundary region can be located between adjacent gates that are not electrically connected to each other, such as gates of different devices, different device regions, different cells, or a combination thereof. The second gate spacer is located between the first gate and the second gate and can electrically isolate the first gate from the second gate. In some embodiments, the second gate spacer and the first gate spacer are configured differently (e.g., a different number of layers and / or different materials). In some embodiments, the second gate spacer and the first gate spacer are configured the same (e.g., the same number of layers and / or the same material).

[0088] In process B, at step 655B, method 600 includes forming a gate electrode over the gate dielectric, filling the remaining portion of the gate opening. Step 655B may include depositing a gate electrode layer filling the remaining portion of the gate opening and performing a planarization process. A gate stack including the gate dielectric and the gate electrode may surround the first semiconductor layer, and the sidewalls of the gate stack may be formed by both the gate dielectric and the gate electrode. At step 658, method 600 includes forming a gate cut opening in the gate electrode. The gate cut opening may be formed within a portion of the gate electrode disposed in the boundary region. At step 660B, method 600 includes selectively forming a gate end cap in the gate cut opening. The gate end cap is formed on the sidewalls of the gate stack, and the gate end cap is disposed on the gate electrode. The gate stack and the gate end cap form a first gate. At step 665B, method 600 includes forming a second gate spacer in the boundary region, filling the remaining portion of the gate cut opening. The second gate isolation wall is located between the first gate and the second gate and can electrically isolate the first gate from the second gate.

[0089] At step 670, method 600 includes forming a gate contact. The gate contact is disposed on the first gate (e.g., its gate electrode). The gate contact can be disposed on a gate end cap. The gate contact can extend above the first gate isolation wall and connect the first gate to the third gate (e.g., its gate electrode). Additional processes are contemplated by this disclosure. Additional steps may be provided before, during, and after method 600, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of method 600. The following discussion illustrates various embodiments of multi-gate-based integrated circuit devices that can be fabricated according to method 600.

[0090] According to various aspects of the present disclosure, Figures 34-52 are partial or full views of a multi-gate device 700 at various stages of fabrication (e.g., in connection with method 600 in Figure 33 ). For ease of description and understanding, Figures 41-52 are views of the gate structure of multi-gate device 700 taken along line G-G' in Figure 40 (and are therefore referred to as gate cross-sectional views). According to various aspects of the present disclosure, Figures 53A, 53B, and 53C are partial or full cross-sectional views of multi-gate device 700 taken along lines AA, BB, and CC (e.g., y- and x-sectional views), respectively, in Figure 52 . Figures 34-52 and 53A-53C have been simplified for clarity to facilitate a better understanding of the inventive concepts of the present disclosure. Furthermore, device 700 and its method of fabrication 600 are similar in some respects to device 200 and its method of fabrication 100 , such as described above with reference to Figures 1, 2-20, and 21A-21C. Therefore, for clarity and simplicity, similar features in Figures 34-52 and Figures 2-20 are identified by the same reference numerals. Additional features may be added to the multi-gate device 700, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 700.

[0091] As described in the present disclosure, in Figures 34-52, a multi-gate device 700 can be processed to form a first transistor in transistor region 202A, a second transistor in transistor region 202B, and a third transistor in transistor region 202C. In some embodiments, the first transistor, the second transistor, the third transistor, or a combination thereof are n-type transistors. In some embodiments, the first transistor, the second transistor, the third transistor, or a combination thereof are p-type transistors. In some embodiments, the multi-gate device 700 has a device region 204A and a device region 204B. Device region 204A includes transistor region 202A and transistor region 202B, and device region 204B includes transistor region 202C. In some embodiments, transistor regions 202A-202C are processed to provide a first multi-gate device and a second multi-gate device in device region 204A and device region 204B, respectively. In some embodiments, the first multi-gate device includes an n-type transistor (e.g., formed in transistor region 202A) and a p-type transistor (formed in transistor region 202B), and the second multi-gate device includes an n-type transistor (formed in transistor region 202C) and a p-type transistor (formed in a transistor region adjacent to transistor region 202C), such that device region 204A and device region 204B each include a complementary metal oxide semiconductor (CMOS) transistor.

[0092] Referring to FIG. 34 , a fin fabrication process is performed to form fins extending from a substrate, such as fin 208A, fin 208B, and fin 208C, extending from substrate 206 , as described above with reference to FIG. Fins 208A-208C each include a portion of a semiconductor layer stack (e.g., semiconductor layer 215 , semiconductor layer 220 , and semiconductor layer 225 ) disposed above a portion of a substrate (e.g., plateau 206 ′). In multi-gate device 700 , as further described below, a first transistor region in transistor region 202A is electrically connected to (e.g., has its gate connected to) a second transistor in transistor region 202B, and a third transistor in transistor region 202C is not electrically connected to either the first transistor or the second transistor. In such an embodiment, the first and second transistors may form part of a device in device region 204A, while the third transistor may form part of a device in device region 204B. Multi-gate device 700 also includes intra-cell region 228A, which is the region between adjacent interconnected devices, and boundary region 228B, which is the region between adjacent unconnected devices. In the depicted embodiment, the first transistor, the second transistor, and the third transistor are each located between a corresponding intra-cell region 228A and a corresponding boundary region 228B. In some embodiments, when the corresponding intra-cell region 228A is located between the third and fourth transistors in adjacent transistor regions, and the corresponding boundary region 228B is located between the first and fifth transistors in adjacent transistor regions, the third transistor can be electrically connected to the fourth transistor, while the first transistor can be electrically disconnected from the fifth transistor. In some embodiments, the fourth transistor and its corresponding transistor region can form part of a device in device region 204B.

[0093] Referring to FIG. 35 , a dummy gate stack 240 is formed over portions of the fins 208A-208C, such as described above with reference to FIG. The dummy gate stack 240 includes a dummy gate dielectric 242, a dummy gate electrode 244, and a hard mask 246 (including, for example, a first mask layer 247 and a second mask layer 248). Referring to FIG. 36 , gate spacers 250 are formed along the sidewalls of the dummy gate stack 240 to form a gate structure 255. Fin spacers 256 are formed along the sidewalls of the source / drain regions of the fins 208A-208C, and portions of the fins 208A-208C (i.e., their source / drain regions) are at least partially removed to form source / drain recesses (trench) 260, such as described above with reference to FIG. 4 .

[0094] With reference to Figures 37 and 38 , the process includes forming inner spacers 262 below the gate spacer 250 along the sidewalls of the semiconductor layer 215 and forming a gate cap 264 below the gate structure 255, such as described above with reference to Figures 5 and 6 . With reference to Figure 39 , epitaxial source / drain electrodes 275A-275C are formed in the source / drain recesses 260, such as described above with reference to Figure 7 . With reference to Figure 40 , a dielectric layer 280 (e.g., including CESL 282 and ILD layer 284) is formed in the multi-gate device 700, such as described above with reference to Figure 8 . With reference to Figures 41-51 , a gate replacement process is performed to replace the dummy gate stack 240 with the gates in the transistor regions 202A-202C, and a channel release process is performed to form a suspended channel layer in the channel region of the transistor regions 202A-202C. The gate at least partially surrounds the suspended channel layer. For ease of description and understanding, Figures 41-51 are taken along line GG' in Figure 40 through the gate structure 255 (and are therefore referred to as gate cross-sectional views). Referring to Figure 41 , a gate opening 285 is formed in the gate structure 255 by removing the dummy gate electrode 244, such as described above with reference to Figure 9 .

[0095] Referring to Figures 42-45 , gate spacers 710 are formed in the intra-cell region 228A above the isolation features 235. Each gate spacer 710 includes an isolation liner 712 and a body isolation layer 714, with the body isolation layer 714 disposed above the isolation liner 712. In Figure 42 , an isolation layer 712' is formed above the multi-gate device 700 and partially fills the gate opening 285. The isolation layer 712' covers the dummy gate dielectric 242 and the gate spacer 250. In the intra-cell region 228A and the boundary region 228B, the isolation layer 712' forms the sidewalls of the gate spacers 710 along portions of the sidewalls of the fins 208A-208C, and forms the bottom of the gate spacers 710 along portions of the tops of the isolation features 235. In some embodiments, the isolation layer 712' is formed by an ALD process. In some embodiments, isolation layer 712' has a substantially uniform thickness across all surfaces of multi-gate device 700. In some embodiments, isolation layer 712' is formed by CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, APCVD, SAVCD, other suitable methods, or combinations thereof. In the depicted embodiment, isolation layer 712' comprises a nitrogen-containing dielectric material, such as a dielectric material comprising nitrogen in combination with silicon, carbon, oxygen, or a combination thereof. For example, isolation layer 712' comprises silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof. In some embodiments, isolation layer 712' comprises a carbon-containing dielectric material, such as a dielectric material comprising carbon in combination with silicon, nitrogen, oxygen, or a combination thereof. For example, isolation layer 712' comprises silicon carbide (SiC), silicon oxycarbide (SiOC), or a combination thereof. In some embodiments, the isolation layer 712' includes n-type dopants and / or p-type dopants.

[0096] Referring to FIG. 43 , the isolation layer 712′ is removed from the boundary region 228B of the multi-gate device 700. For example, a lithography process such as described herein is performed to form a patterned mask layer 715 within the gate opening 285. The patterned mask layer 715 covers the isolation layer 712′ located in the cell region 228A and exposes the isolation layer 712′ located in the boundary region 228B. In FIG. 43 , the patterned mask layer 715 has an opening 296 therein, which exposes the isolation layer 712′ in the boundary region 228B between the fin 208B and the fin 208C (which overlaps with the interface between the transistor region 202B and the transistor region 202C, and the interface between the device region 204A and the device region), as well as the isolation layer 712′ in the boundary region 228B of the adjacent fin 208A (which may overlap with the interface between the transistor region 202A and the adjacent transistor region to the left of the transistor region 202A). The patterned mask layer 715 includes a first mask portion and a second mask portion, which respectively cover the isolation layer 712' in the intra-cell region 228A between fins 208A and 208B (which overlaps the interface between transistor regions 202A and 202B) and the isolation layer 712' in the cell region 228A adjacent to fin 208C (which may overlap the interface between transistor region 202C and the adjacent transistor region to the right of transistor region 202C). The first mask portion may fill the remaining portion of the opening (e.g., trench 230) between fins 208A and 208B, and the second mask portion may fill the remaining portion of the opening (e.g., trench 230) between fin 208C and an adjacent device component / region (e.g., the adjacent fin to the right of fin 208C). The patterned mask layer 715 may also cover the portion of the isolation layer 712' disposed above the tops of the fins 208A-208C. In the depicted embodiment, the patterned mask layer 715 covers the portion of the isolation layer 712' located over the top of the fin 208A, the portion of the isolation layer 712' located over the top of the fin 208B, and the portion of the isolation layer 712' located over the top of the fin 208C.

[0097] An etching process is then performed to remove the exposed portions of the isolation layer 712', thereby forming an isolation liner 712 extending over the tops of the fins 208A-208C in the intra-cell region 228A. For example, the isolation liner 712 is disposed in the intra-cell region 228A between the fin 208A and the fin 208B and forms the sidewalls and bottom of the gate spacer 710 between the fin 208A and the fin 208B. The isolation liner 712 is also disposed in the intra-cell region 228A between the fin 208C and an adjacent device component / region and forms the sidewalls and bottom of the gate spacer 710 between the fin 208C and the adjacent device component / region. The etching process removes the isolation layer 712' selectively relative to the dummy gate dielectric 242, such that the dummy gate dielectric 242 remains in the boundary region 228B. The etching process can also selectively remove the isolation layer 712' relative to the gate spacers 250, the ILD layer 284, the CESL 282, or a combination thereof. In other words, the etching process removes the isolation layer 712' while negligibly removing the dummy gate dielectric 242, the gate spacers 250, the ILD layer 284, the CESL 282, or a combination thereof. For example, an etchant can be selected for the etching process that removes nitrogen- and / or carbon-containing dielectric materials (i.e., the isolation layer 712') at a higher rate than oxygen-containing dielectric materials (i.e., the dummy gate dielectric 242, the gate spacers 250, the ILD layer 284, the CESL 282, etc.). The etching process can be a dry etch, a wet etch, another suitable etch, or a combination thereof. In some embodiments, the patterned mask layer 715 is configured such that the isolation layer 712 ′ is removed from the tops of the fins 208A- 208C and the isolation liner 712 does not extend over the tops of the fins 208 - 208C.

[0098] Referring to FIG. 44 , the patterned mask layer 715 is removed by a resistive stripping process, an etching process, another suitable process, or a combination thereof. A body isolation material 714′ is then formed within the gate opening 285, filling the remaining portion of the openings between the fins 208A-208C in the intra-cell region 228A (e.g., the trenches 230 therebetween). For example, the body isolation material 714′ may merge along the x-direction and / or the y-direction within the intra-cell region 228A. Because the boundary region 228B lacks the isolation liner 712, the body isolation material 714′ may partially, but not completely, fill the openings between the fins 208A-208C in the boundary region 228B (e.g., the trenches 230 therebetween). In the depicted embodiment, the body isolation material 714′ comprises a nitrogen-containing dielectric material, such as a dielectric material including nitrogen in combination with silicon, carbon, oxygen, or a combination thereof. For example, the body isolation material 714' includes SiN, SiON, SiCN, SiOCN, or a combination thereof. In some embodiments, the body isolation material 714' includes a carbon-containing dielectric material, such as a dielectric material including carbon and a combination of silicon, nitrogen, oxygen, or a combination thereof. For example, the body isolation material 714' includes SiC, SiOC, or a combination thereof. The composition and / or material of the body isolation material 714' can be different from the composition and / or material of the dummy gate dielectric 242 and / or the gate spacer 250, enabling selective removal of the body isolation material 714' relative to the dummy gate dielectric 242 and / or the gate spacer 250. In some embodiments, the composition and / or material of the body isolation material 714' is the same as the composition and / or material of the isolation liner 712. In some embodiments, the composition and / or material of the body isolation material 714' is different from the composition and / or material of the isolation liner 712.

[0099] A deposition process is performed to form a body isolation material 714′ in the gate opening 285, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, APCVD, SAVCD, other suitable methods, or combinations thereof. The deposition process can be configured to form a dielectric material that fills a portion of the gate opening 285 in the intra-cell region 228A and partially fills a portion of the gate opening 285 in the boundary region 228B. In some embodiments, where the isolation liner 712 partially covers the tops of the fins 208A-208C, the body isolation material 714′ can fill a portion of the gate opening 285 above the portion of the fins 208A-208C adjacent to the intra-cell region 228A and partially fill a portion of the gate opening 285 above the fins 208A-208C adjacent to the boundary region 228B, as depicted. A planarization process (e.g., CMP) may be performed to remove the body isolation material 714′ from the top of the gate spacer 250, the CESL 282, the ILD layer 284, or a combination thereof. The gate spacer 250, the CESL 282, the ILD layer 284, or a combination thereof may serve as a planarization stop layer, and the planarization process may be performed until the gate spacer 250, the CESL 282, the ILD layer 284, etc. are exposed.

[0100] 45 , the body isolation material 714′ is removed from the boundary region 228B of the multi-gate device 700, thereby forming a body isolation layer 714 in the intra-cell region 228A, which extends over the tops of the fins 208A-208C. For example, a corresponding body isolation layer 714 is disposed over a corresponding isolation liner 712 in the intra-cell region 228A between the fin 208A and the fin 208B, and a corresponding body isolation layer 714 is disposed over a corresponding isolation liner 712 in the intra-cell region 228A between the fin 208C and an adjacent device component / region. In this embodiment, gate spacers 710 (each including a corresponding body isolation layer 714 encapsulated by a corresponding isolation liner 712) are disposed in the intra-cell region 228A and extend over the tops of the fins 208A-208C. The dummy gate dielectric 242 is disposed between the gate spacer 710 (eg, its isolation liner 712 ) and the fins 208A- 208C, and the dummy gate dielectric 242 is disposed between the gate spacer 710 and the isolation feature 235 .

[0101] In some embodiments, a lithography process and an etching process may be performed to remove the bulk isolation material 714' from the boundary region 228B. The lithography process may be similar to the lithography process performed when removing the isolation layer 712' described above with reference to FIG. 43 . For example, a patterned mask layer may be formed over the multi-gate device 700, covering the bulk isolation material 714' in the intra-cell region 228A and exposing the bulk isolation material 714' in the boundary region 228B. The patterned mask layer may have openings therein, exposing the bulk isolation material 714' in the boundary region 228B between the fin 208B and the fin 208C, as well as in the boundary region 228B adjacent to the fin 208A. The patterned mask layer may include a first mask portion and a second mask portion, each covering the bulk isolation material 714' in the intra-cell region 228A between the fin 208A and the fin 208B, as well as in the intra-cell region 228A adjacent to the fin 208C. The patterned mask layer may also cover portions of the body isolation material 714 ′ disposed over the tops of the fins 208A- 208C.

[0102] The etching process selectively removes the exposed portion of the body isolation material 714' relative to the dummy gate dielectric 242, such that the dummy gate dielectric 242 remains in the boundary region 228B. The etching process may also selectively remove the body isolation material 714' relative to the gate spacer 250, the ILD layer 284, the CESL 282, or a combination thereof. In other words, the etching process removes the body isolation material 714' while negligible removal of the dummy gate dielectric 242, the gate spacer 250, the ILD layer 284, the CESL 282, or a combination thereof. For example, an etchant for the etching process may be selected that removes nitrogen- and / or carbon-containing dielectric materials (i.e., the body isolation material 714') at a higher rate than oxygen-containing dielectric materials (i.e., the dummy gate dielectric 242). The etching process may be a dry etch, a wet etch, another suitable etch, or a combination thereof. In some embodiments, the patterned mask layer is configured such that the body isolation material 714' is removed from the tops of the fins 208A-208C, and the body isolation layer 714 does not extend above the tops of the fins 208-208C. In some embodiments, an etching process (e.g., an etch-back process) is performed without performing a lithography process.

[0103] Referring to FIG. 46 , the process includes removing the dummy gate dielectric 242 and performing a channel release process to form a suspended channel layer in the channel region of the transistor regions 202A-202C. Because the gate spacers 710 cover the dummy gate dielectric 242 in the intra-cell region 228A, the dummy gate dielectric 242 is removed from the boundary region 228B and remains in the intra-cell region 228A. In the depicted embodiment, because a portion of the dummy gate dielectric 242 remains, the semiconductor layer 220 and the gate cap 264 each have sidewalls covered by the dummy gate dielectric 242 and sidewalls not covered by the dummy gate dielectric 242, and the dummy gate dielectric 242 extends over the top of the gate cap 264. The etching process selectively removes the dummy gate dielectric 242 relative to the semiconductor layer stack 210, the gate spacer 250, the gate cap 264, the ILD layer 284, the CESL 282, the gate spacers 710, or a combination thereof. In other words, the etching process removes the dummy gate dielectric 242 while negligibly removing the semiconductor layer stack 210, the gate spacer 250, the gate cap 264, the ILD layer 284, the CESL 282, the gate spacers 710, or a combination thereof. For example, the etchant removes the dummy gate dielectric 242 at a higher rate than the semiconductor layer stack 210, the gate spacers 710, the gate spacer 250, the gate cap 264, the ILD layer 284, the CESL 282, or a combination thereof (i.e., the etchant has a high etch selectivity for an interfacial oxide (e.g., silicon oxide)). The etching process is a dry etch, a wet etch, another suitable etch, or a combination thereof. In some embodiments, the etching process includes multiple steps.

[0104] In FIG. 46 , the semiconductor layer 215 exposed by the gate opening 285 is selectively removed to form gaps / openings 286, 288, and 290, thereby suspending the semiconductor layer 220 above the plateau 206' in the channel region of the transistor regions 202A-202C. Thus, the gate opening 285 extends between the semiconductor layers 220, between the semiconductor layer 220 and the gate cap 264, and between the semiconductor layer 220 and the plateau 206'. Gap 286 is located between the semiconductor layers 220, gap 288 is located between the semiconductor layer 220 and the plateau 206', and gap 290 is located between the semiconductor layer 220 and the gate cap 264. In the depicted embodiment, each channel region has three suspended semiconductor layers 220, hereinafter referred to as channel layers 220'. The channel layer 220' is vertically stacked along the z-direction and provides three channels respectively, through which current can flow between corresponding epitaxial sources / drains 275A-275C.

[0105] In some embodiments, the etching process selectively removes the semiconductor layer 215 while performing negligible removal of the mesa 206', the semiconductor layer 220, the dummy gate dielectric 242, the gate cap 264, the inner spacer 262, the gate spacer 250, the dielectric layer 280, the gate spacer 710, or a combination thereof. For example, an etchant is selected for the etching process that etches silicon germanium (i.e., the semiconductor layer 215) at a higher rate than silicon (i.e., the semiconductor layer 220 and the mesa 206') and the dielectric material (i.e., the dummy gate dielectric 242, the gate cap 264, the inner spacer 262, the gate spacer 250, the CESL 282, the ILD layer 284, the isolation liner 712', the body isolation layer 714, or a combination thereof) (i.e., the etchant has a high etch selectivity for silicon germanium). The etching process can be a dry etch, a wet etch, another suitable etch, or a combination thereof. In some embodiments, before performing the etching process, an oxidation process converts the semiconductor layer 215 into a silicon-germanium oxide feature, and the etching process removes the silicon-germanium oxide feature. In some embodiments, the dummy gate dielectric 242 and the semiconductor layer 215 are removed by different etching processes (e.g., a first etching process for removing the dummy gate dielectric 242 and a second etching process for removing the semiconductor layer 215). In some embodiments, a single etching process is performed to remove the dummy gate dielectric 242 and the semiconductor layer 215 (e.g., using an etchant that can remove both).

[0106] An etching process can be performed to modify the profile of the channel layer 220' to provide a target size and / or target shape. For example, the etching process can provide the channel layer 220' with a cylindrical profile (e.g., a nanowire), a rectangular profile (e.g., a nanorod), a sheet-shaped profile (e.g., a nanosheet (e.g., a dimension in the XY plane that is substantially larger than the dimensions in the XZ and YZ planes to form a sheet-like structure), or any other suitable shape. In some embodiments, the channel layer 220' has nanometer dimensions and may be referred to individually or collectively as a "nanostructure." In some embodiments, the channel layer 220' has sub-nanometer dimensions and / or other suitable dimensions. In the depicted embodiment, the channel layer 220' has dimensions that are smaller than the dimensions of the inner spacer 262 and / or the gate cap 264. In some embodiments, the width of the channel layer 220' (e.g., along the y-direction) is smaller than the width of the inner spacer 262 and / or the gate cap 264 (e.g., along the y-direction). In some embodiments, the thickness of the channel layer 220 ′ (eg, along the z-direction) is smaller than the thickness of the inner spacer 262 and / or the gate cap 264 (eg, along the z-direction).

[0107] Referring to FIG. 47 , a trimming process can be performed on the remaining dummy gate dielectric 242 in the intra-cell region 228A. For example, the trimming process can remove exposed portions of the dummy gate dielectric 242, such as portions along the sidewalls of the gate spacer 710 that are not covered by other device features. In such an example, after trimming, the dummy gate dielectric portion 242A is located between the channel layer 220′ and the gate spacer 710, the dummy gate dielectric portion 242B is located between the isolation feature 235 and the gate spacer 710, and the dummy gate dielectric portion 242C is located between the gate cap 264 and the gate spacer 710, as depicted. In some embodiments, the trimming process recesses the dummy gate dielectric portion 242A from the top and bottom of the channel layer 220', such that the dummy gate dielectric portion 242A partially covers the gate spacer facing the sidewall of the channel layer 220', and the gap 300A is located between the sidewall of the channel layer 220' and the gate spacer 710. In some embodiments, the dummy gate dielectric portion 242A is not recessed from the top and bottom of the channel layer 220', and the dummy gate dielectric portion 242A covers the entire gate spacer facing the sidewall of the channel layer 220'. In some embodiments, the trimming process recesses the dummy gate dielectric portion 242C from the bottom of the gate cap 264 and the sidewalls of the gate spacer 710 disposed above the top of the gate cap 264, such that the dummy gate dielectric portion 242C partially covers the gate spacer facing the sidewall of the gate cap 264, and the gap 300B is located between the sidewall of the gate cap 264 and the gate spacer 710. In some embodiments, the dummy gate dielectric portion 242C is not recessed from the bottom of the gate cap 264 and / or from the sidewalls of the gate spacer 710 disposed above the top of the gate cap 264, and the dummy gate dielectric portion 242C covers the entire gate spacer facing the sidewall of the gate cap 264 and / or the gate spacer 710 does not overhang the dummy gate dielectric portion 242C. The present disclosure contemplates trimming processes that provide various configurations of the dummy gate dielectric portion 242A, the dummy gate dielectric portion 242B, the dummy gate dielectric portion 242C, or combinations thereof.

[0108] The trimming process may be an etching process that selectively removes the dummy gate dielectric 242 relative to the channel layer 220′, the gate spacer 250, the gate cap 264, the ILD layer 284, the CESL 282, the gate spacer 710, or a combination thereof. In other words, the etching process removes the dummy gate dielectric 242 (e.g., a dielectric material including silicon and oxygen) while negligibly removing the channel layer 220′, the gate spacer 250, the gate cap 264, the ILD layer 284, the CESL 282, the gate spacer 710, or a combination thereof (e.g., a semiconductor material and / or a dielectric material including silicon and nitrogen and / or carbon). For example, an etchant is selected for the etching process, which removes the dummy gate dielectric 242 at a higher rate than the channel layer 220', the gate spacer 250, the gate cap 264, the ILD layer 284, the CESL 282, the gate spacer 710, or a combination thereof (i.e., the etchant has a high etch selectivity for an interfacial oxide (e.g., silicon oxide)). The etching process may be dry etching, wet etching, other suitable etching methods, or a combination thereof.

[0109] Referring to FIG. 48 , a gate dielectric 722 is formed in and partially fills the gate opening 285 . The gate dielectric 722 partially fills the gaps 286 , 288 , and 290 . The gate dielectric 722 also fills the gap 300A between the channel layer 220 ′ and the gate spacer 710 , as well as the gap 300B between the gate cap 264 and the gate spacer 710 . The gate dielectric 722 includes dielectric layers, such as an interfacial layer 724 and a high-k dielectric layer 726 . In the depicted embodiment, the gate dielectric 722 includes a dummy gate dielectric portion 242A (i.e., the remaining portion of the dummy gate dielectric). In some embodiments, the gate dielectric 722 includes a dummy gate dielectric portion 242C and / or a dummy gate dielectric portion 242B. The gate dielectric 722 surrounds the channel layer 220' and is disposed above the plateau 206', the isolation feature 235, the gate spacer 250, the gate cap 264, and the gate spacer 710. An interface layer 724 and a high-k dielectric layer 726 are disposed on the top, bottom, and sidewalls of the channel layer 220'. In FIG. 48 , because the dummy gate dielectric portion 242A is formed along the portion of the gate spacer facing the sidewall of the channel layer 220', the interface layer 724 and the high-k dielectric layer 726 encapsulate the channel layer 220'. For example, the interface layer 724 and the high-k dielectric layer 726 are disposed on the top, bottom, and sidewalls of the channel layer 220' facing the boundary region 228B. The interface layer 724 and the high-k dielectric layer 726 are also disposed on the sidewalls of the channel layer 220' facing the intra-cell region 228A. The thickness of the dummy gate dielectric portion 242A may be greater than the thickness of the interface layer 724 and / or the thickness of the high-k dielectric layer 726. Furthermore, the interface layer 724 and the high-k dielectric layer 726 encapsulate the mesa 206', the high-k dielectric layer 726 is disposed on the top surface of the isolation feature 235, the high-k dielectric layer 726 is disposed on the sidewalls of the gate spacer 250, the high-k dielectric layer 726 is disposed on the sidewalls of the gate spacer 710, and the high-k dielectric layer 726 is disposed on the top surface, bottom surface, and sidewalls of the gate cap 264 facing the boundary region 228B (e.g., the high-k dielectric layer 726 encapsulates the gate cap 264).

[0110] The interfacial layer 724 includes a dielectric material such as SiO2, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. The interfacial layer 724 is formed by thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof. For example, the interfacial layer 724 is formed by a chemical oxidation process in which the channel layer 220' and the plateau 206' are exposed to hydrofluoric acid. In another example, the interfacial layer 724 is formed by a thermal oxidation process in which the channel layer 220' and the plateau 206' are exposed to an oxygen environment and / or an air environment. In some embodiments, the interfacial layer 724 is formed on exposed semiconductor surfaces (e.g., the channel layer 220' and the plateau 206'), but not on exposed dielectric surfaces (e.g., the gate cap 264 and gate spacer 250, the gate spacer 710, the isolation feature 235, or combinations thereof). In such embodiments, such as depicted, the interfacial layer 724 is located between the semiconductor surface and the high-k dielectric layer 726, but not between the dielectric surface and the high-k dielectric layer 726. In some embodiments, the interfacial layer 724 is formed after forming the high-k dielectric layer 726. For example, after forming the high-k dielectric layer 726, the multi-gate device 700 can be annealed in an oxygen environment and / or a nitrogen environment (e.g., nitrous oxide).

[0111] High-k dielectric layer 726 includes a high-k dielectric material, which refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k of approximately 3.9). For example, high-k dielectric layer 726 includes HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, a hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. The high-k dielectric layer 726 is formed by ALD, CVD, PVD, an oxidation-based deposition process, other suitable processes, or combinations thereof. For example, the ALD process conformally deposits the high-k dielectric layer 726 such that the thickness of the high-k dielectric layer 726 is substantially uniform (conformal) across all surfaces within the gate opening 285.

[0112] Referring to FIG. 49 , a gate electrode 728 is formed over the gate dielectric 722 in the gate opening 285 . The gate electrode 728 partially fills the gate opening 285 and fills the remaining portions of the gap 286 , gap 288 , and gap 290 . For example, each gate electrode 728 includes a portion 728A that fills the remaining portion of the corresponding gap 290 , a portion 728B that fills the remaining portion of the corresponding gap 286 , and a portion 728C that fills the remaining portion of the corresponding gap 288 . In such an embodiment, the gate electrode 728 is disposed along the top and bottom surfaces of the channel layer 220 ′, the bottom surface of the gate cap 264 , and the top surface of the mesa 206 ′.

[0113] The gate electrode 728 includes a conductive material such as polysilicon, Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other suitable conductive materials, or combinations thereof. The gate electrode 728 can have a single-layer structure or a multi-layer structure. In some embodiments, portions 728A-728C each include a work function layer and a bulk (or filler) layer. The work function layer is a conductive layer adjusted to have a desired work function (e.g., an n-type work function or a p-type work function), and the bulk layer is a conductive layer disposed above the work function layer. In some embodiments, the work function layer includes an n-type work function material such as Ti, Ag, Mn, Zr, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer includes a p-type work function material, such as Ru, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The bulk layer may include Al, W, Cu, Ti, Ta, alloys thereof, or combinations thereof. In some embodiments, portions 728A-728C include a diffusion layer and / or a barrier layer, for example, the bulk layer is disposed on the diffusion / barrier layer.

[0114] Forming gate electrode 728 includes depositing a gate electrode material in gate opening 285 that fills the remaining portions of gaps 286, 288, and 290, and etching back the gate electrode material such that the remaining portions of the gate electrode material form portions 728A-728C. The gate electrode material may partially or completely fill gate opening 285. In some embodiments, the etch back is an etch process that selectively removes the gate electrode material while negligibly removing the high-k dielectric layer 726, gate spacers 710, CESL 282, ILD layer 284, or a combination thereof. For example, an etchant is selected for the etch process that removes metal material (i.e., gate electrode material, which may form one or more of portions 728A-728C) at a higher rate than dielectric material (i.e., high-k dielectric layer 726, gate spacers 710, CESL 282, ILD layer 284, or a combination thereof) (i.e., the etchant has a high etch selectivity for the metal material). In some embodiments, after deposition, the gate electrode material is disposed along the top, bottom, and sidewalls of the channel layer 220' and / or the gate cap 264 that do not face the gate spacer 710 (i.e., the gate electrode material covers the channel layer 220' and / or the gate cap 264), and the etchback removes the gate electrode material from the sidewalls of the channel layer 220', the sidewalls of the gate cap 264, and the top of the gate cap 264. In such embodiments, the etchback exposes the high-k dielectric layer 726 along the sidewalls and / or top of the channel layer 220' and / or the gate cap 264 that do not face the gate spacer 710 (e.g., the sidewalls facing the boundary region 228B). In some embodiments, the etching process is configured to stop upon reaching the high-k dielectric layer 726. In some embodiments, the etching process uses the high-k dielectric layer 726 as an etch stop layer. To minimize and / or prevent removal of gate electrode material filling gaps 286, 288, and 290, the etching process may be an anisotropic etch process in which the vertical etch rate is greater than the horizontal etch rate, such that the anisotropic etch removes material substantially in the vertical direction while negligible material removal in the horizontal direction. In some embodiments, the horizontal etch rate may be zero. The etching process may be dry etching, wet etching, other suitable etching methods, or combinations thereof.

[0115] In FIG. 49 , each transistor region 202A-202C has its own gate stack 730. Each gate stack 730 includes its own gate dielectric 722 and its own gate electrode 728. In the depicted embodiment, the high-k dielectric layer 726 spans the boundary region 228B, so that the gate stacks 730 of the transistor regions at the boundary region 228B (e.g., transistor region 202B and transistor region 202C and / or transistor region 202A and its adjacent transistor region to the left) can share the high-k dielectric layer 726 (e.g., the high-k dielectric layer 726 can extend uninterrupted from transistor region 202B to transistor region 202C), but have separate, respective interface layers 724 and separate, respective gate electrodes 728. Because the gate electrode material is etched back and the gate spacers 710 are formed before removing the dummy gate dielectric 242 and forming the gate stacks 730, each gate stack 730 has a corresponding sidewall 732A and a corresponding sidewall 732B. Sidewall 732A is formed by its corresponding gate dielectric 722 (e.g., its high-k dielectric layer 726) and its corresponding gate electrode 728, and sidewall 732B is formed by its corresponding gate dielectric (e.g., its high-k dielectric layer 726 and the dummy gate dielectric portion 242A). Sidewall 732A faces the corresponding boundary region 228B, and sidewall 732B faces the corresponding intra-cell region 228A (i.e., its gate spacer faces the sidewall).

[0116] Furthermore, each gate cap 264 is surrounded by a dielectric layer, such as a corresponding portion of the high-k dielectric layer 726 and a corresponding dummy gate dielectric portion 242C. The gate caps 264 and their respective surrounding dielectric layers are collectively referred to as a gate cap structure 733. In some embodiments, as depicted, the gate stack 730 is disposed below the gate cap structure 733, and the gate cap structure 733 extends laterally (e.g., in the y-direction) beyond the sidewalls 732A of the gate stack 730. For example, the gate cap structure 733 has an overhang portion 734 such that a distance exists between the sidewalls of the gate cap structure 733 and the sidewalls 732A of the gate stack 730 (e.g., along the y-direction). In some embodiments, the gate cap structure 733 and the gate stack 730 can have substantially the same width, such that the sidewalls of the gate cap structure 733 are aligned with the sidewalls 732A (e.g., along the z-direction).

[0117] The gate stack 730 is configured to achieve the desired functionality based on the design requirements of the multi-gate device 700. Depending on its configuration, the gate stack 730 may have different layers within the transistor regions 202A-202C. For example, the number, configuration, material, or combination of layers of the gate dielectric 722 and / or gate electrode 728 in the p-type transistor region may differ from the number, configuration, material, or combination of layers of the gate dielectric 722 and / or gate electrode 728 in the n-type transistor region. In another example, the number, configuration, material, or combination of layers of the gate dielectric 722 and / or gate electrode 728 in the first n-type transistor region may differ from the number, configuration, material, or combination of layers of the gate dielectric 722 and / or gate electrode 728 in the second n-type transistor region. In yet another example, the number, configuration, material, or combination of layers of the gate dielectric 722 and / or gate electrode 728 of the first p-type transistor region may be different from the number, configuration, material, or combination of layers of the gate dielectric 722 and / or gate electrode 728 of the second p-type transistor region. The gate stack 730 may include many other layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof.

[0118] Referring to FIG. 50 , a gate end cap 325 is formed in and partially fills the gate opening 285 . In such an embodiment, a gate 738A is provided in the transistor region 202A, a gate 738B is provided in the transistor region 202B, and a gate 738C is provided in the transistor region 202C. Gates 738A-738C each include a corresponding gate stack 730 (e.g., a corresponding gate dielectric 722 and a corresponding gate electrode 728) and a corresponding gate end cap 325 forming its sidewalls. Gates 738A-738C are also referred to as metal gates and / or high-k / metal gates.

[0119] In the multi-gate device 700, the gate cap 325 covers the sidewalls 732A of the gate stack 730 and is formed by a high-k dielectric layer 726 and a gate electrode 728. For example, the gate cap 325 is disposed on the sidewalls of portions 728A-728C and is physically and / or electrically connected to one or more of the portions 728A-728C. The gate cap 325 is disposed along the sidewalls of the channel layer 220', with the gate dielectric 722 located between the channel layer 220' and the gate cap 325. The gate cap 325 may extend along the sidewalls of the gate cap structure 733 above the gate electrode 728 and may cover the overhanging portion 734 of the gate cap structure 733. In FIG. 50 , a gate end cap 325 extends along the bottom and sidewalls of the gate cap 264, for example, forming part of the overhang 734 of the gate cap structure 733, and a high-k dielectric layer 726 is located between the gate cap 264 and the gate end cap 325. The gate end cap 325 can extend along the sidewalls of the plateau 206 ′ below the gate electrode 728, as depicted, and the gate dielectric 722 can be located between the plateau 206 ′ and the gate end cap 325. In some embodiments, the gate end cap 325 does not extend above and / or below the gate electrode 728. In some embodiments, the gate end cap 325 does not extend above the gate portion 728A of the gate electrode 728.

[0120] The gate end cap 325 includes tungsten, ruthenium, molybdenum, or other conductive materials that may be selectively formed on the gate electrode 728, alloys thereof, or combinations thereof. For example, the gate end cap 325 is a tungsten layer. In another example, the gate end cap 325 is a ruthenium layer. In yet another example, the gate end cap 325 is a molybdenum layer. The gate end cap 325 has a width w6 along the sidewalls 732A of the gate stack 730 (e.g., along the y-direction). In some embodiments, the width w6 is approximately 4 nm to approximately 10 nm. The width w6 may be the total thickness of the gate end cap 325. In some embodiments, the gate end cap 325 has a width w7 along the sidewalls of the gate cap structure 733 (e.g., along the y-direction). The width w7 is less than the width w6. In some embodiments, the width of the gate end cap 325 along the sidewalls of the mesa 206 ′ is width w7. In some embodiments, the width of the gate end cap 325 along the sidewalls of the mesa 206 ′ is less than the width w6 and different from the width w7.

[0121] The gate cap 325 is formed by a selective deposition process, such as a deposition process configured to selectively grow the gate cap material from a metal surface. The selective deposition process can limit (or prevent) the gate cap material from growing from a dielectric surface. For example, forming the gate cap 325 can include performing selective CVD or selective ALD, where parameters of the selective CVD or selective ALD are adjusted to selectively grow a metal material (e.g., tungsten, ruthenium, molybdenum, or alloys thereof) from portions 728A-728C. The selective CVD or selective ALD can be further adjusted to limit (or prevent) the metal material from growing from the high-k dielectric layer 726, the gate spacer 250, the dielectric layer 280, and the gate spacer 710. In FIG. 50 , a selective deposition process is performed until the metal material grown from portions 728A-728C merges to form a gate end cap 325 extending continuously along the sidewall 732A of the gate stack 730 . The gate end cap 325 connects the portions 728A-728C between the channel layer 220 ′. Because the gate spacer 710 covers the sidewall 732B of the gate stack 730 and / or the sidewall 732B of the gate stack 730 is a dielectric sidewall, in the depicted embodiment, the gate end cap 325 is formed on one sidewall of the gate stack 730 rather than on both sidewalls. Deposition parameters may include deposition precursors (e.g., metal precursors and / or reactants), deposition precursor flow rates, deposition temperature, deposition time, deposition pressure, source power, radio frequency (RF) bias, RF bias power, other suitable deposition parameters, or combinations thereof. In some embodiments, a carrier gas is used to deliver the metal precursors and / or reactants. In some embodiments, multiple CVD cycles or ALD cycles are performed to form the gate end cap 325. In some embodiments, the selective deposition process includes multiple deposition / etch cycles, each cycle may include depositing and etching back the metal material.

[0122] Referring to FIG. 51 , the process includes a self-aligned metal gate isolation process (also referred to as a metal gate cut process) that includes forming gate spacers 330 in the boundary region 228B to fill the remaining portion of the gate opening 285. For example, the gate spacers 330 fill the spaces between the gates 738A-738C, and the gate spacers 330 are disposed between the gate end caps 325 of adjacent gates 738A-738C (e.g., one of the gate spacers 330 is located between the corresponding gate end cap 325 of gate 738B and the corresponding gate end cap 325 of gate 738C). The gate spacers 330 may also fill the spaces between the gate caps 264, such that the gate spacers 330 are disposed between adjacent gate cap structures 733. In the depicted embodiment, a high-k dielectric layer 726 is disposed between the gate spacers 330 and the gate cap 264, and between the gate spacers 330 and the isolation feature 235. The gate spacers 330 can electrically isolate the gates 738A-738C from each other. For example, the gate 738B in the transistor region 202B is separated and electrically isolated from the gate 738C in the transistor region 202C by the corresponding gate spacers 330, and is also separated and electrically isolated from the gate 738A in the transistor region 202A by the corresponding gate spacers 710. The gate 738A in the transistor region 202A can also be separated and electrically isolated from other active regions (e.g., the gates of adjacent transistor regions) by the corresponding gate spacers 330. The gate 738C in the transistor region 202C can also be separated and electrically isolated from other active regions (eg, the gate of an adjacent transistor region) by the corresponding gate isolation wall 710 .

[0123] The gate spacer 330 comprises a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable dielectric compositions, or combinations thereof. For example, the gate spacer 330 comprises silicon nitride, silicon carbide nitride, silicon carbon nitride oxide, silicon oxycarbide, or combinations thereof. In the depicted embodiment, the gate spacer 330 is a silicon nitride wall. In some embodiments, the gate cap 264 serves as a planarization stop during the planarization process, and the composition of the gate spacer 330 may differ from that of the gate cap 264. In the depicted embodiment, the gate spacer 330 is formed of a single layer. In some embodiments, the gate spacer 330 may have a multi-layer structure, such as a bulk dielectric layer on one or more dielectric liners.

[0124] The gate spacer 330 has a width w8 (e.g., along the y-direction). In some embodiments, the width w8 is between approximately 5 nm and approximately 600 nm. The gate spacer 330 can be formed by depositing a dielectric material (e.g., silicon nitride) over the multi-gate device 700, filling the remaining portion of the gate opening 285, and performing a planarization process. A planarization process, such as CMP, is performed until the gate cap 264 is reached and exposed, leaving the top surface of the gate cap 264 free of the high-k dielectric layer 726 and the dummy gate dielectric portion 242C. In some embodiments, the gate cap 264 can serve as a planarization stop layer. In some embodiments, the planarization process removes any dielectric material disposed above and / or over the top surface of the gate cap 264 (e.g., the high-k dielectric layer 726, the gate spacer 710, the ILD layer 284, the CESL 282, the gate spacer 250, or a combination thereof), and the remaining portion of the dielectric material forms the gate spacer 330. In some embodiments, the planarization process reduces the thickness of the gate cap 264. Because the fabrication of the gates 738A-738C includes etching back the gate electrodes 728 and the gate end caps 325, and the spacing between adjacent gate cap structures 733 is greater than the spacing between adjacent gates 738A-738C, the gate spacers 330 may have a T-shaped profile, as depicted in FIG. 51 . In such an embodiment, the width of the gate spacers 330 between the gate cap structures 733 is greater than the width of the gate spacers 330 between the gate end caps 325. The dielectric material is formed by CVD, FCVD, HDPCVD, MOCVD, RPCVD, PECVD, APCVD, SAVCD, other suitable deposition processes, or combinations thereof.

[0125] The metal gate cutting process is called "self-aligned" because the gate spacers 330 are aligned between the gates in the boundary region 228B (e.g., gate 738B and gate 738C and / or gate 738A and the adjacent gate to its left) without requiring a lithography process after forming gates 738A-738C. The self-aligned placement of the gate spacers 330 provides electrical isolation between devices in adjacent active regions, such as transistors formed in the boundary region 228B. The self-aligned placement of the gate spacers 330 also allows for higher packaging density without negatively impacting the operation of closely spaced devices in high-density ICs. For example, the spacing S1' between adjacent active regions in the boundary region 228B (e.g., between the mesa 206' / channel layer 220' / gate 738B in the transistor region 202B and the mesa 206' / channel layer 220' / gate 738C in the transistor region 202C) and / or between adjacent active regions in the device region 204A and the device region 204B can be smaller (e.g., approximately 10 nm to approximately 15 nm smaller) than the spacing required between adjacent active regions when implementing a non-self-aligned metal gate (SGM) cutting technique, such as a technique that uses a lithography process to form a gate isolation structure between gates in adjacent device regions. The spacing S1' can be further reduced by providing the gates 738A-738C with gate end caps 325 on one side rather than both sides. In some embodiments, the spacing S1' is approximately 5 nm to approximately 600 nm. Smaller spacing between active regions is possible because the described SGM cutting technique does not suffer from the overlay issues associated with non-self-aligned metal gate cutting techniques. Thus, a smaller spacing between active regions can be achieved without the risk of unintended damage to the channel layer 220' and / or gates 738A-738C, such as may be caused by process variations inherent in non-self-aligned metal gate cutting techniques. Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

[0126] Referring to Figures 52 and 53A-53C, the process may include forming a dielectric layer 340 similar to dielectric layer 280 over the multi-gate device 700 and forming device-level contacts (e.g., gate contact 350A and gate contact 350B) in dielectric layer 340, such as described above with reference to Figures 15 and 16A-16C. Gate contact 350A is disposed on top of the respective gate stacks 730 (e.g., portion 728A thereof and high-k dielectric layer 726) of gates 738A and 738B, and is disposed between gate caps 264 covering gates 738A and 738B. Gate contact 350A is also disposed on top of respective gate spacers 710 between gates 738A and 738B, and the respective gate spacers 710 provide intra-cell region gate isolation. A gate contact 350B is disposed on top of the corresponding gate stack 730 (e.g., portion 728A thereof and high-k dielectric layer 726) of gate 738C and is positioned adjacent to the gate cap 264 covering gate 738C. Gate contact 350B is also disposed on top of the corresponding gate spacer 710 between gate 738C and an adjacent gate, and the corresponding gate spacer 710 provides intra-cell regional gate isolation. Gate contact 350A can physically and / or electrically connect gate 738A and gate 738B, and gate contact 350B can physically and / or electrically connect gate 738C to the gate of an adjacent transistor region. Source / drain contacts 355 are disposed on the corresponding epitaxial source / drain 275B and between corresponding portions of CESL 282.

[0127] In some embodiments, gate contact 350A and / or gate contact 350B do not include a barrier. For example, gate contact 350A and / or gate contact 350B may include a metal plug that physically contacts gate electrode 728, high-k dielectric layer 726, gate spacer 710, gate cap 264, dielectric layer 340, other adjacent dielectric layers, or a combination thereof. In some embodiments, gate contact 350A and / or gate contact 350B include a metal plug disposed above the diffusion / barrier layer. In some embodiments, forming gate contact 350 may include forming a patterned mask layer above dielectric layer 340, wherein the patterned mask layer has a first opening and a second opening. The first opening overlaps a portion of gate 738A, a portion of gate 738B, and the gate spacer 710 therebetween, and the second opening overlaps a portion of gate 738C and the gate spacer 710 adjacent thereto. An etching process using the patterned mask layer as an etch mask can be performed to form a first gate contact opening and a second gate contact opening. The first gate contact opening exposes a portion of gate 738A, a portion of gate 738B, and the gate spacer 710 therebetween, and the second gate contact opening exposes a portion of gate 738C and the gate spacer 710 adjacent thereto. The etching process selectively removes dielectric material (e.g., dielectric layer 340, gate cap 264, high-k dielectric layer 726, gate spacer 710, or a combination thereof) exposed by the first and second openings of the patterned mask layer, while removing negligible metal material (e.g., gate electrode 728). In some embodiments, the etching process is configured to stop upon reaching and / or exposing gate electrode 728. The etching process is a dry etch, a wet etch, another suitable etch, or a combination thereof. One or more deposition processes may then be performed to form gate contact material (e.g., one or more conductive layers) over the dielectric layer 340, filling the first and second gate contact openings. A planarization process may be performed to remove excess gate contact material, such as gate contact material above the top surface of the dielectric layer 340. The remaining portions of the contact material filling the first and second gate contact openings may provide gate contacts 350A and 350B, respectively.

[0128] In Figures 52 and 53A-53C, a multi-gate device 700 includes transistors. For example, the transistors in transistor region 202A include corresponding channel layers 220', epitaxial source / drain electrodes 275A, and gate electrodes 738A; the transistors in transistor region 202B include corresponding channel layers 220', epitaxial source / drain electrodes 275B, and gate electrodes 738B; and the transistors in transistor region 202C include corresponding channel layers 220', epitaxial source / drain electrodes 275C, and gate electrodes 738C. Gate contact 350A electrically connects the gates of the transistors in transistor region 202A and transistor region 202B, such as gate electrodes 738A and 738B. Gate contact 350B can electrically connect the gate of the transistor in transistor region 202C (e.g., gate electrode 738C) to the gate of another transistor in an adjacent transistor region. In the depicted embodiment, the transistors are separated and / or isolated by two types of gate spacers: gate spacers 710 (formed in the intra-cell region 228A between the electrically connected gates of the transistors) and gate spacers 330 (formed in the boundary region 228B between the electrically isolated gates of the transistors). For example, in transistor region 202B, gate 738B of the transistor is separated from gate 738A (which is electrically connected to gate 738B via gate contact 350A) by gate spacers 710, and gate 738B is separated from gate 738C (which is not electrically connected to gate 738B) by gate spacers 330. In other words, the gates of adjacent transistors in the same cell (e.g., the same logic cell or the same memory cell) can be separated and / or isolated by the gate isolation wall 710 in the intra-cell region 228A, and the gates of adjacent transistors in different cells (e.g., different logic cells or different memory cells) can be separated and / or isolated by the gate isolation wall 330 in the boundary region 228B.

[0129] Each gate (e.g., gate 738B) is disposed along the x-direction between a corresponding epitaxial source / drain (e.g., epitaxial source / drain 275B), and an inner spacer 262 is disposed between each gate and its corresponding epitaxial source / drain. Furthermore, each gate (e.g., gate 738B) is bonded to a corresponding channel layer (e.g., channel layer 220' in transistor region 202B), and the channel layer extends along the x-direction between the corresponding epitaxial source / drain (e.g., epitaxial source / drain 275B). Each gate (e.g., gate 738B) surrounds its corresponding channel layer. In the YZ plane, each gate has a gate dielectric surrounding its corresponding channel layer (e.g., gate dielectric 722 of gate 738B), gate electrodes disposed along the top and bottom of its respective channel layer (e.g., gate electrode 728 of gate 738B), and a gate end cap (e.g., gate end cap 325 of gate 738B) along the sidewalls of its respective channel layer, the sidewalls of its respective gate electrode, and the sidewalls of its respective gate dielectric. In the XZ plane, each gate has a high-k dielectric layer surrounding the gate dielectric of its corresponding gate electrode (e.g., high-k dielectric layer 726 of gate 738B), and an interfacial layer disposed between the high-k dielectric layer and its corresponding channel layer (e.g., interfacial layer 724 of gate 738B). In addition, each gate (e.g., gate 738B) has a gate cap (e.g., gate cap 264) disposed thereon, wherein the gate cap is disposed over the top of the corresponding gate electrode (e.g., portion 728A of gate 738B). Portions of the gate dielectric (e.g., high-k dielectric layer 726 of gate 738B) wrap around the corners of the gate cap, are disposed between the gate cap and the top of the corresponding gate electrode, are disposed between the gate cap and the corresponding gate end cap, and are disposed between the gate cap and the corresponding gate spacer 330.

[0130] Gates 738A-738C each have sidewalls S7 and S8. Sidewall S7 is formed by the corresponding gate dielectric 722 (e.g., high-k dielectric layer 726 and the corresponding dummy gate dielectric portion 242A), and sidewall S8 is formed by the corresponding gate end cap 325. In such an embodiment, sidewall 732A of gate stack 730 is separated from the corresponding gate spacer 330 by the corresponding gate end cap 325, and sidewall 732B of gate stack 730 is not separated from and physically contacts the corresponding gate spacer 710. Gate contacts 350A and 350B extend through gate cap 264, extend over sidewalls S7 of gates 738A-738C, physically contact the high-k dielectric layer 726, physically contact portion 728A, and physically contact the gate spacer 710. Furthermore, gate spacers 710 are disposed between a corresponding pair of sidewalls S7, and gate spacers 330 are disposed between a corresponding pair of sidewalls S8. In the depicted embodiment, sidewalls S8 are generally straight, and gate endcap 325 has a rectangular profile / shape. In some embodiments, as shown in FIG. 54 , sidewalls S8 are wavy, and gate endcap 325 has a scalloped profile / shape. In such embodiments, gate endcap 325 has a curved segment that intersects gate spacers 330. Due to deposition / growth variations in the selective deposition process, different sidewall profiles, such as wavy sidewalls, may occur.

[0131] In the depicted embodiment, gates 738A-738C have π-gate (pi-gate) portions formed from portions of the high-k dielectric layer 726 located between the channel layer 220′ and the cladding portions 728A-728C. For example, gates 738A-738C have two π-gate portions formed from respective portions of the high-k dielectric layer 726 cladding their respective portions 728B, and one π-gate portion formed from respective portions of the high-k dielectric layer 726 cladding their respective portions 728C. For example, each π-gate portion of the high-k dielectric layer 726 is disposed on the top, bottom, and sidewalls (e.g., the sidewalls facing the gate spacer 710) of the respective portions 728B or 728C. Each Π-gate portion of the high-k dielectric layer 726 further extends vertically beyond the top and bottom of the corresponding portion 728B or the corresponding portion 728C to the dummy gate dielectric portion 242A, such that each Π-gate portion of the high-k dielectric layer 726 overlaps the sidewalls of the channel layer 220'. The Π-gate portion of the high-k dielectric layer 726 may extend laterally from the sidewalls of the channel layer 220' (e.g., along the y-direction) and vertically along the sidewalls of the channel layer 220' (e.g., along the z-direction). Distance d3 is between the sidewalls of the channel layer 220' and the surface of the Π-gate portion of the high-k dielectric layer 726 forming sidewall S7. Distance d3 can also be considered to be between the sidewalls of the channel layer 220' and the sidewalls of the gate spacer 710. Distance d4 lies between the top (or bottom) of channel layer 220' and the end of the π gate portion of high-k dielectric layer 726, which intersects dummy gate dielectric portion 242A. Distance d4 can also be considered to lie between the top (or bottom) of channel layer 220' and dummy gate dielectric portion 242A. In some embodiments, distance d3 is approximately 0.1 nm to approximately 5 nm. In some embodiments, distance d4 is approximately 0.1 nm to approximately 2.5 nm. The trimming process of dummy gate dielectric 242 ( FIG. 33 ) can be tailored to achieve a desired lateral extension and / or desired vertical extension of the π gate portion of high-k dielectric layer 726 relative to channel layer 220'. The π gate portion can improve short channel effect (SCE) control of transistor regions 202A-202C and / or transistors in multi-gate device 700.

[0132] In Figures 34-52 and 53A-53C, gate cap 264 is formed simultaneously with inner spacer 262. For example, gate cap 264 and inner spacer 262 are formed by selectively etching semiconductor layer 225 and semiconductor layer 215 to form gaps 266, 268, and 270 (Figure 37); depositing one or more dielectric layers to fill gaps 266, 268, and 270 (Figure 38); and selectively etching the one or more dielectric layers so that the remaining portions of the one or more dielectric layers form gate cap 264 and inner spacer 262 (Figure 38). In some embodiments, gate cap 264 can be formed before or after inner spacer 262. For example, instead of forming gate cap 264 and inner spacer 262 as depicted and described with reference to Figures 37 and 38, gate cap 264 can be formed before inner spacer 262, as depicted and described with reference to Figures 55-58.

[0133] According to various aspects of the present disclosure, Figures 55-58 are partial views of a multi-gate device 700 at various stages of fabrication associated with forming the gate cap 264 and the inner spacer 262. In such an embodiment, the multi-gate device 700 has already undergone the processes associated with Figures 34-36 (Figure 55), the multi-gate device 700 has undergone processes to form the gate cap 264 (Figures 55 and 56), the multi-gate device 200 has undergone processes to form the inner spacer 262 (Figures 57 and 58), and the multi-gate device 700 may undergo the processes associated with Figures 39-52 after forming the gate cap 264 and the inner spacer 262. The process may include selectively etching the semiconductor layer 225 to form a gap 270 ( FIG. 55 ); depositing one or more dielectric layers on the multi-gate device 700 to fill the gap 270 ( FIG. 56 ); and selectively etching the one or more dielectric layers so that the remaining portions of the one or more dielectric layers form a gate cap 264 ( FIG. 56 ). Subsequently, the process may include selectively etching the semiconductor layer 215 to form gaps 266 and 268 ( FIG. 57 ); depositing one or more dielectric layers on the multi-gate device 700 to fill the gaps 266 and 268 ( FIG. 58 ); and selectively etching the one or more dielectric layers so that the remaining portions of the one or more dielectric layers form an inner spacer 262 ( FIG. 58 ). In some embodiments, the composition of the gate cap 264 is different from the composition of the inner spacer 262. In some embodiments, the processes associated with Figures 55 and 56 may be performed after the processes associated with Figures 57 and 58 to form a gate cap 264 after the inner spacer 262. In such embodiments, the multi-gate device 700 includes the semiconductor layer 225 when the inner spacer 262 is formed, and the inner spacer 262 when the gate cap 264 is formed. For the sake of clarity, Figures 55-58 have been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to the multi-gate device 700 of Figures 55-58, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 200 of Figures 55-58.

[0134] In Figures 34-52 and 53A-53C, gate electrode 728 is disposed on the top and bottom of channel layer 220', but not along the sidewalls of channel layer 220', and gate electrode 728 includes separate portions 728A-728C electrically connected via gate end cap 325. In some embodiments, the process can be configured to provide a gate electrode that encapsulates channel layer 220', for example, where the gate electrode is disposed on the top, bottom, and sides of channel layer 220', such as depicted and described with reference to Figures 59-64. According to various aspects of the present disclosure, Figures 59-64 are partial views of a multi-gate device 800 at various stages of fabrication (e.g., associated with method 600 of Figure 33). According to various aspects of the present disclosure, Figures 65A, 65B, and 65C are cross-sectional views (e.g., y- and x-sectional views) of a portion or the entirety of multi-gate device 800, respectively, taken along lines AA, BB, and CC of Figure 64. For the sake of clarity, Figures 59-64 and 65A-65C have been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to the multi-gate device 800, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 800.

[0135] The fabrication of the multi-gate device 800 is similar in many respects to the fabrication of the multi-gate device 700. For example, in FIG. 59 , the multi-gate device 800 has undergone the processes associated with FIGS. 34-48 to form the gate spacers 710 and the gate dielectric 722 (including the dummy gate dielectric portion 242A, the interfacial layer 724, and the high-k dielectric layer 726) that partially fill the gate opening 285. In Figures 60-63, instead of forming a gate electrode 728 that partially fills the gate opening 285, the process includes forming a gate electrode layer 828' that fills the remaining portion of the gate opening 285 (Figure 60) and performing a gate cut process to form gate cut openings (e.g., gate cut opening 829A and gate cut opening 829B) that extend through the gate electrode layer 828' in the boundary region 228B to form corresponding gate electrodes 828 in the transistor regions 202A-202C (Figure 61). In Figure 60, forming the gate electrode layer 828' may include depositing a gate electrode material over the multi-gate device 800 that fills the remaining portion of the gate opening 285 (including the gap 286, the gap 288, and the remaining portion of the gap 290) and performing a planarization process. A planarization process (e.g., CMP) removes any gate electrode material from the top of the gate spacer 710, the dielectric layer 280, the gate spacer 250, or a combination thereof. To separate the gate electrodes 828 of different transistor regions within the device area (e.g., the transistor region 202A and the transistor region 202B within the device area 204A), a planarization process may be performed until the gate spacer 710 is reached and exposed. In some embodiments, the gate spacer 710 serves as a planarization stop layer.

[0136] In FIG. 61 , the gate cutting process may include a lithography process and an etching process. In some embodiments, the lithography process includes forming a patterned mask layer over the multi-gate device 800, which partially exposes the gate electrode layer 828', partially covers the gate device 828', and covers the gate spacer 710. For example, the patterned mask layer may include an opening that exposes a portion of the gate electrode layer 828' in the boundary region 228B that is located near the interface between the transistor regions (e.g., near the interface between the transistor regions 202B and 202C). In some embodiments, the etching process includes removing the exposed portion of the gate electrode layer 828' to form gate cutting openings 829A and 829B in the boundary region 228B and near the interface between the transistor regions. The etching process may use the patterned mask layer as an etching mask, so that the gate cutting openings 829A and 829B correspond to the first opening and the second opening in the patterned mask layer, respectively. The etching process can selectively remove metal materials (e.g., gate electrode layer 828′) while negligibly removing dielectric materials (e.g., gate dielectric 722, such as its high-k dielectric layer 726). The etching process can be dry etching, wet etching, other suitable etching methods, or a combination thereof.

[0137] In such an embodiment, each transistor region 202A-202C has a corresponding gate stack 830. Each gate stack 830 includes a corresponding gate dielectric 722 and a corresponding gate electrode 828. In the depicted embodiment, the high-k dielectric layer 726 spans the boundary region 228B, so that the gate stacks 830 of the transistor regions at the boundary region 228B (e.g., the transistor region 202B and the transistor region 202C and / or the transistor region 202A and the adjacent transistor region to its left) can share the high-k dielectric layer 726 (e.g., the high-k dielectric layer 726 can extend uninterrupted from the transistor region 202B to the transistor region 202C), but have separate, respective interface layers 724 and separate, respective gate electrodes 828. Because the multi-gate device 800 is fabricated by performing a gate-cut process to separate the gates at the boundary region 228B (rather than the deposition and etch-back process described for fabricating the multi-gate device 700), and the gate spacers 710 are formed before removing the dummy gate dielectric 242 and forming the gate stacks 830, each gate stack 830 has corresponding sidewalls 832A and corresponding sidewalls 832B. Sidewalls 832A face the corresponding boundary region 228B, while sidewalls 832B face the corresponding intra-cell region 228A (i.e., their gate spacers face the sidewalls). Sidewalls 832A are formed by the corresponding gate electrode 828, rather than by both the corresponding gate dielectric (e.g., its high-k dielectric layer) and the corresponding gate electrode. Sidewalls 832B are formed by the corresponding gate dielectric (e.g., the high-k dielectric layer 726 and its dummy gate dielectric portion 242A).

[0138] Furthermore, in the multi-gate device 800, the gate electrode 828 covers the channel layer 220', such that the gate electrode 828 is disposed along the top, bottom, and sidewall surfaces of the channel layer 220'. For example, each gate electrode 828 has a first portion disposed between the corresponding gate cap 264 and the corresponding top channel layer 220' (filling the remaining portion of gap 290), a second portion disposed between the corresponding channel layer 220' (filling the remaining portion of gap 286), a third portion disposed between the corresponding bottom channel layer 220' and the corresponding plateau 206' (filling the remaining portion of gap 288), and a sidewall portion extending along the sidewalls of the channel layer 220'. The sidewall portion extends from the third portion to the second portion and then to the first portion, such that the third portion, the second portion, and the first portion are connected by the sidewall portion of the gate electrode 828 rather than the gate cap. In some embodiments, the sidewall portion may extend below the top surface of the corresponding plateau 206', as depicted. In some embodiments, the sidewall portion may extend above the top surface of the corresponding gate cap 264, as depicted. In some embodiments, a portion of each gate electrode 828 is disposed above the top surface of the corresponding gate cap 264 and adjacent to the corresponding gate spacer 710, such that the gate electrode 828 encapsulates the gate cap 264.

[0139] Overlap shift / variation during the lithography process used to form the patterned mask layer may cause the opening in the patterned mask layer, and therefore the gate cut opening 829A and / or gate cut opening 829B, to shift leftward or rightward at the interface between the transistor regions in the boundary region 228B. This results in the sidewall portion of the gate electrode 828 (which may also be referred to as the gate electrode end cap) having different thicknesses along the sidewalls of the channel layer 220'. For example, in FIG. 61 , the sidewall portion of the gate electrode 828 in the transistor region 202B has a thickness t7, while the sidewall portion of the gate electrode 828 in the transistor region 202C has a thickness t8. Thickness t7 is less than thickness t8, which may be caused by the leftward shift of the gate cut opening 829B. In some embodiments, thickness t7 is approximately 1 nm to approximately 20 nm. In some embodiments, thickness t8 is approximately 1 nm to approximately 20 nm. In some embodiments, thickness t7 is greater than thickness t8, which may be caused by the rightward shift of the gate cut opening 829B. In some embodiments, as shown in FIG. 66A , thickness t7 is approximately the same as thickness t8 due to minimal displacement of gate cut opening 829B, such as when gate cut opening 829B is located in the middle of boundary region 228B (e.g., gate cut opening 829B is centrally aligned with isolation feature 235 in boundary region 228B and / or with the interface between transistor region 202B and transistor region 202C).

[0140] In FIG. 62 , fabrication of the multi-gate device 800 may include forming a gate cap 835 on the exposed sidewalls 832A of the gate stack 830 . The gate cap 835 partially fills the gate cut openings (e.g., gate cut opening 829A and gate cut opening 829B). In such an embodiment, gate 838A is disposed in transistor region 202A, gate 838B is disposed in transistor region 202B, and gate 838C is disposed in transistor region 202C. Each gate 838A-838C includes a corresponding gate stack 830 (e.g., a corresponding gate dielectric 722 and a corresponding gate electrode 828 ) and a corresponding gate cap 835 forming its sidewalls. The gate cap 835 is similar to the gate cap 325 and may include materials and / or configurations similar to those described above with reference to FIG. 50 and be formed in a manner similar to that described above with reference to FIG. For example, the gate end cap 835 may include tungsten, ruthenium, molybdenum, alloys thereof, or combinations thereof, and the gate electrode 828 may include titanium (e.g., TiN, TiAl, TiAlC, or combinations thereof). In some embodiments, the gate electrode 828 is a work function layer.

[0141] The gate end cap 835 covers the sidewalls 832A of the gate stack 830 formed by the gate electrode 828. In the multi-gate device 800, because the gate electrode 828 covers the channel layer 220' and the gate cap 264, the gate end cap 835 is disposed along the sidewalls of the channel layer 220' and along the sidewalls of the gate cap 264, and is separated from the channel layer 220' and the gate cap 264 by the gate dielectric 722 and the gate electrode 828. Furthermore, the gate end cap 835 can extend below the top surface of the mesa 206' and along its sidewalls. The gate end cap 835 can extend above the top surface of the gate cap 264 and along its sidewalls, with the gate dielectric 722 and the gate electrode 828 between the mesa 206' and the gate end cap 835. In some embodiments, the gate end cap 835 does not extend below the top surface of the mesa 206'. In some embodiments, the gate end cap 835 does not extend above the top surface of the gate shield 264.

[0142] The gate end cap 835 has a width w9 along the sidewall 832A of the gate stack 830 (e.g., along the y-direction). In some embodiments, the width w9 is approximately 2 nm to approximately 5 nm. Because the gate electrode 828 covers the channel layer 220' and is formed by a gate cut process, the gate cap structure 733 does not overhang the gate electrode 828, and the width w9 can be substantially uniform along the length of the gate end cap 835 (e.g., along the z-direction). In some embodiments, the width w9 can vary along the length of the gate end cap 835.

[0143] In FIG. 63 , the fabrication of the multi-gate device 800 may include forming gate spacers 330 between gates 838A-838C, which fill the remaining portions of the gate cut openings (e.g., gate cut opening 829A and gate cut opening 829B). The gate spacers 330 fill the spaces between the gates 838A-838C and are positioned between the gate end caps 835 of adjacent gates 838A-838C (e.g., one of the gate spacers 330 is positioned between the corresponding gate end cap 835 of gate 838B and the corresponding gate end cap 835 of gate 838C). The gate spacers 330 may also fill the spaces between adjacent gate caps 264. In the depicted embodiment, both the gate 828 and the high-k dielectric layer 726 are disposed between the gate spacer 330 and the gate cap 264, and the gate spacer 330 has a width w10 (e.g., along the y-direction) that is less than the width w8. In some embodiments, the width w10 is approximately 5 nm to approximately 600 nm. Because the gates 838A-838C are fabricated using a gate-slice process, the gate spacer 330 can have a rectangular profile, as shown in FIG. 63 . In such an embodiment, the width w10 of the gate spacer 330 is substantially uniform along its height (e.g., along the z-direction).

[0144] The gate spacers 330 can be formed in a manner similar to that described above with reference to FIG. 51 . For example, the gate spacers 330 can be formed by depositing a dielectric material (e.g., silicon nitride) over the multi-gate device 800 to fill the remaining portions of the gate cut openings (e.g., gate cut openings 829A and gate cut openings 829B), and performing a planarization process. A planarization process, such as CMP, is performed until the gate cap 264 is reached and exposed, such that the top surface of the gate cap 264 is free of the gate electrode 828, the high-k dielectric layer 726, and the dummy gate dielectric portion 242C. In some embodiments, the gate cap 264 can serve as a planarization stop layer. In some embodiments, the planarization process removes any dielectric material (e.g., high-k dielectric layer 726, gate spacers 710, ILD layer 284, CESL 282, gate spacers 250, or a combination thereof) disposed above and / or on the top surface of gate cap 264, and the remaining portion of the dielectric material forms gate spacers 330.

[0145] In Figures 64 and 65A-65C, fabrication of the multi-gate device 800 may include forming gate contacts, such as gate contact 350A and gate contact 350B, to gates 838A-838C in a manner similar to that described above with reference to Figures 52 and 53A-53C. In the depicted embodiment, each gate 838A-838C has sidewalls S9 formed by its respective gate stack 830 (e.g., its gate dielectric 722) and sidewalls S10 formed by its respective gate endcap 835. In such an embodiment, the sidewalls 832B of each gate stack 830 physically contact the corresponding gate spacer 710, and the sidewalls 832A of each gate stack 830 are separated from the corresponding gate spacer 330 by the corresponding gate endcap 835. In the depicted embodiment, the sidewalls S10 are generally straight, and the gate endcap 835 has a rectangular profile / shape. In some embodiments, the sidewall S10 is corrugated, such as depicted and described with reference to FIG. 54 , and the gate end cap 835 has a scalloped profile / shape.

[0146] Gate isolation walls 330 can electrically isolate gates 838A-838C from each other. For example, gate 838B in transistor region 202B is separated and electrically isolated from gate 838C in transistor region 202C by corresponding gate isolation walls 330, and is also separated and electrically isolated from gate 838A in transistor region 202A by corresponding gate isolation walls 710. Gate 838A in transistor region 202A can also be separated and electrically isolated from other active regions (e.g., gates of adjacent transistor regions) by corresponding gate isolation walls 330. Gate 838C in transistor region 202C can also be separated and electrically isolated from other active regions (e.g., gates of adjacent transistor regions) by corresponding gate isolation walls 710. In the depicted embodiment, the gate spacer 330 is positioned to the left in the boundary region 228B, and the thickness of the gate electrode end cap portion adjacent to the left sidewall of the gate spacer 330 is less than the thickness of the gate electrode end cap portion adjacent to the right sidewall of the gate spacer 330. In some embodiments, as shown in FIG. 66B , the gate spacer 330 is positioned in the middle / center of the boundary region 228B, and the thickness of the gate electrode end cap portion adjacent to the left sidewall of the gate spacer 330 is approximately the same as the thickness of the gate electrode end cap portion adjacent to the right sidewall of the gate spacer 330. In some embodiments, the gate spacer 330 is positioned to the right in the boundary region 228B, and the thickness of the gate electrode end cap portion adjacent to the left sidewall of the gate spacer 330 is greater than the thickness of the gate electrode end cap portion adjacent to the right sidewall of the gate spacer 330.

[0147] In the multi-gate device 800, the gate contacts 350A and 350B extend over the sidewalls S9 of the gates 838A-838C (i.e., the sidewalls 832B of the gate stack 830 that physically contact the gate spacers 710), and may not extend over and / or physically contact the gate end cap 835. Furthermore, the gate electrode 828 may extend over the bottom of the gate contacts 350A and 350B, such as the sidewall portions of the gate electrode 828 that extend along the sidewalls of the gate cap 264. The gate contact 350A is disposed on top of the gate electrodes 828 of the gates 838A and 838B, the gate contact 350A is disposed on top of the gate isolation wall 710 between the gates 838A and 838B, the gate contact 350A is disposed between the gate caps 264 covering the tops of the gate electrodes 828 of the gates 838A and 838B, and the high-k dielectric layer 726 is disposed between the gate caps 264 and the tops of the gate electrodes 828. The gate contact 350B is disposed on top of the gate electrode 828 of the gate 838C and an adjacent gate (e.g., in a transistor region adjacent to the transistor region 202C), the gate contact 350B is disposed on top of the gate isolation wall 710 between the gate 838C and the adjacent gate, the gate contact 350B is disposed between the gate cap 264 covering the top of the gate electrode 828 of the gate 838C and the adjacent gate, and the high-k dielectric layer 726 is disposed between the gate cap 264 and the top of the gate electrode 828.

[0148] In multi-gate devices 700 and 800, as described above, transistors are separated and / or isolated by gate spacers 710 (e.g., in intra-cell region 228A between the electrically connected gates of the transistors) and gate spacers 330 (e.g., in boundary region 228B between the electrically isolated gates of the transistors). In such embodiments, the transistors have separate gate electrodes. In some embodiments, the process can be configured to separate and / or isolate the transistors using one type of gate spacer (e.g., gate spacer 710 in boundary region 228B) and provide a common gate electrode and / or common gate dielectric for adjacent transistors in the same cell, such as depicted and described with reference to Figures 67-70. In such embodiments, no gate spacers are provided in intra-cell region 228A. Figures 67-70 are partial views of a multi-gate device 900 at various stages of fabrication (e.g., in connection with method 600 of Figure 33), according to various aspects of the present disclosure. According to various aspects of the present disclosure, Figures 71A, 71B, and 71C are partial or full cross-sectional views (e.g., y- and x-sectional views) of the multi-gate device 900, respectively, along lines AA, BB, and CC of Figure 70. Figures 67-70 and 71A-71C have been simplified for clarity to facilitate a better understanding of the inventive concepts of the present disclosure. Additional features may be incorporated into the multi-gate device 900, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 900.

[0149] The fabrication of the multi-gate device 900 is similar in many respects to the fabrication of the multi-gate device 700 and / or the multi-gate device 800. For example, in FIG. 67 , the multi-gate device 900 has undergone a process similar to that of FIGS. 34-48 to form gate spacers 710 and gate dielectric 722 (including dummy gate dielectric portion 242A, interface layer 724, and high-k dielectric layer 726) partially filling the gate opening 285. However, in the multi-gate device 900 , the gate spacers 710 are formed in the boundary region 228B, rather than in the intra-cell region 228A as in the multi-gate devices 700 and 800 . In FIGS. 67 and 68 , instead of forming the gate electrode 728 partially filling the gate opening 285, the process includes forming the gate electrode 928 filling the remaining portion of the gate opening 285. Forming the gate electrode 928 may include depositing a gate electrode layer 928' over the multi-gate device 900, filling the remaining portion of the gate opening 285 (including the remaining portion of the gap 286, gap 288, and gap 290) ( FIG. 68 ), and performing a planarization process ( FIG. 69 ). The planarization process (e.g., CMP) removes any gate electrode layer 928' from atop the gate spacers 710, dielectric layer 280, gate cap 264, gate spacers 250, or a combination thereof. To separate the gate electrodes 928 of transistors adjacent to the boundary region 228B (e.g., transistor region 202C in device region 204B and transistor region 202B in device region 204A), a planarization process may be performed until the gate spacers 710 and / or gate cap 264 are reached and exposed. In some embodiments, the gate spacers 710 serve as a planarization stop layer. In some embodiments, the gate cap 264 serves as a planarization stop layer.

[0150] In multi-gate device 900, gate 938A is disposed in device region 204A, and gate 938B is disposed in device region 204B. In such an embodiment, gate 938A is a common gate for transistor region 202A and transistor region 202B, and gate 938A forms part of the transistor in transistor region 202A and transistor region 202B. Furthermore, gate 938B is a common gate for transistor region 202C and the adjacent transistor region (e.g., on the left), and gate 938B forms part of the transistor in transistor region 202C and the adjacent transistor region. Gate 938A and gate 938B each include their own gate stack 930, and each gate stack 930 includes their own gate dielectric 722 and their own gate electrode 928. In the depicted embodiment, the high-k dielectric layer 726 and the gate electrode 928 span the intra-cell region 228A, allowing the gate stacks 930 of transistors adjacent to the intra-cell region 228A (e.g., transistors in transistor regions 202A and 202B and / or transistors in transistor region 202C and the adjacent transistor region to its left) to share the high-k dielectric layer 726 and gate electrode 928 (e.g., each may extend uninterrupted) and have separate, respective interface layers 724. Because the gate spacers 710 are formed in the boundary region 228B before the dummy gate dielectric 242 is removed and the gate stacks 930 are formed, and because the gate spacers 330 are not formed in the intra-cell region 228A, each gate stack 930 has sidewalls 932 facing the corresponding boundary region 228B (i.e., sidewall-facing gate spacers). Sidewalls 932 are formed by the corresponding gate dielectric (e.g., high-k dielectric layer 726 and its dummy gate dielectric portion 242A), and sidewalls 932 physically contact gate spacers 710. In multi-gate device 900, gate stack 930 may not have sidewalls in intra-cell region 228A, and gates (e.g., gates 938A and 938B) may not have gate end caps, such as gate end cap 325 and / or gate end cap 835. In such an embodiment, gates of adjacent transistors in different cells (e.g., different logic cells or different memory cells, and / or belonging to different devices and / or different device regions) may be separated and / or isolated by gate spacers 710 in boundary region 228B, while adjacent transistors in the same cell (e.g., the same logic cell or the same memory cell, and / or belonging to the same device region and / or the same device) may share gates (e.g., a common gate electrode).

[0151] Furthermore, in the multi-gate device 900, the gate electrodes 928 encapsulate the channel layers 220', such that the gate electrodes 928 are disposed along the top, bottom, and sidewall surfaces of the channel layers 220'. For example, each gate electrode 928 includes a first portion disposed between the corresponding gate cap 264 and the corresponding top channel layer 220' (filling the remaining portion of the gap 290), a second portion disposed between the corresponding channel layers 220' (filling the remaining portion of the gap 286), and a third portion disposed between the corresponding bottom channel layer 220' and the corresponding plateau 206' (filling the remaining portion of the gap 288). Each gate electrode 928 also includes a middle portion that fills the remaining portion of the intra-cell region 228A above the isolation feature 235 and between the channel layers 220' of adjacent transistors (e.g., between the channel layers 220' of transistors in the same device region). For example, for gate 938A, the middle portion of gate electrode 928 is located between the channel layer 220' of the transistor in transistor region 202A and the channel layer 220' of the transistor in transistor region 202B, both of which are in device region 204A. The middle portion extends along the sidewalls of channel layer 220' from the third portion to the second portion and then to the first portion, such that the third portion, the second portion, and the first portion are connected by the middle portion of gate electrode 928, rather than the gate end caps. In some embodiments, the middle portion may extend below the top surface of the corresponding plateau 206', as depicted. In some embodiments, the middle portion may extend along the sidewalls and be located between the corresponding gate caps 264, as depicted.

[0152] In Figures 70 and 71A-71C, instead of forming gate contacts 350A and / or gate contacts 350B, the fabrication of multi-gate device 900 may include forming gate vias, such as gate via 950A and gate via 950B, in dielectric layer 340 to gates 938A and 938B, respectively. Gate via 950A extends through dielectric layer 340 and is disposed atop a middle portion of gate 928 of gate 938A. Gate via 950A is disposed between gate caps 264 in transistor regions 202A and 202B, and does not extend below the top of gate caps 264. Gate via 950B extends through dielectric layer 340 and gate caps 264 in transistor region 202C, and is disposed atop a first portion of gate 938B. Gate via 950B also extends through a portion of the high-k dielectric layer 726 of the gate cap 264 enclosing the transistor region 202C. Gate vias 950A and 950B can physically and / or electrically connect gates 938A and 938B, respectively, to metallization layers of the multi-layer interconnect MLI formed thereover, as described herein. Furthermore, in the depicted embodiment, gates 938A and 938B have sidewalls S11 formed by their respective gate stacks 930 (e.g., by their gate dielectrics 722). In such an embodiment, the sidewalls 932 of each gate stack 930 physically contact the corresponding gate spacer 710, and gate vias 350A and 350B do not extend above the sidewalls S11 of gates 938A and 938, respectively.

[0153] Gate vias 950A and 950B include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, a low-resistance metal composition, alloys thereof, or combinations thereof. In the depicted embodiment, gate vias 950A and 950B include tungsten, ruthenium, cobalt, alloys thereof, or combinations thereof. For example, gate vias 950A and / or gate vias 950B may include tungsten contacts, ruthenium contacts, or cobalt contacts. In some embodiments, gate vias 950A and / or gate vias 950B do not have a barrier. For example, gate vias 950A and / or gate vias 950B may include a metal plug that physically contacts the gate electrode 928, the high-k dielectric layer 726, the gate cap 264, the dielectric layer 340, other adjacent dielectric layers, or combinations thereof. In some embodiments, gate via 950A and / or gate via 950B include a metal plug disposed above a diffusion / barrier layer. The diffusion / barrier layer may include a material that promotes adhesion between the metal plug and adjacent dielectric materials (e.g., dielectric layer 340, gate cap 264, etc.) and / or a material that prevents diffusion of metal components from the metal plug into the adjacent dielectric materials. In some embodiments, the diffusion / barrier layer includes tantalum, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, tantalum carbide, titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, other suitable materials, or combinations thereof. In some embodiments, the diffusion / barrier layer may have a multilayer structure, such as a first sublayer and a second sublayer.

[0154] In some embodiments, forming the gate via can include forming a patterned mask layer over the dielectric layer 340, wherein the patterned mask layer has a first opening and a second opening. The first opening overlaps a portion of the gate 938A, such as a middle portion thereof, and the second opening overlaps a portion of the gate 938B, such as a first portion thereof. An etching process using the patterned mask layer as an etching mask can be performed to form the first gate via opening and the second gate via opening. The first gate via opening extends through the dielectric layer 340 to expose a middle portion of the gate 938A, which is located between the corresponding gate caps 264, and the second gate via opening extends through the dielectric layer 340, the corresponding gate caps 264, and the corresponding high-k dielectric layer 726 to expose a first portion of the gate 938B. The etching process selectively removes dielectric material (e.g., dielectric layer 340, gate cap 264, high-k dielectric layer 726, or a combination thereof) exposed by the first and second openings of the patterned mask layer, while negligible removal of metal material (e.g., gate electrode 928). In some embodiments, the etching process is configured to stop upon reaching and / or exposing gate electrode 928. The etching process is a dry etch, a wet etch, another suitable etch, or a combination thereof. One or more deposition processes (e.g., CVD, ALD, PVD, etc.) may then be performed to form gate via material (e.g., one or more conductive layers) over dielectric layer 340, filling the first and second gate via openings. A planarization process (e.g., CMP) may be performed to remove excess gate via material, such as gate via material above the top surface of dielectric layer 340. The remaining portions of the via material filling the first and second gate via openings may provide gate vias 950A and 950B, respectively.

[0155] In the above-described embodiments, the process includes performing a trim process, such as described above with reference to FIG. 47 , to provide gates 738A-738C, gates 838A-838C, gates 938A, and gates 938B, wherein the gate portion is formed from a portion of the high-k dielectric layer 726 that covers the gate electrode portion. In some embodiments, the trim process is omitted from the process, and the dummy gate dielectric 242 is not trimmed as described in FIG. 47 . According to various aspects of the present disclosure, when the process flow omits the trim process, FIG. 72-74 are partial views of multi-gate devices 700, multi-gate devices 800, and multi-gate devices 900, respectively. In FIG. 72-74 , the gate dielectric 722 includes a dummy gate dielectric 242, rather than a dummy gate dielectric portion 242A. The dummy gate dielectric 242 covers the gate spacers 710. For example, the dummy gate dielectric 242 is located between the sidewalls of the gate spacer 710 and the channel layer 220′, between the sidewalls of the gate spacer 710 and the gate electrode (e.g., gate electrode 728, gate electrode 828, or gate electrode 928), and between the bottom of the gate spacer 710 and the isolation feature 235. In such an embodiment, the high-k dielectric layer 726 covers the channel layer 220′ and may not be disposed along both sidewalls of the channel layer 220′. Furthermore, sidewalls S7 of gates 738A-738C of multi-gate device 700 ( FIG. 72 ), sidewalls S9 of gates 838A-838C of multi-gate device 800 ( FIG. 41 ), and sidewalls S11 and S6 of gates 938A and 938B of multi-gate device 900 ( FIG. 42 ) are formed from dummy gate dielectric 242 rather than from both high-k dielectric layer 726 and dummy gate dielectric portion 242A. For clarity, FIGS. 72-74 have been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to the multi-gate devices of FIGS. 72-74 , and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-gate devices of FIGS. 72-74 .

[0156] In some embodiments, device region 204A and / or device region 204B may be a core region (often referred to as a logic region), a memory region (e.g., a static random-access memory (SRAM) region), an analog region, a peripheral region (often referred to as an input / output (I / O) region), a dummy region, other suitable regions, or a combination thereof. Device region 204A and / or device region 204B may include various passive and active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), CMOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable devices, or a combination thereof. Multi-gate device 200 may be included in a microprocessor, a memory device, other integrated circuit devices, or a combination thereof. In some embodiments, the multi-gate device 200 is part of an IC chip, a system on chip (SoC), or a portion thereof.

[0157] As can be seen from the above description, the multi-gate device described in the present disclosure provides advantages over conventional multi-gate devices. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed in the present disclosure, and not all embodiments require specific advantages. One advantage of the manufacturing process described in the present disclosure is that because the gate mask (e.g., gate hard mask) is formed after the dummy gate is formed and before the metal gate is formed, the gate mask can protect the underlying channel layer during the gate replacement process. Another advantage is that the manufacturing process described in the present disclosure reduces the size and / or footprint of the metal gate of the transistor compared to transistors manufactured using conventional metal gate isolation and cutting techniques, thereby allowing for higher transistor packaging density and increased IC pattern density. The reduction in metal gate size and / or footprint is achieved because the disclosed self-aligned metal gate isolation and singulation techniques provide transistors with individual gate electrode structures separated by gate spacers and connected to gate contacts spanning the gate spacers, rather than providing transistors with a shared gate electrode structure spanning the spacing (e.g., spacing S) between transistor regions and connected to gate vias. Another advantage of the reduced size and / or footprint is reduced parasitic capacitance. For example, smaller metal gates reduce the parasitic capacitance (Cgd) between the metal gate and the source / drain, thereby improving transistor speed and performance. Furthermore, as noted above, the self-aligned metal gate isolation and singulation techniques described herein are independent of lithographic process variations, allowing for smaller spacing between transistor active regions and, therefore, further increasing transistor packaging density and IC pattern density.

[0158] The present disclosure provides many different embodiments. An exemplary semiconductor structure includes: a semiconductor layer; a first isolation member and a second isolation member; a first gate isolation wall and a second gate isolation wall; a first gate and a second gate; a gate end cap; and a gate cap. The first gate isolation wall is disposed on the first isolation member, and the second gate isolation wall is disposed on the second isolation member. The first gate is disposed between the first gate isolation wall and the second gate isolation wall. The first gate includes: a gate stack surrounding the semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A first sidewall of the gate stack is formed by the gate dielectric and the gate electrode, and the gate end cap is disposed on the first sidewall. The gate cap is disposed on the gate stack, with a portion of the gate dielectric disposed between the gate electrode and the gate cap. A gate contact is disposed on the first gate, extending over the first gate isolation wall and connecting the first gate to the second gate.

[0159] In some embodiments, the gate contact extends over the first sidewall and physically contacts the gate end cap. In some embodiments, the gate contact extends over the second sidewall of the gate stack. In some embodiments, the first gate spacer physically contacts the second sidewall. In some embodiments, the gate end cap is a first gate end cap, and the second gate end cap is disposed over the second sidewall, between the first gate spacer and the second sidewall. In some embodiments, the gate end cap provides the first gate with a gate sidewall having a scalloped profile.

[0160] In some embodiments, the first sidewall includes a gate dielectric portion disposed between the first gate electrode portion and the second gate electrode portion. The gate dielectric portion is formed of a gate dielectric, and the first gate electrode portion and the second gate electrode portion are each formed of a gate electrode. In some embodiments, a gate end cap may be disposed over the gate dielectric portion, the first gate electrode portion, and the second gate electrode portion, and the gate end cap may connect the first gate electrode portion and the second gate electrode portion. In some embodiments, the gate end cap includes a first gate end cap segment disposed over the first gate electrode portion and a second gate end cap segment disposed over the second gate electrode portion. In some embodiments, the first gate end cap segment and the second gate end cap segment extend over the gate dielectric portion.

[0161] Another example semiconductor structure includes a first gate stack, a second gate stack, a first gate cap, a second gate cap, a gate spacer, and a gate contact. The first gate stack is disposed on a first semiconductor layer, and the second gate stack is disposed on a second semiconductor layer. The first gate stack has a first gate dielectric and a first gate electrode, and the second gate stack has a second gate dielectric and a second gate electrode. The first gate stack has a first sidewall formed by both the first gate dielectric and the first gate electrode, and the second gate stack has a second sidewall formed by both the second gate dielectric and the second gate electrode. The first gate cap is disposed on the first gate stack, and the second gate cap is disposed on the second gate stack. The gate spacer is disposed between the first gate stack and the second gate stack. A gate contact is disposed on and connected to the first gate stack and the second gate stack. A gate contact is also disposed on the gate spacer and disposed between the first gate cap and the second gate cap.

[0162] In some embodiments, a first gate end cap is disposed on a first portion of the first sidewall of the first gate stack, and a second gate end cap is disposed on a first portion of the second sidewall of the second gate stack. The first gate end cap connects a first portion of the first gate electrode and a second portion of the first gate electrode. The second gate end cap connects a first portion of the second gate electrode and a second portion of the second gate electrode. In some embodiments, the first gate end cap extends above the first gate electrode, and the second gate end cap extends above the second gate electrode. In some embodiments, the first gate end cap extends above the first gate cap, and the second gate end cap extends above the second gate cap. In some embodiments, the first gate end cap and the second gate end cap each have a contoured surface. In some embodiments, a gate spacer is disposed between and in physical contact with a second portion of the first sidewall of the first gate stack and a second portion of the second sidewall of the second gate stack.

[0163] In some embodiments, the third gate end cap is disposed on the second sidewall of the first gate stack, and the fourth gate end cap is disposed on the second sidewall of the second gate stack. A gate spacer is disposed between the third and fourth gate end caps, and a gate contact is disposed on the third and fourth gate end caps. In some embodiments, the third gate end cap connects the first portion of the first gate electrode and the second portion of the first gate electrode, and the fourth gate end cap connects the first portion of the second gate electrode and the second portion of the second gate electrode. In some embodiments, the third and fourth gate end caps are each segmented, with the third gate end cap not connecting the first portion of the first gate electrode and the second portion of the first gate electrode, and the fourth gate end cap not connecting the first portion of the second gate electrode and the second portion of the second gate electrode. In some embodiments, the gate spacer physically contacts the second sidewall of the first gate stack and the second sidewall of the second gate stack.

[0164] An example method for forming a semiconductor structure includes forming a gate dielectric in a gate opening. The gate dielectric surrounds a first semiconductor layer, a second semiconductor layer, a first gate cap on the first semiconductor layer, and a second gate cap on the second semiconductor layer. The gate dielectric partially fills a first gap between the first semiconductor layer and the first gate cap, and a second gap between the second semiconductor layer and the second gate cap. The method further includes depositing and etching back a gate electrode material to form a first gate electrode and a second gate electrode in the gate opening. The first gate electrode fills a remaining portion of the first gap between the first semiconductor layer and the first gate cap, and the second gate electrode fills a remaining portion of the second gap between the second semiconductor layer and the second gate cap. The first gate electrode and a first portion of the gate dielectric form a first gate stack having a first sidewall, and the second gate electrode and a second portion of the gate dielectric form a second gate stack having a second sidewall. The method further includes selectively depositing a first gate end cap on the first sidewall of the first gate stack and selectively depositing a second gate end cap on the second sidewall of the second gate stack. The method further includes forming a gate spacer in the gate opening to fill the remaining space between the first gate stack and the second gate stack. The method further includes forming a gate contact on the first gate electrode and the second gate electrode. The gate contact is disposed on the gate spacer and between the first gate cap and the second gate cap.

[0165] In some embodiments, the selective deposition is adjusted to form a first gate end-cap segment on a first portion of the first gate electrode and a second gate end-cap segment on a second portion of the first gate electrode. In some embodiments, the selective deposition is adjusted to merge the first gate end-cap segment and the second gate end-cap segment.

[0166] An exemplary semiconductor structure includes a semiconductor layer; a first gate; a first isolation feature and a second isolation feature; a first gate isolation wall and a second gate isolation wall. The first gate isolation wall is disposed on the first isolation feature, and the second gate isolation wall is disposed on the second isolation feature. The first gate is disposed between the first gate isolation wall and the second gate isolation wall. The first gate includes a gate stack surrounding the semiconductor layer. The gate stack has a gate dielectric and a gate electrode. The gate stack has a first sidewall and a second sidewall. The first sidewall is formed by the gate dielectric, the second sidewall is formed by the gate electrode, and the first sidewall physically contacts the first gate isolation wall. The semiconductor structure further includes a gate end cap, a gate shield, and a gate contact. The gate end cap is disposed on the second sidewall of the gate stack and between the gate stack and the second gate isolation wall. The gate shield is disposed on the gate stack, with a portion of the gate dielectric disposed between the gate electrode and the gate shield. The gate contact is arranged on the first gate, and the gate contact extends on the first gate isolation wall and connects the first gate to the second gate.

[0167] In some embodiments, the first sidewall of the gate stack is formed by a dummy gate dielectric layer portion of the gate dielectric. In some embodiments, the gate dielectric includes a high-k dielectric layer, and the high-k dielectric layer forms a pi-gate portion of the gate stack. In some embodiments, the first sidewall of the gate stack is formed by the high-k dielectric layer and the dummy gate dielectric layer portion of the gate dielectric, and the dummy gate dielectric layer portion is disposed between the sidewall of the semiconductor layer and the first gate spacer. In some embodiments, a gate electrode covers the semiconductor layer, and the gate electrode is disposed between the gate end cap and the gate dielectric. In some embodiments, the first gate spacer has a first configuration, and the second gate spacer has a second configuration, and the second configuration is different from the first configuration.

[0168] In some embodiments, the second sidewall of the gate stack is formed by both the gate electrode and the gate dielectric. In some embodiments, the second sidewall of the gate stack is formed by a high-k dielectric layer of the gate dielectric. In some embodiments, the first sidewall has a gate dielectric portion disposed between the first gate electrode portion and the second gate electrode portion, the gate dielectric portion being formed from the gate dielectric, and the first gate electrode portion and the second gate electrode portion being each formed from a gate electrode. In such embodiments, a gate endcap is disposed over the gate dielectric portion, the first gate electrode portion, and the second gate electrode portion, and the gate endcap connects the first gate electrode portion and the second gate electrode portion. In some embodiments, the first sidewall has a gate dielectric portion disposed between the first gate electrode portion and the second gate electrode portion, the gate dielectric portion being formed from the gate dielectric, and the first gate electrode portion and the second gate electrode portion being each formed from a gate electrode, and the gate endcap has a first gate endcap segment disposed over the first gate electrode portion and a second gate endcap segment disposed over the second gate electrode portion.

[0169] An example semiconductor structure includes a first gate stack and a second gate stack. The first gate stack is disposed on a first semiconductor layer, and the second gate stack is disposed on a second semiconductor layer. The first gate stack has a first gate dielectric and a first gate electrode. The second gate stack has a second gate dielectric and a second gate electrode. The first gate stack has a first sidewall and a second sidewall, the first sidewall being formed by the first gate dielectric and the second sidewall being formed by the first gate electrode. The second gate stack has a third sidewall and a fourth sidewall, the third sidewall being formed by the second gate dielectric and the fourth sidewall being formed by the second gate electrode.

[0170] The semiconductor structure also includes a first gate cap and a second gate cap. The first gate cap is disposed on the first gate stack, and the second gate cap is disposed on the second gate stack. The semiconductor structure also includes a first gate spacer and a second gate spacer. The first gate spacer is disposed between the first gate stack and the second gate layer, a first sidewall of the first gate stack and a third sidewall of the second gate stack physically contact the first gate spacer, and the second gate stack is disposed between the first and second gate spacers. In some embodiments, the first gate spacer is located in an intra-cell region (e.g., an isolation region between electrically connected active regions), and the second gate spacer is located in a boundary region (e.g., an isolation region between electrically separated active regions). The semiconductor structure also includes gate contacts disposed on and connected to the first and second gate stacks. The gate contact is disposed on the first gate spacer and between the first and second gate caps.

[0171] In some embodiments, the semiconductor structure further includes a first gate endcap disposed on the second sidewall of the first gate stack and a second gate endcap disposed on the fourth sidewall of the second gate stack. The second gate endcap is disposed between the fourth sidewall of the second gate stack and the second gate spacer. In some embodiments, the first gate endcap connects the first portion of the first gate electrode and the second portion of the first gate electrode, and the second gate endcap connects the first portion of the second gate electrode and the second portion of the second gate electrode. In some embodiments, the second sidewall of the first gate stack is formed by both the first gate electrode and the first gate dielectric, and the fourth sidewall of the second gate stack is formed by both the second gate electrode and the second gate dielectric. The first gate endcap physically contacts the first gate dielectric, and the second gate endcap physically contacts the second gate dielectric. In some embodiments, the first gate electrode is disposed between the first gate endcap and the first gate dielectric, and the second gate electrode is disposed between the second gate endcap and the second gate dielectric. In some embodiments, the first gate electrode is disposed between the first gate endcap and the first gate cap, and the second gate electrode is disposed between the second gate endcap and the second gate cap.

[0172] An example method for forming a semiconductor structure includes removing a dummy gate electrode layer to form a gate opening exposing a dummy gate dielectric layer. The method also includes forming a first gate isolation wall in the gate opening in a first isolation region. The first isolation region is located between a first active region and a second active region. The method also includes forming a gate dielectric in the gate opening. The gate dielectric surrounds a first semiconductor layer, a second semiconductor layer, a first gate cap above the first semiconductor layer, and a second gate cap above the second semiconductor layer. The first semiconductor layer and the first gate cap are disposed in the first active region, and the second semiconductor layer and the second gate cap are disposed in the second active region. The gate dielectric partially fills a first gap between the first semiconductor layer and the first gate cap, and a second gap between the second semiconductor layer and the second gate cap.

[0173] The method also includes forming a first gate electrode and a second gate electrode in the gate opening. The first gate electrode fills a remaining portion of a first gap between the first semiconductor layer and the first gate cap, and the second gate electrode fills a remaining portion of a second gap between the second semiconductor layer and the second gate cap. The first gate electrode and the first portion of the gate dielectric form a first gate stack having a first sidewall and a second sidewall. The first sidewall is formed by the first portion of the gate dielectric, and the second sidewall is formed by the first gate electrode. The second gate electrode and the second portion of the gate dielectric form a second gate stack having a third sidewall and a fourth sidewall. The third sidewall is formed by the second portion of the gate dielectric, and the fourth sidewall is formed by the second gate electrode.

[0174] The method also includes selectively depositing a first gate end cap on the second sidewall of the first gate stack and a second gate end cap on the fourth sidewall of the second gate stack. The method also includes forming a second gate isolation wall in the gate opening of the second isolation region. The second active region is located between the first isolation region and the second isolation region, and the second gate isolation wall fills a remaining portion of the gate opening. The method may also include forming a gate contact on the first gate electrode and the second gate electrode. The gate contact is disposed on the first gate isolation wall and between the first gate cap and the second gate cap.

[0175] In some embodiments, forming the first and second gate electrodes in the gate opening includes depositing and etching back gate electrode material such that the first and second gate electrodes partially fill the gate opening. In some embodiments, forming the first and second gate electrodes in the gate opening includes depositing and planarizing gate electrode material such that the first and second gate electrodes fill the remaining portion of the gate opening. In such embodiments, the method further includes selectively depositing a second gate end cap after forming the gate cut opening in the second gate electrode. The second gate end cap partially fills the gate cut opening, and a second gate spacer is formed in the gate cut opening and fills the remaining portion of the gate cut opening.

[0176] The above summarizes the features of several embodiments to help those skilled in the art better understand the concepts of the embodiments of the present invention. Those skilled in the art will appreciate that other processes and structures can be readily designed or modified based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and that various modifications, substitutions, and replacements may be made without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0177] 100: Method 105: Steps 110: Steps 115: Steps 120: Steps 125: Steps 130: Steps 135: Steps 140: Steps 145: Steps 150: Steps 155: Steps 160: Steps 165: Steps 200: Installation 206:Substrate 210: Stack 215: semiconductor layer 220: semiconductor layer 225: semiconductor layer 230: Groove 235: Isolation components 240: Stack 242: Dielectric 244: Electrode 246:Mask 247: Mask layer 248: Mask layer 250: spacer 255: Gate structure 256: Spacer 260: Groove 262: Spacer 264: Gate mask 266: Gap 268: Gap 270: Gap 280: dielectric layer 282: Contact Etch Stop Layer / CESL 284: Interlayer dielectric layer / ILD layer 285: Opening 286: Gap / Opening 288: Gap / Opening 290: Gap / Opening 296: Opening 302: Dielectric 304: Interface layer 306: dielectric layer 308: Electrode 320: Stack 322: Sidewall 323: Gate mask structure 324: Suspension part 325: End cap 330: Isolation Wall 340: dielectric layer 350: Contact 355: Contact 400: Device 500: Device 510: Mask layer 600:Method 605: Steps 610: Steps 615: Steps 620: Steps 625: Steps 630: Steps 635: Steps 640: Steps 645: Steps 650: Steps 658: Steps 670: Steps 700: Device 710: Isolation Wall 712: Lining 714: Isolation layer 715: Mask layer 722: Dielectric 724: Interface layer 726: dielectric layer 728: Electrode 730: Stack 733: Gate mask structure 734: Suspension part 800: Device 828: Electrode 829: Mask layer 830: Stack 835: End cap 900: Device 928: Electrode 930: Stack 932: Sidewall 202A: Transistor area 202B: Transistor area 202C: Transistor area 204A: Equipment area 204B: Equipment area 206':High platform 208A: Fins 208B: Fins 208C: fins 220': Channel layer 228A: Area 228B: Area 242A: Dielectric part 242B: Dielectric part 242C: Dielectric part 275A: Source / Drain 275B: Source / Drain 275C: Source / Drain 300A: Gap 300B: Gap 308A: Part 308B: Part 308C: Part 325-1: End cap 325-2: End cap 325A: Segment 325B: Segment 325C: Segmentation 328A: Gate 328B: Gate 328C: Gate 350A:Contact 350B: Contact 655A: Steps 655B: Steps 660A: Steps 660B: Steps 665A: Steps 665B: Steps 712': Isolation layer 714': Isolation materials 728A: Part 728B: Part 728C: Part 732A: Sidewall 732B: Sidewall 738A: Gate 738B: Gate 738C: Gate 828': Electrode layer 829A: Opening 829B: Opening 832A: Sidewall 832B: Sidewall 838A: Gate 838B: Gate 838C: Gate 928': Electrode layer 938A: Gate 938B: Gate 950A:Through hole 950B:Through hole A:Process AA:Line B:Process BB:Line CC:Line d1: distance d2: distance d3: distance d4: distance G-G': line S: Spacing S1: Sidewall S1': Spacing S2: Sidewall S5: Sidewall S6: Sidewall S7: Sidewall S8: Sidewall S9: Sidewall S10: Sidewall S11: Sidewall t1: thickness t2: thickness t3: thickness t4: thickness t5: thickness t7: thickness t8: thickness w1: width w2: width w3:width w4:width w5: width w6: width w7: width w8:width w9:width w10: width

Claims

1. A semiconductor structure, comprising: A semiconductor layer; A first isolation component and a second isolation component; a first gate isolation wall and a second gate isolation wall, wherein the first gate isolation wall is disposed on the first isolation component, and the second gate isolation wall is disposed on the second isolation component; A first gate is disposed between a first gate isolation wall and a second gate isolation wall, wherein the first gate includes: a gate stack surrounding the semiconductor layer, wherein the gate stack has a gate dielectric and a gate electrode, the gate stack has a first sidewall and a second sidewall, wherein the first sidewall is formed by the gate dielectric and the gate electrode, and a gate end cap disposed on the first sidewall; a gate cover disposed on the gate stack, wherein a portion of the gate dielectric is disposed between the gate electrode and the gate cover; and a gate contact disposed on the first gate, wherein the gate contact extends on the first gate isolation wall and connects the first gate to the second gate, wherein the first gate isolation wall has a first configuration, the second gate isolation wall has a second configuration, and the second configuration is different from the first configuration.

2. The semiconductor structure as claimed in claim 1, wherein the gate contact extends on the first sidewall and physically contacts the gate end cap.

3. The semiconductor structure as described in claim 1, wherein: The first sidewall has a gate dielectric portion disposed between a first gate electrode portion and a second gate electrode portion, the gate dielectric portion being formed of the gate dielectric, and the first gate electrode portion and the second gate electrode portion being each formed of the gate electrode; and a gate end cap disposed on the gate dielectric portion, the first gate electrode portion and the second gate electrode portion, wherein the gate end cap connects the first gate electrode portion and the second gate electrode portion.

4. The semiconductor structure as described in claim 1, wherein: The first sidewall has a gate dielectric portion disposed between a first gate electrode portion and a second gate electrode portion, the gate dielectric portion being formed of the gate dielectric, and the first gate electrode portion and the second gate electrode portion being each formed of the gate electrode; and the gate end cap has a first gate end cap segment disposed on the first gate electrode portion, and a second gate end cap segment disposed on the second gate electrode portion.

5. The semiconductor structure as claimed in claim 4, wherein the first gate end cap segment and the second gate end cap segment extend over the gate dielectric portion.

6. The semiconductor structure as claimed in claim 1, wherein the gate contact extends on the second sidewall and the first gate isolation wall is in physical contact with the second sidewall.

7. The semiconductor structure as described in any one of claims 1 to 6, wherein the gate end cap provides a gate sidewall with a fan-shaped profile for the first gate.

8. A semiconductor structure, comprising: A semiconductor layer; A first isolation component and a second isolation component; a first gate isolation wall and a second gate isolation wall, wherein the first gate isolation wall is disposed on the first isolation component, and the second gate isolation wall is disposed on the second isolation component; A first gate is disposed between the first gate isolation wall and the second gate isolation wall, wherein the first gate includes: a gate stack surrounding the semiconductor layer, wherein the gate stack has a gate dielectric and a gate electrode, the gate stack has a first sidewall and a second sidewall, wherein the first sidewall of the gate stack is formed by the gate dielectric, the second sidewall of the gate stack is formed by the gate electrode, and the first sidewall of the gate stack is in physical contact with the first gate isolation wall, and a gate end cap is disposed on the second sidewall of the gate stack, wherein the gate end cap is between the gate stack and the second gate isolation wall; A gate shield is disposed on the gate stack, wherein a portion of the gate dielectric is disposed between the gate electrode and the gate shield; and a gate contact is disposed on the first gate, wherein the gate contact extends on the first gate isolation wall and connects the first gate to a second gate, wherein the first gate isolation wall has a first configuration, the second gate isolation wall has a second configuration, and the second configuration is different from the first configuration.

9. The semiconductor structure as claimed in claim 8, wherein the second sidewall of the gate stack is formed by both the gate electrode and the gate dielectric.

10. The semiconductor structure as described in claim 9, wherein the second sidewall of the gate stack is formed of a high dielectric constant dielectric layer of the gate dielectric.

11. The semiconductor structure as claimed in claim 8, wherein the first sidewall of the gate stack is formed by a high dielectric constant dielectric layer of the gate dielectric and a dummy gate dielectric layer portion, wherein the dummy gate dielectric layer portion is disposed between the sidewall of the semiconductor layer and the first gate isolation wall.

12. The semiconductor structure as claimed in claim 8, wherein the first sidewall of the gate stack is formed from a portion of a dummy gate dielectric layer of the gate dielectric.

13. A method for forming a semiconductor structure, comprising: A gate dielectric is formed in a gate opening, wherein: the gate dielectric surrounds a first semiconductor layer, a second semiconductor layer, a first gate shield on the first semiconductor layer, and a second gate shield on the second semiconductor layer, and the gate dielectric partially fills a first gap between the first semiconductor layer and the first gate shield and a second gap between the second semiconductor layer and the second gate shield; a gate electrode material is deposited and etched back to form a first gate electrode and a second gate electrode in the gate opening, wherein: the first gate electrode fills the remaining portion of the first gap between the first semiconductor layer and the first gate shield, and the second gate electrode fills the remaining portion of the second gap between the second semiconductor layer and the second gate shield, and a first portion of the first gate electrode and the gate dielectric form a first gate stack with a first sidewall, and a second portion of the second gate electrode and the gate dielectric form a second gate stack with a second sidewall; A first gate end cap is selectively deposited on the first sidewall of the first gate stack, and a second gate end cap is selectively deposited on the second sidewall of the second gate stack; a gate isolation wall is formed in the gate opening, which fills the remaining space between the first gate stack and the second gate stack; and a gate contact is formed on the first gate electrode and the second gate electrode, wherein the gate contact is disposed on the gate isolation wall and between the first gate cover and the second gate cover.

14. The method of forming a semiconductor structure as claimed in claim 13, wherein the selective deposition is configured to form a first gate cap segment on a first portion of the first gate electrode and a second gate cap segment on a second portion of the first gate electrode.

15. The method of forming a semiconductor structure as described in claim 14, wherein the selective deposition is adjusted to merge the first gate end cap segment and the second gate end cap segment.

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