Magnetic tunnel junction structure, probabilistic bit structures including the same and method of forming the probabilistic bit structure
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2024-01-24
- Publication Date
- 2026-08-01
Smart Images
Figure TWG2TB001903514_001 
Figure TWG2TB001903514_002 
Figure TWG2TB001903514_003
Abstract
Description
Technical Field
[0001] The embodiments of the present invention are related to a magnetic tunneling junction structure, including a probabilistic bit structure of the magnetic tunneling junction structure and a method for forming the same. Prior Art
[0002] The following is about the fields of quantum computing, probabilistic bits, quantum data storage, and related fields. Summary of the invention
[0003] An embodiment of the present invention discloses a probabilistic bit structure, which includes: a transistor; a magnetic tunneling junction (MTJ) operably connected to the transistor through a bottom electrode vertical interconnect (BEVA) to form a magnetoresistive random access memory (MRAM); and a heater including at least one conductive loop surrounding the MTJ or the BEVA.
[0004] An embodiment of the present invention discloses a method for forming a probabilistic bit structure, the method comprising: forming a transistor region on a substrate; forming a first intermetallic dielectric (IMD) region on the substrate and the transistor region; forming a magnetic tunneling junction (MTJ) structure on the first IMD region, the MTJ structure comprising: an MTJ unit comprising an insulating layer formed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) formed and connected to the MTJ unit; a bottom electrode vertical interconnect channel (BEVA) formed and connected to the MTJ unit; a heater formed between the first IMD region and the TEVA; and a metallization layer first contact and a metallization layer second contact, which are formed and connected to the heater, wherein when a voltage or current is applied to the metallization layer first and second contacts, the heater heats the MTJ structure.
[0005] An embodiment of the present invention discloses a magnetic tunneling junction (MTJ) structure, which includes: an MTJ unit, which includes an insulating layer disposed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) connected to the MTJ unit; a bottom electrode vertical interconnect channel (BEVA) connected to the MTJ unit; and a heater, which includes at least one conductive loop surrounding the MTJ unit or the BEVA. Simple diagram description
[0006] The present disclosure will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.
[0007] FIG. 1A diagrammatically illustrates an example embodiment of a semiconductor structure suitable for use as a probability bit and including a heat-assisted magnetic tunneling junction (MTJ) structure according to the present disclosure, and FIG. 1B illustrates a graph of experimental switching data of an MTJ structure operated at a temperature of 150° C. The y-axis indicates the read current of the MTJ cell, and the x-axis indicates the retention time of the MTJ cell.
[0008] Figure 2A diagrammatically illustrates a side cross-sectional view of a first example embodiment of a probability bit structure including a thermally assisted MTJ cell, wherein a heater surrounds the MTJ cell bottom electrode vertical interconnect channel (BEVA); Figure 2B diagrammatically illustrates a side cross-sectional view of a second example embodiment of a probability bit structure including a thermally assisted MTJ cell, wherein a heater surrounds the MTJ cell; and Figure 2C diagrammatically illustrates a side cross-sectional view of a third example embodiment of a probability bit structure including a plurality of thermally assisted MTJ cells, wherein a heater surrounds multiple MTJ cell BEVAs.
[0009] 3A to 3F schematically illustrate top views of example embodiments of heaters suitable for MTJ-based probability bits according to the present disclosure, with FIG. 3A illustrating a square heater, FIG. 3B illustrating a rectangular heater, FIG. 3C illustrating another rectangular heater, FIG. 3D illustrating a circular heater, FIG. 3E illustrating an elliptical heater, and FIG. 3F illustrating another elliptical heater.
[0010] 4A to 4E illustrate, by means of successive diagrammatic side cross-sectional views, various steps for forming a probability bit including a thermally assisted MTJ structure.
[0011] 5A to 5F show, by means of diagrammatic perspective and side cross-sectional views, various detailed views of the MTJ heater of a probability bit produced by the steps depicted in FIG4A. FIG5B is a cross-sectional view along plane XX' (FIG5A), FIG5D is a cross-sectional view along plane YY' (FIG5C), and FIG5F is a cross-sectional view along plane YY' (FIG5E). Implementation
[0012] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first member formed on or above a second member may include embodiments in which the first and second members are formed to be in direct contact, and may also include embodiments in which additional members may be formed between the first and second members so that the first and second members may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.
[0013] Furthermore, for ease of description, spatially relative terms (such as "below", "beneath", "lower", "above", "upper" and the like) may be used herein to describe the relationship of one element or component to another element or components as depicted in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.
[0014] As used herein, the terms "surrounding" and "surrounds" or similar phrases refer to the perimeter of a heater or heater layer as disclosed herein, wherein the heater shape has a continuous boundary or perimeter that encloses or encloses a heating zone defined by a continuous segment or individual segments. Additionally, the terms "surrounding" and "surrounds" or similar phrases as used herein may include a heater shape that is not a continuous boundary or perimeter, and may include one or more discontinuities.
[0015] As used herein, the term "heated region" or similar phrases refers to a region or area that is heated by a heater or heater layer.
[0016] The terms "ring" and "heating zone" are not limited to a circular ring shape and include, but are not limited to, other geometric shapes, including circles, squares, rectangles, ellipses, other polygons, and other curved shapes.
[0017] The example embodiments described below relate to a thermally assisted probability bit structure and method of forming the same, including using a magnetic tunneling junction (MTJ) cell to store programmable probability bits (p bits) with appropriate randomness. These probability bits can be used as data storage in a quantum computing (QC) system.
[0018] A magnetoresistive random access memory (MRAM) cell is formed from a magnetic tunneling junction (MTJ) in which two ferromagnetic layers are separated by a thin insulating barrier, and a transistor operably connected to the MTJ to drive the MRAM cell by applying a potential difference across the two ferromagnetic layers. When a potential difference is applied across the two ferromagnetic layers, current flows through the insulating barrier by quantum mechanical tunneling. The resistance of the MTJ depends on the relative orientation of the magnetic elements in the two ferromagnetic layers. The resistance is lowest when the magnetizations are aligned parallel and highest when the magnetizations are antiparallel. One of the relative orientations can be used to represent a "1" and the other to represent a "0". Generally, the magnetic orientation of one of the layers (the pinned layer) remains fixed, while the magnetic orientation of the other layer (the free layer) is set during a write operation. The state of the MRAM cell can be interrogated by measuring the resistance of the junction. In order for an array of MRAM cells to provide reliable data storage, a sufficiently large resistance difference between the two possible states must be achieved for each cell in the array.
[0019] Conventional computing systems use deterministic bit structures that typically store either a "0" or a "1" value. Increasing the computing efficiency of a conventional computing system may require increasing storage (e.g., quantized as the number of bits) and the resulting power consumption. The efficiency of conventional computing systems is limited by storage and power consumption.
[0020] Quantum computing (QC) is used to significantly improve computing efficiency with low energy and fewer bits. Quantum computing systems use semiconductor structures or devices to store p bits. These are referred to as probability bit structures, or more simply probability bits, as described herein. Typically, probability bit structures operate at low temperatures (e.g., below 4K in some designs). This is problematic because it therefore requires cooling of the p-bit storage array, for example, typically using liquid helium as a coolant fluid to obtain temperatures below 4K.
[0021] The present disclosure and various non-limiting illustrative embodiments described herein provide a probability bit comprising an MRAM structure and a thermally coupled electrically controllable heater. One or more MTJ cells of the MRAM structure are heated to an elevated operating temperature (i.e., elevated relative to room temperature, typically considered to be about 20°C to 22°C). The elevated temperature increases the thermal fluctuation rate between the "0" value and the "1" value of the data stored in the MRAM. A probability bit stores a superposition of a "0" value and a "1" value and thus the thermal fluctuations in the disclosed p bits effectively provide the desired superposition of the "0" value and the "1" value, thereby achieving operation as a probability bit. As recognized herein, by increasing the operating temperature of the MRAM, the fluctuation rate can be advantageously significantly increased, thereby providing p bits with faster switching speeds. In the experimental examples provided herein, millisecond fluctuations were observed at an operating temperature of 150°C. Since thermal fluctuation rates generally scale approximately exponentially with increasing temperature, it is expected that increasing the operating temperature of the MRAM cell of the probability bit to about 200°C should advantageously provide thermal fluctuations of the stored values in the MRAM in the microsecond or nanosecond range. Furthermore, in the probability bit as disclosed herein, heating is provided locally by a (micro)heater, which can be formed, for example, as a ring heater tightly surrounding the MTJ or its bottom electrode vertical interconnect channel (BEVA), thereby achieving efficient heating of the MTJ of the probability bit only and thus advantageously low power consumption of the QC memory. Another advantage of the disclosed probability bit structures is that they do not need to be cooled to a cryogenic operating temperature, such as below 4K.
[0022] As discussed above, the use of QC significantly improves computational efficiency with low energy and fewer bits (<100) compared to conventional (i.e., von Neumann) computing architectures with deterministic bits (i.e., storing either a "0" or a "1" rather than a superposition of such values), which suffer from a bottleneck of low efficiency and high energy consumption compared to QC. However, in order to realize quantum computing, probabilistic bit structures (i.e., probabilistic bit devices) are required.
[0023] The present disclosure and embodiments described herein provide probability bit structures and methods of forming the same, which include one or more MTJ cells that are heated to implement a probability bit storing a qubit value that is a superposition of a "0" value and a "1" value represented by rapid thermally induced fluctuations of an MRAM between a "0" value and a "1" value. Advantageously, the disclosed probability bits can be operated at ambient room temperature (e.g., 20° C. to 22° C. in some typical buildings), wherein localized heating of the MTJ devices provides elevated MTJ temperatures, thereby enabling low power operation of the probability bit array.
[0024] Disclosed herein are random MTJ-based probabilistic bits (p bits) operating at an ambient temperature of about 25°C or less (e.g., ambient room temperature). The desired temperature of the random MTJ with microsecond to nanosecond retention is generated in these p bits by an MTJ cell heater. The current / voltage supplied to the MTJ heater comes from the peripheral circuitry.
[0025] An important characteristic of a probabilistic bit of a QC device is the superposition of a "0" and "1" state. In the MTJ-based probabilistic bit structure disclosed herein, a random MTJ with a short state holding time simulates the superposition within a specific time. For example, if the MTJ state holding time is 1 nsec, 1000 fluctuations ("0" à "1" and "1" à "0") occur within 2000 nsec. In other words, within this 2000 nsec time frame, from an observer's perspective, the "0" and "1" states are superimposed.
[0026] According to one aspect of the present disclosure, a MTJ cell is heated in situ by a ring heater, thereby performing random switching at room temperature. The ring heater provides substantially uniform heat distribution and thermally assists the MTJ cell to perform random switching at room temperature and can reduce the retention time to microseconds to nanoseconds at elevated MTJ cell temperatures (e.g., 200° C. or higher). Other ways to achieve a reduced retention time in the microsecond to nanosecond range may include modifying the MTJ by reducing the MTJ free layer thickness or reducing the MTJ size.
[0027] Referring to FIG. 1B , a graph of experimental switching data of an MTJ structure operating at 150° C. is depicted. The y-axis indicates the read current of the MTJ cell, and the x-axis indicates the retention time of the MTJ cell. As shown, the MTJ structure at 150° C. performs at a switching rate in the millisecond range. As previously described, increasing the operating temperature to about 200° C. is expected to advantageously provide thermal fluctuations of stored values in the MRAM in the microsecond or nanosecond range due to fluctuations scaling approximately exponentially with increasing temperature.
[0028] Referring to FIG. 1A , an example embodiment of a probability bit structure 1 including a thermally assisted MTJ structure 500 is illustrated. As shown in FIG. 1A , the probability bit structure includes a MOSFET transistor positioned in a MOSFET transistor region 100, a first intermetal dielectric (IMD) region 200 formed on the transistor region 100, and a second IMD region 300 formed on the first IMD region 200, the second IMD region 300 including an MTJ cell 502 and a heater arrangement 520. The MOSFET of the MOSFET transistor region 100 and the MTJ cell 502 are electrically connected to form a magnetoresistive random access memory (MRAM). Although the transistor region 100 described herein includes an MRAM using a planar MOSFET to form the probability bit, it should be understood that the probability bit structure is not limited to this particular semiconductor device, but other types of electronic devices may be used as drivers of the MRAM, such as a bipolar junction transistor (BJT), a FinFET, a gate all around (GAA) transistor, etc.
[0029] The MOSFET transistor region 100 includes a MOSFET including a raised gate 102 region, a source 101 region, and a drain 103 region formed on a Si substrate 104 by a known workflow of a lithography process, an etching process, a deposition process, a p- and n-doping process, and / or a polishing process. According to the example embodiment shown, the MOSFET gate 102 controls the MOSFET to turn on and off the MTJ cell 502, for example, for use as a word line associated with an MRAM cell read / write operation.
[0030] The first intermetal dielectric (IMD) region 200 formed above the transistor region 100 includes a transistor source via 202 electrically contacting the source region 101 and a transistor drain via 201 electrically contacting the transistor drain region 103, and a top patterned metallization layer including exemplary illustrative conductive traces 206 and 205 formed by known photolithography, etching, deposition, and polishing processes. A patterned metallization layer provides contacts for the source and drain vias.
[0031] An exemplary illustrative second IMD region 300 includes a bottom via 301, a bottom patterned metallization layer 305. It should be appreciated that in alternative embodiments, this layer 300 may be omitted, or instead may be repeated to provide multiple metallization layers with connecting vias.
[0032] The third IMD region 400 / 401 formed on the second IMD region 300 includes an MTJ cell 502, a heater 520 including a conductive loop, a top electrode vertical interconnect via (TEVA) 503, a bottom electrode vertical interconnect via (BEVA) 501 connected to the bottom patterned metallization layer 305, and a top patterned metallization layer 505. Although generally described as a third IMD region, this can be implemented as a plurality of IMD regions or manufactured using a plurality of IMD regions as appropriate.
[0033] The non-limiting illustrative example MTJ cell 502 includes a free layer 513, an insulator or barrier layer 512, and a fixed layer 511. The MTJ cell 502 is connected to the TEVA 503 and BEVA 501, which are connected to the top metallization layer 505 and the bottom metallization layer 305, respectively. The bottom metallization layer 305 provides the connection of the MTJ cell 502 to the MOSFET drain 103 for operation control by an external control device (not shown). The magnetic moment of the MTJ cell 502 can be in-plane or can be perpendicular.
[0034] As will be further described herein, the heater 520 includes a conductive loop surrounding the BEVA 501 (as shown in FIG. 1A ) or surrounding the MTJ 502 (e.g., see the alternative embodiment of FIG. 2B ), and the MTJ heater 520 is displaced a distance from the BEVA 501 (or from the MTJ if surrounding the MTJ configuration) and has a substantially continuous shape surrounding the BEVA 501 (or alternatively, surrounding the MTJ). The shape of the heater 520 is not limited to a particular geometry, but is a continuous or substantially continuous shape, such as but not limited to a circle, square, rectangle, ellipse, etc. When a voltage or current is applied to the heater 520 contacts (not shown in FIG. 1A ) by an external device (not shown), the heater 520 material radiates heat uniformly toward the BEVA 501 and raises the temperature of the MTJ cell 502, thereby providing a thermally assisted MTJ structure.
[0035] According to example embodiments of the disclosed probabilistic bit structures, the heater 520 may surround the BEVA 501 shown, surround multiple BEVAs of a multi-MTJ cell configuration, surround the MTJ cell 502, or surround multiple MTJ cells of a multi-MTJ cell configuration. In some non-limiting illustrative embodiments, the MTJ cell 502 free layer material is CoFeB, CoFe, FeB, CoB, NiFe, or NiFeMo; the insulator or barrier layer material is MgO or Al 2 O 3; and the fixed layer material is optionally multilayered and includes Co and Pt, Fe and Pt, Co and Pd, or Fe and Pd in some non-limiting illustrative embodiments. In some non-limiting illustrative embodiments, the heater material is W, Ti, Ta, Mo, WN, TiN, TaN, MoN, or graphene. In some non-limiting illustrative embodiments, the BEVA 501 and TEVA 503 materials are W, Ti, Ta, Mo, TiN, TaN, MoN, or Cu.
[0036] To control the heater 520, a switching device (not shown, such as an NMOS or other type of transistor, etc.) may be used to selectively turn on and off the heater 520. In addition to providing the switching device, a peripheral circuit (not shown) may also be provided to control a voltage / current applied to the heater 520. In various contemplated embodiments, the heaters 520 may be controlled individually, or more than one heater 520 associated with a plurality of MTJ cells may be controlled to turn on and off simultaneously.
[0037] 2A to 2C , cross-sectional views of example embodiments of a probability bit structure including a thermally assisted MTJ cell 502 are shown according to various non-limiting illustrative embodiments of the present disclosure. FIG. 2A is a first example embodiment of a probability bit structure including a thermally assisted MTJ cell 502, wherein a heater 520 surrounds the MTJ cell BEVA 501, FIG. 2B is a second example embodiment of a probability bit structure including a thermally assisted MTJ cell 502, wherein a heater 520 surrounds the MTJ cell 502, and FIG. 2C is a third example embodiment of a probability bit structure including a plurality of thermally assisted MTJ cells 502 and 602, wherein a heater 520 surrounds a plurality of MTJ cells BEVA 501 and 601.
[0038] As shown in FIG2A , this probability bit embodiment includes a thermally assisted MTJ cell 502, wherein a heater 520 surrounds the MTJ cell BEVA 501. The MTJ structure includes an IMD region 401, which includes an MTJ cell 502, a heater 520, a plurality of TEVAs 503, 531, 532, and 533, a BEVA 501, a bottom patterned metallization layer 305 and 306, and a top patterned metallization layer 505, 525, 526, and 527. In addition, the MTJ structure includes an insulating layer 527 sandwiched between the MTJ cell 502 and the heater 520, and another insulating layer 528 encapsulates the MTJ cell 502.
[0039] MTJ cell 502 includes a free layer 513, an insulator or barrier layer 512, and a fixed layer 511. MTJ cell 502 is connected to a TEVA 503 and a BEVA 501, which are connected to the top metallization layer 505 and the bottom metallization layer 305, respectively. According to an example embodiment, the bottom metallization layer 305 provides the connection of MTJ cell 502 to the MOSFET drain 103 for operation control by an external control device (not shown). The MOSFET and MTJ cell 502 are electrically connected to form a magnetoresistive random access memory (MRAM), as previously described with reference to FIG. 1A. The magnetic moment of MTJ cell 502 can be in-plane or can be perpendicular.
[0040] Additional TEVAs 531 and 532 provide connection of the heater 520 to an external control device to turn the heater 520 on and off. A further additional TEVA 533 connects the top metallization layer 527 to the bottom metallization layer 306 to facilitate a direct connection to an integrated control device or other structure, such as to a source 101 of a MOSFET used to control the MTJ cell 502.
[0041] As shown, the heater 520 is displaced or offset by a distance distBEVA from the BEVA 501. According to an example non-limiting illustrative embodiment, the distance distBEVA is greater than 80 nm to ensure sufficient distance to avoid electrical shunting between the heater 520 and the BEVA 501.
[0042] According to example embodiments of the disclosed probabilistic bit structures, the MTJ cell free layer 513 material is CoFeB, CoFe, FeB, CoB, NiFe, or NiFeMo in some non-limiting illustrative embodiments; the insulator or barrier layer material is MgO or Al2O3 in some non-limiting illustrative embodiments; and the fixed layer material is optionally multilayered and includes Co and Pt, Fe and Pt, Co and Pd, or Fe and Pd in some non-limiting illustrative embodiments. In some non-limiting illustrative embodiments, the heater material is W, Ti, Ta, Mo, WN, TiN, TaN, MoN, or graphene. In some non-limiting illustrative embodiments, the BEVA and TEVA materials are W, Ti, Ta, Mo, TiN, TaN, MoN, or Cu.
[0043] According to example embodiments of the disclosed probabilistic bit structures, the thickness of the MTJ cell free layer 513 material is between about 2 nm and about 5 nm in some non-limiting illustrative embodiments, the thickness of the insulator or barrier layer 512 material is between about 1 nm and about 2 nm in some non-limiting illustrative embodiments, and the thickness of the fixed layer material is between about 5 nm and about 15 nm in some non-limiting illustrative embodiments.
[0044] According to example embodiments of the disclosed probabilistic bit structure, the thickness of the MTJ heater 520 is between about 50 nm and about 300 nm, and the dimensions (length / width) of the heater 520 are between about 50 nm and about 300 nm in some non-limiting illustrative embodiments. The heater current to operate the heater 520 to achieve the desired MTJ cell temperature depends on the dimensions and materials of the heater 520. For switching speeds in the microsecond or nanosecond range, in some non-limiting illustrative embodiments, the target MTJ cell temperature is 200°C, and the heater current may be at least >500 uA, although these are also merely illustrative values that may vary or be different depending on the construction of the heater 520.
[0045] As shown in FIG2B , this probability bit embodiment includes a thermally assisted MTJ cell 502, wherein a heater 520 surrounds the MTJ cell 502. The MTJ structure includes an IMD region 401, which includes an MTJ cell 502, a heater 520, a plurality of TEVAs 503, 531, 532, and 533, a BEVA 501, a bottom patterned metallization layer 305 and 306, and a top patterned metallization layer 505, 525, 526, and 527. In addition, the MTJ structure includes an insulating layer 527 sandwiched between the MTJ cell 502 and the heater 520, and another insulating layer 528 encapsulates the MTJ cell 502.
[0046] MTJ cell 502 includes a free layer 513, an insulator or barrier layer 512, and a fixed layer 511. MTJ cell 502 is connected to a TEVA 503 and a BEVA 501, which are connected to the top metallization layer 505 and the bottom metallization layer 305, respectively. According to an example embodiment, the bottom metallization layer 305 provides the connection of MTJ cell 502 to the MOSFET drain 103 for operation control by an external control device (not shown). The MOSFET electrically connected to MTJ cell 502 forms MRAM, as previously described with reference to FIG. 1A. The magnetic moment of MTJ cell 502 can be in-plane or can be perpendicular.
[0047] Additional TEVAs 531 and 532 provide connection of heater 520 to an external control device to turn the heater on and off. A further additional TEVA 533 connects top metallization layer 527 to bottom metallization layer 306 to facilitate a direct connection to an integrated control device or other structure, such as to a source 101 of a MOSFET used to control MTJ cell 502.
[0048] 2B, the heater 520 is displaced or offset by a distance distMTJ from the MTJ cell 502. According to an example non-limiting illustrative embodiment, the distance distMTJ is greater than 50 nm to ensure sufficient distance to avoid electrical shunting between the heater 520 and the MTJ cell 502.
[0049] According to example embodiments of the disclosed probabilistic bit structures, the MTJ cell free layer material is CoFeB, CoFe, FeB, CoB, NiFe or NiFeMo in some non-limiting illustrative embodiments; the insulator or barrier layer material is MgO or Al2O3 in some non-limiting illustrative embodiments; and the fixed layer material is optionally multilayered and includes Co and Pt, Fe and Pt, Co and Pd or Fe and Pd in some non-limiting illustrative embodiments. The heater material is W, Ti, Ta, Mo, WN, TiN, TaN, MoN or graphene. The BEVA and TEVA materials are W, Ti, Ta, Mo, TiN, TaN, MoN or Cu.
[0050] According to example embodiments of the disclosed probabilistic bit structures, the thickness of the MTJ cell free layer 513 material is between about 2 nm and about 5 nm in some non-limiting illustrative embodiments, the thickness of the insulator or barrier layer 527 material is between about 1 nm and about 2 nm in some non-limiting illustrative embodiments, and the thickness of the fixed layer 611 material is between about 5 nm and about 15 nm in some non-limiting illustrative embodiments.
[0051] According to example embodiments of the disclosed probabilistic bit structures, the thickness of the MTJ heater 520 is between about 50 nm and about 300 nm in some non-limiting illustrative embodiments, and the size (length / width) of the heater 520 is between about 50 nm and about 300 nm in some non-limiting illustrative embodiments. The heater current to operate the heater 520 to achieve the desired MTJ cell temperature depends on the size and material of the heater 520. For switching speeds in the microsecond or nanosecond range, in some non-limiting illustrative embodiments, the target MTJ cell temperature is 200°C, and the heater current may be at least >500 uA, although these are also merely illustrative values that may vary or be different depending on the construction of the heater 520.
[0052] As shown in FIG2C , this probability bit embodiment includes a plurality of thermally assisted MTJ cells 502 and 602 and respective BEVAs 501 and 601, wherein a heater 520 surrounds the plurality of BEVAs 501 and 601 associated with the MTJ cells. (In another variant embodiment, similar to the embodiment of FIG2B , the heater may surround a plurality of MTJ cells).
[0053] 2C includes an IMD region 401 including a first MTJ cell 502, a second MTJ cell 602, a heater 520, a plurality of TEVAs 503, 531, 532, and 533, a first and second BEVA 501 and 601, a bottom patterned metallization layer 305, 306, and 307, and a top patterned metallization layer 505, 525, 526, 527, and 605. In addition, the MTJ structure includes an insulating layer 527 sandwiched between the first MTJ cell 502 and the second MTJ cell 602, a heater 520, and another insulating layer 528 encapsulating the MTJ cells.
[0054] Each of the MTJ cells 502 and 602 includes a free layer 513, 613, an insulator or barrier layer 512, 612, and a fixed layer 511, 611. Each of the MTJ cells is connected to a TEVA 503, 603 and a BEVA 501, 601, which are connected to the top metallization layer 505, 605 and the bottom metallization layer 305, 307, respectively. According to an example embodiment, the bottom metallization layer 305, 307 provides each of the first and second MTJ cells 502, 602 with connection to a common or individual MOSFET drain for operational control by an external control device (not shown) to form one or more MRAM devices of probability bits (although other types of transistors or other types of drive electronics for forming MRAM configurations are also contemplated). The magnetic moment of the MTJ cells can be in-plane or can be perpendicular.
[0055] Additional TEVAs 531 and 532 provide connection of heater 520 to an external control device to turn heater 520 on and off. A further additional TEVA 533 connects top metallization layer 527 to bottom metallization layer 306 to facilitate a direct connection to an integrated control device or other structure, such as to a source 101 of a MOSFET used to control the MTJ cell.
[0056] 2C, the heater 520 is displaced or offset by a distance distBEVA from each of the BEVAs 501 and 601. According to an example non-limiting illustrative embodiment, the distance distBEVA is greater than 80 nm to ensure sufficient distance to avoid electrical shunting between the heater 520 and the BEVAs 501 and 601.
[0057] According to example embodiments of the disclosed probabilistic bit structures, the MTJ cell free layer 513 material is CoFeB, CoFe, FeB, CoB, NiFe, or NiFeMo in some non-limiting illustrative embodiments; the insulator or barrier layer material is MgO or Al2O3 in some non-limiting illustrative embodiments; and the fixed layer material is optionally multilayered and includes Co and Pt, Fe and Pt, Co and Pd, or Fe and Pd in some non-limiting illustrative embodiments. In some non-limiting illustrative embodiments, the heater material is W, Ti, Ta, Mo, WN, TiN, TaN, MoN, or graphene. In some non-limiting illustrative embodiments, the BEVA and TEVA materials are W, Ti, Ta, Mo, TiN, TaN, MoN, or Cu.
[0058] According to example embodiments of the disclosed probabilistic bit structures, the thickness of the MTJ cell free layer 513, 613 material is between about 2 nm and about 5 nm in some non-limiting illustrative embodiments, the thickness of the insulator or barrier layer 512, 612 material is between about 1 nm and about 2 nm in some non-limiting illustrative embodiments, and the thickness of the fixed layer 511, 611 material is between about 5 nm and about 15 nm in some non-limiting illustrative embodiments.
[0059] 3A-3F illustrate top views of example embodiments of a heater according to the present disclosure.
[0060] As previously described, the heater 520 can have various layouts. FIGS. 3A-3F show some non-limiting illustrative embodiments of the heater 520 by way of isolated top views. In the following description of the embodiments with reference to FIGS. 3A-3F , all heater dimensions should be understood as non-limiting illustrative examples. FIG. 3A depicts a square heater 520 with a heater 520 segment having a thickness of 50 nm to 300 nm, a width Hwidth=150 nm to 300 nm, and a length Hlength=150 nm to 300 nm.
[0061] FIG. 3B illustrates a rectangular heater 520 , with the thickness of the heater 520 segment being 50 nm to 300 nm, the width Hwidth=150 nm to 300 nm, and the length Hlength=300 nm to 500 nm.
[0062] FIG. 3C shows another rectangular heater 520 , the thickness of the heater 520 segment is 50 nm to 300 nm, the width Hwidth=300 nm to 500 nm, and the length Hlength=150 nm to 300 nm.
[0063] FIG. 3D shows a circular heater 520 , wherein the thickness of the continuous section of the heater 520 is 50 nm to 300 nm, and the diameter Hdiameter=150 nm to 300 nm.
[0064] FIG. 3E illustrates an elliptical heater 520 , wherein the thickness of the continuous section of the heater 520 is 50 nm to 300 nm, the major axis length Hlength=300 nm to 500 nm, and the minor axis length Hwidth=150 nm to 300 nm.
[0065] FIG. 3F shows another elliptical heater 520 , the thickness of the continuous section of the heater 520 is 50 nm to 300 nm, the major axis length Hwidth=300 nm to 500 nm, and the minor axis length Hlength=150 nm to 300 nm.
[0066] The illustrative heater 520 embodiment of FIGS. 3A-3F includes a single conductive loop surrounding a BEVA or MTJ; however, it is contemplated that the heater includes two or more conductive loops surrounding a BEVA or MTJ, wherein the multiple loops provide increased thermal heating.
[0067] 4A to 4E illustrate various steps for forming a probabilistic bit structure according to the present disclosure by means of successive diagrammatic side cross-sectional views, the probabilistic bit structure comprising a thermally assisted MTJ structure including a heater surrounding an MTJ cell BEVA (Example 1). In the following description of the fabrication process depicted in FIGS. 4A to 4E , all heater dimensions and materials should be understood as non-limiting illustrative examples. FIG. 4A shows the device structure after processing steps including etching a SiO2 intermetallic dielectric (IMD) layer / region, depositing a heater material, and performing chemical mechanical polishing (CMP); FIG. 4B shows the device structure after further processing steps including depositing a SiNx insulating layer, etching the insulating layer and the SiO2 intermetallic dielectric (IMD) layer / region, depositing a TaN / TiN BEVA, and performing CMP; FIG. 4C shows the device structure after further processing steps including an MTJ cell deposition process, etching the MTJ cell, and depositing a SiNx insulating layer to encapsulate the MTJ cell; FIG. 4D shows the device structure after further processing steps including depositing a SiO2 intermetallic dielectric (IMD) layer / region to encapsulate the MTJ cell and the previously deposited insulating layer, and performing CMP; and FIG. 4E shows the device structure after further processing steps including etching and deposition to form multiple TEVAs. The device structure after further processing steps of depositing a top metallization layer for connecting the MTJ structure to a voltage / current source to operate the heater and for read / write operations associated with the MTJ cell (similar to the formation of BEVA). The non-limiting illustrative manufacturing process described above in Figures 4A to 4E is described in further detail below.
[0068] It should be understood that the MTJ structure is formed on an interconnect structure that has been previously deposited on another semiconductor structure (such as a transistor, i.e., MOSFET), which forms an MRAM with the MTJ after forming the MTJ structure on the transistor region, as will be described with reference to Figures 4A to 4E. For example, a MOSFET as shown in Figure 1A is formed on a Si substrate (104, see Figure 1A) using a known process. The substrate 104 can be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. One or more shallow trench isolation (STI) regions can include a dielectric-filled trench in the substrate 104.
[0069] A wordline transistor may be disposed between the STI regions. The wordline transistor includes a wordline gate electrode and a wordline source / drain region, and may include other regions, such as a wordline gate dielectric, a wordline sidewall spacer, etc. The source / drain region is disposed between the wordline gate electrodes in the substrate and is doped to have a first conductivity type that is opposite to a second conductivity type of a channel region below a gate dielectric. The wordline gate electrode may be, for example, doped polysilicon or a metal such as aluminum, copper, or a combination thereof. The wordline gate dielectric may be, for example, an oxide (such as silicon dioxide) or a high-K dielectric material. For example, the wordline sidewall spacer may be made of silicon nitride (e.g., Si 3 N 4 ).
[0070] The interconnect structure is disposed on the substrate and couples devices (e.g., transistors and MTJ structures) to each other. The interconnect structure may include a plurality of IMD layers and a plurality of metallization layers stacked on top of each other in an alternating manner. The IMD layers may be made of, for example, a low-K dielectric (such as undoped silicate glass) or an oxide (such as silicon dioxide) or an extremely low-K dielectric layer. The metallization layer includes metal lines formed in the trenches and may be made of a metal (such as copper or aluminum). Contacts that will connect to the metallization layer contacts shown in the MTJ structure of FIG. 4A extend from the IMD bottom metallization layer to the source / drain region; and vias may extend between the metallization layers. The contacts and vias extend through dielectric capping layers (which may be made of dielectric material and may serve as an etch stop layer during manufacturing). The dielectric capping layer may be made of an extremely low-K dielectric material (such as, for example, SiC). The contacts and vias may be made of a metal (such as, for example, copper or tungsten).
[0071] An MRAM cell including an MTJ cell as disclosed herein is configured to store respective data states, disposed in an interconnect structure between adjacent metal layers, as shown in FIGS. 4A to 4E . As will be further described below, the MRAM cell includes a bottom electrode and a top electrode made of a conductive material. The MRAM cell includes an MTJ between its top and bottom electrodes. The MRAM cell may also include MRAM sidewall spacers.
[0072] In summary, the above paragraphs describe forming a transistor (such as a MOSFET) on a Si substrate, further including forming one (several) interconnect structures connected to the contacts shown in the MTJ structure shown in Figure 4A. In addition, a MTJ SiO2IMD (Figure 4A) is formed on top of this previously formed structure, which also includes the electrical metallization layer contacts shown in Figure 4A.
[0073] Referring to FIG. 4A , there is shown the steps of forming an MTJ structure by etching the SiO 2 intermetal dielectric (IMD) layer / region 400 and depositing a heater 520 material, as previously described herein. Additionally, after depositing the heater 520 material, the process performs chemical mechanical polishing (CMP) on the top surface. Suitable heater materials include W, Ti, Ta, Mo, WN, TiN, TaN, MoN, or graphene.
[0074] 4B, there are shown the steps of depositing a SiNx insulating layer 527, etching the insulating layer 527 and the SiO2 intermetal dielectric (IMD) layer / region 400, depositing TaN / TiN BEVA 501, and performing chemical mechanical polishing on the top surface insulating layer 527. Other suitable BEVA materials include W, Ti, Ta, Mo, TiN, TaN, MoN or Cu.
[0075] Referring to FIG. 4C , there are shown the steps of depositing an MTJ cell 502, etching the MTJ cell 502, and depositing a SiNx insulating layer 528 that encapsulates the MTJ cell 502. The MTJ cell formation process includes forming an MTJ stack, including depositing multiple layers to produce a fixed layer 511, an insulator 512, and a free layer 513. These layers can be formed using a photoresist mask, other known lithography, deposition, and etching processes. Suitable MTJ cell free layer 513 materials include CoFeB, CoFe, FeB, CoB, NiFe, or NiFeMo; suitable insulator or barrier layer 512 materials include MgO or Al 2 O 3; and suitable fixed multilayer materials 511 include Co and Pt, Fe and Pt, Co and Pd, or Fe and Pd.
[0076] 4D where a SiO 2 inter-metal dielectric (IMD) layer / region 401 is deposited to encapsulate the MTJ cell 502 and the previously deposited insulating layer 528 and CMP is performed on the top surface of the deposited IMD 401 .
[0077] 4E, there is shown the steps of etching and depositing to form a plurality of TEVAs 503, 531, 532 and 533 (similar to the formation of BEVA 501) and depositing top metallization layers 505, 525, 526 and 527 for connecting the MTJ structure to a voltage / current source to operate the heater 520 and for read / write operations associated with the MTJ cell 502. Suitable TEVA materials include SiO2, W, Ti, Ta, Mo, TiN, TaN, MoN or Cu.
[0078] 5A-5F are various other detailed views of the MTJ heater 520 produced by the steps depicted in FIG4A. FIG5B is a cross-sectional view of the heater 520 taken along the plane XX' shown in FIG5A. FIG5D is a cross-sectional view of the heater 520 taken along the plane YY' shown in FIG5C. FIG5F is a cross-sectional view of the heater 520 taken along the plane YY' shown in FIG5E.
[0079] Some further embodiments are described below.
[0080] In a non-limiting illustrative embodiment, a probability bit structure includes: a transistor; a magnetic tunneling junction (MTJ) operably connected to the transistor via a bottom electrode vertical interconnect (BEVA) to form a magnetoresistive random access memory (MRAM); and a heater including at least one conductive loop surrounding the MTJ or the BEVA.
[0081] In a non-limiting illustrative embodiment, a method of forming a probabilistic bit structure includes: forming a transistor region on a substrate; forming a first intermetallic dielectric (IMD) region on the substrate and the transistor region; forming a magnetic tunneling junction (MTJ) structure on the first IMD region, the MTJ structure including: an MTJ cell including an insulating layer formed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) formed and connected to the MTJ cell; a bottom electrode vertical interconnect channel (BEVA) formed and connected to the MTJ cell; a heater formed between the first IMD region and the TEVA; and a metallization layer first contact and a metallization layer second contact formed and connected to the heater, wherein when a voltage or current is applied to the metallization layer first and second contacts, the heater heats the MTJ structure.
[0082] In a non-limiting illustrative embodiment, a magnetic tunneling junction (MTJ) structure includes: an MTJ cell, which includes an insulating layer disposed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) connected to the MTJ cell; a bottom electrode vertical interconnect channel (BEVA) connected to the MTJ cell; and a heater, which includes at least one conductive loop surrounding the MTJ cell or the BEVA.
[0083] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.
[0084] 1: Probability bit structure 100: MOSFET transistor area 101: Source region / source 102: Raised gate region 103: Transistor drain region / MOSFET drain 104:Si substrate 200: first intermetal dielectric (IMD) region 201: Transistor drain path 202: Transistor source path 205: Conductive traces 206: Conductive traces 300: Second IMD area 301: Bottom channel 305: Bottom patterned metallization layer 306: Bottom patterned metallization layer 307: Bottom patterned metallization layer 400: Third IMD region / SiO2 intermetallic dielectric (IMD) layer / region 401: Third IMD region / SiO2 intermetallic dielectric (IMD) layer / region 500: Thermally Assisted Magnetic Tunneling Junction (MTJ) Structure 501: Bottom electrode vertical interconnect channel (BEVA) / MTJ unit BEVA / first BEVA or TaN / TiN BEVA 502: thermally assisted MTJ unit / first MTJ unit 503: Top Electrode Vertical Interconnect Via (TEVA) 505: Top patterned metallization layer 511:Fixed layer / Fixed multi-layer material 512: insulator or barrier layer 513: Free Layer 520: Heater Configuration / Heater / MTJ Heater 525: Top patterned metallization layer 526: Top patterned metallization layer 527: Top patterned metallization layer / insulation layer 528: Insulation layer / SiN x insulation layer 531:TEVA 532:TEVA 533:TEVA 601: MTJ unit BEVA / second BEVA 602: Thermally assisted MTJ unit / second MTJ unit 603:TEVA 605: Top patterned metallization layer 611: Fixed layer 612: Insulator or barrier layer 613: Free Layer distBEVA: distance distMTJ: distance Hdiameter: diameter Hlength: length / major axis length / minor axis length Hwidth: width / minor axis length / major axis length
Claims
1. A probabilistic bit structure comprising: a transistor; a magnetic tunneling junction (MTJ) operatively connected to the transistor via a bottom electrode vertical interconnect (BEVA) to form a magnetoresistive random access memory (MRAM); a heater including at least one conductive loop surrounding the MTJ or the BEVA; and a first electrical contact and a second electrical contact disposed on opposite sides of the MTJ and connected to the heater, wherein the MTJ includes an insulating layer disposed between a free layer and a fixed layer, and the MTJ has an in-plane magnetic moment or a vertical moment.
2. The probability bit structure of claim 1, wherein the at least one conductive circuit of the heater is shaped into a square, rectangle, circle or ellipse.
3. The probability bit structure of claim 1, further comprising: a substrate; a transistor region disposed on the substrate and including the transistor; a first intermetallic dielectric (IMD) region disposed on the substrate and the transistor region; an MTJ structure disposed on the first IMD region, the MTJ structure including the MTJ, a top electrode vertical interconnect channel (TEVA) connected to the MTJ, a BEVA connected to the MTJ, and a heater, wherein the heater heats the MTJ structure when a voltage or current is applied to the first and second electrical contacts.
4. As in the probability bit structure of Request 1, wherein the free layer material is one of CoFeB, CoFe, FeB, CoB, NiFe or NiFeMo, the insulating layer material is one of MgO or Al2O3, and the fixed layer material is one of multiple layers including Co and Pt, Fe and Pt, Co and Pd or Fe and Pd.
5. The probability bit structure of claim 1, wherein the at least one conductive loop of the heater surrounds the BEVA.
6. A method for forming a probabilistic bit structure, the method comprising: forming a transistor region on a substrate; forming a first intermetallic dielectric (IMD) region on the substrate and the transistor region; and forming a magnetic tunneling junction (MTJ) structure on the first IMD region, the MTJ structure comprising: An MTJ cell includes an insulating layer formed between a free layer and a fixed layer, and the MTJ cell has an in-plane magnetic moment or a vertical moment; a top electrode vertical interconnect channel (TEVA) formed and connected to the MTJ cell; a bottom electrode vertical interconnect channel (BEVA) formed and connected to the MTJ cell; a heater formed between the first IMD region and the TEVA; and a first metallization layer contact and a second metallization layer contact respectively disposed on opposite sides of the MTJ cell, and formed and connected to the heater, wherein when a voltage or current is applied to the first and second metallization layer contacts, the heater heats the MTJ structure.
7. The method of claim 6, wherein 1) the heater is formed to surround at least a portion of the BEVA and the heater is positioned at a distance of more than 80 nm from the BEVA, or 2) the heater is formed to surround at least a portion of the MTJ cell and the heater is positioned at a distance of more than 50 nm from the MTJ cell.
8. The method of claim 6, wherein 1) the heater comprises W, Ti, Ta, Mo, WN, TiN, TaN, MoN or graphene, 2) the free layer material is one of CoFeB, CoFe, FeB, CoB, NiFe or NiFeMo, 3) the insulating layer material is one of MgO or Al2O3, 4) the fixed layer material is one of a multilayer comprising Co and Pt, Fe and Pt, Co and Pd or Fe and Pd, and 5) the TEVA material and BEVA material are one of W, Ti, Ta, Mo, TiN, TaN, MoN or Cu.
9. A magnetic tunneling junction (MTJ) structure comprising: an MTJ unit including an insulating layer disposed between a free layer and a fixed layer, and the MTJ unit having an in-plane magnetic moment or a vertical moment; a top electrode vertical interconnect channel (TEVA) connected to the MTJ unit; a bottom electrode vertical interconnect channel (BEVA) connected to the MTJ unit; a heater including at least one conductive loop surrounding the MTJ unit or the BEVA; and a first electrical contact and a second electrical contact respectively disposed on opposite sides of the MTJ unit and connected to the heater.
10. The magnetic tunneling junction (MTJ) structure of claim 9, wherein the heater includes at least one conductive loop surrounding the MTJ unit.