Electrically erasable programmable nonvolatile memory cell

Abstract

An electrically erasable programmable non-volatile memory cell includes: a semiconductor substrate having a bit line region, a surface region spaced apart from the bit line region in a lateral direction, and a trench region spaced apart from the surface region in the lateral direction, the trench region including a bottom portion and a sidewall portion adjacent to a trench in the semiconductor substrate; a conductive control gate; a conductive word line; and a floating gate insulated from the substrate and the word line, and including: a first tip substantially aligned with the sidewall portion of the trench region of the substrate; and a second tip self-aligned with an edge of the word line furthest from a second portion of the control gate.

Description

NOR Memory Cell with a Floating Gate This disclosure generally relates to semiconductor memory devices, including but not limited to electrically programmable and erasable non-volatile memory cells having a floating gate, sometimes referred to as NOR memory cells. When programming an array of non-volatile semiconductor memory cells (e.g., conventional stacked-gate memory cells where each memory cell has a floating gate and a control gate), in order to "inject" electrons onto the floating gate, the accelerated electrons traveling in the depletion region and at least partially away from the floating gate must collide with impurities or lattice defects in the substrate to generate momentum in the direction toward the floating gate. In addition, only those electrons having sufficient energy in the direction of the floating gate to overcome the energy barrier at the silicon oxide interface (i.e., the substrate-gate oxide interface) plus the potential change across the floating gate oxide will be injected onto the floating gate. As a result, the efficiency of the programming operation highly depends on the direction and energy of the programming electrons. The electric field within the memory cell may interfere with the traveling direction of electrons during the programming operation. Such fields may pull the electrons in a direction that is not optimal for injection onto the floating gate. The memory cell structure can be adjusted to overcome the competing electric fields and maintain an optimal electron traveling direction during the programming operation. However, such adjustments may affect the threshold voltage of a particular gate in a way that adversely affects other operations of the memory cell. For example, the read current is sensitive to the control gate voltage threshold value. Thus, optimizing the memory cell for programming efficiency may make the memory cell less efficient during other operations, thereby presenting a design trade-off. Accordingly, there is a need to improve the programming efficiency of non-volatile memory cells in a manner that minimizes the impact on other operations. The present invention describes devices and methods configured to increase programming efficiency while maintaining a sufficiently high read current when erasing the cells. The memory cell structure as described herein includes a plurality of indium implants strategically placed throughout the substrate of the memory cell. These implants, in combination with the particular architecture of the memory cell, advantageously address the trade-off between programming efficiency and the threshold voltage that affects the read current. According to some embodiments, an electrically erasable programmable non-volatile memory cell, sometimes referred to as a NOR memory cell, includes: a semiconductor substrate having a bit line region, a surface region spaced from the bit line region in a lateral direction, and a trench region spaced from the surface region in the lateral direction, the trench region including a bottom portion and a sidewall portion adjacent to a trench in the semiconductor substrate; a conductive control gate including: a first portion disposed inside the trench, insulated from the bottom portion and the sidewall portion of the trench region of the substrate, and spaced from the sidewall portion of the trench region by a first distance in the lateral direction; and a second portion disposed above the trench and extending away from the trench; a conductive word line insulated from the control gate and offset from the second portion of the control gate by a second distance greater than the first distance in the lateral direction; a tantalum nitride floating gate insulated from the substrate and the word line and including: a first end substantially aligned with the sidewall portion of the trench region of the substrate; and a second end aligned with an edge of the word line farthest from the second portion of the control gate. In some embodiments, the electrically erasable programmable non-volatile memory cell includes two or more of the following: a first indium implant disposed in a region of the substrate below the bottom portion of the trench region; a second indium implant disposed in a region of the substrate adjacent to the sidewall portion and the surface region of the substrate; and a third indium implant disposed in a region of the substrate adjacent to a lower portion of a source or drain node of the memory cell. Related Applications This application claims the benefit of U.S. Provisional Patent Application No. 63 / 443,343, filed Feb. 3, 2023, and U.S. Provisional Patent Application No. 63 / 626,450, filed Jan. 29, 2024. Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. However, it will be apparent to one of ordinary skill in the art that the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure the scope of the embodiments. It will also be understood that, although in some cases the terms first, second, etc. are used herein to describe various elements, such elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various described embodiments, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact. Both the first contact and the second contact are contacts, but they are not the same contact unless the context clearly indicates otherwise. The terms used in the description of the various embodiments described herein are for the purpose of describing particular embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, as used in the description of the various embodiments and the appended claims, the singular forms "a" and "the" are also intended to include the plural forms. The terms "first", "second", etc. are only used to distinguish one element from another and do not limit the element itself. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It should be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "if" is interpreted, depending on the context, to mean "when" or "after" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if a determination" or "if [a stated condition or event] is detected" is interpreted, depending on the context, to mean "after a determination" or "in accordance with a determination" or "in response to a determination" or "after [a stated condition or event] is detected" or "in response to [a stated condition or event] being detected". Unless otherwise stated, all distances, material thicknesses, voltages, and currents included in the following description are examples and should be assumed to be specified within a tolerance of ten percent. For example, unless otherwise stated, the stated distance or thickness of 200 Å includes a 10% margin and thus includes a range of 180 Å to 220 Å. Attention is now directed to embodiments of an electrically erasable programmable non-volatile memory cell (sometimes referred to as a NOR memory cell or a split-gate NOR memory cell) according to some embodiments. FIG. 1 is a cross-section of a pair of memory cells 100, 101. These memory cells are mirror images of each other, with one memory cell formed on each side of a shared control / erase gate 120 and including the shared control / erase gate. For simplicity, the remainder of the present invention will only refer to one memory cell, namely memory cell 100. However, it should be understood that the mirror-image memory cell 101 (the adjacent memory cell) has corresponding features and behaves similarly in similar situations. In some embodiments, memory cell 100 includes: a semiconductor substrate 102 having a bit line region 104 (sometimes referred to as a drain region or a source region), a surface region 106 laterally spaced from the bit line region, and a trench region 108a / 108b laterally spaced from the surface region, the trench region including a bottom portion 108a adjacent to the bottom surface of a trench 109 in the substrate 102 and a sidewall portion 108b adjacent to the sidewall of the trench 109. In some embodiments, the sidewall portion 108b of the trench region is substantially perpendicular to the surface 111 of the substrate. In some embodiments, the bit line region 104 serves as a drain or a source; it should be understood that the drain and the source of a transistor can be switched during operation. Further, in some embodiments, the bit line region 104 includes a substrate region 105, which is a shallower doped region than the bit line region 104 (e.g., a moderately N-doped region in a P-doped substrate). In some embodiments, the region 105, sometimes referred to as an LDD region, is not moderately N-doped, thereby increasing the threshold voltage required to conduct current through a channel (along the surface of the substrate) between the bit line region 104 and the bit line region of another memory cell. The substrate 102 further includes a surface region 106. The surface region 106 is disposed between the bit line region 104 and the trench sidewall portion 108b. The substrate 102 further includes a horizontal surface 111, which is disposed above the bit line region 104 and extends laterally toward the trench sidewall portion 108b. The surface region 106 includes a portion of the surface 111 between the bit line region 104 and the trench sidewall portion 108b. In some embodiments, at least a portion of the surface 111 is a silicon oxide interface (e.g., between a silicon substrate and an oxide-based insulating region). For the purposes of the present invention, the term "trench" describes a region (109) from which substrate material (102) has been removed and thus where no substrate material exists, while the terms "trench region" (108a / 108b), "bottom portion" (108a), and "sidewall portion" (108b) describe regions of the substrate 102 adjacent to the trench 109. In some embodiments, the memory cell 100 further includes a conductive control / erase gate 120 (alternatively referred to as a control gate or an erase gate). Depending on the operating mode of the memory cell 100, the control / erase gate 120 acts as a control gate or an erase gate. For example, when the memory cell 100 (specifically, the floating gate 150) is being written or read, the gate 120 acts as a control gate, and when the memory cell 100 (specifically, the floating gate 150) is being erased, the gate 120 acts as an erase gate. The control / erase gate 120 includes a first portion 122 that is disposed inside the trench 109, insulated from the bottom portion 108a and the sidewall portion 108b of the trench region of the substrate 102, and spaced apart from the trench sidewall portion 108b by a first distance A in the lateral direction. The control / erase gate 120 further includes a second portion 124 that is disposed above the first portion 122 and extends away from the trench 109. In some embodiments, the first control / erase gate portion 122 and the second control / erase gate portion 124 are heavily doped (e.g., n+) polysilicon, or alternatively are (or include) metal (e.g., tungsten). In some embodiments, the second control / erase gate portion 124 includes a region 124a that extends in the lateral direction at the end of the memory cell 100 that is farthest from the substrate 102. Since the region 124a is substantially orthogonal to the first portion 122 and the lower region of the second portion 124 of the control / erase gate 120 (e.g., forms an angle between 45 o and 135 o degrees), the control / erase gate 120 can be referred to as a T-shaped gate. In some embodiments, the region 124a includes a self-aligned metal silicide (sometimes referred to as a self-aligned silicide), which increases the conductivity of the control / erase gate. In other words, a metal contact (silicide) is added on top of the region 124a for providing a signal or a reference voltage to the control / erase gate 120 and for increasing the conductivity of the control / erase line. In some embodiments, the memory cell 100 further includes a conductive word line 130 (optionally referred to as a gate), which is insulated from the control / erase gate 120 and offset by a second distance B greater than the first distance A from the second portion of the control / erase gate 124 in the lateral direction. The word line 130 is further disposed above the floating gate 150 and insulated from the floating gate. In some embodiments, the memory cell 100 further includes a conductive floating gate 150 that is insulated from the substrate 102 and the word line 130. The floating gate 150 includes a first end 152 that is generally aligned with a sidewall portion 108b of the trench region of the substrate 102 (more specifically, generally aligned with the sidewall of the trench); and a second end 154 that is self-aligned with an edge 132 of the word line 130 that is farthest from a second portion 124 of the control / erase gate. In some embodiments, the first end 152 of the floating gate includes a sharp tip, a portion of which has a cross-section smaller than the cross-section of the second end 154 of the floating gate. In some embodiments, the floating gate 150 is generally parallel to the surface 111 of the substrate. In some embodiments, the capacitive coupling between the floating gate 150 and the control / erase gate 120 is extremely small because the thickness of the floating gate is extremely thin, such as 20 Å or less; thus, the cross-sectional area of the floating gate end 152 facing the control / erase gate 120 is much smaller than the cross-sectional area of the word line 130 disposed on top of the floating gate 120. This small capacitive coupling combined with a wider spacing B (between the control / erase gate 120 and the word line 130) relative to the spacing A (between the control / erase gate 120 and the floating gate 150) enables the thin floating gate edge 152 to act as an efficient tunneling injector. As a result, the erase operation requires a relatively low voltage, as described in detail below with reference to FIG. 2. In some embodiments, the memory cell 100 further includes a dielectric layer 140 between the floating gate 150 and the word line 130. The dielectric layer 140 is a "thin" dielectric layer to provide strong capacitive coupling between the floating gate 150 and the word line 130. In some embodiments, the dielectric layer 140 includes an oxide, a nitride, a combination of an oxide and a nitride, or other high dielectric constant materials. In some embodiments, the dielectric layer 140 has a combined total thickness between 8 nm and 10 nm. In some embodiments, due to the manufacturing process, the dielectric layer 140 includes a first portion 142 that is generally aligned with the first end 152 of the floating gate and the sidewall portion 108b of the trench region of the substrate, and a second portion 144 that is generally aligned with the second end 154 of the floating gate and the edge 132 of the word line that is farthest from the second portion 124 of the control gate. In some embodiments, the memory cell 100 further includes an insulating material 160 between the control / erase gate 120 and the word line 130, between the control / erase gate 120 and the floating gate 150, between the control / erase gate 120 and the substrate 102, and between the control / erase gate 120 and the dielectric layer 140. In some embodiments, the insulating material 160 includes an oxide, a nitride, a combination of an oxide and a nitride, or other dielectric materials. In some embodiments, the insulating material 160 provides lower capacitive coupling between the control / erase gate 120 and the word line 130 compared to a conventional silicon oxide layer. In some embodiments, the memory cell 100 further includes an erase gate insulating region 162 disposed between a first end 152 of the floating gate 150 and a second portion 124 of the control / erase gate 120. The erase gate insulating region 162 has a thickness that permits electrons to tunnel from the first end 152 of the floating gate to the second portion 124 of the control / erase gate during an erase operation. In some embodiments, the erase gate insulating region thickness is greater than 120 Å and permits electron tunneling between the control gate and the floating gate when a voltage not greater than 7 V is applied. In some embodiments, the memory cell 100 further includes a floating gate insulating region 164 (e.g., sometimes referred to herein as the floating gate oxide 164) disposed between a surface portion 111 of the substrate and the floating gate 150. The floating gate insulating region 164 has a thickness that permits positive injection of electrons traveling in an upward path into the floating gate during a programming operation. In some embodiments, the floating gate insulating region 164 has a thickness of at least 100 Å, which prevents floating gate charge loss even in a high temperature environment, thereby increasing the charge retention ability of the memory cell, which improves the product life of the memory cell. In some embodiments, the conductive elements (e.g., the control / erase gate 120, the floating gate 150, and / or the word line 130) of the memory cell 100 are formed of suitably doped polysilicon. It should be understood that "polysilicon" refers to any suitable conductive material formed at least in part from a silicon or metal material and that can be used to form the conductive elements of a non-volatile memory cell. In some embodiments, the floating gate 150 is formed of tantalum nitride, which is extremely thermally stable even at up to 1000 °C. In some embodiments, the floating gate 150 can have a thickness as small as 10 Å. In some embodiments, the insulating elements (e.g., the insulating material 160) of the memory cell 100 are formed of silicon dioxide, silicon nitride, and / or any suitable insulator that can be used to form the insulating elements of a non-volatile memory cell. Attention is now turned to the channel portions of the memory cell 100, as depicted in FIG. 2. These channel portions operate during the programming operation of the memory cell 100 (described in more detail below). In some embodiments, the surface portion 106 of the mirror memory cell 101, the sidewall portion 108b of the trench region of the mirror memory cell 101, the bottom portion 108a of the trench region, and the sidewall portion 108b of the trench region of the memory cell 100 form a continuous channel 190 extending from the bit line region 104 of the mirror memory cell 101 to a portion of the sidewall region 108b of the substrate closest to the memory cell 100. In some embodiments, adjacent portions of the channel 190 are adjacent to or overlap each other, and in some embodiments, the surface region 106 of the mirror memory cell 101 overlaps the bit line region 104 of the mirror memory cell 101. In other words, portions 106, 108a, and 108b form the continuous channel 190. In some embodiments, the continuous channel region formed by portion 106 (of unit 101), portion 108b (of unit 101), portion 108a (of unit 100), and 108b (of unit 100) is non-coplanar because the sidewall portion 108b of the channel 190 extends generally perpendicular to the lateral direction in which the surface portion 106 extends, and the bottom portion 108a of the channel 190 extends generally perpendicular to the direction of the sidewall portion 108b of the channel 190. In some embodiments, "generally perpendicular" means an angle in the range of 75 degrees to 105 degrees. The operation of the memory cell 100 in accordance with some embodiments will now be described with reference to FIG. 2. The following discussion discloses the erase operation, the programming operation, and the read operation of the memory cell 100. All items are described with reference to items included in the memory cell 100, unless explicitly stated as referring to the mirror memory cell 101, with reference to FIG. 2. To erase the memory cell 100 (during an erase operation), a negative high voltage (e.g., approximately -7 V (or, -7 V to -8 V)) is applied to the word line 130, and a positive high voltage (e.g., approximately 6 V) is applied to the erase gate 120, keeping the source / drain (bit line region 104) and the substrate 102 grounded. The floating gate 150 is coupled to the negative voltage by capacitive coupling to the word line 130, which causes Fowler-Nordheim (F-N) tunneling of electrons injected from the floating gate tip (the first end 152) due to the enhanced field at the floating gate tip (the first end 152, the end pointing to the erase gate 120). As electrons are pulled out, the floating gate 150 becomes positively charged until the voltage drop between the floating gate 150 and the erase gate 120 is no longer strong enough to sustain a meaningful F-N tunneling current. As pointed out above, the capacitive coupling between the floating gate 150 and the erase gate 120 is much smaller than the capacitive coupling between the floating gate 150 and the word line 130. Therefore, a relatively low high voltage is required for the erase operation, thereby allowing efficient erasing (also referred to as erasure or erase) of the memory cell 100. In some embodiments, during an erase operation, the word lines 130 of two adjacent memory cells 100 and 101 are biased at the same voltage (e.g., approximately -7 V (or, -7 V to -8 V)). With the two word lines set to the same voltage, both memory cells 100 and 101 are erased simultaneously because the memory cells along the word line pair are considered the minimum erase sector. For a memory cell 100 (in a programming operation), electrons are injected into the floating gate 150 of the memory cell 100 to neutralize the positive charge from an erase operation on the same memory cell, or to negatively charge the floating gate 150 of the memory cell 100. Example voltage bias values for the programming operation include: approximately 4V to 4.5V on the source / drain (bit line region 104) of the memory cell 100, 0V on the source / drain (bit line region 104) of the mirror memory cell 101, a positive high voltage (e.g., approximately 6V to 8V) to the word line 130 of both the memory cell 100 and the mirror memory cell 101, and 1.6V to 1.8V to the control / erase gate 120. These voltage bias values cause a subthreshold current of electrons (e.g., less than 100 nA) to flow from the bit line region 104 of the mirror memory cell 101 along the channel 190 to the bit line region 104 of the memory cell 100. In some embodiments, a fixed potential (i.e., a fixed voltage) is applied to the control / erase gate 120 (e.g., 1.8V) and the source / drain (bit line region 104) (e.g., 4V) of the memory cell 100, and the source / drain (bit line region 104 of the mirror unit 101) is controlled by a signal pulse from 1.8V to ground and then back to 1.8V to perform the programming operation. As electrons flow under the control / erase gate 120 through the bottom trench portion 108a and turn upward at the transition from the bottom trench portion 108a to the sidewall trench portion (at the corner of the trench marked X in FIG. 2), they experience a strong vertical electric field component that accelerates the electrons upward toward the substrate surface 111 under the floating gate 150. If the electrons acquire sufficient energy (e.g., 3.2 eV) to overcome the energy barrier at the substrate and the SiO2 interface at the substrate surface 111 under the floating gate 150, the electrons cross the surface 111 and are pulled toward the floating gate 150 by the attractive Coulomb force. This programming mechanism provides increased programming speed. The potential of the floating gate 150 decreases as the floating gate acquires electrons. This process continues until the floating gate potential is low enough to reduce the vertical field under the surface portion 106 and prevent electrons in the channel from acquiring sufficient energy in the vertical direction to overcome the energy barrier at the interface (the surface 111 under the floating gate 150). Thus, during a programming operation, the word line potential (as mentioned above), the control gate potential (as mentioned above), and the bit line potential (as mentioned above) are configured such that electrons can travel towards the floating gate 150 below the bottom portion 108a of the trench region and above the sidewall portion 108b of the trench region (of the memory cell 100). In some embodiments, the floating gate 150 can reach a programmed state within 20 ns or less during such a programming operation. In other words, in some embodiments, the memory cell 100 is configured to reach a programmed state within 20 ns or less during the programming operation of the floating gate 150. Additional details regarding the programming process are discussed below. To read the memory cell 100 (during a read operation), 0 V is applied to the source / drain (bit line region 104) and the word line 130 of the memory cell 100, Vdd (e.g., 1.8 V) is applied to the source / drain (bit line region 104) of the mirror memory cell 101, 3 V to 4 V (alternatively, 2.5 V to 5 V) is applied to the control gate 120, and 0 V or Vdd (e.g., 1.8 V) (i.e., no charge pump is required) is applied to the word line 130 of the mirror memory cell 101. These voltage bias values fully turn on the bottom portion 108a of the trench of the channel 190 and the sidewall portion 108b of the trench, and in the case of a fully depleted substrate region under the floating gate of the mirror cell 101, electrons can freely flow from any part of the trench sidewall 108b towards the bit line region 104 of the mirror cell 101 with little resistance (e.g., in the opposite direction of path 206 in FIG. 2). In other words, during a read operation, the portion of the substrate on the side of the mirror cell 101 is fully depleted due to the 1.8 V applied to the source / drain 104 of the mirror cell 101 and the deep halo implant 306 in the region adjacent to the source / drain (bit line region 104) of the mirror cell 101 (see FIG. 3, and the discussion of FIG. 3 below). Regardless of the floating gate voltage of the mirror cell, the mirror cell channel region 190 is fully depleted. If the floating gate voltage of the mirror cell is positively charged, the mirror cell channel region has an inversion layer, but if the floating gate voltage of the mirror cell is negatively charged, it does not have an inversion layer. In either case, the resistance to electron flow in the mirror cell channel region is nearly the same, and the effect on the read current is less than 3%. In other words, the read current is insensitive to the programmed / erased state of the mirror cell within a 3% tolerance. Thus, in some embodiments, during the read operation of the memory cell 100 as discussed above, the only node that requires a charge pump (e.g., to maintain the node at a voltage different from the fixed voltage potential provided to the integrated circuit in which the memory cell 100 resides) is the control / erase gate 120, thereby keeping the power consumption caused by the charge pump to a minimum. In an embodiment that includes a trench implant and a deep halo implant but does not include a corner implant (discussed below for implants), if the floating gate 150 is sufficiently positively charged (e.g., +1.0 V or +1.0 V to +2.0 V in the erased state), the field generated by the floating gate 150 fully turns on the remaining portion of the channel 190 (the surface portion 106 of the memory cell 100), and a high read current is generated and detected, where the floating gate-channel threshold voltage is adjusted to be approximately -1.0 V to -1.2 V. On the other hand, if the floating gate 150 is negatively charged (e.g., in the programmed state, where the potential is approximately -1.0 V to -1.5 V), the field generated by the floating gate 150 is not sufficient to turn on the portion of the channel 190 between the trench sidewall portion 108b of the channel 190 and the bit line region 104 of the memory cell 100 (e.g., the surface portion 106 of the memory cell 100), and the read current will be at a sub-threshold level. The following discussion describes an embodiment that includes features for high-efficiency programming. As mentioned above, to program the floating gate 150 of the memory cell 100, electrons flow from the source node (bit line region 104) along the portion of the channel 190 that is located in the mirror memory cell 101 (surface portion 106, trench sidewall portion 108b, and trench bottom portion 108a). At the transition from the trench bottom portion 108a (of the memory cell 100) to the trench sidewall portion 108b (the trench corner marked as X in FIG. 2), the electrons are no longer confined to the inversion layer, and they are released to face a much stronger electric field. This electric field is in a fully depleted space charge region that pulls the electrons upward and to the left (e.g., in the directions of paths 204 and 206). To increase the programming efficiency, the electrons need to be pulled mainly upward toward the floating gate 150 (in the direction of path 202). These programming electrons gain kinetic energy when accelerating, and if the energy is higher than the energy barrier height at the silicon / oxide interface at the surface 111, the electrons will be injected into the floating gate insulating region 164 (FIG. 1), and then be pulled to the floating gate 150. At the trench corner X, the electrons are affected by the pulling forces (e.g., attractive Coulomb forces, or electrostatic forces caused by the electric field) from the floating gate 150 of the memory cell 100 at the top side (in the directions of paths 202 and 204), from the drain node (bit line region 104) of the memory cell 100 (in the direction of path 206), and from the control / erase gate 120 (in the direction of the control / erase gate 120). Thus, if the pulling force from the drain (bit line region 104) is approximately the same as the pulling force from the control gate, electrons mainly flow in the direction of path 202. However, if the pulling force from the drain (bit line region 104) is stronger than the pulling force from the control gate, electrons mainly flow in the direction of path 204 or 206 (depending on how much stronger the pulling force from the drain is compared to the pulling force from the control gate). Although FIG. 2 depicts three electron paths 202, 204, and 206, these paths are shown as three discrete lines for purposes of illustrating the examples described herein. However, in reality, those of ordinary skill in the art will understand that the path taken by electrons when pulled from position X is more similar to a spectrum, and the paths themselves can vary based on the amount of the aforementioned pulling force and the pulling force from the top due to the floating gate potential. The pulling force from the floating gate decreases as the programming mechanism progresses. If the pulling force from the drain node (bit line region 104) is stronger than the pulling force from the control / erase gate 230, electrons will mainly flow towards path 204 or 206 when moving upward, which is not desirable because the horizontal direction of electron movement is less favorable in terms of obtaining the energy required to be injected vertically into the floating gate 150. In other words, the electrons after passing through corner X must have a sufficient vertical component in the flow direction to obtain enough energy to be injected into the floating gate 150. Therefore, in some embodiments, it is necessary to increase the control gate voltage during the programming operation to counteract the pulling force from the drain (bit line region 104), thereby canceling the horizontal component in the flow direction of the electrons after the electrons pass through corner X and ensuring a sufficient vertical component in the flow direction of the electrons to obtain enough energy to be injected into the floating gate 150. However, increasing the control gate voltage during the programming operation while maintaining a low programming current will require a high control gate threshold value, which has a negative impact on the read current. To address this trade-off, in some embodiments, the memory cells 100 and 101 include (e.g., are configured with) a plurality of implants to optimize the threshold voltage for different portions of the channel 190 to achieve high programming efficiency while maintaining a sufficiently high read current for erased cells. For embodiments in which the word lines 130 of two memory cells from a memory cell pair 100 / 101 are biased at the same voltage for read operations (e.g., 0 V), program operations (e.g., 7 V), and erase operations (e.g., -7 V), such mirror cell structures can be implemented as described above with reference to FIGS. 1 to 2, but with the additional feature that the word lines 130 of each memory cell pair are electrically connected together. In such embodiments, a mirror cell structure comprising two memory cells 100 / 101 can be implemented as a 4-node device, where the nodes consist of: (i) a source (e.g., 104 in cell 100 / 101), (ii) a drain (e.g., 104 in cell 101 / 100), (iii) word lines (two word lines 130 electrically connected together), and (iv) a control / erase gate 120. FIG. 3 illustrates a plurality of implants in the substrate 102 of the memory cells 100 / 101 according to some embodiments. In some embodiments, the implants include indium (atomic number 49), which is similar to boron and is a p-type dopant, but is much heavier than boron and diffuses much slower in a silicon substrate than boron in a high-temperature environment. In some embodiments, the dopant of the implants described herein is gallium. Referring to FIG. 3, the substrate 102 includes: (i) a first indium implant, referred to as a "trench implant" 302, which is disposed in a region of the substrate below the bottom of the trench; (ii) a second indium implant, referred to as a "corner implant" 304, which is disposed in regions of the substrate adjacent to the sidewalls of the trench and in the surface region of the substrate for each memory cell 100 / 101; and (iii) a third indium implant, referred to as a "deep halo implant" 306, which is disposed in a region of the substrate adjacent to the lower portion (e.g., bottom) of the source / drain (bit line region 104) of each memory cell 100 / 101. In some embodiments, the trench implant 302 increases the threshold voltage of the trench bottom channel (the portion of channel 190 located within the trench bottom portion 108a, FIG. 2), such that the channel current is controlled to approximately 100 nA, where the control gate 120 voltage Vcg is at approximately 1.6 V to 2.0 V during a program operation to program the memory cell in 10 ns to 20 ns (or less). In some embodiments including the corner implant 304, the corner implant 304 of each memory cell 100 / 101 controls the threshold voltage of the floating gate channel (the portion of channel 190 in surface region 106, FIG. 2) to be about 0.2 V, such that the read current will be less than 1 μA for a programmed cell and greater than 10 μA for an erased cell. Thus, the substrate 102 includes a second indium implant (corner implant 304) which results in a threshold voltage of the channel of the floating gate 150 (region 106, FIG. 2) of approximately 0.2 V, such that the read current (i) is less than 1 μA when the floating gate 150 is programmed (e.g., to be negatively charged or uncharged), and (ii) is greater than 10 μA when the floating gate 150 is erased (e.g., positively charged at +2.0 V). In some embodiments, the deep halogen implant 306 in combination with the trench implant 302 controls the punch-through current of unselected columns (control gate 120 voltage Vcg, word line 130 voltage Vwl) to 10 pA or less. The deep halogen implant 306 (which preferably does not include lateral p-type halogen between the deep halogen implant and the surface of the substrate) provides an additional advantage: during the read operation of a memory cell 100 or 101, the read current is insensitive to the programmed or erased state of the mirror memory cell 101 or 100 within a 3% tolerance. Thus, the substrate 102 includes a third indium implant (deep halogen implant 306) which in combination with the trench implant 302 keeps the punch-through current of unselected columns at 10 pA or less, and further, the difference in read current of the erased cell 100 when the mirror cell 101 is in the erased state or the programmed state is less than 3%. More generally, in some embodiments, when reading the memory cell 100, the state of the mirror cell 101 has an impact on the read current of less than 3%, while in some other embodiments, when reading the memory cell 100, the state of the mirror cell 101 has an impact on the read current of less than 10% or 15%. In some embodiments, the substrate 102 for adjacent memory cells 100 / 101 includes only two of the three types of implants discussed above, as depicted in FIGS. 4 - 5. For example, as shown in FIG. 4, in some embodiments, the substrate 102 includes the trench implant 302 and the halogen implant 306, or a halogen implant similar to the implant 602 shown in FIG. 6, but does not include the corner implant. In some such embodiments, during the read operation of the memory cell 100, a voltage of 3 V to 4 V is applied to the word line of the mirror cell 101 to reduce or minimize the sensitivity of the read current to the programmed / erased state of the mirror cell 101. In another example, in some embodiments, the substrate 102 includes corner implants 304 and deep halo implants 306, but does not include trench implants, as depicted in FIG. 5. FIGS. 6 to 7 are diagrams illustrating halo implants in the substrate of the memory cell 100 / 101 according to some embodiments. Conventional halo implants 602 (FIG. 6) are disposed around the bit line region 104 (source / drain node), extending from the lower region 104 all the way to the surface 111 of the substrate 102. For such implants, during a read operation, when the source / drain node (region 104) of the mirror cell 101 is at 1.8 V, the channel region 106 of the mirror cell 101 is partially depleted due to the source / drain voltage, and the read current when reading the memory cell 100 is more sensitive to the programmed / erased state of the mirror cell 101 than in the memory cells described above with reference to FIGS. 1 to 5 (e.g., the read current when reading the cell 100 can vary by up to 25% or even more depending on the state of the mirror cell 101). Deep halo implants 306 (FIG. 7) are disposed only around the lower part of the bit line region 104 (source / drain node), and not between the lower part of the substrate 102 and the surface 111 (not in the region 702 of the substrate). For such implants, during a read operation, when the source / drain node (region 104 of the mirror memory cell 101) is at 1.8 V, the channel region 106 of the mirror memory cell 101 is completely depleted, independent of the floating gate voltage of the floating gate of the mirror memory cell 101. The deep halo implants 306 have no significant effect on the doping profile in the channel region 106 (i.e., at the interface between the substrate and the source / drain), where "no significant effect" is defined herein as not preventing the depletion region in the mirror cell 101 from reaching the trench sidewall portion 108b of the channel 190, thereby allowing electrons to flow with minimal resistance from the trench sidewall portion 108b in the mirror cell 101 towards the source / drain (bit line region 104) of the mirror cell 101 when a read voltage is applied to the source / drain (bit line region 104) of the mirror cell 101. Plan view of the memory array Attention is now turned to FIGS. 8 and 9, which respectively illustrate alternative plan views of memory cell arrays 800 and 900 according to some embodiments. In some embodiments, the bit lines are interconnected with the drain / source regions of the paired memory cells. Manufacturing process Attention is now turned to FIGS. 10A to 10F, which illustrate a process for manufacturing the memory cell 100 / 101 according to some embodiments. The process according to some embodiments begins in FIG. 10A, which shows a cross-sectional view of a silicon substrate 1002, a dielectric layer 1004 (e.g., thermal silicon dioxide or low-trap silicon nitride), a tantalum nitride floating gate material 1006, an oxide layer 1008, and a silicon nitride layer 1010. A number of N-wells or P-wells are formed, including stripping all oxides. A floating gate dielectric layer 1004 (e.g., thermal SiO2 or low-trap Si3N4) (e.g., approximately 100 Å, or greater than 100 Å) is formed on the substrate 1002. Next, a floating gate material 1006 TaN (tantalum nitride) (e.g., 20 Å or thinner) is deposited. Next, an oxide layer 1008 (e.g., approximately 20 Å or thinner) and a silicon nitride layer 1010 (e.g., 100 Å) are deposited. Next, an STI (shallow trench isolation) mask is placed for forming STI (including CMP, stopping on the silicon nitride layer). As shown in FIG. 10B, the nitride layer 1010 is stripped, and a high-quality Si3N4 thin film 1012 (~80 Å) is redeposited as a coupling dielectric between the word line and the TaN floating gate. A cell array protection mask is applied to protect the memory cell array region, and the nitride / oxide / TaN / oxide stack is removed from other regions (e.g., non-cell region 1014). Next, HV gate oxide and LV thin gate oxide 1016 are grown in the non-cell region, where the masking operation defines the thin oxide region. As shown in FIG. 10C, polycrystalline silicon gate material 1018 is deposited by appropriate doping. Next, a gate mask 1020 is applied in a masking operation to define the word line 1022 and the peripheral transistor gate 1024. As shown in FIG. 10D, a layer 1026 of Si3N4 (e.g., ~20 Å to 30 Å) is deposited, and a layer 1028 of SiO2 (e.g., 80 Å) is deposited. A trench masking operation is performed to form a trench 1030 in the control / erase gate region. In some embodiments, corner implantation is performed before trench etching to dope the trench corners with a p-type dopant. As shown in FIG. 10E, a photoresist stripping operation is performed. Next, a high-temperature oxide (HTO) layer 1032 (e.g., 120 Å to 150 Å) or a low-trap Si3N4 layer is added as a tunneling dielectric. Next, doped polycrystalline silicon 1034 is deposited to fill the trench region between the word lines, and then the doped polycrystalline silicon is partially etched back. Next, a source / drain TaN removal mask is placed at position 1036 to protect the trench region and the peripheral region to remove the remaining polycrystalline silicon, tunneling dielectric, and TaN in the memory cell array source / drain region. Next, a non-cell region oxide removal mask is placed to protect the memory cell array region to remove the remaining polycrystalline silicon, tunneling dielectric, and oxide in the non-cell region. As shown in FIG. 10F, source / drain regions 1038 are formed using a typical back-end source / drain formation process. The manufacturing process Attention is now turned to FIGS. 11A through 11M, which illustrate a process for manufacturing memory cells 100 / 101 according to some embodiments. The process according to some embodiments begins in FIG. 11A, which shows a cross-sectional view of a silicon substrate 1102, a dielectric layer 1104 (e.g., thermal silicon dioxide or low-trap silicon nitride), a floating gate material 1106, an oxide layer 1108, and a silicon nitride layer 1110. A number of wells are formed, including N wells, deep N wells, and P wells (for the peripheral region), including stripping all oxides. A floating gate dielectric layer 1104 (e.g., thermal SiO2 or low-trap Si3N4) (e.g., approximately 100 Å or thicker) is formed on the substrate 1102. Next, peripheral HV oxide (e.g., 135 Å to 160 Å) and thin oxide (e.g., 32 Å or thinner) regions (not shown) are formed. Next, polycrystalline silicon floating gate material 1106 (~300 Å, N-doped (Poly 1)) is formed, and an oxide layer 1108 (e.g., approximately 20 Å) and a sacrificial silicon nitride layer 1110 (e.g., Si3N4, 100 Å) are deposited. Next, an STI mask is placed for forming STI (including CMP, stopping on the silicon nitride layer). As shown in FIG. 11B, the portion of the oxide in the STI (above the substrate) is removed by anisotropic etching. As shown in FIG. 11C, the remaining silicon nitride is removed, and a layer 1114 of high-quality 100 Å silicon nitride or a combination of oxide and silicon nitride is redeposited as a coupling dielectric material between the word line and the floating gate. Next, a cell array protection mask is placed to protect the memory cell array region, and nitride / oxide is removed from other regions (non-cell regions). Next, N-doped polycrystalline silicon (Poly 2) 1116 is deposited, which will become the word line material in the cell array and the gate material for the peripheral transistors (Poly 2 is connected to Poly 1). Next, an oxide 1118 is deposited. As shown in FIG. 11D, a gate mask 1120 is placed to define the word lines and word line pick-up regions in the cell array and the gates of the peripheral transistors (not shown). As shown in FIG. 11E, anisotropic etching is performed to remove the oxide / poly 2 / nitride stack, and Poly 1 is partially removed, leaving approximately 100 Å (in region 1122). Next, the photoresist is stripped. As shown in FIG. 11F, a high-quality 130 Å HTO layer 1124 is deposited, followed by anisotropic etching to remove the 130 Å HTO on top of the remaining 100 Å Poly 1. As shown in FIG. 11G, polysilicon (Poly 1) 1106 is isotropically etched by appropriate over-etching to produce a sharp Poly 1 edge 1126 (also referred to as a tip, sharp tip, or pointed tip) that will act as a tunneling injector. Although the tantalum floating gate described above with reference to FIGS. 10A to 10F may have a thickness of 10 Å to 20 Å, the Poly 1 floating gate 1106 may have a thickness of 300 Å to 400 Å, where the tip 1126 has a thickness of less than 30 Å, typically 10 Å to 20 Å. As shown in FIG. 11H, a trench mask 1128 is placed, and a corner implant 1130 is applied to define the threshold voltage of the floating gate channel (e.g., an indium implant, at a 7-degree angle along the word line direction, where the diffused portion of the implanted indium dopes the trench corner). The corner implant 1130 corresponds to the corner implant 304 in FIG. 3. As shown in FIG. 11I, a portion of the substrate silicon 1102 is subjected to anisotropic etching to produce a ~400 Å trench 1132. Then, a trench implant 1134 (e.g., indium 80 Kev, tilted at a 7-degree angle along the word line direction) is applied. The trench implant 1134 corresponds to the trench implant 302 in FIG. 3. As shown in FIG. 11J, the photoresist is stripped from the region 1136. As shown in FIG. 11K, an HTO layer 1138 (e.g., 120 Å) is deposited as a tunneling dielectric material between the floating gate and the control / erase gate. As shown in FIG. 11L, a doped polysilicon (Poly 3) 1140 is deposited as a control / erase gate material using a control / erase gate mask to define the erase gate. As shown in FIG. 11M, source / drain regions 1142 are formed. In some embodiments, in the process for forming the source / drain regions 1142, there is no conventional halogen-based implant using lateral halogen in the memory cell array region. Instead, an indium punch-through suppression (deep halogen) implant 1144 is applied. The deep halogen implant 1144 corresponds to the deep halogen implant 306 in FIG. 3. In some embodiments, the steps for applying implants 1130 (FIG. 11H), 1134 (FIG. 11I), and 1144 (FIG. 11M) are applied in a similar manner to the process flow in FIGS. 10A to 10F. As shown in FIG. 11M, the shape of the floating gate 150 is defined by a shallow trench isolation (STI) on one side and a word line 130 on the other side, so no separate mask is involved in forming the floating gate 150. Second manufacturing process Attention is now turned to FIGS. 12A through 12V, which illustrate a process for fabricating a pair of electrically erasable programmable non-volatile memory cells (including electrically erasable programmable non-volatile memory cells 1200 / 1201) according to some embodiments. FIGS. 12A through 12V show cross-sectional views of a pair of memory cells 1200, 1201 as the fabrication process progresses. It should be noted that the structures shown in FIGS. 12A through 12V and FIGS. 12W, 13A through 13V, and 13W are not drawn to scale, and some features are shown in disproportionately large sizes so that those features can be visible in these figures. As shown in FIG. 12A, the process for fabricating an electrically erasable programmable non-volatile memory cell begins with a substrate 1202, and an insulator layer 1204 and a floating gate layer 1206 (such as polysilicon) are disposed on the substrate. FIG. 12A shows a cross-sectional view of a silicon substrate 1202, a dielectric layer 1204 (e.g., thermal silicon dioxide or low-trap silicon nitride), and a floating gate layer 1206 (e.g., polysilicon). In some embodiments, the polysilicon floating gate layer 1206 has a thickness of 200 angstroms to 400 angstroms (200 Å to 400 Å) within a ten percent (10%) margin, such as a thickness of 300 Å. The dielectric layer 1204 is sometimes referred to as a floating gate oxide layer because it is positioned between the floating gate layer 1206 and the substrate 1202. Next, as shown in FIG. 12B, a sequence of additional layers 1208 through 1216 is deposited on the structure in FIG. 12A, which includes a dielectric (such as an oxide) layer 1208 (sometimes referred to as a coupling oxide / dielectric or word line gate oxide / dielectric), a polysilicon layer 1210 (sometimes referred to as a Poly2 layer or word line layer), a stacked dielectric (such as an oxide) layer 1212, a silicon nitride (such as Si 3 N 4 ) layer 1214, and another dielectric (such as an oxide) layer 1216 on top. In some embodiments, the dielectric layer 1216 is used to protect the memory structure elements below the dielectric layer 1216 during subsequent processing. As shown in FIG. 12C, using a mask 1220 and an appropriate etchant and process (e.g., anisotropic etching), trenches 1222 are opened in the structure shown in FIG. 12B, removing the unprotected portions of the dielectric layer 1216, the silicon nitride layer 1214, and the stacked dielectric layer 1212 that are not protected by the mask 1220. The etching operation depicted in FIG. 12C stops at the polysilicon layer 1210. It should be noted that the reference numeral 1222 is used herein to identify the trenches, even when the shape of the trenches (such as width and depth) changes during subsequent processing steps. At this initial stage, the "trenches" 1222 are not truly trenches because they have not yet extended into the substrate 1202. Next, as shown in FIG. 12D, a word line (WL) spacer (e.g., dielectric) material is deposited and etched back to form word line (WL) spacers 1224 on the outer vertical edges outside the trenches 1222. As a result, the trenches 1222 are generally narrowed. Next, as shown in FIG. 12E, using the WL spacers 1224 as a mask, anisotropic etching 1226 is used to etch the polysilicon word line layer 1210 and the coupling oxide / dielectric layer 1208, and partially etch the polysilicon floating gate layer 1206, such that the trenches 1222 are now separated from the substrate 1202 by a portion of the polysilicon floating gate layer 1206 and the floating gate oxide / dielectric 1204. Next, as shown in FIGS. 12F and 12G, an offset spacer 1228 (e.g., dielectric material) is deposited and etched back to create a narrower trench 1222 (for ease of reference, even as the process continues, the label 1222 continues to be applied to the "trench", even though the dimensions of the trench, including width and depth, change), where the offset spacer 1128 separates the word line layer 1210 from the trench. The boundary between the WL spacer 1224 and the offset spacer 1228 is indicated by a dash line. In some embodiments, the WL spacer 1224 and the offset spacer 1228 are formed of the same dielectric, such as silicon oxide. Next, as shown in FIG. 12H, an etching operation, such as isotropic etching, removes the remaining portion of the polysilicon layer 1206 at the bottom of the trenches 1222, and also etches the portion of the polysilicon layer 1206 located below the offset spacer 1228 and adjacent to the bottom of the trenches 1222, thereby forming a polysilicon tip 1232 facing the trenches 1222 (e.g., the tip 1232 is the narrowest portion of the polysilicon layer, and is also part of the polysilicon floating gate 150 (see FIG. 12W), which is formed by the polysilicon layer 1206 closest to the trenches 1222). Next, as shown in FIG. 12I, a first tunnel oxide 1234 (e.g., dielectric layer) is deposited in the trenches 1222. At this time, the polysilicon tip 1232 is separated from the trenches 1222 only by the first tunneling oxide 1234, while the other portions of the polysilicon layer 1206 (floating gate 150) and the word line layer 1210 are separated from the trenches 1222 by the offset spacer 1228 and the first tunneling oxide 1234. Next, as shown in FIG. 12J, an oxide etch (e.g., an anisotropic etch) operation is performed to extend the trench 1222 into the substrate while minimizing the etch of the first tunnel oxide 1234. In some embodiments, the lateral thickness of the first tunneling oxide 1234 after completion of the etch operation in FIG. 12J is approximately 70 Å (e.g., less than 100 Å) within a 10% to 15% margin, and in some embodiments has a thickness of 50 Å to 100 Å. As shown in FIG. 12J, the floating gate 150 covers the entire portion of the floating gate oxide 164 except for the portion closest to the trench 1222 (sometimes referred to herein as the offset gap 1238). The presence of the offset gap 1238 in the memory cell increases the floating gate threshold voltage (e.g., the voltage of the floating gate 150 relative to the voltage of the substrate 102) of the channel 190 (see FIG. 12W) passing under the floating gate oxide 1204 / 164, which is required to achieve at least a predefined current level (e.g., the current level required to determine the state of the memory cell 1200 during a read operation). Next, as shown in FIG. 12K, a trench implant operation is performed during which a trench implant 1240 is introduced into the substrate below the trench 1222 (e.g., in the region of the substrate 102 below the bottom of the trench 1222). In some embodiments, the trench implant 1240 comprises an indium implant. The nature of the trench implant 1240 (e.g., to determine or increase the threshold voltage of the bottom portion of the channel 190) is discussed above with respect to the trench implant 302. Next, typically after the trench implant, as shown in FIG. 12L, a second tunneling oxide 1242 (e.g., a dielectric layer) is deposited in the trench 1222. At this time, the polysilicon tip 1232 is separated from the trench by both the first tunneling oxide 1234 and the second tunneling oxide 1242, while the other portions of the polysilicon layer 1206 (the floating gate 150) and the word line layer 1210 are separated from the trench 1222 by the WL spacer 1224, the offset spacer 1228, the first tunneling oxide 1234, and the second tunneling oxide 1242. The dashed line in FIG. 12L indicates the boundary between the WL spacer 1224, the offset spacer 1228, the first tunnel oxide 1234, and the second tunnel oxide 1242. In some embodiments, the lateral thickness of the second tunneling oxide 1242 is approximately 80 Å within a 10% to 20% margin, and in some embodiments, has a thickness of 50 Å to 110 Å. Next, as shown in FIG. 12M, one or more conductive materials are deposited in the trench 1222 to form the control gate. In some embodiments, the conductive material forming the control gate includes polysilicon, and in some embodiments includes metals such as titanium nitride and / or tungsten. Additionally, as shown in FIG. 12M, an etching operation 1244 is performed to remove the excess upper portion of the insulator layer and the conductive material forming the control gate. It should be noted that electrical connections to the control gate are formed using conductors extending in a direction not visible in the cross-sectional view of FIG. 12M, such as electrical connections to the control gates of the same column or row or other memory cell pairs in the memory cell. Next, as shown in FIG. 12N, a dielectric material (e.g., oxide) is formed on top of the memory cell pair, and then planarized, for example, using chemical mechanical planarization (CMP). Thereafter, as shown in FIG. 12O, the silicon nitride structure formed by the silicon nitride layer 1214 is removed by etching 1248, resulting in the structure shown in FIG. 12O. As shown in FIG. 12P, another etching operation 1250 removes the portions of the word line, floating gate, and word line gate layers 1206, 1208, 1210 that are farthest from the control gate, so as to form the structure shown in FIG. 12P. In FIG. 12P, portions of the polysilicon layers 1206, 1210 are exposed, and those portions are then covered with a dielectric layer, as shown in FIG. 12Q, to form a protective dielectric layer over the outer portions of the word line and floating gate. Next, a first silicon nitride spacer 1254 is added to (e.g., deposited and then anisotropically etched) the outer portions of the memory pair structure, as shown in FIG. 12R, followed by the oxide etching operation shown in FIG. 12S, and then a silicon oxide layer is deposited, and subsequently a second silicon nitride spacer is added to the outer portions of the memory pair structure, as shown in FIG. 12T. Next, as shown in FIG. 12U, a deep halogen implantation operation 1260 is performed to add a dopant, such as indium, in the region of the substrate below the drain / source regions (bit line region 104) of the two memory cells 1200, 1201. The characteristics of the deep halogen implant 1260 are discussed above with respect to the deep halogen implant 306. Finally, perform bit line (e.g., N+) and LDD implant operations to form bit lines and LDD regions for each memory cell 1200, 1201. The LDD implant is optional depending on the desired threshold level of the floating gate 150 (see FIG. 12W). Additionally, as shown in FIG. 12W, the floating gate 150 (e.g., the remaining portion of the floating gate region 1206 after the etching operation shown in FIG. 12P) does not overlap with the LDD region 105 of each memory cell 1200, 1201 (regardless of whether the "LDD region" 105 is implanted with N+ dopant), thereby forming an offset region in the substrate 102 between the source / drain (bit line) region 104 and the portion of the channel 190 covered by the floating gate 150. The LDD region 105 is sometimes referred to herein as the distal portion of the channel within an electrically erasable programmable non-volatile memory cell, which is the farthest from the trench region and does not overlap with the floating gate 150. No. 2 Memory Cell Structure FIG. 12W shows a block diagram of a memory cell pair structure including electrically erasable programmable non-volatile memory cells 1200 and 1201 produced by the manufacturing process described above. An example of a plan view of a memory cell array using the memory cell pair structure of FIG. 12W according to an embodiment is shown in FIG. 9. In some embodiments, memory cell 1200 includes: A semiconductor substrate (102) having a bit line region (104), a surface region (106) spaced apart from the bit line region in a lateral direction (e.g., the horizontal direction in FIG. 12W), and a trench region spaced apart from the surface region 106 in the lateral direction, the trench region including a bottom portion (108a) and a sidewall portion (108b) adjacent to a trench (109) in the semiconductor substrate; A conductive control gate (120) including: A first portion (122) disposed inside the trench, insulated from the bottom portion and the sidewall portion of the trench region of the substrate, and spaced apart from a sidewall of the sidewall portion of the trench region by a first distance (A) in the lateral direction; and A second portion (124) disposed above the trench (109) and extending away from the trench; A conductive word line (130) insulated from the control gate (120) and offset from the second portion (124) of the control gate by a second distance (B) greater than the first distance (A) in the lateral direction; A floating gate (150) (e.g., a polysilicon floating gate), insulated from the substrate (102) and the word line (130) and including: A first end (152) that includes a portion of the floating gate closest to the control gate and is separated from the second portion of the control gate by a third distance (C) greater than the first distance (A) and less than the second distance (B) in the lateral direction; and A second end (154) that is aligned with an edge 132 of the word line that is farthest from the second portion of the control gate. In some embodiments, the second memory cell 1201 in the memory cell pair has the same structural components as the first memory cell 1200, except that the two memory cells share the same control gate 120 and the components of the second memory cell 1201 are configured as a mirror image of the components of the first memory cell 1200. In some embodiments, as shown in FIG. 12W (and also in FIG. 12L), the conductive word line is insulated from the control gate and is offset from the second portion of the control gate by an insulator sequence that includes an offset spacer, a first tunneling oxide, and a second tunneling oxide, and the insulator sequence separates the word line from the control gate by a second distance (B) greater than the first distance (A) in the lateral direction. Additionally, in such embodiments, the first end (152) of the floating gate is separated from the second portion (124) of the control gate (120) by the first tunneling oxide and the second tunneling oxide rather than the offset spacer. In some embodiments, the second tunneling oxide extends into the trench, but the first tunneling oxide does not extend into the trench. In some embodiments, the memory cell 1200 further includes: a first indium implant (1240) disposed in a region of the substrate below the bottom portion of the trench region; and a second indium implant (1260) disposed in a region of the substrate adjacent to a source or drain region of the memory cell. Additionally, in some embodiments, the first indium implant causes a threshold voltage of a channel in the bottom portion of the trench region to control a programming current to 100 nA during a programming operation, where a control gate voltage is between 1.6 V and 2.0 V, and the floating gate is configured to reach a programmed state within 20 ns or less after applying the programming current. In some embodiments, the second indium implant in combination with the first indium implant causes (i) the punch-through current of an unselected column of the memory cell to be 10 pA or less, and (ii) the read current to be insensitive to the programmed / erased state of a mirror cell (e.g., the memory cell 1201) within a 10% tolerance. In some embodiments, the lateral extent of the first tunneling oxide corresponds to a portion of a channel (190, FIG. 12W) in the substrate that extends from the bit line region (104) of the substrate (102) to a sidewall portion of the trench region (109), the portion not overlapping with the floating gate (150); see FIG. 12W. In other words, the width (or lateral extent) of the first tunneling oxide corresponds to the offset gap 1238 shown in FIG. 12J. See the discussion of FIG. 12J above. In some embodiments, an erase gate insulation region (162, FIG. 12W) is disposed between the first end (152) of the floating gate (150) and the second portion (124) of the control gate (120), the erase gate insulation region corresponding to portions of the first and second tunneling oxides disposed between the first end of the floating gate and the second portion of the control gate, and the erase gate insulation region having a thickness that permits electrons to tunnel from the first end of the floating gate to the second portion of the control gate during an erase operation. In some embodiments, the erase gate insulation region thickness is greater than 120 Å (e.g., 150 Å, within a 10% or 15% error margin), and permits tunneling of electrons when a voltage of no greater than 7 V is applied between the control gate and the floating gate. In some embodiments, the floating gate comprises polysilicon having a thickness between 200 Å and 400 Å and a tip having a thickness less than 20 Å at the first end. In some embodiments, the control gate is configured to act as an erase gate during an erase operation. In some embodiments, the memory cell 1200 includes a floating gate insulation region (164) disposed between a surface region of the substrate and the floating gate, wherein the floating gate insulation region has a thickness that permits positive injection of electrons traveling in an upward path into the floating gate during a programming operation. In some embodiments, a word line potential of the word line, a control gate potential of the control gate, and a bit line potential of the bit line region are configured such that electrons can travel under the bottom portion of the trench region during a programming operation and then travel upward toward the floating gate. In some embodiments, the floating gate 150 is configured to reach a programmed state in 20 ns or less during a programming operation. In some embodiments, a word line (130) is electrically connected to a word line of a mirror memory cell; an electrically erasable programmable non-volatile memory cell (1200) and a mirror memory cell (1201) form a four-node memory cell pair, and the four nodes are composed of a source node, a drain node, a word line node, and a control / erase node; and the word line node includes the electrically connected word lines, the control / erase node includes the control gate shared by the electrically erasable programmable non-volatile memory cell (1200) and the mirror memory cell (1201), and the source node or the drain node includes or is electrically connected to the bit line region (104) of the electrically erasable programmable non-volatile memory cell (1200). Alternatively, the word line (130) is not electrically connected to the word line of the mirror memory cell; the electrically erasable programmable non-volatile memory cell (1200) and the mirror memory cell (1201) form a five-node memory cell pair, and the five nodes are composed of a source node, a drain node, a first word line node (for the first memory cell 1200), a second word line node (for the mirror memory cell 1201), and a control / erase node; and the first word line node includes the word line of the first memory cell, the second word line node includes the word line of the mirror memory cell, the control / erase node includes the control gate shared by the electrically erasable programmable non-volatile memory cell (1200) and the mirror memory cell (1201), the source node includes or is electrically connected to the bit line region (104) of the electrically erasable programmable non-volatile memory cell (1200), and the drain node includes or is electrically connected to the bit line region (104) of the electrically erasable programmable mirror memory cell (1201). of the memory cell pair 4 nodes and 5 node configurations The memory cell pair shown in FIG. 12W includes two memory cells 1200 and 1201 sharing a control gate, which can be used as a four-node device where the word lines of the two memory cells are electrically connected to the same node and are jointly controlled, or as a five-node device where the word lines of the two memory cells are separately controlled. The following table shows examples of the control voltages to be applied to the nodes of the four-node device and the five-node device for performing read operations (the first memory cell and the second memory cell), programming operations (the first memory cell and the second memory cell), and erase operations. Unless otherwise indicated, all voltage examples for operating the memory cell pair should be considered as voltage ranges varying within up to 10% of the control voltage examples provided in the table herein. Table 1 - Control Voltages for the Polysilicon Floating Gate of the Four-Node Memory Cell Pair Table 2 - Control Voltages of Polysilicon Floating Gates of 5 - Node Memory Cell Pairs The Third Manufacturing Process Figures 13A through 13V illustrate a process for manufacturing a pair of electrically erasable programmable non - volatile memory cells including electrically erasable programmable non - volatile memory cells 1300 / 1301, the pair of electrically erasable programmable non - volatile memory cells having tantalum nitride floating gates, in contrast to the polysilicon floating gates of the pair of memory cells manufactured using the process of Figures 12A through 12V. As indicated in the description of this third manufacturing process hereinbelow, many parts of the manufacturing process of Figures 13A through 13V are the same as those in the manufacturing process of Figures 12A through 12V. Figures 13A through 13V show cross - sectional views of a pair of memory cells 1300, 1301 as the manufacturing process progresses. It should be noted that the structures shown in Figures 13A through 13V and Figure 13W are not drawn to scale, and some features are shown at disproportionately large sizes so that those features can be visible in these figures. As shown in Figure 13A, the process of manufacturing an electrically erasable programmable non - volatile memory cell begins with a substrate 1302, on which an insulating layer 1304 and a floating gate layer 1306 (such as tantalum nitride (TaN)) are disposed. Figure 13A shows a cross - sectional view of a silicon substrate 1302, a dielectric layer 1304 (e.g., thermal silicon dioxide or low - trap silicon nitride), a floating gate layer 1306 (e.g., TaN), and a dielectric (e.g., oxide) layer 1308 (sometimes referred to as a coupling oxide / dielectric or word - line gate oxide / dielectric). In some embodiments, the TaN floating gate layer 1306 has a thickness of 8 angstroms to 20 angstroms (8Å to 20Å), for example, a thickness of 10Å within a ten percent (10%) margin. The dielectric layer 1304 is sometimes referred to as a floating - gate oxide layer because it is positioned between the floating gate layer 1306 and the substrate 1302. Next, as shown in Figure 13B, a sequence of additional layers 1310 to 1316 is deposited on the structure shown in Figure 13A, which includes a polysilicon layer 1310 (sometimes referred to as a Poly2 layer or a word - line layer), a stacked dielectric (e.g., oxide) layer 1312, a silicon nitride (e.g., Si 3 N 4 ) layer 1314, and another dielectric (e.g., oxide) layer 1316 on top. In some embodiments, the dielectric layer 1316 is used to protect the memory - structure elements below the dielectric layer 1316 during subsequent processing. As shown in FIG. 13C, using mask 1320 and appropriate etchant and process (e.g., anisotropic etching), trenches 1322 are opened in the structure shown in FIG. 13B, removing the unprotected portions of dielectric layer 1316, silicon nitride layer 1314, and stacked dielectric layer 1312 by mask 1320. The etching operation depicted in FIG. 13C stops at silicon nitride layer 1314. It should be noted that reference numeral 1322 is used herein to identify the trenches, even when the shape of the trenches (e.g., width and depth) changes during subsequent processing steps. At this initial stage, the "trenches" 1322 are not truly trenches yet because they have not extended into substrate 1302. Next, as shown in FIG. 13D, a word line (WL) spacer (e.g., dielectric) material is deposited and etched back to form word line (WL) spacers 1324 on the outer vertical edges of trenches 1322. As a result, trenches 1322 are generally narrowed. Next, as shown in FIG. 13E, using WL spacers 1324 as a mask, anisotropic etching 1326 (e.g., polysilicon etching) is used to etch polysilicon word line layer 1310 such that trenches 1322 are now separated from substrate 1302 by TaN floating gate layer 1306 and floating gate oxide / dielectric 1304. Next, as shown in FIGS. 13F and 13G, offset spacers 1328 (e.g., dielectric material) are deposited and etched back 1330 to produce narrower trenches 1322 (for ease of reference, even as the processing continues, label 1322 continues to be applied to the "trenches", even if the size of the trenches (including width and depth) changes), where offset spacers 1328 separate word line layer 1310 from the trenches. The boundary between WL spacers 1324 and offset spacers 1328 is indicated by a dashed line. In some embodiments, WL spacers 1324 and offset spacers 1328 are formed of the same dielectric, e.g., silicon oxide. Next, as shown in FIG. 13H, an etching operation 1332 such as isotropic etching removes TaN layer 1306 at the bottom of trenches 1322, thereby forming the end of TaN layer 1306 facing trenches 1322 (TaN tip) (e.g., TaN tip 1333 is the portion of TaN floating gate 150 formed from TaN layer 1306 that is closest to trenches 1322 (see FIG. 13W)). Next, as shown in FIG. 13I, a first tunneling oxide 1334 (e.g., a dielectric layer) is deposited in the trench 1322. Then, as shown in FIG. 13J, an oxide etch (e.g., an anisotropic etch) operation is performed to extend the trench 1322 into the substrate while minimizing the etch of the first tunneling oxide 1334. At this time, the TaN tip 1333 is separated from the trench 1322 by the first tunneling oxide 1334, and the word line layer 1310 is separated from the trench 1322 by the offset spacer 1328 and the first tunneling oxide 1334. In some embodiments, the lateral thickness of the first tunneling oxide 1334 after completion of the etch operation in FIG. 13J is approximately 70 Å within a margin of 10% to 15%, and in some embodiments, has a thickness of 50 Å to 100 Å. As shown in FIG. 13W, the floating gate 150 (corresponding to the TaN layer 1306) covers the entire portion of the floating gate oxide 164, except for the portion closest to the trench 1322 (sometimes referred to herein as the offset gap 1338). The presence of the offset gap 1338 in the memory cell increases the floating gate threshold voltage of the channel 190 (see FIG. 13W) passing under the floating gate oxide 1304 / 164 (e.g., the voltage of the floating gate 150 relative to the voltage of the substrate 102 required to achieve at least a predefined current (e.g., the current required to determine the state of the memory cell 1300 during a read operation)). Next, as shown in FIG. 13K, a trench implant operation is performed, during which a trench implant 1340 is introduced into the substrate below the trench 1322 (e.g., in the region of the substrate 102 below the bottom of the trench 1322). In some embodiments, the trench implant 1340 includes an indium implant. The properties of the trench implant 1340 are discussed above with respect to the trench implant 302 (e.g., to determine or increase the threshold voltage of the bottom portion of the channel 190). Next, typically after the trench implant, as shown in FIG. 13L, a second tunneling oxide 1342 (e.g., a dielectric layer) is deposited in the trench 1322. At this time, the TaN tip 1333 is separated from the trench by both the first tunneling oxide 1334 and the second tunneling oxide 1342, and the word line layer 1310 is separated from the trench 1322 by the offset spacer 1328, the first tunneling oxide 1334, and the second tunneling oxide 1342. The dash lines in FIG. 13L indicate the boundaries between the WL spacer 1324, the offset spacer 1328, the first tunnel oxide 1334, and the second tunnel oxide 1342. In some embodiments, the lateral thickness of the second tunneling oxide 1342 is approximately 80 Å within a margin of 10% to 20%, and in some embodiments, has a thickness of 50 Å to 110 Å. Next, as shown in FIG. 13M, one or more conductive materials are deposited in the trench 1322 to form the control gate. In some embodiments, the conductive material forming the control gate includes polysilicon, and in some embodiments includes metals such as titanium nitride and / or tungsten. Additionally, as shown in FIG. 13M, an etching operation 1344 is performed to remove the excess upper portion of the insulator layer and the conductive material forming the control gate. It should be noted that conductors extending in a direction not visible in the cross-sectional view of FIG. 13M are used to form electrical connections to the control gate, such as to the control gates of other memory cell pairs in the same column memory cells. Next, as shown in FIG. 13N, a dielectric material (e.g., oxide) is formed on top of the memory cell pair, and then planarized, for example, using chemical mechanical planarization (CMP). Thereafter, as shown in FIG. 13O, the silicon nitride structure formed by the silicon nitride layer 1314 is removed by etching 1348, resulting in the structure shown in FIG. 13O. As shown in FIG. 13P, another etching operation 1350 removes the portions of the word line, floating gate, and word line gate layers 1306, 1308, 1310 that are farthest from the control gate, so as to form the structure shown in FIG. 13P. In FIG. 13P, portions of the TaN layer 1306 and the polysilicon layer 1310 are exposed, and those portions are covered with a deposited dielectric layer 1352 in a subsequent step, as shown in FIG. 13Q, to form a protective dielectric layer over the outer portions of the word line and the floating gate. Next, a first spacer 1354 is added to (e.g., deposited, then anisotropically etched) the outer portions of the memory pair structure, as shown in FIG. 13R, followed by an oxide etching operation shown in FIG. 13S, and then a second spacer is added to (e.g., deposited, and then anisotropically etched) the outer portions of the memory pair structure, as shown in FIG. 13T. Next, as shown in FIG. 13U, a deep halogen implantation operation 1360 is performed to add a dopant, such as indium, in the region of the substrate below the drain / source regions (bit line region 104) of the two memory cells 1300, 1301. The characteristics of the deep halogen implant 1360 are discussed above with respect to the deep halogen implant 306. Finally, perform bit line (e.g., N+) and LDD implant operations to form bit lines and LDD regions for each memory cell 1300, 1301. The LDD implant is optional depending on the desired threshold level of the floating gate 150 (see FIG. 13W). Additionally, as shown in FIG. 13W, the floating gate 150 (e.g., the remaining portion of the floating gate region 1306 after the etching operation shown in FIG. 13P) does not overlap with the LDD region 105 of each memory cell 1300, 1301 (regardless of whether the "LDD region" 105 is implanted with an N+ dopant), thereby forming an offset region in the substrate 102 between the source / drain (bit line) region 104 and the portion of the channel 190 covered by the floating gate 150. The LDD region 105 is sometimes referred to herein as the distal portion of the channel within an electrically erasable programmable non-volatile memory cell, which is the farthest from the trench region and does not overlap with the floating gate 150. In some embodiments, a method of manufacturing an electrically erasable programmable non-volatile memory cell, such as the manufacturing method depicted by the sequence of FIGS. 12A to 12V or the manufacturing method depicted by FIGS. 13A to 13V, includes: after forming a base structure, including a layer sequence on a substrate, the layer sequence including a floating gate layer separated from the substrate by a floating gate insulating layer, a word line layer separated from the floating gate layer by a dielectric layer, and one or more protective layers above the word line layer: 1) Form a trench through the layer sequence to form electrically separated portions of the floating gate layer and the word line layer, including a first floating gate region and a first word line region for a first memory cell in a pair of memory cells and a second floating gate region and a second word line region for a second memory cell, and first and second protective regions respectively positioned above the first word line region and the second word line region for the first memory cell and the second memory cell; 2) Sequentially form an offset spacer, a first tunneling oxide, and a second tunneling oxide in the trench such that the portions of the first floating gate region and the second floating gate region closest to the trench are separated from a control gate formed in the trench by the first tunneling oxide and the second tunneling oxide rather than the offset spacer, and the first word line and the second word line are separated from the trench by the offset spacer, the first tunneling oxide, and the second tunneling oxide; and 3) Form the control gate in the trench. In some embodiments, in the foregoing manufacturing method, a portion of the trench extends into the substrate, and the second tunneling oxide extends into the portion of the trench that extends into the substrate, but the first tunneling oxide does not extend into the portion of the trench that extends into the substrate. In some embodiments, the foregoing manufacturing method includes forming a conductive control gate within the trench, wherein the conductive control gate is a control gate for both the first memory cell and the second memory cell of the pair of memory cells. In some embodiments, in the foregoing manufacturing method, the first tunneling oxide has a lateral thickness less than 100 Å. Similarly, in some embodiments, in the foregoing manufacturing method, the second tunneling oxide has a lateral thickness less than 100 Å. In some embodiments, the foregoing manufacturing method includes: forming a first indium implant in a region of the substrate below a bottom portion of the trench region; and forming a second indium implant in a region of the substrate adjacent to a source / drain region of the first memory cell and a source / drain region of the second memory cell. Figure 3 Memory cell structure FIG. 13W shows a block diagram of a memory cell pair structure including electrically erasable programmable non-volatile memory cells 1300 and 1301 produced by the manufacturing procedures described above. An example of a plan view of a memory cell array using the memory cell pair structure of FIG. 13W according to an embodiment is shown in FIG. 9. In some embodiments, memory cell 1300 includes the same elements as those described above for memory cell 1200, except that the floating gate (150) is formed of tantalum nitride (TaN) or includes tantalum nitride (TaN) instead of polysilicon. The TaN floating gate typically has a thickness of 8 angstroms to 20 angstroms (8 Å to 20 Å), for example, a thickness of 10 Å within a margin of ten percent (10%). The tip 1333 of the TaN floating gate (see FIG. 13H), which includes the portion of the TaN floating gate closest to the control gate, typically has the same thickness as the TaN floating gate, for example, 8 Å to 20 Å. The foregoing discussion of the four-node and five-node implementations (configurations) of memory cell pair 1200 / 1201 applies equally to memory cell pair 1300 / 1301, and the control voltages shown in Tables 1 and 2 above also apply equally to memory cells 1300 and 1301, taking into account adjustments for the floating gate threshold voltage differences between tantalum nitride and polysilicon floating gates as appropriate. The foregoing description has been described with reference to specific embodiments. However, the foregoing illustrative discussion is not intended to be exhaustive or to limit the scope of the claims to the exact forms disclosed. Given the above teachings, many variations including memory device structures other than floating gates (e.g., charge trapping memory device structures or mask programmable read-only memories (mask ROMs)) are possible. The embodiments were chosen and described in order to best explain the operating principles and practical applications, thereby enabling those skilled in the art. The various diagrams illustrate several components in a specific order. However, components that do not depend on the order can be reordered, and other components can be combined or separated. Although some reordering or other grouping is specifically mentioned, other reordering or grouping will be obvious to those of ordinary skill in the art, so the ordering and grouping presented herein are not an exhaustive list of alternatives. 100: Memory cell 101: Mirror memory cell 102: Semiconductor substrate 104: Bit line region 105: LDD region 106: Channel region 108a: Bottom part 108b: Sidewall part 109: Groove 111: Substrate surface 120: Control / erase gate 122: First part of the control / erase gate 124: Second part of the control / erase gate 130: Word line 132: Edge of the word line 140: Dielectric layer 142: First part of the dielectric layer 144: Second part of the dielectric layer 150: Floating gate 152: First end of the floating gate 154: Second end of the floating gate 160: Insulating material 162: Erase gate insulation region 164: Floating gate insulation region 190: Channel 202: Path 204: Path 206: Path 230: Control / erase gate 302: Groove implant 304: Corner implant 306: Deep halo implant 602: Conventional halo implant 702: Region of the substrate 800: Memory cell array 900: Memory cell array 1002: Silicon substrate 1004: Gate dielectric layer 1006: Floating gate material 1008: Oxide layer 1010: Silicon nitride layer 1012: High-quality Si3N4 thin film 1014: Non-cell region 1016: LV thin gate oxide 1018: Polysilicon gate material 1020: Gate mask 1022: Word line 1024: Peripheral transistor gate 1026: Silicon nitride layer 1028: Silicon dioxide layer 1030: Groove 1032: High-temperature oxide 1034: Doped polysilicon 1036: Position of the TaN removal mask for source / drain 1038: Source / drain region 1102: Silicon substrate 1104: Gate dielectric layer 1106: Floating gate material 1106: Polysilicon floating gate material 1108: Oxide layer 1110: Sacrificial silicon nitride layer 1114: Silicon nitride layer 1118: Zinc oxide 1120: Gate mask 1122: Region 1126: Edge 1128: Spacer 1128: Groove mask 1130: Corner implant 1132: Groove 1134: Groove implant 1136: Region 1138: HTO layer 1142: Source / drain region 1144: Deep halo implant 1200: Memory cell 1201: Mirror memory cell 1202: Silicon substrate 1202: Substrate 1204: Gate oxide / dielectric 1206: Floating gate layer 1208: Oxide / dielectric layer 1210: Polysilicon layer 1212: Dielectric layer 1214: Silicon nitride layer 1216: Dielectric layer 1220: Mask 1222: Groove 1224: WL spacer 1226: Anisotropic etching 1228: Spacer 1232: Polysilicon tip 1234: First tunneling oxide1238: Offset Gap 1240: Groove Implant 1242: Second Tunnel Oxide 1244: Etching Operation 1248: Etching Operation 1250: Etching Operation 1254: First Silicon Nitride Spacer 1260: Deep Halogen Implant 1300: Memory Cell 1301: Memory Cell 1302: Silicon Substrate 1304: Dielectric Layer 1306: Floating Gate Layer 1308: Dielectric Layer 1310: Polysilicon Layer 1312: Dielectric Layer 1314: Silicon Nitride Layer 1316: Dielectric Layer 1320: Mask 1322: Groove 1324: WL Spacer 1326: Anisotropic Etching 1328: Spacer 1332: Etching Operation 1333: Tip 1334: First Tunnel Oxide 1338: Offset Gap 1340: Groove Implant 1342: Second Tunnel Oxide 1344: Etching Operation 1348: Etching Operation 1350: Etching Operation 1352: Dielectric Layer 1354: First Spacer 1360: Deep Halogen Implant To better understand the various described embodiments, reference should be made to the following embodiments in conjunction with the following drawings, in which like reference numerals throughout the figures refer to corresponding parts. FIG. 1 is a diagram showing a cross-sectional view of a pair of electrically erasable programmable non-volatile memory cells according to some embodiments. FIG. 2 is a diagram showing the effect of a competing electric field on electron flow during a programming operation according to some embodiments. FIGS. 3 to 5 are diagrams showing indium implants with post-implantation annealing and redistribution in the substrate of a memory cell according to some embodiments. FIGS. 6 to 7 are diagrams showing halogen implants in the substrate of a memory cell according to some embodiments. FIGS. 8 to 9 are diagrams showing alternative floor plans of a memory cell array according to some embodiments. FIGS. 10A to 10F illustrate a process for manufacturing an array of electrically erasable programmable non-volatile memory cells according to some embodiments. FIGS. 11A to 11M illustrate a process for manufacturing an array of electrically erasable programmable non-volatile memory cells according to some embodiments. FIGS. 12A to 12V and FIG. 12W illustrate a process for manufacturing an array of electrically erasable programmable non-volatile memory cells each having a polysilicon floating gate according to some embodiments and a block diagram of a pair of resulting memory cells. FIGS. 13A to 13V and FIG. 13W illustrate a process for manufacturing an array of electrically erasable programmable non-volatile memory cells each having a tantalum nitride floating gate according to some embodiments, and a block diagram of a pair of resulting memory cells. 102: Semiconductor substrate 104: Bit line region 105: LDD region 106: Channel region 108a: Bottom part 108b: Sidewall part 109: Groove 111: Substrate surface 120: Control / erase gate 122: First part of the control / erase gate 124: Second part of the control / erase gate 130: Word line 132: Edge of the word line 140: Dielectric layer 150: Floating gate 152: First end of the floating gate 154: Second end of the floating gate 160: Insulating material 162: Erase gate insulation region 164: Floating gate insulation region 190: Channel 1200: Memory cell 1201: Mirror memory cell 1228: Spacer 1234: First tunneling oxide 1240: Groove implant 1242: Second tunneling oxide 1260: Deep halo implant

Claims

1. An electrically erasable programmable non-volatile memory cell, comprising: a semiconductor substrate (102) having a bit line region (104), a surface region (106) spaced apart from the bit line region in a lateral direction, and a trench region (108) spaced apart from the surface region in the lateral direction, the trench region including a bottom portion (108a) and a sidewall portion (108b) adjacent to a trench in the semiconductor substrate; a conductivity control gate (120) comprising: a first portion (122) disposed inside the trench, insulated from the bottom portion and sidewall portion of the trench region of the substrate, and spaced apart from a sidewall of the sidewall portion of the trench region by a first distance (A) in the lateral direction; and a second portion disposed above the trench and extending away from the trench; A conductive word line (130) insulated from the control gate and offset in the lateral direction from the second portion of the control gate by a second distance greater than the first distance (B); a floating gate (150) insulated from the substrate and the word line and comprising: a first end (152) comprising the portion of the floating gate closest to the control gate, separated in the lateral direction from the second portion of the control gate by a third distance greater than the first distance and less than the second distance; and a second end (154) self-aligned with the edge (132) of the word line furthest from the second portion of the control gate.

2. The electrically erasable programmable nonvolatile memory cell of claim 1, wherein the conductive word line is insulated from the control gate and offset from the second portion of the control gate by an insulator sequence comprising an offset spacer, a first tunneling oxide and a second tunneling oxide, the insulator sequence causing the word line to be separated from the control gate in the lateral direction by a second distance greater than the first distance; and the first end of the floating gate is separated from the second portion of the control gate by the first tunneling oxide and the second tunneling oxide instead of the offset spacer.

3. The electrically erasable programmable nonvolatile memory cell of claim 2, wherein the second tunneling oxide extends into the trench, but the first tunneling oxide does not extend into the trench.

4. An electrically erasable programmable nonvolatile memory cell as claimed in any of claims 1 to 3, further comprising: a first indium implant (302) disposed in a region of the substrate below the bottom portion of the trench region; and a second indium implant (306) disposed in a region of the substrate adjacent to a source or drain region of the memory cell.

5. As in request 4, an electrically erasable programmable non-volatile memory cell, wherein: The first indium implant causes a threshold voltage of one of the channels in the bottom portion of the trench region to control a programmed current to 100 nA during programmed operation, wherein a control gate voltage is between 1.6 V and 2.0 V; wherein the floating gate is configured to reach a programmed state within 20 ns or less after the programmed current is applied.

6. As in request 4, an electrically erasable programmable non-volatile memory cell, wherein: The first indium implant and the second indium implant enable (i) a breakdown current of an unselected column of a memory cell to be 10 pA or less, and (ii) a read current to be insensitive to the programming / erasing state of one of a mirror cell within a tolerance of 10%.

7. An electrically erasable programmable nonvolatile memory cell as claimed in either claim 2 or 3, wherein a lateral extent of the first tunneling oxide corresponds to a portion of a sidewall portion of a channel in the substrate extending from the bit line region of the substrate to the trench region, the portion not overlapping the floating gate.

8. An electrically erasable programmable nonvolatile memory cell as claimed in either claim 2 or 3, wherein a distal portion of a channel in the substrate, including a portion of a sidewall portion of the channel extending from the bit line region of the substrate to the trench region, does not overlap with the floating gate, and the distal portion is the furthest from the trench region within the electrically erasable programmable nonvolatile memory cell.

9. An electrically erasable programmable nonvolatile memory cell as claimed in either claim 2 or 3, wherein an erase gate insulation region (162) is disposed between the first end of the floating gate and the second portion of the control gate, the erase gate insulation region corresponding to the portions of the first tunneling oxide and the second tunneling oxide disposed between the first end of the floating gate and the second portion of the control gate, and the erase gate insulation region having a thickness that allows electrons to tunnel from the first end of the floating gate to the second portion of the control gate during an erase operation.

10. The electrically erasable programmable nonvolatile memory cell of claim 9, wherein the thickness of the erase gate insulation region is greater than 120 Å, and electrons are allowed to tunnel between the control gate and the floating gate when no more than 7 V is applied.

11. An electrically erasable programmable nonvolatile memory cell as claimed in any of claims 1 to 3, wherein the floating gate comprises tantalum nitride having a thickness between 10 Å and 20 Å.

12. An electrically erasable programmable nonvolatile memory cell as claimed in any of claims 1 to 3, wherein the floating gate comprises polysilicon having a thickness between 200 Å and 400 Å, and a tip at the first end has a thickness of less than 20 Å.

13. An electrically erasable programmable nonvolatile memory cell as claimed in any of claims 1 to 3, wherein the control gate is configured to act as an erase gate during an erase operation.

14. An electrically erasable programmable nonvolatile memory cell as claimed in any of claims 1 to 3, further comprising a floating gate insulating region (164) disposed between the surface region of the substrate and the floating gate, wherein the floating gate insulating region has a thickness that allows electrons traveling in an upward path to be injected onto the floating gate during a programming operation.

15. An electrically erasable programmable nonvolatile memory cell as claimed in any of claims 1 to 3, wherein a word line potential of the word line, a control gate potential of the control gate, and a bit line potential of the bit line region are configured such that electrons can travel below the bottom portion of the trench region during a programmed operation and then upward toward the floating gate.

16. An electrically erasable programmable nonvolatile memory cell as claimed in any of claims 1 to 3, wherein the floating gate is configured to reach a programmed state within 20 ns or less during a programmed operation.

17. An electrically erasable programmable nonvolatile memory cell, as described in any of requests 1 to 3, wherein: The word line is electrically connected to a word line of a mirror memory cell; the electrically erasable programmable nonvolatile memory cell and the mirror memory cell form a four-node memory cell pair, the four nodes consisting of a source node, a drain node, a word line node and a control / erase node; and the word line node includes the word lines electrically connected, the control / erase node includes the control gate shared by the electrically erasable programmable nonvolatile memory cell and the mirror memory cell, and the source node or drain node includes or is electrically connected to the bit line region of the electrically erasable programmable nonvolatile memory cell.

18. An electrically erasable programmable non-volatile memory cell comprising: a semiconductor substrate (102) having a bit line region (104), a surface region (106) spaced apart from the bit line region in a lateral direction, and a trench region (108) spaced apart from the surface region in the lateral direction, the trench region including a bottom portion (108a) and a sidewall portion (108b) adjacent to a trench in the semiconductor substrate; a conductivity control gate (120) comprising: a first portion (122) disposed inside the trench, insulated from the bottom portion and sidewall portion of the trench region of the substrate, and spaced apart from the sidewall portion of the trench region by a first distance (A) in the lateral direction; and a second portion disposed above the trench and extending away from the trench; A conductive word line (130) insulated from the control gate and offset in the lateral direction from the second portion of the control gate by a second distance (B) greater than the first distance; a conductive floating gate (150) insulated from the substrate and the word line and comprising: a first end (152) comprising the portion of the floating gate closest to the control gate; and a second end (154) self-aligned with an edge (132) of the word line furthest from the second portion of the control gate; a first indium implant (302, 1240) disposed in a region of the substrate below the bottom portion of the trench region; and a second indium implant (306, 1260) disposed in a region of the substrate adjacent to a source or drain region of the memory cell.

19. The electrically erasable programmable nonvolatile memory cell of claim 18, wherein the first end of the conductive floating gate includes a top portion and a bottom portion adjacent to the top portion, and the bottom portion of the floating gate extends closer to the control gate in the lateral direction than the top portion of the floating gate.

20. An electrically erasable programmable nonvolatile memory cell as claimed in any of claims 18 to 19, wherein the second indium implant makes a read current insensitive to the programmed / erased state of one of the mirror cells within a tolerance of 10%.

21. An electrically erasable programmable nonvolatile memory cell, as described in any of requests 18 to 19, wherein: The word line is electrically connected to a word line of a mirror memory cell; the electrically erasable programmable nonvolatile memory cell and the mirror memory cell form a four-node memory cell pair, the four nodes consisting of a source node, a drain node, a word line node and a control / erase node, the source node including or electrically connected to the bit line region of the electrically erasable programmable nonvolatile memory cell, the drain node connected to a bit line region of the mirror memory cell, and the control / erase node including or electrically connected to the conductive control gate; and the word line node including or electrically connected to the electrically connected word lines.

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