Semiconductor device and methods of forming same

Abstract

An exemplary gate stack includes a gate dielectric (e.g., a high-dielectric-constant dielectric layer above an interface layer) and a gate electrode (e.g., a work function layer above the high-dielectric-constant dielectric layer, a capping layer above the work function layer, and a bulk fill layer above the capping layer). The gate stack surrounds and / or encloses a first semiconductor layer disposed above a second semiconductor layer. The gate dielectric and the work function layer (but not the capping layer and / or bulk fill layer) fill the space between the first and second semiconductor layers. The oxygen ratio in the outer portion of the gate stack to the inner portion of the gate stack can be from about 1 to about 1.25. The thickness of the work function layer inside the gate stack can be less than the thickness of the work function layer outside the gate stack.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly to semiconductor devices and methods of forming the same. Prior Art

[0002] Multi-gate devices (MGDs) are being introduced to meet the semiconductor integrated circuit (IC) industry's growing demand for smaller, faster electronic components that can simultaneously support a wide range of increasingly complex and sophisticated functions. MGDs have a gate that extends partially or completely around a channel region, providing access to the channel region on at least two sides. Exemplary MGDs include fin-like field effect (FinFET) transistors, gate-all-around (GAA) transistors (e.g., transistors based on nanostructures such as nanowires, nanosheets, or nanorods), other three-dimensional (3D) transistors (e.g., forksheet transistors), or combinations thereof. MGDs enable significant scaling of IC technology and have been observed to improve gate control, increase gate-channel coupling, reduce off-state current, and mitigate short-channel effects (SCEs), while seamlessly integrating with conventional IC manufacturing processes.

[0003] However, as IC technology nodes continue to scale, fabricating gate stacks around the channel region of multi-gate devices has become challenging. For example, the gate stacks of multi-gate devices are typically formed using a gate replacement process, which involves removing a dummy gate to form a gate opening that exposes the channel layer and filling the gate opening with various gate layers (e.g., gate dielectric and gate electrode). The reduction in device feature size has led to a reduction in gate opening size, which in turn reduces the volume of the gate stack. Consequently, the gate layer surrounding the channel layer can easily fill the gate opening and / or the space between adjacent channel layers. This leaves limited room in the gate opening for fine-tuning the threshold voltage (Vt) of the multi-gate device, for example, by using multiple work function layers and / or thicker work function layers. Various combinations and / or configurations of layers in gate stacks have been explored to maximize multi-gate device performance while minimizing performance mismatches, such as threshold voltage variations (σVt), between multi-gate devices in an IC (e.g., those forming memory). While existing gate stack structures and their fabrication methods for multi-gate devices are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Summary of the Invention

[0004] The present disclosure provides a method for forming a semiconductor element, comprising: forming a first semiconductor layer and a second semiconductor layer above a substrate, wherein the first semiconductor layer is disposed above the second semiconductor layer, and a space is defined between the first and second semiconductor layers; forming a gate dielectric above the first and second semiconductor layers, wherein the gate dielectric partially fills the space between the first and second semiconductor layers; forming a work function layer on the gate dielectric, wherein the work function layer fills the remaining portion of the space between the first and second semiconductor layers; and forming a cover member on the work function layer.

[0005] The present disclosure provides a method for forming a semiconductor element, comprising: forming a first interface layer around a first channel layer and forming a second interface layer around a second channel layer, wherein the channel stack includes a first channel layer disposed above the second channel layer, the first interface layer partially filling a space between the first channel layer and the second channel layer, and the second interface layer partially filling a space between the first channel layer and the second channel layer; forming a first high-k dielectric layer and a second high-k dielectric layer, the first high-k dielectric layer being above the first interface layer and around the first channel layer, and the high-k dielectric layer being above the second interface layer and around the second channel layer, wherein the first high-k dielectric layer partially fills a space between the first channel layer and the second channel layer, and the second high-k dielectric layer partially fills a space between the first channel layer and the second channel layer; forming a work function layer around the first channel layer and the second channel layer, wherein the work function layer fills the first channel layer. The work function layer is formed by depositing a work function material until a first portion of the work function material merges with a second portion of the work function material, the first portion being formed above a first high-k dielectric layer and surrounding the first channel layer, and the second portion being formed above a second high-k dielectric layer and surrounding the second channel layer, wherein the first portion of the work function material merges with the second portion of the work function material in the space between the first channel layer and the second channel layer, and continuing to deposit the work function material to increase the thickness of the first portion of the work function material and the second portion of the work function material; and forming a cap over the work function layer, wherein the cap wraps around the channel stack, and the steps of forming the cap include: forming a first metal nitride layer over the work function layer, forming a second metal nitride layer over the first metal nitride layer after breaking vacuum, and forming a silicon-containing layer over the second metal nitride layer.

[0006] A semiconductor device includes: a first channel layer and a second channel layer; a gate stack including: a gate dielectric disposed around the first channel layer and the second channel layer, wherein the gate dielectric includes an interface layer and a high-k dielectric, the high-k dielectric being disposed above the interface layer; and a gate electrode disposed above the gate dielectric, wherein the gate electrode is located around the first channel layer and the second channel layer, and wherein the gate electrode includes: a work function layer disposed above the high-k dielectric layer, wherein the work function layer is located around the first channel layer and the second channel layer; and a cover disposed Above the work function layer, wherein the cap includes a metal nitride layer and a silicon layer, the metal nitride layer is disposed above the work function layer, and the silicon layer is disposed above the metal nitride layer; wherein the gate dielectric and the work function layer fill the space between the first channel layer and the second channel layer; wherein the outer region of the gate stack has a first oxygen content, the inner region of the gate stack has a second oxygen content, and the ratio of the first oxygen content to the second oxygen content is approximately 1 to approximately 1.25; and wherein the first thickness of the work function layer in the outer region of the gate stack is greater than the second thickness of the work function layer in the inner region of the gate stack. Simple diagram description

[0007] The presently disclosed embodiments are best understood by the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale. In fact, the dimensions of various elements may be arbitrarily increased or decreased to clearly illustrate the components of the presently disclosed embodiments. FIG. 1 is a flow chart of a method for partially or fully fabricating a gate stack of a device according to various aspects of the present disclosure. FIG. 2 is a perspective view of a portion or all of a device (eg, a transistor) at a manufacturing stage associated with a method (eg, the method of FIG. 1 ) for manufacturing a gate stack for the device according to various aspects of the present disclosure. 3A-14A and 3B-14B are partial or complete cross-sectional views of a device (e.g., a transistor) at various manufacturing stages associated with the method for manufacturing the gate stack of FIG. 1 according to various aspects of the present disclosure. 15A and 15B are partial or full cross-sectional views of a device (eg, a transistor) having a gate stack that can be manufactured by the method of FIG. 1 according to various aspects of the present disclosure. 16A and 16B are energy-dispersive x-ray spectroscopy (EDX) images of oxygen in the inner and outer regions of gate stacks with different configurations according to various aspects of the present disclosure. FIG. 17 is a partial or entire cross-sectional view of a stacked device structure according to various aspects of the present disclosure. Implementation Method

[0008] The present disclosure relates generally to integrated circuit (IC) devices, and more particularly to transistor gate stacks and methods of fabricating the same.

[0009] The following disclosure provides numerous embodiments or examples for implementing various elements of the subject matter provided. Specific examples of various elements and their configurations are described below to simplify the illustration of the disclosed embodiments. Of course, the foregoing descriptions are merely examples and are not intended to limit the disclosed embodiments. For example, a description of a first element formed above a second element may include embodiments in which the first and second elements are in direct contact, as well as embodiments in which additional elements are formed between the first and second elements, preventing them from directly contacting each other. Furthermore, spatially relative terms such as "below," "above," "horizontally," "vertically," "above," "below," "below," "up," "down," "top," "bottom," and their derivatives (e.g., "horizontally," "downwardly," "upwardly," etc.) are used to facilitate descriptions of the relationship of one element to another in the disclosure. Spatially relative terms are intended to encompass different orientations of the device including the element. The disclosure may also repeat element numbers and / or letters throughout the various examples. This repetition is for simplicity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, when words like "about," "approximately," and the like are used to describe a number or a range of numbers, those terms are intended to encompass numbers within a reasonable range of variation that is understood by those skilled in the art to occur during manufacturing. For example, a reference to a number or range between numbers encompasses a reasonable range that includes the number being described, such as within + / - 10% of the number being described, based on known manufacturing tolerances associated with manufacturing components having the properties associated with that number. For example, the phrase "approximately 5 nanometers" encompasses a range of dimensions from 4.5 nanometers to 5.5 nanometers, where those skilled in the art understand that manufacturing tolerances associated with deposited material layers are + / - 10%. Furthermore, to account for variations inherent in any manufacturing process, when device components are described as having "substantially" properties and / or characteristics, the terms are intended to encompass properties and / or characteristics that are within the tolerances of the manufacturing process. For example, a "substantially vertical" or "substantially horizontal" component is intended to encompass components that are approximately vertical and horizontal within the given tolerances of the manufacturing process used to produce such component, but not mathematically or perfectly vertical and horizontal.

[0011] Multi-gate devices, such as fin-like field effect (FinFET) transistors, gate-all-around (GAA) transistors, forksheet transistors, and other non-planar transistors, have gained popularity due to their enhanced performance compared to traditional planar transistors. As multi-gate device dimensions shrink to facilitate further scaling of IC technology nodes, traditional multi-gate device manufacturing methods face challenges. For example, during the gate replacement process, unintentional and / or undesirable oxidation of gate stack components, such as the work function layer and / or gate dielectric layer, can lead to performance degradation, such as slower device speeds and / or undesirable threshold voltage (Vt) variations. This problem is exacerbated in certain IC applications, such as static random-access memory (SRAM) devices, where n-type transistor performance can be more critical than p-type transistor performance.

[0012] To address these challenges, the present disclosure provides a gate stack and corresponding gate stack fabrication method that reduces oxygen differences between the inner portion of the gate stack (e.g., the inner film stack between the channel layers) and the outer portion (e.g., the outer film stack not present between the channel layers). For example, the proposed gate stack may omit a cap in its inner region, such as an ex-situ cap, configure layers with different work function thicknesses in the inner and outer regions, reduce the work function of aluminum content layers, or a combination thereof. As described herein, because such a gate stack configuration accounts for and / or compensates for oxygen diffusion / migration that occurs during fabrication (such as when forming the cap), the proposed gate stack reduces oxygen differences between its inner and outer regions, thereby improving device reliability and / or performance, for example, by providing faster device speeds and / or smaller threshold voltage variations. Details of an improved gate stack for multi-gate devices and methods for fabricating and / or designing the same are described herein.

[0013] FIG1 is a flow chart of a method 100 for partially or fully fabricating a gate stack for a device according to various aspects of the present disclosure. FIG2 is a perspective view of a device 200 at a stage in a method for fabricating a gate stack (e.g., method 100 of FIG1 ) according to various aspects of the present disclosure. FIG3A-14A and FIG3B-14B are cross-sectional views of a device 200 at various stages in a method for fabricating a gate stack (e.g., method 100 of FIG1 ) according to various aspects of the present disclosure. FIG3A and FIG3B are cross-sectional views of a device 200 (e.g., a transistor) taken along lines AA and BB, respectively, in FIG2 . FIG4A-14A are cross-sectional views of the device 200 at subsequent stages in the fabrication of the method 100 of FIG1 , and FIG4B-14B are cross-sectional views of the device 200 at subsequent stages in the fabrication of the method 100 of FIG1 . Figures 15A and 15B are cross-sectional views of a device 200 having different gate stack structures that can be fabricated using method 100 of Figure 1 according to various aspects of the present disclosure. For ease of description and understanding, Figures 1, 2, 3A-14A, 3B-14B, 15A, and 15B are discussed simultaneously herein. For clarity, Figures 1, 2, 3A-14A, 3B-14B, 15A, and 15B have been simplified to facilitate a better understanding of the inventive concepts of the present disclosure. Additional steps may be provided before, during, and after method 100 of Figure 1, and some of the steps described may be moved, replaced, or deleted for additional embodiments of method 100 of Figure 1. Additional components may be added to device 200, and some of the components described below may be replaced, modified, or deleted in other embodiments of device 200.

[0014] Referring to Figures 1, 2, 3A, and 3B, the method 100 at block 105 includes forming a gate structure above the semiconductor stack. The gate structure includes a dummy gate and a gate spacer. This may include receiving and / or forming a device precursor comprising a substrate (wafer) 202, a semiconductor stack 210 (depicted as having a mesa 202' (i.e., a patterned, protruding portion of the substrate 202), a semiconductor layer 215, and a semiconductor layer 220), a substrate isolation structure 222, an inner spacer 224, a source / drain 225, a gate structure 230 (depicted as having a dummy gate 232 and a gate spacer 240), and a dielectric layer 250. The semiconductor stack 210 is located in a channel region C of the device 200, and the source / drain 225 is located in the source / drain regions S / D of the device 200. In FIG. 3A (e.g., an XZ cross-sectional view), the semiconductor layer 220 and the mesa 202′ extend along the x-direction between the source / drain 225. The inner spacer 224 is located between the semiconductor layer 215 and the source / drain 225. The gate structure 230 is disposed above the top of the semiconductor stack 210 and between the source / drain 225. In FIG. 3B (e.g., a YZ cross-sectional view), the gate structure 230 is located on the top and side surfaces of the semiconductor stack 210 and wraps around the semiconductor stack 210.

[0015] Substrate 202 includes an elemental semiconductor, such as silicon and / or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination thereof. In the depicted embodiment, substrate 202 is a silicon substrate. In some embodiments, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Substrate 202 (and mesa 202') may include various doped regions, such as p-type doped regions (e.g., p-wells), n-type doped regions (e.g., n-wells), or a combination thereof. The n-type doped region includes an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The p-type doped region includes a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, the doped region includes a combination of p-type and n-type dopants. The doped region can be formed directly above and / or in substrate 202, for example, assuming a p-well structure, an n-well structure, a dual-well structure, a raised structure, other suitable structures, or a combination thereof. In some embodiments, substrate 202, mesa 202', and the semiconductor layer thereon include an n-well, for example, when device 200 is a p-type transistor, or include a p-well, for example, when device 200 is an n-type transistor.

[0016] Semiconductor stack 210 extends along the x-direction and has a length along the x-direction, a width along the y-direction, and a height along the z-direction. Semiconductor layers 215 and 220 are stacked vertically (e.g., along the z-direction) from the top surface of substrate 202 in an interleaving and / or alternating configuration. The composition of semiconductor layer 215 differs from that of semiconductor layer 220 to achieve etch selectivity and / or different oxidation rates in subsequent processes. For example, semiconductor layer 215 and semiconductor layer 220 may include different materials, constituent atomic percentages, constituent weight percentages, thicknesses, or a combination thereof to achieve a desired etch selectivity during an etching process, such as an etching process performed to form a suspended channel layer in channel region C. In some embodiments, semiconductor layer 215 comprises silicon germanium and semiconductor layer 220 comprises silicon, and for a given etchant, the silicon etch rate of semiconductor layer 220 is different from the silicon germanium etch rate of semiconductor layer 215. In some embodiments, semiconductor layer 215 and semiconductor layer 220 comprise the same material but with different atomic percentages of the components to achieve etch selectivity. For example, semiconductor layer 215 and semiconductor layer 220 comprise silicon germanium with different atomic percentages of silicon and / or different atomic percentages of germanium. The present disclosure contemplates semiconductor layer 215 and semiconductor layer 220 comprising any combination of semiconductor materials that provide a desired etch selectivity, a desired oxidation rate difference, a desired performance characteristic (e.g., a material that maximizes current flow), or a combination thereof, including any semiconductor material disclosed herein.

[0017] The substrate isolation structure 222 electrically isolates the active device region and / or passive device region of the device 200 from each other. For example, the substrate isolation structure 222 separates and electrically isolates the active region of the device 200 (e.g., the semiconductor stack 210 and / or its source / drain 225) from other device regions and / or devices. The substrate isolation structure 222 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including, for example, silicon, oxygen, nitrogen, carbon, other suitable isolation components), or combinations thereof. The substrate isolation structure 222 can have a multi-layer structure. For example, the substrate isolation structure 222 can include a bulk dielectric (e.g., an oxide layer) above a dielectric liner (including, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride, or combinations thereof). In another example, substrate isolation structure 222 may include a dielectric layer over a doped liner, such as a boron silicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner. The dimensions and / or properties of substrate isolation structure 222 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or a combination thereof. In the depicted embodiment, substrate isolation structure 222 may be a shallow trench isolation (STI) structure.

[0018] The inner spacer 224 is disposed below the gate spacer 240 and along the sidewalls of the semiconductor layer 215. The inner spacer 224 is disposed between and separates the semiconductor layer 215 from the source / drain 225. The inner spacer 224 is further disposed between adjacent semiconductor layers 220 and between the bottommost semiconductor layer 220 and the mesa 202'. The inner spacer 224 comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable components, or combinations thereof, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxynitride carbon, or silicon oxynitride carbon. In some embodiments, the inner spacer 224 comprises a low-k dielectric material. In some embodiments, dopants (e.g., p-type dopants, n-type dopants, or combinations thereof) are introduced into the dielectric material, and the inner spacer 224 comprises a doped dielectric material.

[0019] The source / drain 225 comprises a semiconductor material and may be doped with n-type dopants and / or p-type dopants. When forming part of a p-type transistor, the source / drain 225 may comprise silicon germanium or germanium doped with boron, other p-type dopants, or a combination thereof. When forming part of an n-type transistor, the source / drain 225 may comprise silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof. The source / drain 225 may comprise more than one semiconductor layer, wherein the semiconductor layers comprise the same or different materials and / or the same or different dopant concentrations. The source / drain 225 may comprise a material and / or dopant that achieves a desired tensile stress and / or compressive stress in the channel region C. In some embodiments, the source / drain 225 is formed using an epitaxial growth process and may be referred to as an epitaxial source / drain 225. In some embodiments, doped regions such as heavily doped source / drain (HDD) regions, lightly doped source / drain (LDD) regions, other doped regions, or combinations thereof are disposed within the source / drain 225. In some embodiments, doped regions such as LDD regions may extend into the channel region C. As used herein, source / drain regions, source / drain regions, source / drain components, and the like may refer to a source of a device, a drain of a device, or sources and / or drains of multiple devices. In some embodiments, a bottom source / drain isolation structure may be formed between the substrate 202 and the source / drain 225.

[0020] The dummy gate 232 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the semiconductor stack 210. For example, the dummy gate 232 extends longitudinally along the y-direction, having a length along the y-direction, a width along the x-direction, and a height along the z-direction. In FIG3A , the dummy gate 232 is disposed on top of the semiconductor stack 210. In FIG3B , the dummy gate 232 is disposed above the top and sidewalls of the semiconductor stack 210 and wraps around the semiconductor stack 210. The dummy gate 232 may include a dummy gate electrode and a dummy gate dielectric. The dummy gate electrode may include a suitable dummy gate material, such as polysilicon (e.g., a polysilicon gate), and the dummy gate dielectric may include a suitable dielectric material, such as silicon oxide (i.e., a dummy oxide). The dummy gate 232 may include additional layers, such as a hard mask layer (e.g., a nitride mask), other suitable layers, or combinations thereof.

[0021] The gate spacer 240 is adjacent to and along the sidewalls of the dummy gate 232. The gate spacer 240 may include a seal spacer, an offset spacer, a sacrificial spacer, a dummy spacer, a main spacer, other suitable spacers, or a combination thereof. The gate spacer 240 may have a single-layer structure or a multi-layer structure. The gate spacer 240 includes a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable components, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, etc.). For example, the gate spacer 240 may include silicon, oxygen, nitrogen, carbon, and hydrogen (i.e., the gate spacer 240 may be a SiONCH layer).

[0022] A dielectric layer 250 is disposed over the substrate 202, the substrate isolation structure 222, the source / drain 225, and the gate structure 230. The dielectric layer 250 may have a multi-layer structure, such as a contact etch stop layer (CESL) 252 and an interlayer dielectric (ILD) layer 254. The ILD layer 254 is formed over the CESL 252. The ILD layer 254 includes a dielectric material, such as silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from tetraethylorthosilicate (TEOS), borosilicic glass (BSG), PSG, borophosphosilicate glass (BPSG), phosphosilicic glass (PSG), xerogel, aerogel, amorphous fluorinated carbon, parylene, a benzocyclobutene-based (BCB) dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer 254 includes a dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, ILD layer 254 includes a dielectric material having a dielectric constant less than about 2.5 (i.e., an extremely low-k dielectric material), such as porous silicon oxide, silicon carbide, a carbon-doped oxide (e.g., SiCOH)-based material (having, for example, Si—CH bonds), or a combination thereof. CESL 252 includes a dielectric material different from the dielectric material of ILD layer 254. For example, when ILD layer 254 includes silicon and oxygen (e.g., porous silicon oxide), CESL 252 may include silicon and nitrogen, and CESL 254 may be a silicon nitride layer, a silicon carbonitride layer, or a silicon carbon oxynitride layer.

[0023] In some embodiments, a device precursor is received before and / or after forming the dielectric layer 250. Forming the dielectric layer 250 may include depositing a dielectric material over the substrate 202, the substrate isolation structure 222, the source / drain 225, and the gate structure 230 and performing a planarization process, such as chemical mechanical polishing (CMP), on the dielectric material. The planarization process removes any dielectric material from above the gate structure 230. The dummy gate 232 may serve as a planarization stop layer, and the planarization process may be performed until the dummy gate 232 is reached. The planarization process may planarize the top surface of the dielectric layer 250 and the top surface of the gate structure 230. In some embodiments, dielectric layer 250 is a device-level dielectric layer of a multilayer interconnect (MLI) component, which electrically connects devices (e.g., transistors, resistors, capacitors, inductors, etc.), components of a device (e.g., gates and / or sources / drains), devices within an MLI component, components of an MLI component, or a combination thereof, so that the devices and / or components can operate as specified by design requirements.

[0024] Referring to FIG. 1 , FIG. 4A , and FIG. 4B , method 100 includes, at block 110 , removing the dummy gate 232 to form a gate opening 255 exposing the semiconductor stack 210 . The gate opening 255 has sidewalls formed by the gate spacer 240 and a bottom formed by the semiconductor stack 210 and / or the substrate isolation structure 222 . In some embodiments, the etching process selectively removes the dummy gate 232 relative to the gate spacer 240 , the dielectric layer 250 , or a combination thereof. For example, the etching process etches the dummy gate 232 while not (or negligibly) etching the gate spacer 240 , the substrate isolation structure 222 , the dielectric layer 250 , or a combination thereof. The etchant of the etching process may etch polysilicon (i.e., the dummy gate 232 ) at a higher rate than dielectric materials (i.e., the gate spacer 240 , the substrate isolation structure 222 , the dielectric layer 250 , etc.). The etching process may be dry etching, wet etching, other suitable etching methods, or a combination thereof. In some embodiments, the patterned mask layer covers the dielectric layer 250 and / or the gate spacer 240 but exposes the dummy gate 232 during the etching process.

[0025] Referring to FIG. 1 , FIG. 5A , and FIG. 5B , method 100 may include, at block 115 , performing a channel release process on the semiconductor stack to form a first channel layer disposed above the second channel layer. For example, the semiconductor layer 215 exposed by the gate opening 255 is selectively removed to form gaps 260 between the semiconductor layers 220 and between the semiconductor layers 220 and the mesas 202 ′, thereby suspending the semiconductor layers 220 in the channel region C. In the depicted embodiment, three suspended semiconductor layers 220 are vertically stacked along the z-direction (i.e., the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are vertically stacked and separated from each other by gaps 260 ). The suspended semiconductor layers 220 provide three channels through which current can flow between the source / drain 225. Therefore, the suspended semiconductor layers 220 are hereinafter referred to as channel layers 220 ′. The channel layer 220' has a width W along the y-direction, a thickness T along the z-direction, and a spacing S along the z-direction. In some embodiments, the width W is about 10 nm to about 60 nm. In some embodiments, the thickness T is about 5 nm to about 10 nm. In some embodiments, the spacing S is about 5 nm to about 15 nm.

[0026] In some embodiments, the channel release process includes an etching process that selectively removes the semiconductor layer 215 relative to the semiconductor layer 220, the mesa 202', the gate spacer 240, the inner spacer 224, the substrate isolation structure 222, the dielectric layer 250, or a combination thereof. For example, the etching process etches the semiconductor layer 215 while not (or negligibly) etching the semiconductor layer 220, the mesa 202', the gate spacer 240, the inner spacer 224, the substrate isolation structure 222, the dielectric layer 250, or a combination thereof. The etchant of the etching process can etch silicon germanium (i.e., the semiconductor layer 215) at a higher rate than silicon (i.e., the semiconductor layer 220) and dielectric materials (i.e., the gate spacer 240, the inner spacer 224, the substrate isolation structure 222, the dielectric layer 250, etc.). The etching process can be dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, before performing the etching process, an oxidation process converts the semiconductor layer 215 into a semiconductor oxide component (e.g., silicon germanium oxide), and the etching process subsequently removes the semiconductor oxide component. In some embodiments, during and / or after removing the semiconductor layer 215, an etching process is performed to modify the profile of the semiconductor layer 220 to achieve a target size and / or target shape of the channel layer 220' (e.g., a cylindrical channel layer), such as a cylindrical channel layer (e.g., nanowires), a rectangular channel layer (e.g., nanobars), a sheet-shaped channel layer (e.g., nanosheets), etc.

[0027] Referring to FIG. 1 , FIG. 6A-FIG. 14A, and FIG. 6B-FIG. 14B, method 100 includes, at block 120, forming a gate stack in a gate opening 255. The gate stack includes a gate dielectric 230A (e.g., at least one dielectric gate layer) and a gate electrode 230B (e.g., at least one conductive gate layer, such as a work function layer and / or a bulk / fill metal layer). The gate stack fills the gate opening 255 and, in the depicted embodiment, the air gap 260 (see FIG. 14A and FIG. 14B). For example, the gate stack is disposed between channel layers 220′ and between the channel layers 220′ and the mesa 202′. In the XZ plane ( FIG. 14A ), the gate stack is disposed between gate spacers 240 and between interspacers 224. In the YZ plane ( FIG. 14B ), the gate stack at least partially surrounds (e.g., encircles) the channel layer 220 ′. The gate stack may include more or fewer layers than depicted and described herein. The gate stack and gate spacer 240 may be collectively referred to as a gate structure 230 .

[0028] Referring to FIG. 1 , FIG. 6A , and FIG. 6B , method 100 , at block 125 , includes forming an interfacial layer 262 in the gate opening 255 . The interfacial layer 262 partially fills the gate opening 255 and partially fills the gap 260 (i.e., the space) between the channel layers 220 ′. The interfacial layer 262 comprises a dielectric material, such as SiO 2 , SiGeO x , HfSiO , SiON , other dielectric materials, or combinations thereof. In some embodiments, the interfacial layer 262 is formed on semiconductor surfaces (e.g., the channel layer 220 ′ and the mesa 202 ′) but not on dielectric surfaces (e.g., the inner spacer 224 , the substrate isolation structure 222 , the gate spacer 240 , and the dielectric layer 250 ), as shown. For example, the interfacial layer 262 can be formed by an oxidation process, such as thermal oxidation and / or chemical oxidation, in which oxygen reacts with the semiconductor surface to form a semiconductor oxide (i.e., the interfacial layer 262 ) rather than the dielectric surface. In FIG. 6A , the interface layer 262 covers the top surface of the channel layer 220', the bottom surface of the channel layer 220', and the top surface of the mesa 202'. In FIG. 6B , the interface layer 262 surrounds the channel layer 220' and wraps around the mesa 202'. In some embodiments, the interface layer 262 is formed by atomic layer deposition (ALD) and / or other suitable methods. In some embodiments, the interface layer 262 has a substantially uniform thickness, as shown. In some embodiments, the interface layer 262 has a thickness of approximately 5 Å to approximately 25 Å.

[0029] Referring to FIG. 1 , FIG. 7A , and FIG. 7B , method 100 includes, at block 130 , forming a high-k dielectric layer 264 over the interfacial layer 262 . The high-k dielectric layer 264 partially fills the gate opening 255 and partially fills the gap 260 (i.e., the space) between the channel layers 220 ′. The high-k dielectric layer 264 may be formed over the gate spacer 240 , the interspacer 224 , the substrate isolation structure 222 , and the dielectric layer 250 (e.g., when formed by a conformal deposition process). High-k dielectric layer 264 includes a high-k dielectric material, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, AlSiO3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3P4, HfO2-Al2O3, other high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials having a dielectric constant greater than that of silicon dioxide (k≈3.9). For example, the high-k dielectric layer 264 is a hafnium-based oxide (e.g., HfO 2) layer or a zirconium-based oxide (e.g., ZrO 2) layer. In FIG. 7A , the high-k dielectric layer 264 has a u-shaped profile in the top portion of the gate opening 255 and a rectangular profile in the bottom portion of the gate opening 255 (i.e., in the gap 260 ). In FIG. 7B , the high-k dielectric layer 264 surrounds the channel layer 220 ′ and wraps around the mesa 202 ′. The high-k dielectric layer 264 is formed by ALD, chemical vapor deposition (CVD), physical vapor deposition (PVD), other suitable processes, or a combination thereof. The thickness of the high-k dielectric layer 264 is greater than the thickness of the interface layer 262 . In some embodiments, the high-k dielectric layer 264 has a thickness of about 10 Å to about 50 Å. In some embodiments, the high-k dielectric layer 264 has a substantially uniform thickness, such as shown.

[0030] Referring to Figures 1, 8A, 8B, 9A, and 9B, method 100, at block 135, includes forming a square work function layer 272 on the high-k dielectric layer 264. The work function layer 272 partially fills the gate opening 255 and fills the remainder of the gap 260 (i.e., the space) between the channel layers 220'. In the depicted embodiment, the gaps 260 between the channel layers 220' and between the bottommost channel layer 220' and the mesa 202' are thus filled by the work function layer 272 and the gate dielectric 230A (e.g., the high-k dielectric layer 264 and the interfacial layer 262). In Figure 9A, the work function layer 272 has a U-shaped profile in the top portion of the gate opening 255 and a rectangular profile in the bottom portion of the gate opening 255 (i.e., in the gap 260). In FIG. 9B , the work function layer 272 surrounds the channel layer 220 ′ and wraps around the mesa 202 ′.

[0031] The work function layer 272 is formed by ALD, CVD, PVD, other suitable processes, or combinations thereof. In the depicted embodiment, the work function layer 272 is formed by depositing a work function material in the gate opening 255 (including the gap 260) to form the work function layer 272' around the channel layer 220'. The work function layer 272' merges together and fills the remaining portion of the gap 260 (FIGS. 8A and 8B). The work function material is then deposited in the gate opening 255 to increase the thickness of the work function layer 272' in the outer region (i.e., those portions not between the channel layers 220') and to increase the merging of the work function layer 272' (FIGS. 9A and 9B). As a result, the work function layer 272' around the channel layer 220' is combined to form the work function layer 272. In Figures 8A and 8B, when the work function layer 272' merges between the channel layers 220' and fills the remaining portion of the gap 260, the work function layer 272' has a thickness t1. In some embodiments, the thickness t1 is from about 15 Å to about 25 Å. In some embodiments, the thickness t1 is approximately ½ of the spacing S between the channel layers 220'. In Figures 9A and 9B, the thickness of the outer region of the work function layer 272' is increased by a thickness t2. In some embodiments, the thickness t2 is from about 5 Å to about 15 Å. In some embodiments, the thickness t2 is less than the thickness t1. In some embodiments, the thickness t2 is greater than the thickness t1. In some embodiments, the thickness t2 is approximately equal to the thickness t1. In some embodiments, the work function layer 272' is formed by a conformal deposition process and has a substantially uniform thickness. For example, the thickness t1 of each work function layer 272' can be the same along the top, bottom, and both sidewalls of the corresponding channel layer 220'.

[0032] Therefore, the thickness of the outer regions of the work function layer 272 (i.e., those portions along the sidewalls of the channel layer 220' and along the top of the topmost channel layer 220') is greater than the thickness of the inner regions of the work function layer 272 (i.e., those portions between the channel layers 220' and between the bottommost channel layer 220' and the mesa 202'). For example, a portion of the work function layer 272 surrounding the topmost channel layer 220' has an outer thickness TO and an inner thickness TI, with the outer thickness TO being greater than the inner thickness TI. A portion of the work function layer 272 has an outer thickness TO along the top and sidewalls of the topmost channel layer 220', and a portion of the work function layer 272 has an inner thickness TI along the bottom of the topmost channel layer 220'. In the illustrated embodiment, the outer thickness TO is the sum of thickness t1 and thickness t2, and the inner thickness TI is thickness t1. In some embodiments, the outer thickness TO is from about 20 Å to about 40 Å. In some embodiments, the inner thickness TI is from about 15 Å to about 25 Å. In some embodiments, the inner thickness TI is approximately 1 / 2 of the spacing S between the channel layers 220'. In addition, the portion of the work function layer 220' surrounding the middle channel layer 220' may have an outer thickness TO along the sidewalls of the middle channel layer 220' and an inner thickness TI along the top and bottom of the middle channel layer 220', and the portion of the work function layer 220' surrounding the bottom channel layer 220' may have an outer thickness TO along the sidewalls of the bottom channel layer 220' and an inner thickness TI along the top and bottom of the bottom channel layer 220'.

[0033] Work function layer 272 is a conductive layer tuned to have a desired work function. Work function layer 272 can be an n-type work function metal (N-WFM) layer, a p-type work function metal (P-WFM) layer, or a combination thereof. The N-WFM layer (also known as an n-metal layer) includes an n-type work function material, which generally refers to a conductive material tuned to have an n-type work function, and the p-WFM layer (also known as a p-metal layer) includes a p-type work function material, which generally refers to a conductive material tuned to have a p-type work function. The n-type work function material can include a metal with a sufficiently low effective work function, such as aluminum, titanium, tantalum, zirconium, other n-type metals, alloys thereof, or combinations thereof. In some embodiments, the N-WFM layer is a titanium aluminum layer, a titanium aluminum carbide layer, a tantalum carbide layer, a tantalum carbonitride layer, or a tantalum silicon nitride layer. The p-type work function material can include a metal with a sufficiently high effective work function, such as titanium, tantalum, ruthenium, molybdenum, tungsten, platinum, other p-type metals, alloys thereof, or combinations thereof. In some embodiments, the P-WFM layer is a titanium nitride layer, a titanium carbide layer, a titanium silicon nitride layer, a tantalum nitride layer, a tungsten carbonitride layer, or a molybdenum layer. In some embodiments, the work function layer has a multilayer structure, such as more than one N-WFM layer, more than one P-WFM layer, or both an N-WFM layer and a P-WFM layer. In some embodiments, work function layer 272 is configured to have an n-type work function or a p-type work function, depending on the type of transistor to which it belongs. For example, when device 200 is configured as an n-type transistor, work function layer 272 can be an N-WFM layer, and when device 200 is configured as a p-type transistor, work function layer 272 can be a P-WFM layer.

[0034] In the depicted embodiment, the work function layer 272 is an N-WFM layer formed by ALD, such as a titanium aluminum carbide (TiAlC) layer or a titanium aluminide (TiAl) layer. For example, the work function layer 272 includes titanium, aluminum, and carbon. In another example, the work function layer 272 includes titanium and aluminum. The aluminum concentration / content in the work function layer 272 depends on the thickness of the work function layer 272. For example, the aluminum content in the work function layer 272 is inversely proportional to the thickness of the work function layer 272. To maintain a desired threshold voltage, the aluminum content in the work function layer 272 can be increased or decreased depending on the thickness of the work function layer 272. Therefore, if a desired threshold voltage corresponds to a work function layer having a given thickness and a given aluminum content, then when the work function layer 272 is configured to have a thickness less than the given thickness, the aluminum content can be configured to be greater than the given aluminum content to maintain the desired threshold voltage (i.e., the aluminum content increases as the thickness decreases). Furthermore, if the work function layer 272 is configured to have a thickness greater than a given thickness, the aluminum content of the work function layer 272 can be configured to be less than the given aluminum content to maintain a desired threshold voltage (i.e., the aluminum content decreases as the thickness increases). In the depicted embodiment, since the thickness of the work function layer 272 is increased to fill the remaining portion of the gap 260 (i.e., the work function layer 272 is thicker), the work function layer 272 can be configured to have a lower aluminum content to obtain a given threshold voltage. For example, the work function layer 272 has a total thickness (e.g., t1+t2) of less than about 20 Å (e.g., 15 Å to about 20 Å), such a thickness does not fill the remaining portion of the gap 260 between the channel layers 220 ′. The work function layer 272 may have an aluminum content greater than 33 atomic percent (at%) (e.g., about 40 at%) to achieve a desired threshold voltage. In the depicted embodiment, the thicker work function layer 272 has a total thickness greater than 20 Å (e.g., about 25 Å to about 35 Å), such a thickness fills the remaining portion of the gap 260. The thicker work function layer 272 may have a lower aluminum content, such as about 25 at% to about 33 at% aluminum content, to achieve the same desired threshold voltage. A thicker work function layer 272 with an aluminum content less than about 25 at% may not maintain the desired threshold voltage, while a thicker work function layer 272 with an aluminum content greater than about 33 at% may undesirably increase gate resistance. Configuring the work function layer 272 with a lower aluminum content (e.g., about 25 at % to about 33 at %) reduces gate resistance, particularly gate resistance associated with inner portions of the gate stack, such as those portions filling the gaps 260 between the channel layers 220' and / or those portions filling the gaps 260 between the channel layers 220' and the mesas 202'.

[0035] 1 , 10A-12A, and 10B-12B, method 100 includes, at block 140, forming a cap 274 over the work function layer 272. In FIG12A and FIG12B, cap 274 includes a cap layer 276 and a cap layer 278, and cap layer 276 has a composition different from that of cap layer 278. For example, cap layer 276 is a metal-comprising layer, such as a metal nitride layer, and cap layer 278 is a semiconductor-comprising layer, such as a silicon layer. In some embodiments, block 140 includes forming a metal nitride layer (e.g., capping layer 276) over the work function layer 272 (see FIGS. 10A, 10B, 11A, and 11B) and forming a silicon-comprising layer (e.g., capping layer 278) over the metal nitride layer (see FIGS. 12A and 12B). In some embodiments, forming capping layer 276 includes forming a first portion of capping layer 276 (e.g., capping sublayer 276A) over the work function layer 272 ( FIGS. 10A and 10B) and, after breaking vacuum, forming a second portion of capping layer 276 (e.g., capping sublayer 276B) ( FIGS. 11A and 11B). In the depicted embodiment, since capping layer 276 is a metal nitride layer, capping sublayer 276A and capping sublayer 276B are metal nitride sublayers. In some embodiments, cover sublayer 276 has more than two sublayers, wherein the vacuum can be broken after forming each sublayer, or the vacuum can be broken after forming some sublayers but not others. In some embodiments, cover layer 278 has a multilayer structure. In some embodiments, cover 274 has more than two cover layers.

[0036] Referring to Figures 10A, 10B, 11A, and 11B, a cap sublayer 276A is formed over the work function layer 272 and partially fills the top portion of the gate opening 255 (Figures 10A and 10B). A cap sublayer 276B is formed over the cap sublayer 276A and partially fills the top portion of the gate opening 255 (Figures 11A and 11B). Because the work function layer 272 fills the remaining portion of the bottom portion of the gate opening 255 (i.e., gap 260), the cap sublayers 276A and 276B are not formed in the space between adjacent channel layers 220'. The cap sublayers 276A and 276B are formed using ALD, CVD, PVD, other suitable processes, or a combination thereof. In Figures 10A and 11A, the cap sublayers 276A and 276B have a U-shaped profile. In Figures 10B and 11B, the cover sub-layer 276A and the cover sub-layer 276B surround the channel layer 220'.

[0037] As noted, capping sublayer 276A and capping sublayer 276B are metal nitride layers that may include TiN, TiSiN, TaSiN, TaN, TaCN, WN, WCN, other metal nitrides, or combinations thereof. In some embodiments, capping sublayer 276A and capping sublayer 276B comprise the same metal nitride material. For example, capping sublayer 276A and capping sublayer 276B comprise titanium and nitrogen, and capping sublayer 276A and capping sublayer 276B are TiN sublayers. In some embodiments, capping sublayer 276A and capping sublayer 276B comprise different metal nitride materials. The thickness of capping sublayer 276A may be greater than the thickness of capping sublayer 276B. In some embodiments, the thickness of capping sublayer 276A is approximately 5 Å to approximately 15 Å. In some embodiments, the thickness of capping sublayer 276B is approximately 2 Å to approximately 8 Å. In some embodiments, the total thickness of the cap layer 276 (e.g., the sum of the thickness of the cap sublayer 276A and the thickness of the cap sublayer 276B) is from about 5 Å to about 25 Å. In some embodiments, the thickness of the cap sublayer 276A is less than the thickness of the cap sublayer 276B. In some embodiments, the thickness of the cap sublayer 276A is the same as the thickness of the cap sublayer 276B.

[0038] Lid sublayer 276B and lid sublayer 276A are formed "ex-situ," which generally refers to a vacuum break between processing steps. For example, device 200 is contained within a vacuum-controlled environment when lid sublayer 276A and lid sublayer 276B are formed, but device 200 is not maintained under vacuum conditions between forming lid sublayer 276A and lid sublayer 276B (i.e., device 200 may be exposed to oxygen). In other words, vacuum is broken between forming lid sublayer 276A and lid sublayer 276B, exposing device 200 to air (e.g., atmospheric oxygen) between these processing steps. In some embodiments, lid sublayer 276A and lid sublayer 276B are formed in the same processing chamber, and vacuum is broken between forming lid sublayer 276A and lid sublayer 276B. In some embodiments, lid sublayer 276A and lid sublayer 276B are formed in different process chambers of a semiconductor process tool and / or semiconductor process system, and vacuum is broken when device 200 is transferred from the process chamber used to form lid sublayer 276A to the process chamber used to form lid sublayer 276B. In some embodiments, lid sublayer 276A and lid sublayer 276B are formed in different semiconductor process tools and / or different semiconductor process systems, and vacuum is broken when device 200 is transferred between semiconductor process tools and / or semiconductor process systems.

[0039] Because the vacuum is broken when forming cap layer 276, cap layer 276 is referred to as an ex-situ capping layer, and cap 274 may be referred to as an ex-situ cap. In some embodiments, breaking the vacuum before forming cap sublayer 276B exposes cap sublayer 276A to an oxygen environment. For example, when the vacuum is broken (i.e., device 200 is no longer in a vacuum-conditioned environment), cap sublayer 276A is exposed to air (e.g., atmospheric oxygen), and cap sublayer 276A may absorb oxygen from the oxygen environment, which may bond with the metal and thereby provide cap sublayer 276A with metal-oxygen bonds. As cap sublayer 276A absorbs oxygen, the exposed surface of cap sublayer 276A may be converted into a thin metal oxide layer and / or a thin metal oxynitride layer, depicted as oxidized surface 276O (also referred to as oxide layer 276O). The oxide layer 276O may include metal-oxygen bonds, metal-nitrogen bonds, metal-oxygen-nitrogen bonds, or a combination thereof. In some embodiments, the oxide layer 276O of the capping sublayer 276A has a thickness of about 0.1 nm to about 0.2 nm. In embodiments where the cap sublayer 276A includes metal-oxygen bonds before the vacuum is broken, such as embodiments where the cap sublayer 276A includes oxygen and / or oxygen has diffused into the cap sublayer 276A during fabrication of the device 200, the metal-oxygen bonds of the cap sublayer 276A may increase as the cap sublayer 276A absorbs oxygen from the oxygen environment. Forming and / or increasing metal-oxygen bonds in the capping sublayer 276A can reduce and / or repair oxygen vacancies therein. This can mitigate oxygen diffusion from the capping layer 274 and / or subsequently formed layers into the work function layer 272 and / or the gate dielectric 230A during fabrication of the device 200, thereby reducing unintended oxidation and minimizing threshold voltage shifts and / or other device performance changes (e.g., reductions in speed and / or mobility) caused by such oxidation. Furthermore, reducing and / or repairing oxygen vacancies can reduce gate resistance. In the depicted embodiment, in which the capping sublayer 276A is a TiN sublayer, the TiN sublayer can absorb oxygen from an oxygen environment, which forms and / or increases Ti-O bonds within the TiN sublayer. In such embodiments, the oxide layer 276O and / or the capping sublayer 276A can include Ti-ON bonds, Ti-OO bonds, Ti-ON bonds, or a combination thereof.

[0040] Referring to FIG. 12A and FIG. 12B , a capping layer 278 is formed over capping layer 276 (e.g., over capping sublayer 276B thereof). Capping layer 278 partially fills the top portion of gate opening 255. Because work function layer 272 fills the remaining portion of the bottom portion of gate opening 255 (i.e., gap 260), capping layer 278 is not formed in the space between adjacent channel layers 220 ′. In FIG. 12A , capping layer 278 has a U-shaped profile in the top portion of gate opening 255. In FIG. 12B , capping layer 278 surrounds channel layer 220 ′.

[0041] Cap layer 278 comprises a material with a strong oxygen affinity, which prevents oxygen from diffusing into work function layer 272 and mitigates threshold voltage shifting that may be caused by oxidation of the work function metal. For example, cap layer 278 is a silicon-containing layer that may include silicon, polycrystalline silicon, amorphous silicon, or a combination thereof. In some embodiments, cap layer 278 has a thickness of approximately 10 Å to approximately 20 Å. In the depicted embodiment, the thickness of cap layer 278 is less than the thickness of cap layer 276. In some embodiments, the thickness of cap layer 278 is greater than the thickness of cap layer 276. In some embodiments, the thickness of cap layer 278 is the same as the thickness of cap layer 276. Cap layer 278 is formed using ALD, CVD, PVD, other suitable processes, or combinations thereof. In some embodiments, cap layer 278 is formed ex situ (e.g., vacuum is broken between the formation of cap sublayer 276B and cap layer 278). In some embodiments, cap layer 278 is formed in situ (eg, without breaking vacuum between forming cap sub-layer 276B and cap layer 278).

[0042] Referring to FIG. 1 , FIG. 13A , FIG. 13B , FIG. 14A , and FIG. 14B , method 100 includes, at block 145 , forming a bulk (fill) layer 280 over cap 274 . Bulk / fill layer 280 fills the remaining portion of gate opening 255 . In FIG. 14A , bulk layer 280 has a U-shaped profile in the top portion of gate opening 255 . In FIG. 14B , bulk layer 280 wraps around channel layer 220 ′. Because work function layer 272 fills the remaining portion of the bottom portion of gate opening 255 (i.e., gap 260 ), bulk / fill layer 280 is not formed in the space between adjacent channel layers 220 ′.

[0043] Bulk / fill layer 280 includes a conductive material, such as Al, W, Cu, Ti, Ta, polysilicon, other suitable metals, and / or alloys thereof, or combinations thereof. Referring to FIG. 13A and FIG. 13B , the conductive material is deposited (e.g., by ALD, CVD, PVD, other suitable processes, or combinations thereof) over dielectric layer 250 and fills gate opening 255. In some embodiments, bulk layer 280 is a tungsten layer formed by PVD or CVD. In some embodiments, bulk layer 280 is a fluorine-free tungsten (FFW) layer. In some embodiments, bulk layer 280 is formed ex situ (e.g., vacuum is broken between forming cap layer 278 and bulk layer 280). In some embodiments, bulk layer 280 is formed in situ (e.g., vacuum is not broken between forming cap layer 278 and bulk layer 280).

[0044] In some embodiments, bulk layer 280 has a multi-layer structure, such as a glue layer and a metal fill layer (e.g., a tungsten layer). The glue layer may include a material that promotes adhesion between adjacent layers (such as between work function layer 272 / capping member 274 and a subsequently formed metal fill layer) and / or a material that prevents or eliminates diffusion and / or reaction of components between adjacent layers. For example, the glue layer may include a metal and nitrogen, such as TiN, TaN, W2N, TiSiN, TaSiN, other suitable metal nitride materials, or combinations thereof. The glue may be formed ex situ (e.g., with vacuum broken between forming capping layer 278 and the glue layer) or in situ (e.g., without vacuum broken between forming capping layer 278 and the glue layer). The metal fill layer may be formed ex situ (e.g., with vacuum broken between forming the glue layer and the metal fill layer) or in situ (e.g., without vacuum broken between forming the glue layer and the metal fill layer).

[0045] Referring to FIG. 14A and FIG. 14B , a planarization process is performed to remove excess gate material, such as that disposed above the dielectric layer 250. For example, the CMP process removes portions of the bulk layer 280, the capping member 274 (e.g., the capping layer 276 and the capping layer 278), the work function layer 272, and the high-k dielectric layer 264 disposed above the dielectric layer 250. The CMP process may be performed until the top surface of the dielectric layer 250 is reached and / or exposed. In some embodiments, the CMP process may continue to reduce the thickness of the dielectric layer 250 and, accordingly, reduce the height of the gate structure 230 (e.g., its gate stack). In the depicted embodiment, after the planarization process, the top of the gate structure 230 is substantially planar with the top of the dielectric layer 250, and the gate material fills the remaining portion of the gate opening 255 to form the gate stack of the gate structure 230.

[0046] Thus, method 100 provides device 200 with a gate stack having a gate dielectric 230A (e.g., interface layer 262 and high-k dielectric layer 264) and a gate dielectric 230B (e.g., bulk / fill layer 280, capping member 274 (e.g., capping layer 276 and capping layer 276), and work function layer 272). Because gate dielectric layer 230A includes high-k dielectric layer 264, the gate stack can be referred to as a high-k metal gate. As described above, introducing vacuum break during the formation of capping layer 276 (and thereby introducing oxygen into the gate stack) can improve device performance by reducing oxidation, minimizing threshold voltage variation, increasing speed and / or mobility, or a combination thereof. However, it has been observed that when the capping layer 276 is incorporated and / or formed in the inner region of the gate stack (i.e., those regions between adjacent channel layers 220' and / or between the bottom channel layer 220' and the mesa 202'), the oxygen content in the outer region of the gate stack (e.g., those regions not between adjacent channel layers 220' and / or between the bottom channel layer 220' and the mesa 202') is greater than the oxygen content in the inner region of the gate stack, which can lead to undesirable threshold voltage changes. The disclosed gate stack reduces the oxygen difference between the inner and outer regions by filling the spaces between adjacent channel layers 220' and / or between the bottom channel layer 220' and the mesa 202' with the work function layer 272, so that the capping layer 276 is not incorporated and / or formed in the inner region of the gate stack.

[0047] Referring to FIG. 16A and FIG. 16B , FIG. 16A is an energy-dispersive X-ray spectroscopy (EDX) graph 300A of oxygen in the inner and outer regions of a gate stack having a cap (e.g., a portion of cap layer 276) in the inner region according to various aspects of the present disclosure, and FIG. 16B is an EDX graph 300B of oxygen in the inner and outer regions of a gate stack without a cap in the inner region according to various aspects of the present disclosure, such as the gate stack of device 200. Each of EDX graphs 300A and 300B has a y-axis representing oxygen concentration (in arbitrary units) and an x-axis representing position within the gate stack (in nanometers (nm)). EDX images 300A and 300B provide outer oxygen profiles obtained from the outer film layer stacks of their respective gate stacks (e.g., outer film layer stack 302A and outer film layer stack 302B), and the outer oxygen profiles are represented by curves 304A and 304B, respectively. The outer film layer stacks may include an interfacial (IL) layer (e.g., interfacial layer 262), a high-k (HK) dielectric layer (e.g., high-k dielectric layer 264), a work function (WF) layer (e.g., work function layer 272), and a cap layer formed by cap 1 (e.g., cap layer 276) and cap 2 (e.g., cap layer 278). Outer film layer stacks 302A and 302B may be portions of the gate stacks disposed along the sidewalls of the respective channel layers or disposed on top of the respective uppermost channel layers. Outer film layer stack 302A is distinct from outer film layer stack 302B. For example, the thickness of the WF layer of the outer film layer stack 302A is smaller than the thickness of the WF layer of the outer film layer stack 302B, and the total thickness of the covers (eg, cover 1 and cover 2) of the outer film layer stack 302A is greater than the thickness of the covers of the outer film layer stack 302B.

[0048] EDX images 300A and 300B also provide internal oxygen profiles obtained from the inner film layer stacks of their respective gate stacks (e.g., inner film layer stack 310A and inner film stack 310B), and the internal oxygen profiles are represented by curves 312A and 312B, respectively. The inner film layer stacks may include an IL layer (e.g., interface layer 262) and an HK layer (e.g., high-k dielectric layer 264). Inner film layer stack 310A differs from inner film layer stack 310B. For example, inner film layer stack 310A also includes a WF layer (e.g., work function layer 272) and a portion of a cap layer, such as a portion of cap 1 (e.g., cap layer 276), while inner film layer stack 310B also includes a WF layer (e.g., work function layer 272) but does not include a portion of the cap layer. Inner film layer stack 310A and inner film layer stack 310B may be portions of the gate stack located between adjacent channel layers, such as between the respective topmost channel layer and the respective intermediate channel layer. Thus, the gate stack corresponding to the EDX image 300B does not include a cap between adjacent channel layers and may be configured like the gate stack of the device 200 described herein.

[0049] For the gate stack corresponding to EDX image 300A, region 320A of EDX image 300A corresponds to the gate electrode portion of the gate stack, which forms part of both the outer film layer stack 302A and the inner film layer stack 310A. As shown by curves 304A and 312A, in region 320A, the outer and inner oxygen concentrations are substantially similar (i.e., the difference between them is relatively small) until the WF layer reaches a thickness t, at which point the outer oxygen concentration begins to increase and the inner oxygen concentration begins to decrease. Therefore, the oxygen content of the upper portion of the WF layer in the outer film layer stack 302A is greater than the oxygen content of the upper portion of the WF layer in the inner film layer stack 310A, and the oxygen content of the lower portion of the cap 1 in the outer film layer stack 302A is greater than the oxygen content of the lower portion of the cap 1 in the inner film layer stack 310A. In some cases, it has been observed that a gate stack configured as a gate stack corresponding to the EDX diagram 300A has a ratio of oxygen content in the outer region to oxygen content in the inner region of about 1.3 to about 1.5 (e.g., about 1.4). This oxygen content difference and / or oxygen content ratio may undesirably increase the threshold voltage, for example, from about 70 millivolts (mV) to about 80 mV.

[0050] In contrast, as shown by curves 304B and 312B in region 320B of EDX image 300B, which corresponds to the gate electrode portion of the gate stack and forms a portion of the outer film layer stack 302B and the inner film layer stack 310B, the outer and inner oxygen concentrations are substantially similar (i.e., the difference between them is relatively small) throughout the thickness of region 320B. Thus, while the oxygen content of the outer film layer stack 302B may be slightly greater than the oxygen content of the inner film layer stack 310B, the difference between them is significantly less than the difference provided when both the cap 1 and the WF layer form the remainder of the inner film layer stack (e.g., inner film layer stack 310A). A gate stack configured as a gate stack corresponding to EDX image 300B (such as disclosed herein) can therefore reduce the ratio of the oxygen content in the outer region of the gate stack to the oxygen content in the inner region. In some cases, a gate stack configured to correspond to the EDX map 300B (e.g., the gate stack of device 200) has a ratio of oxygen content in the outer region to oxygen content in the inner region of about 1.0 to about 1.25 (e.g., about 1.1). Such an oxygen content difference and / or oxygen content ratio can reduce the threshold voltage to, for example, about 40 mV to about 50 mV, which can improve performance.

[0051] Furthermore, increasing the thickness of the WF layer (e.g., T0) in the outer film layer stack 302B relative to the thickness of the WF layer (e.g., T1) in the inner film layer stack 310B can reduce oxygen migration and / or diffusion into the inner film layer stack 310B. For example, the WF layer of the gate stack corresponding to the EDX image 300B is configured with a sacrificial / buffer portion (i.e., a portion of the WF layer (e.g., having a thickness of t2) deposited / grown after filling the space between adjacent channel layers). This can compensate for oxygen diffusion and / or migration into the WF layer that occurs during the formation of the cap 1 and / or other subsequently deposited gate stacks. In other words, the outer film layer stack 302B is configured to address oxygen diffusion into the WF layer and provide a greater distance between the cap 1 and the portion of the WF layer belonging to the inner film layer stack 310B. Therefore, as shown by curve 304B in the region corresponding to the sacrificial portion of the WF layer in the EDX image 300B, the oxygen content of the sacrificial portion of the WF layer begins to increase, and the oxygen content of the WF layer of the outer film layer stack 302B decreases from the first oxygen concentration to the second oxygen concentration, and then increases from the second oxygen concentration to a third oxygen concentration that is less than the first oxygen concentration.

[0052] Referring again to FIG. 14A and FIG. 14B , the disclosed gate stack having an inner film layer stack formed of a gate dielectric and a low aluminum content work function layer (e.g., less than about 33 at%) and its fabrication method offer numerous advantages. Compared to devices having a gate stack having an inner film layer stack configured with a gate dielectric layer, a high aluminum content work function layer (e.g., greater than 33 at% to compensate for its thinness), and an ex-situ cap (e.g., a portion of a metal nitride layer), the gate stack of device 200 omits the cap in its inner film layer stack, thereby reducing gate induced leakage current (I gi ), subthreshold leakage current (I sb ), and overall gate resistance (R g ) by approximately 0.5 times to approximately 0.8 times (in some cases, by as much as 40%), improving time-dependent dielectric breakdown (TDDB), or a combination thereof. Such improvements can be achieved while maintaining and / or reducing a desired threshold voltage and / or reducing the threshold voltage variation between the inner and outer film layer stacks of the gate stack. Different embodiments may have different advantages, and no embodiment requires a particular advantage.

[0053] Referring to FIG. 15A and FIG. 15B , in some embodiments, when work function material 272' is deposited as described with reference to FIG. 8A and FIG. 8B , portions of work function material 272' along the sidewalls of channel layer 220' may merge at the ends of gap 260 before completely filling the middle of gap 260, resulting in air gaps 290 (also referred to as voids) forming within the spaces between work function layer 272 and channel layer 220'. In such embodiments, respective air gaps 290 are formed between a portion of work function material 272' formed along the bottom of a first channel layer 220' and a portion of work function material 272' formed along the top of a second channel layer 220'. Air gaps 290 can have various shapes and profiles, and in some embodiments, more than one air gap can be formed in the space between adjacent channel layers 220'. In the depicted embodiment, the length of air gaps 290 is greater than or equal to the width of channel layer 220'. In some embodiments, the length of the air gap 290 is less than the width of the channel layer 220'.

[0054] In some embodiments, the process may further include etching back the gate electrode 230B and / or the gate dielectric 230A and forming a hard mask, such as a self-aligned cap (SAC), over the etched-back gate electrode 230B and / or the gate dielectric 230A. The hard mask may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, other suitable dielectric materials, or combinations thereof.

[0055] In some embodiments, the process may further include forming interconnects, such as gate contacts and / or source / drain contacts. In some embodiments, forming the source / drain contacts includes forming source / drain contact openings in dielectric layer 250 that expose the epitaxial source / drain (e.g., epitaxial source / drain 225) and forming at least one conductive layer (e.g., metal) in the source / drain contact openings. In some embodiments, the source / drain contact openings are formed by forming a patterned mask layer (e.g., an etch mask) over dielectric layer 250 and etching the exposed portions of dielectric layer 250. In some embodiments, the step of forming at least one conductive layer in the source / drain contact opening includes forming a metal silicide layer over the epitaxial source / drain, depositing a barrier / liner layer that partially fills the source / drain contact opening, depositing a metal layer over the barrier / liner layer that fills the remaining portion of the source / drain contact opening, and performing a planarization process to remove portions of the barrier / liner layer and / or metal layer disposed over the dielectric layer 250 and / or the top of the gate structure 230. In some embodiments, one or more insulating layers may be formed in the source / drain contact opening and processed to form contact spacers, such as dielectric layers and / or air gaps, along the sidewalls of the conductive portions of the source / drain contacts (e.g., the barrier layer and / or the bulk metal layer).

[0056] In some embodiments, the device 200 is an n-type transistor, and portions of the gate stack are formed simultaneously with the p-type transistor. For example, the process may include forming the interfacial layer 262 and the high-k dielectric layer 264 simultaneously with the interfacial layer and the high-k dielectric layer of the gate stack of the p-type transistor; masking the p-type device region including the p-type transistor with a first mask layer (e.g., a hard mask layer and / or a photoresist layer) and forming the work function layer 272, the cap layer 276, and the cap layer 278; removing the first mask layer; masking the n-type device region including the n-type transistor (e.g., device 200) with a second mask layer (e.g., a hard mask layer and / or a photoresist layer) and forming the work function layer (e.g., a P-WFM layer) and / or the cap of the gate stack of the p-type transistor; removing the second mask layer; and forming the bulk layer 282 simultaneously with the bulk layer of the p-type transistor (e.g., forming the bulk layer (e.g., bulk layer 282) in both the p-type device region and the n-type device region). In such an embodiment, the work function layer and the cap of the n-type transistor are formed before the work function layer of the p-type transistor. In some embodiments, the work function layer and the cap of the n-type transistor are formed after the work function layer of the p-type transistor. For example, the process may include forming the interfacial layer 262 and the high-k dielectric layer 264 simultaneously with the interfacial layer and the high-k dielectric layer of the gate stack of the p-type transistor; masking the n-type device region including the n-type transistor (e.g., device 200) with a first mask layer (e.g., a hard mask layer and / or a photoresist layer) and forming a work function layer (e.g., a P-WFM layer) and / or a cap of the gate stack of the p-type transistor; removing the first mask layer; masking the p-type device region including the p-type transistor with a second mask layer (e.g., a hard mask layer and / or a photoresist layer) and forming the work function layer 272, the cap layer 276, and the cap layer 278; removing the second mask layer; and forming the bulk layer 282 simultaneously with the bulk layer of the p-type transistor. The present disclosure contemplates various process flows for implementing the gate fabrication methods herein.

[0057] The present disclosure provides many different embodiments. The gate stacks disclosed herein can be implemented in a variety of device types. For example, the gate stacks described herein are suitable for planar field-effect transistors (planar FETs), multi-gate transistors such as fin field-effect transistors (FinFETs), gate-all-around (GAA) field-effect transistors, omega-gate (Ω-gate) devices, pi-gate (π-gate) devices, fork-sheet devices, or combinations thereof, as well as strained-semiconductor devices, silicon-on-insulator (SOI) devices, partially-depleted SOI devices, fully-depleted SOI devices, other devices, or combinations thereof. The gate stacks described herein are also suitable for stacked transistor devices, such as complementary field-effect transistors (CFETs).

[0058] FIG17 is a cross-sectional view of a portion or all of a stacked device structure 400 that can implement the gate stacking described herein, according to various aspects of the present disclosure. Stacked device structure 400 includes a device stack 412A and a device stack 412B. Device stack 412A and device stack 412B each include a respective upper device 414U vertically stacked above a respective lower device 414L. Devices 414U and 414L are disposed above a substrate 415, and isolation structures 416 are disposed between and separate devices 414U and 414L. Isolation structures 416 include isolation structures 417 and 418. In some embodiments, devices 414U and 414L are stacked back-to-front. For example, the back side of device 414U is bonded and / or attached to the front side of device 414L. FIG17 has been simplified for clarity to facilitate a better understanding of the inventive concepts of the present disclosure. Additional components may be added to the stacked device structure 400 , and some of the components described below may be replaced, modified, or deleted in other embodiments of the stacked device structure 400 .

[0059] Device 414U and device 414L include at least one electrically functional device. For example, device stack 412A is a transistor stack including an upper transistor 420U-1 and a lower transistor 420L-1, and device stack 412B is a transistor stack including an upper transistor 420U-2 and a lower transistor 420L-2. Transistor 420U-1 can be separated and / or electrically isolated from transistor 420L-1 by isolation structure 416, and transistor 420U-2 can be separated and / or electrically isolated from transistor 420L-2 by isolation structure 416. In the depicted embodiment, transistor 420U-1 and transistor 420L-1 have opposite conductivity types, and transistor 420U-2 and transistor 420L-2 have opposite conductivity types. For example, transistors 420U-1 and 420U-2 are n-type transistors, and transistors 420L-1 and 420L-2 are p-type transistors, or vice versa. In such embodiments, transistors 420U-1 and 420L-1 form a first CFET, and transistors 420U-2 and 420L-2 form a second CFET. In some embodiments, transistors 420U-1 and 420L-1 have the same conductivity type, and / or transistors 420U-2 and 420L-2 have the same conductivity type. For example, transistors 420U-1 and 420L-1 and / or transistors 420U-2 and 420L-2 are both n-type transistors or both p-type transistors.

[0060] The device 414U includes various components and / or elements, such as a semiconductor layer 426U, a semiconductor layer 426M, a gate spacer 444, an inner spacer 454, an epitaxial source / drain 462U, a CESL 470U, an ILD layer 472U, a gate dielectric (e.g., a gate dielectric 478U-1 and a gate dielectric 478L-1), a gate electrode (e.g., a gate electrode 480U-1 and a gate electrode 480L-1), and a hard mask 492. The gate dielectric 478U-1 and the gate electrode 480U-1 together form an upper gate stack 490U-1, and the gate dielectric 478L-1 and the gate electrode 480L-1 together form a lower gate stack 490L-1. Gate stack 490U-1 and gate stack 490L-1 are collectively referred to as gate 490A of device stack 412A, and gate 490A may provide a metal gate or high-k metal gate for the first CFET. Gate stack 490U-1 is separated from gate stack 490L-1 by a corresponding isolation structure 417 (and semiconductor layer 426M in the depicted embodiment), and the epitaxial source / drain 462U of device 414U is separated from the epitaxial source / drain 462L of device 414L by an isolation structure 418.

[0061] The device 414L includes various components and / or elements, such as a mesa 415′ (e.g., an extension of the substrate 415), a semiconductor layer 426L, a semiconductor layer 426M, a substrate isolation structure 28, an inner spacer 454, an epitaxial source / drain 462L, a CESL 470L, an ILD layer 472L, gate dielectrics (e.g., gate dielectric 478U-2 and gate dielectric 478L-2), and gate electrodes (e.g., gate electrode 480U-2 and gate electrode 480L-2). The gate dielectric 478U-2 and the gate electrode 480U-2 together form an upper gate stack 490U-2, and the gate dielectric 478L-2 and the gate electrode 480L-2 together form a lower gate stack 490L-2. Gate stack 490U-2 and gate stack 490L-2 are collectively referred to as gate 490B of device stack 412B, and gate 490B provides the metal gate or high-k metal gate of the second CFET. Gate stack 490U-2 is separated from gate stack 490L-2 by a corresponding isolation structure 417 (and semiconductor layer 426M), and the epitaxial source / drain 462L of device 414L is separated from the epitaxial source / drain 462U of device 414L by an isolation structure 418.

[0062] Transistor 420L-1 and transistor 420L-2 are configured as GAA transistors. For example, each of transistor 420L-1 and transistor 420L-2 has two channels (e.g., nanowires, nanosheets, nanorods, etc.) provided by semiconductor layer 426L (also referred to as a channel layer or channel), which is suspended above substrate 415 and extends between corresponding source / drain electrodes (such as epitaxial source / drain electrodes 462L). In some embodiments, transistor 420L-1 and / or transistor 420L-2 include more or fewer channels (and therefore more or fewer semiconductor layers 426L). Transistor 420L-1 has a gate stack 490L-1 disposed above its semiconductor layer 426L and between its epitaxial source / drain 462L. Transistor 420L-2 has a gate stack 490L-2 disposed above its semiconductor layer 426L and between its epitaxial source / drain 462L. Along the gate width direction, gate stacks 490L-1 and 490L-2 are disposed above and between the corresponding top semiconductor layer 426L, and between the corresponding bottom semiconductor layer 426L and substrate 415 (e.g., its mesa 415'). Along the gate length direction, gate stacks 490L-1 and 490L-2 may wrap around and / or surround the corresponding semiconductor layer 426L. During operation of the GAA transistors, current can flow between the corresponding semiconductor layer 426L and the corresponding epitaxial source / drain 462L. In the depicted embodiment, transistor 420L-1 and transistor 420L-2 have a common epitaxial source / drain 462L, such as a middle epitaxial source / drain 462L. In some embodiments, transistor 420L-1 and transistor 420L-2 do not have a common epitaxial source / drain 462L. Each of transistors 420L-1 and 420L-2 also has a semiconductor layer 426M (also referred to as a dummy channel layer or dummy channel) suspended above substrate 415 and extending between corresponding isolation structures 418. A corresponding isolation structure 417 is disposed between the semiconductor layer 426M of transistors 420L-1 and 420U-1, and a corresponding isolation structure 417 is disposed between the semiconductor layer 426M of transistors 420L-2 and 420U-2. Furthermore, each of transistors 420L-1 and 420L-2 has an inner spacer 454 disposed between its gate stack (e.g., gate stack 490L-1 or gate stack 490L-2) and its epitaxial source / drain 462L.

[0063] Transistor 420U-1 and transistor 420U-2 are also configured as GAA transistors. For example, each of transistor 420U-1 and transistor 420U-2 has two channels (e.g., nanowires, nanosheets, nanorods, etc.) provided by semiconductor layer 426U (also referred to as a channel layer or channel), which is suspended above substrate 415 and extends between corresponding source / drain electrodes (such as epitaxial source / drain electrodes 462U). In some embodiments, transistor 420U-1 and / or transistor 420U-2 includes more or fewer channels (and therefore more or fewer semiconductor layers 426U). Transistor 420U-1 has a gate stack 490U-1 disposed above its semiconductor layer 426U and between its epitaxial source / drain 462U. Transistor 420U-2 has a gate stack 490U-2 disposed above its semiconductor layer 426U and between its epitaxial source / drain 462U. Along the gate width, gate stack 490U-1 and gate stack 490U-2 are located above and between the corresponding top semiconductor layer 426U, and between the corresponding semiconductor layers 426U and the corresponding semiconductor layer 426M. Along the gate length, gate stack 490U-1 and gate stack 490U-2 may wrap around and / or surround the corresponding semiconductor layer 426U. During operation of the GAA transistor, current may flow between the corresponding semiconductor layer 426U and the corresponding epitaxial source / drain 462U. In the depicted embodiment, transistor 420U-1 and transistor 420U-2 have a common epitaxial source / drain 462U, such as an intermediate epitaxial source / drain 462U. In some embodiments, transistor 420U-1 and transistor 420U-2 do not have a common epitaxial source / drain 462U. Furthermore, each of transistors 420U-1 and 420U-2 has gate spacers 444 disposed along the sidewalls of an upper portion of its gate stack (e.g., gate stack 490L-1 or gate stack 490L-2), inner spacers 454 disposed between its gate stack and its epitaxial source / drain 462U, and a hard mask 492 disposed above its gate stack and between its gate spacers 444. The hard mask 492 can be considered part of the gate stack.

[0064] Isolation structure 416 includes isolation structure 417 and isolation structure 418, respectively, located between the channel region and source / drain region of device 414L and device 414U. For example, isolation structure 417 is located between the channel region of the lower transistor (e.g., transistor 420L-1) and the channel region of the upper channel (e.g., transistor 420U-1) (e.g., between their channels and / or their gates), and isolation structure 418 is located between the source / drain region of the lower transistor (e.g., transistor 420L-1) and the source / drain region of the upper channel (e.g., transistor 420U-1). In the depicted embodiment, isolation structure 417 is located between semiconductor layer 426M of the lower transistor and the upper transistor, and isolation structure 418 is located between epitaxial source / drain 462L of the lower transistor and epitaxial source / drain 462U of the upper transistor. Thus, isolation structure 417 can provide electrical isolation for the channel and / or gate of the stacked device, and isolation structure 418 can provide electrical isolation for the source / drain of the stacked device. Isolation structure 417 and isolation structure 418 can comprise a single layer or multiple layers. Isolation structure 417 and isolation structure 418 comprise a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or combinations thereof). Isolation structure 417 and isolation structure 418 can comprise the same or different materials and / or configurations. In the depicted embodiment, the thickness of isolation structure 417 is less than the thickness of isolation structure 418, and the configuration of isolation structure 417 is different from the configuration of isolation structure 418. In some embodiments, isolation structures 418 include CESL 470L and ILD layer 472L, as shown (ie, each isolation structure 418 is formed from a respective portion of CESL 470L and a respective portion of ILD layer 472L).

[0065] Substrate 415 can be similar to substrate 202 described above, mesa 415′ can be similar to mesa 202′ described above, and semiconductor layers 426U, 426M, and 426L can be similar to semiconductor layers 220 and 220′ described above. For example, in the depicted embodiment, substrate 415, mesa 415′, semiconductor layers 426U, 426M, and 426L comprise silicon. In some embodiments, semiconductor layers 426U and 426L comprise different semiconductor materials, such as silicon and silicon-germanium, respectively, or vice versa. In such embodiments, semiconductor layer 426M of the upper transistor and semiconductor layer 426M of the lower transistor can comprise different materials. For ease of description herein, semiconductor layers 426U, 426M, and 426L may be collectively referred to as semiconductor layers 426.

[0066] Gate spacers 444 are disposed along the sidewalls of the top portion of the upper gate stacks (e.g., gate stacks 490U-1 and 490U-2). Inner spacers 454 are disposed below gate spacers 444 along the sidewalls of the upper gate stacks 490U and / or lower gate stacks (e.g., gate stacks 490L-1 and 490L-2). Fin / mesa spacers may also be disposed along the sidewalls of the mesas 415'. Inner spacers 454 are located between semiconductor layers 426U, between semiconductor layers 426L, between the bottom semiconductor layer 426U and semiconductor layer 426M, between the top semiconductor layer 426L and semiconductor layer 426M, and between the bottom semiconductor layer 426M and the mesas 415'. Gate spacers 444 may be similar to gate spacers 240 described above, and inner spacers 454 may be similar to inner spacers 224 described above.

[0067] Each of gates 490A and 490B is disposed between respective epitaxial source / drain stacks. Each epitaxial source / drain stack includes a corresponding epitaxial source / drain 462U, a corresponding epitaxial source / drain 462L, and a corresponding isolation structure 418 therebetween. Epitaxial source / drain 462L and epitaxial source / drain 462U can be similar to epitaxial source / drain 225 described above. Epitaxial source / drain 462L and epitaxial source / drain 462U can have the same or different compositions and / or materials depending on the configuration of their respective transistors. For example, where the upper transistor is an n-type field effect transistor (NFET) and the lower transistor is a p-type field effect transistor (PFET), such as in the depicted embodiment, the epitaxial source / drain 462U may include silicon doped with phosphorus and / or carbon, and the epitaxial source / drain 462L may include silicon germanium doped with boron.

[0068] ILD layer 472U and ILD layer 472L can be similar to ILD layer 254 described above, and CESL 470L and CESL 470U can be similar to CESL 252 described above. Gate dielectric 478U-1, gate dielectric 478L-1, gate dielectric 478U-2, and gate dielectric 478L-2 each include at least one dielectric gate layer, such as an interfacial layer and / or a high-k dielectric layer, as described further below. Gate electrode 480U-1, gate electrode 480L-1, gate electrode 480U-2, and gate electrode 480L-2 each include at least one conductive gate layer, such as a work function layer, a metal fill (bulk) layer, additional layers (e.g., a barrier layer and / or one or more capping layers), or combinations thereof. The gate dielectric 478U-1, gate dielectric 478L-1, gate dielectric 478U-2, gate dielectric 478L-2, or a combination thereof can be similar to the gate dielectric 230A described above. The gate electrode 480U-1, gate electrode 480L-1, gate electrode 480U-2, gate electrode 480L-2, or a combination thereof can be similar to the gate dielectric 230A described above. In some embodiments, the composition and / or configuration of the gate dielectric 478U-1 and gate dielectric 478U-2 differ from the composition and / or configuration of the gate dielectric 478L-1 and gate dielectric 478L-2. In some embodiments, the composition and / or configuration of the gate electrode 480U-1 and gate electrode 480U-2 differ from the composition and / or configuration of the gate electrode 480L-1 and gate electrode 480L-2. For example, gate electrodes 480U-1 and 480U-2 can be configured as gate electrode 230B, and gate electrodes 480L-1 and 480L-2 can be configured differently from gate electrode 230B. In some embodiments, the work function layers of gate electrodes 480U-1 and 480U-2 can be n-type work function layers, and the work function layers of gate electrodes 480L-1 and 480L-2 can be p-type work function layers. In some embodiments, gate electrodes 480U-1, 480L-1, 480U-2, and 480L-2 have the same type of work function layer (e.g., n-type metal (n-metal) or p-type metal (p-metal)). In some embodiments, gate electrode 480U-1 and gate electrode 480U-2 each include a first work function layer, and gate electrode 480L-1 and gate electrode 480L-2 each include a second work function layer. The first work function layer and the second work function layer may include different types of work function layers (e.g., p-type metal and n-type metal, respectively).

[0069] Hard mask 492 comprises a different material than ILD layer 472U and / or subsequently formed ILD layers to achieve etch selectivity during subsequent etching processes. In some embodiments, hard mask 492 comprises silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, hard mask 492 comprises a metal and oxygen and / or nitrogen, such as aluminum oxide (e.g., AlO or Al2O3), aluminum nitride (e.g., AlN), aluminum oxynitride (e.g., AlON), zirconium oxide, zirconium nitride, hafnium oxide (e.g., HfO or HFO2), zirconium aluminum oxide (e.g., MgO), other metal oxides, other metal nitrides, or combinations thereof.

[0070] An exemplary method includes forming a first semiconductor layer and a second semiconductor layer over a substrate. The first semiconductor layer is disposed over the second semiconductor layer with a space between the first and second semiconductor layers. The method also includes forming a gate dielectric over the first and second semiconductor layers. The gate dielectric partially fills the space between the first and second semiconductor layers. The method also includes forming a work function layer over the gate dielectric. The work function layer fills the remaining portion of the space between the first and second semiconductor layers. The method also includes forming a cap over the work function layer. In some embodiments, the method also includes forming a metal fill layer over the cap.

[0071] In some embodiments, an air gap is formed in a work function layer located in a space between the first semiconductor layer and the second semiconductor layer. In some embodiments, forming the work function layer includes depositing a conductive material including titanium, aluminum, and carbon. In some embodiments, forming the work function layer provides a first portion of the work function layer along a bottom portion of the first semiconductor layer, the first portion having a first thickness that is less than approximately twice a second thickness of a second portion of the work function layer along a top portion of the first semiconductor layer.

[0072] In some embodiments, the step of forming the cap includes forming a metal nitride layer above the work function layer and forming a silicon-containing layer above the metal nitride layer. In some embodiments, the step of forming the metal nitride layer includes forming a first metal nitride sublayer above the work function layer and forming a second metal nitride sublayer after breaking vacuum. In some embodiments, the first semiconductor layer and the second semiconductor layer form a channel stack, and the cap is disposed above the top of the channel stack along a first direction and surrounds the channel stack along a second direction.

[0073] In some embodiments, forming a work function layer includes depositing a conductive material having a thickness around the first semiconductor layer and the second semiconductor layer. In the space between the first semiconductor layer and the second semiconductor layer, the conductive material having a thickness around the first semiconductor layer merges with the conductive material having a thickness around the second semiconductor layer. In such embodiments, forming a work function layer also includes continuing the deposition step to increase the thickness of the conductive material along the sidewalls of the first semiconductor layer, the sidewalls of the second semiconductor layer, and the top of the first semiconductor layer.

[0074] In some embodiments, the method includes removing the dummy gate to form a gate opening exposing the semiconductor stack, and performing a channel release process to remove the third semiconductor layer from the semiconductor stack, thereby suspending the first semiconductor layer above the second semiconductor layer and suspending the second semiconductor layer above the substrate.

[0075] An exemplary method for forming a gate stack for a transistor includes forming a first interface layer around a first channel layer and forming a second interface layer around a second channel layer. The channel stack includes a first channel layer disposed above a second channel layer. The first interface layer partially fills a space between the first channel layer and the second channel layer, and the second interface layer partially fills a space between the first channel layer and the second channel layer. The method includes forming a first high-k dielectric layer above and around the first interface layer, and forming a second high-k dielectric layer above and around the second interface layer. The first high-k dielectric layer partially fills a space between the first channel layer and the second channel layer, and the second high-k dielectric layer partially fills a space between the first channel layer and the second channel layer. The method includes forming a work function layer around the first channel layer and the second channel layer. The work function layer fills a remaining portion of the space between the first channel layer and the second channel layer.

[0076] The step of forming the work function layer can be performed by depositing a work function material until a first portion of the work function material merges with a second portion of the work function material, the first portion being formed above the first high-k dielectric layer and around the first channel layer, and the second portion being formed above the second high-k dielectric layer and around the second channel layer. The first portion of the work function material and the second portion of the work function material merge in the space between the first channel layer and the second channel layer. The work function layer can also be formed by continuously depositing the work function material to increase the thickness of the first portion of the work function material and the second portion of the work function material. In some embodiments, in the space between the first channel layer and the second channel layer, the ends of the first portion of the work function material and the second portion of the work function material merge before their centers, thereby forming an air gap between the first portion of the work function material and the second portion of the work function material in the space between the first channel layer and the second channel layer. In some embodiments, the work function layer is a titanium aluminum carbide layer, and the aluminum content of the work function layer is approximately 25 at% to approximately 33 at%.

[0077] The method also includes forming a cap over the work function layer. The cap surrounds the channel stack. The step of forming the cap may include forming a first metal nitride layer over the work function layer and forming a second metal nitride layer over the first metal nitride layer. The second metal nitride layer may be formed after breaking vacuum. The step of forming the cap may also include forming a silicon-containing layer over the second metal nitride layer. In some embodiments, the first metal nitride layer is a first titanium nitride layer, and the second metal nitride layer is a second titanium nitride layer. In some embodiments, after forming the cap, an outer region of the gate stack has a first oxygen content, an inner region of the gate stack has a second oxygen content, a ratio of the first oxygen content to the second oxygen content is from about 1 to about 1.25, the inner region of the gate stack fills the space between the first channel layer and the second channel layer, and the outer region of the gate stack is not in the space between the first channel layer and the second channel layer.

[0078] In some embodiments, the gate opening exposes the first and second channel layers, and includes a first interfacial layer, a first high-k dielectric layer, a work function layer, and a cap that partially fills a top portion of the gate opening above the first channel layer. In such embodiments, the method may further include forming a bulk / fill layer above the cap. The bulk / fill layer may fill the remaining portion of the top portion of the gate opening and surround the channel stack. In some embodiments, the transistor is an n-type transistor, and the work function layer is an n-type work function metal layer.

[0079] An exemplary transistor includes a first channel layer, a second channel layer, and a gate stack. The gate stack includes a gate dielectric disposed around the first and second channel layers. The gate dielectric includes an interface layer and a high-k dielectric layer disposed above the interface layer. The gate stack also includes a gate electrode disposed above the gate dielectric. The gate electrode is located around the first and second channel layers. The gate electrode includes a work function layer disposed above the high-k dielectric layer. The work function layer is located around the first and second channel layers. The gate electrode also includes a cap disposed above the work function layer. The cap includes a metal nitride layer disposed above the work function layer and a silicon layer disposed above the metal nitride layer. The gate dielectric and the work function layer fill the space between the first and second channel layers. An outer region of the gate stack has a first oxygen content, an inner region of the gate stack has a second oxygen content, and a ratio of the first oxygen content to the second oxygen content is approximately 1 to approximately 1.25. Furthermore, a first thickness of the work function layer in the outer region of the gate stack is greater than a second thickness of the work function layer in the inner region of the gate stack. In some embodiments, the work function layer comprises titanium, aluminum, and carbon. In some embodiments, the aluminum content of the work function layer is from about 25 atomic percent (at%) to about 33 at%. In some embodiments, an air gap is located in the work function layer.

[0080] The above overview of several embodiments is provided to facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that they can design or modify other processes and structures based on the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

[0081] 100: Method 105: Block 110: Block 115: Block 120: Block 125: Block 130: Block 135: Block 140: Block 145:Block 200: Installation 202:Substrate 202': table 210:Semiconductor stacking 215: semiconductor layer 220: semiconductor layer 220': Channel layer 222: substrate isolation structure 224:Internal spacer 225: Source / Drain (S / D) 230: Gate structure 230A: Gate dielectric 232: Virtual Gate 240: Gate spacer 250: dielectric layer 252: Contact etch stop layer (CESL) 254: Interlayer dielectric (ILD) layer 255: Gate opening 260: Gap 262: Interface layer 264: High dielectric constant dielectric layer 272: Work function layer 272': Work function layer 274: Cover 276: Covering 276A: Cover sublayer 276B: cap layer 276O: Oxide layer 278: Covering 280: Cover block (filling) layer 282: Block layer 290: Air Gap 300A: EDX image 300B:EDX image 302A: Outer film layer stacking 302B: Outer film layer stacking 304A: Curve 304B: Curve 310A: Inner film layer stacking 310B: Inner membrane layer stacking 312A: Curve 312B: Curve 320A: Area 320B: Area 400: stacking device structure 412A: Device stacking 412B: Device stacking 414L: Lower device 414U: Upper device 415:Substrate 415': table 416:Isolation Structure 417: Isolation Structure 418: Isolation Structure 420U-1: Power-on transistor 420U-2: Power-on transistor 420L-1: Lower transistor 420L-2: Lower transistor 426U: semiconductor layer 426L: Semiconductor layer 426M: semiconductor layer 444: Gate spacer 454:Internal spacer 462U: Epitaxial source / drain 462L: Epitaxial Source / Drain 470U:CESL 470L:CESL 472U:ILD layer 472L:ILD layer 478U-1: Gate Dielectric 478U-2: Gate Dielectric 478L-1: Gate Dielectric 478L-2: Gate Dielectric 480U-1: Gate electrode 480U-2: Gate electrode 480-L1: Gate electrode 480-L2: Gate electrode 492:Hard Mask AA: Section Line BB: cutting line X: X direction Y: Y direction Z: Z direction S / D: Source / Drain region C: Channel area t 1: thickness t 2: thickness tO: thickness TI:Thickness S: Spacing

Claims

1. A method for forming a semiconductor device, comprising: A first semiconductor layer and a second semiconductor layer are formed on a substrate, wherein the first semiconductor layer is disposed above the second semiconductor layer and a space is formed between the first semiconductor layer and the second semiconductor layer; a gate dielectric is formed on the first semiconductor layer and the second semiconductor layer, wherein the gate dielectric partially fills the space between the first semiconductor layer and the second semiconductor layer; a work function layer is formed on the gate dielectric, wherein the work function layer fills a remainder of the space between the first semiconductor layer and the second semiconductor layer; and a cap is formed on the work function layer, wherein the portion of the work function layer around the first semiconductor layer merges with the portion around the second semiconductor layer to isolate the cap outside the space between the first semiconductor layer and the second semiconductor layer.

2. The method of forming a semiconductor element as claimed in claim 1, wherein forming the work function layer provides a first portion of the work function layer along a bottom of the first semiconductor layer, the first portion having a first thickness less than about twice the thickness of a second portion of the work function layer along a top of the first semiconductor layer.

3. A method for forming a semiconductor element as described in claim 1 or 2, wherein the step of forming the cover includes: A metal nitride layer is formed above the work function layer; and a silicon-comprising layer is formed above the metal nitride layer.

4. A method for forming a semiconductor device as described in claim 1, wherein the step of forming the work function layer includes: A conductive material having a thickness is deposited around the first semiconductor layer and the second semiconductor layer, wherein in the space between the first semiconductor layer and the second semiconductor layer, the conductive material having the thickness around the first semiconductor layer is merged with the conductive material having the thickness around the second semiconductor layer. And continue the deposition step to increase the thickness of the conductive material along a plurality of first sidewalls of the first semiconductor layer, a plurality of second sidewalls of the second semiconductor layer, and a top of the first semiconductor layer.

5. A method for forming a semiconductor element as claimed in claim 1, wherein an air gap is formed in the work function layer, the work function layer being in the space between the first semiconductor layer and the second semiconductor layer.

6. The method for forming a semiconductor device as described in claim 1 further includes: Remove a dummy gate to form a gate opening that exposes a semiconductor stack; And perform a channel release process to remove a third semiconductor layer from the semiconductor stack, thereby suspending the first semiconductor layer over the second semiconductor layer and suspending the second semiconductor layer over the substrate.

7. A method for forming a semiconductor element as described in claim 1, wherein: The first semiconductor layer and the second semiconductor layer form a channel stack; along a first direction, the cover is disposed on a top of the channel stack; and along a second direction, the cover wraps around the channel stack.

8. A method for forming a semiconductor device, comprising: A first interface layer is formed around a first channel layer and a second interface layer is formed around a second channel layer, wherein a channel stack includes the first channel layer disposed above the second channel layer, the first interface layer partially fills a space between the first channel layer and the second channel layer, and the second interface layer partially fills the space between the first channel layer and the second channel layer; a first high-k dielectric layer and a second high-k dielectric layer are formed, the first high-k dielectric layer being above the first interface layer and surrounding the first channel layer, and the second high-k dielectric layer being above the second interface layer and surrounding the second channel layer, wherein the first high-k dielectric layer partially fills the space between the first channel layer and the second channel layer, and the second high-k dielectric layer partially fills the space between the first channel layer and the second channel layer; a work function layer is formed around the first channel layer and the second channel layer, wherein the work function layer fills a remainder of the space between the first channel layer and the second channel layer. The work function layer is formed by the following steps: depositing a work function material until a first portion of the work function material merges with a second portion of the work function material, the first portion being formed above the first high dielectric constant layer and surrounding the first channel layer, and the second portion being formed above the second high dielectric constant layer and surrounding the second channel layer, wherein the first portion of the work function material merges with the second portion of the work function material in the space between the first channel layer and the second channel layer, and continuing to deposit the work function material to increase the thickness of the first portion and the second portion of the work function material; The step of forming a cover over the work function layer, wherein the cover wraps around the channel stack, includes: forming a first metal nitride layer over the work function layer; forming a second metal nitride layer over the first metal nitride layer after vacuum breaking; and forming a silicon-containing layer over the second metal nitride layer, wherein a portion of the work function layer around the first channel layer merges with a portion around the second channel layer to isolate the cover outside the space between the first channel layer and the second channel layer.

9. A method of forming a semiconductor element as claimed in claim 8, wherein in the space between the first channel layer and the second channel layer, the ends of the first portion of the work function material and the second portion of the work function material merge before their centers, thereby forming an air gap between the first portion of the work function material and the second portion of the work function material in the space between the first channel layer and the second channel layer.

10. A method of forming a semiconductor device as claimed in claim 8, wherein after forming the capping member, an outer region of the gate stack has a first oxygen content, an inner region of the gate stack has a second oxygen content, the ratio of the first oxygen content to the second oxygen content is about 1 to about 1.25, the inner region of the gate stack fills the space between the first channel layer and the second channel layer, and the outer region of the gate stack is not in the space between the first channel layer and the second channel layer.

11. A method for forming a semiconductor element as described in claim 8, wherein: A gate opening exposes the first channel layer and the second channel layer; the first interface layer, the first high dielectric constant dielectric layer, the work function layer, and the capping portion fill a top of the gate opening, the top being above the first channel layer; and the method further includes forming a bulk / fill layer above the capping, wherein the bulk / fill layer fills a remaining portion of the top of the gate opening, wherein the bulk / fill layer surrounds the channel stack.

12. A method for forming a semiconductor element as claimed in claim 8, wherein the semiconductor element is an n-type transistor and the work function layer is an n-type work function metal layer.

13. A semiconductor element, comprising: A first channel layer and a second channel layer; A gate stack includes: a gate dielectric disposed around a first channel layer and a second channel layer, wherein the gate dielectric includes an interface layer and a high-dielectric-constant dielectric, the high-dielectric-constant dielectric being disposed above the interface layer; and a gate electrode disposed above the gate dielectric, wherein the gate electrode is located around the first channel layer and the second channel layer, and wherein the gate electrode includes: a work function layer disposed above the high-dielectric-constant dielectric layer, wherein the work function layer is located around the first channel layer and the second channel layer; and a capping member disposed above the work function layer, wherein the capping member includes a metal nitride layer and a silicon layer, the metal nitride layer being disposed above the work function layer, and the silicon layer being disposed above the metal nitride layer; wherein the gate dielectric and the work function layer fill a space between the first channel layer and the second channel layer; The gate stack has an outer region with a first oxygen content and an inner region with a second oxygen content, wherein the ratio of the first oxygen content to the second oxygen content is about 1 to about 1.25; and wherein a first thickness of the work function layer in the outer region of the gate stack is greater than a second thickness of the work function layer in the inner region of the gate stack, and wherein a portion of the work function layer around the first channel layer merges with a portion around the second channel layer to isolate the cover outside the space between the first channel layer and the second channel layer.

14. The semiconductor device as claimed in claim 13, wherein the work function layer comprises titanium, aluminum and carbon, wherein the aluminum content of the work function layer is from about 25 atomic percent (at%) to about 33 at.

15. The semiconductor device as claimed in claim 13, wherein an air gap exists in the work function layer, and the work function layer is located in the space between the first channel layer and the second channel layer.

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