Input / output circuit, memory circuit and operation method of the same
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2024-03-26
- Publication Date
- 2026-08-01
Smart Images
Figure TWG2TB001903535_001 
Figure TWG2TB001903535_002 
Figure TWG2TB001903535_003
Abstract
Description
Sense Amplifier and Output Latch Circuit for Testing None Multiple components are incorporated into a memory circuit for design for testability (DFT), including D flip-flop circuits, write latch circuits, read sense amplifiers, and output Q latch circuits. However, during the DFT test mode, the sense amplifier and output Q latch circuit remain idle, while in the write mode, the sense amplifier alone is idle. The DFT memory circuit may further include write and shadow latch circuits, a 3-to-1 multiplexer (MUX), a passive matrix (PM) isolation (ISO) clamp circuit, and power-saving logic circuits. The presence of these additional features creates significant forbidden zones for memory design, thereby affecting the overall size of the circuit. None The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. In addition, embodiments of the present disclosure may repeat element symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. In addition, for ease of description, spatial relativity terms (such as "under", "below", "lower", "above", "upper", and the like) may be used herein to describe the relationship of one element or feature illustrated in the figures to another element (or elements) or feature (or features). Except for the orientation depicted in the figures, the spatial relativity terms are intended to include different orientations of the elements in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and thus the spatial relativity descriptors used herein may be interpreted similarly. A memory design may be required to have a design for testability (DFT) function. The memory design may include at least one of the following: a latch circuit, a flip-flop circuit, or a combinational logic circuit. In some methods, a test pattern (e.g., a binary vector) is applied as an SI input to the DFT circuit. This disclosure provides a DFT function for a memory device by using an existing sense amplifier and data output latch circuit (e.g., called a Q latch) to replace the DFT D flip-flop circuit and write latch circuit. This disclosure can eliminate the need for the associated circuits of the write and shadow latches in each input / output (I / O) circuit, thereby improving the use of area and reducing the additional area consumption. This effect is achieved by eliminating the need for additional logic circuits such as write latches, shadow latches, 3-to-1 multiplexers (MUXes), passive matrix (PM) clamp circuits, and power-saving logic circuits. In some embodiments, the sense amplifier may cooperate with the data output latch circuit (e.g., called a Q latch) to generate test results in the test mode, rather than being idle as in some methods. Thus, the additional shadow latch circuit for shifting the test pattern in the test mode is eliminated from the DFT circuit. Additionally, as described above, since the write latch may be idle during a read operation and the sense amplifier is being precharged during a write operation, the write latch for performing the write operation is typically not operable simultaneously. This disclosure replaces the write latch by modifying the existing sense amplifier to reduce the area occupied by the original write latch. By this method, power consumption and leakage current can be reduced because the replacement operation does not require any additional power consumption or induce new leakage current. FIG. 1 illustrates a block diagram of a memory device 100 according to some embodiments of this disclosure. The memory device 100 may include an input circuit 109, a bypass circuit 102, a first latch 104, a second latch 106, a first transistor 108, and a second transistor 110. The input circuit 109 may be operably coupled to the bypass circuit 102. The input circuit 109 may include a D latch circuit 116, an inverter 118, and a NOR gate 120. The memory device 100 may include an input / output circuit 160 and a memory array 150. The bypass circuit 102 may include an exclusive OR (XOR) gate 103 having two input terminals. The XOR gate 103 is coupled between the output of the input circuit 109 and the first latch 104. The bypass circuit 102 can be used to directly receive the data signal D 132 and indirectly receive the write enable signal BWEB 134. In some embodiments, the bypass circuit 102 may use one of its input terminals to receive the write enable signal BWEB 134 at least via the inverter 118 and the NOR gate 120. In some embodiments, BWEB represents the bit write enable bus bar function, which performs the logical inversion of the start bit write signal. The NOR gate 120 may use one of its input terminals to receive the control signal 148 (e.g., the test start signal DFTB). When the control signal 148 is in the first logic state (e.g., "1"), the memory device 100 is set to the non-test mode, and when the control signal 148 is in the second logic state (e.g., "0"), the memory device 100 is set to the test mode. The NOR gate 120 may use the other of its input terminals to receive the write enable signal BWE 144. The D input of the D latch circuit 116 can be used to receive the write enable signal BWEB 134. In some embodiments, the D latch circuit 116 is a low-pass latch circuit that allows data to pass when the clock phase is low (e.g., the low logic state, "0"). In various embodiments, the D latch circuit 116 is shared among normal, shift, and capture modes and paths. The XOR gate 103 can be used to generate a bypass data signal SXOR 136 based on the data signal D 132 and the write enable signal BWEB 134. The output terminal of the bypass circuit 102 is coupled to the first latch 104 to transmit the bypass data signal SXOR 136 to the first switch 112 and the second switch 114. The first latch 104 may be operatively coupled between a first data line 138 (e.g., a data line (DL)) and a second data line 140 (e.g., a data line bar (DLB)). The first latch 104 may include a first switch 112 and a second switch 114 operatively coupled between an output of the bypass circuit 102 and a second latch 106. The first switch 112 is operatively coupled between the first data line 138 and the output of the bypass circuit 102 (e.g., the bypass data signal SXOR 136). The second switch 114 is operatively coupled between the second data line 140 and the output of the bypass circuit 102 (e.g., the bypass data signal SXOR 136). In some embodiments, the first latch 104 may be a sense amplifier. The first latch 104 may be the master latch of the data signal D 132. The first latch 104 may replace the write latch of the data signal D 132. The first latch 104 may be used to sense signals from the data line DL 138 and the data line DLB 140, respectively, which signals represent data bits (1 or 0) stored in respective memory cells, and to amplify small voltage swings to recognize a logic low level such that the data can be properly interpreted by the logic circuitry of the memory device 100. In some embodiments, the first latch 104 may be coupled to the memory array 150 via the first data line 138 and the second data line 140. The second latch 106 may be operatively coupled to the first latch 104. The second latch 106 may be used to generate an output signal Q 142 based on a voltage level present on the second data line 140. In some embodiments, the second latch 106 is implemented as a high-pass latch circuit that allows data to pass when the clock phase is high (e.g., a high logic state, "1"). The first latch 104 and the second latch 106 operate together as a data flip-flop (e.g., a D flip-flop) in at least one of a plurality of operating modes (e.g., a normal mode or a test mode), in which a clock signal (e.g., the clock signal DCK 146) is deactivated and a sense enable signal (e.g., the sense enable signal SAE 144) serves as the clock source of the data flip-flop to perform a bistable toggle. The first transistor 108 may be coupled to the first latch 104 and gated by the sense enable signal SAE 144. The second transistor 110 may be coupled to the first latch 104 and gated by the clock signal DCK 146. The first transistor 108 and the second transistor 110 may be alternately activated in each of a plurality of operating modes (e.g., a normal mode or an operating mode) of the memory device 100 (e.g., an input / output circuit). In some embodiments, the memory device 100 has different operating modes including a normal mode (e.g., read and write modes) and a DFT test mode (e.g., shift mode and capture mode), where the shift mode includes two sub - modes called scan mode and debug mode. In the normal mode (e.g., read mode or write mode), the memory device 100 does not perform any tests; instead, the memory device 100 performs its regular functions it is designed to perform, such as starting to read data from the memory (e.g., static random access memory (SRAM)) and writing data to the memory. In some embodiments, the normal path travels through an input section, a memory core logic section, and an output section. Specifically, for example, in the write mode or read mode, the normal path travels through the bypass circuit 102, the first latch 104, and the second latch 106. For example, in the non - DFT test mode, the test start signal DFTB 148 can be set to "1", which causes the bypass circuit 102 to pass the directly received data signal D 132 through the XOR gate 103, and causes the bypass circuit 102 to output the bypass data signal SXOR 136 (data signal D 132) to the first latch 104. When the memory device 100 is in the read mode, the second transistor 110, the first switch 112, and the second switch 114 are deactivated, and the first transistor 108 is activated. When the memory device 100 is in the write mode, the first transistor 108 is deactivated, and the second transistor 110, the first switch 112, and the second switch 114 are activated. In the DFT test mode, test - related features are implemented, and specific input data (e.g., data signal D 132 and write enable signal BWEB 134) are applied to the memory device 100 to perform various test functions on the memory device 100. For example, in the DFT test mode, the test start signal DFTB 148 can be set to "0", which causes the bypass circuit 102 to generate an XOR output 136 based on the directly received signal signal D 132 and the indirectly received write enable signal BWEB 134. The memory device 100 can compare the output data (e.g., output signal Q 142 in FIG. 1) with the "designed" output data that the memory device 100 is designed to generate. If the observed output matches the "designed" output, the memory device 100 passes the test; if the observed output does not match the "designed" output, the memory device 100 fails the test. When the memory device 100 is in the test mode, the first transistor 108, the first switch 112, and the second switch 114 are activated, and the second transistor 110 is deactivated. In the shift mode and capture mode, which can be regarded as test modes, tests are performed on different parts of the memory device 100. In the capture mode of the DFT test mode, the data signal D 132 is directly output to the first input terminal of the bypass circuit 102; and the write enable signal BWEB 134 is output to the second input terminal of the bypass circuit 102 via the D latch circuit 116, the inverter 118, and the NOR gate 120. The data of the data signal D 132 can be further latched in the first latch 104 and the second latch 106, and read out as the output signal Q 142. In some embodiments, the write enable signal BWEB 134 can be programmed to perform tests. In the shift mode of the DFT test mode, the data signal D 132 is directly output to the first input terminal of the bypass circuit 102; and the write enable signal BWEB 134 is output to the second input terminal of the bypass circuit 102 via the D latch circuit 116, the inverter 118, and the NOR gate 120. The first latch 104 can provide the data signal corresponding to the data signal D 132 to the second latch 106 for temporary storage of test data. In some embodiments, both the capture path and the shift path are passed through the input section and travel through the memory core logic section, and then travel to the output section. Specifically, for example, both the capture path and the shift path travel through the first latch 104 and the second latch 106 in the memory core logic section. Details of the configuration and operation will be described in the following paragraphs. In some embodiments, the system includes a plurality of memory devices 100 coupled to each other in sequence, where the first memory device 100 receives a data signal (referred to as the data signal input as the data signal D in FIG. 1) from an external test device, and the read data from the first memory device 100 (e.g., the signal generated by the inverter 212 in FIG. 2) is transmitted as a data signal (input as the data signal D 132 in FIG. 1) to the subsequent memory device 100, and so on. The configuration of FIG. 1 is given for illustrative purposes. Various embodiments are within the scope of this disclosure. For example, in some embodiments, the D latch circuit 116 is not included in the input circuit 102. FIG. 2 illustrates a detailed schematic diagram of the memory device 100 of FIG. 1 according to some embodiments of the present disclosure. The memory device 100 may include an input circuit 109, a bypass circuit 102, a first latch 104, a second latch 106, a first transistor 108, and a second transistor 110. The input circuit 109 may be configured to transmit signals corresponding to the data signal D 132 and the write enable signal BWEB 134 to the bypass circuit 102. The data signal D 132 is directly transmitted to the bypass circuit 102. The write enable signal BWEB 134 may be transmitted to the bypass circuit 102 via at least an inverter 118 and a NOR gate 120. The bypass circuit 102 may include an XOR gate 103, and the XOR gate 103 is configured to generate a bypass data signal SXOR 136 (e.g., signal D or signal XOR) according to the data signal D and the write enable signal BWEB. In the input circuit 109, additional logic circuits such as an inverter 118 and a NOR gate 120 may be included to eliminate the need for incoming data latches and shadow latch related circuits. The NOR gate 120 may have one of its input terminals configured to receive a test enable signal DFTB 148. Due to the additional logic circuits, two test modes (e.g., non-DFT test mode and DFT test mode) may be defined. In the non-DFT test mode, the first latch 104 may act as a write latch. In the DFT test mode, the first latch 104 and the second latch 106 operate together as data flip-flops (e.g., D flip-flops). In the non-DFT test mode, the test enable signal DFTB 148 may be at "1", which may cause the NOR gate 120 to output "0". The XOR gate 103 may receive the data signal D 132 and the output "0" of the NOR gate 120. In this situation, the XOR gate 103 may generate the bypass data signal SXOR 136 (data signal D 132), and may transmit the bypass data signal SXOR 136 (data signal D 132) to the first latch 104. The inverter 118 of the first latch 104 may generate an inverted bypass data signal 262 according to the bypass data signal SXOR 136 (data signal D 132). The first latch 104 may use the data signal D 132 and the inverted bypass data signal 262 as outputs to operate as a write latch. In the non-DFT test mode, the first latch 104 may act as a write latch. In some embodiments, the first latch 104 may be a sense amplifier. In the DFT test mode, the test start signal DFTB 148 can be at "0", which can cause the NOR gate 120 to output the write start signal BWEB 134. The XOR gate 103 can receive the data signal D 132 and the write start signal BWEB 134. In this situation, the XOR gate 103 can generate a bypass data signal SXOR 136 (data signal XOR) according to the data signal D 132 and the write start signal BWEB 134. The XOR gate 103 can transmit the bypass data signal SXOR 136 (data signal XOR) to the first latch 104. The inverter 118 of the first latch 104 can generate an inverted bypass data signal XORB 262 according to the bypass data signal SXOR 136 (data signal XOR). The first latch 104 can use the bypass data signal SXOR 136 (data signal XOR) and the inverted bypass data signal XORB 262 as inputs to operate as a DFT D flip-flop. In the DFT test mode, the first latch 104 and the second latch 106 jointly operate as data flip-flops (e.g., D flip-flops), where the clock signal (e.g., clock signal DCK 146) is disabled and the sense start signal (e.g., sense start signal SAE 144) is used as the clock source of the data flip-flop for bistable triggering. The D input terminal of the D latch circuit 116 can be used to receive the write start signal BWEB 134. In some embodiments, the D latch circuit 116 is a low-pass latch circuit that allows data to pass when the phase of the clock (e.g., write start signal BWEB 134) is low (e.g., low logic state, "0"). The low-pass latch circuit can be triggered by a short low signal in the input signal, which allows low-frequency or slowly changing signals to pass while blocking high-frequency signals. In some embodiments, the D latch circuit 116 can be a BWEB input latch that changes the state of the latch according to the input write start signal BWEB 134. The D latch circuit 116 can be controlled by the write start signal BWEB 134. In some embodiments, the first latch 104 may include a read gating circuit 250, a latching circuit 252, a precharge circuit 254, and an inverter 220 having a terminal coupled to the bypass circuit 102. The read gating circuit 250 may transmit the bypass data signal SXOR 136 and the inverted bypass data signal 262 to the data wire DL 138 and the data wire DLB 140, respectively, in response to the enable signals D_SAE and D_SAEB. For ease of illustration, the read gating circuit 250 is coupled between the data wire DL 138, the data wire DLB 140, the bypass circuit 102, and the inverter 220 of the first latch 104. The read gating circuit 250 may include a first switch 112 and a second switch 114. The first switch 112 may include a transmission gate that, in response to the enable signals D_SAE and D_SAEB, is coupled to the data wire DL 138 in the bypass circuit 102, the terminal of the inverter 220, and the output of the XOR gate 103, and is configured to transmit the bypass data signal SXOR 136 from the XOR gate 103 to the data wire DL 138. The second switch 114 may include a transmission gate coupled to the other terminal of the inverter 220 and the data wire DLD 140. The second switch 114 may be configured to transmit the inverted bypass data signal 262 (e.g., the DB or XORB signal) from the inverter 220 to the data wire DLB 140 in response to the enable signals D_SAE and D_SAEB. Each of the switches 112-114 (e.g., the transmission gate) may include a P-type transistor and an N-type transistor, as illustrated in FIG. 2. The latch circuit 252 may have terminals coupled to the data line DL 138 and the data line DLB 140. When signaled (e.g., read mode or DFT test mode), the latch circuit 252 may transfer an input state to an output state by the data line DL 138 and the data line DLB 140, and the output remains insensitive to changes in the input state thereafter until signaled again. In other words, the first switch 112 is coupled between the bypass circuit 102 and one of the terminals of the latch circuit 252, and the second switch 114 is coupled between the inverter 220 and the other terminal of the latch circuit 252. For ease of explanation, the latch circuit 252 may include P-type transistors P1~P2 coupled to a voltage terminal (e.g., providing a power supply voltage VDDM and labeled as VDDM hereinafter), and N-type transistors N1~N2 coupled to the first transistor 108 and the second transistor 110. The first transistor 108 and the second transistor 110 may be N-type transistors N3~N4. The first transistor 108 may be coupled to the power supply voltage VSS (e.g., providing a ground potential and labeled as VSS hereinafter) and operate in response to the sense activation signal SAE 144, which is referred to as a periodic signal for activating the first latch 104 (e.g., sense amplifier) for a specific mode (e.g., read mode or DFT test mode). The first transistor 108 may be gated by the sense activation signal SAE 144. The second transistor 110 may be coupled to the power supply voltage VSS (e.g., providing a ground potential) and operate in response to the clock signal DCK 146, which is referred to as a periodic signal for activating the first latch 104 (e.g., sense amplifier) for a specific mode (e.g., write mode). The second transistor 110 may be gated by the clock signal DCK 146. Transistors N1 and P1 form an inverter, and this inverter is cross-coupled with the inverter formed by transistors N2 and P2. The precharge circuit 254 is coupled to the data line DL 138 and the data line DLB 140. In some embodiments, during the test mode, when the activation signal SAE has a low logic state, the precharge circuit 254 is used to turn off in response to the precharge activation signal DLEQB having a high logic state. In some embodiments, the precharge circuit 254 may include P-type transistors P3~P5 having a control terminal receiving the precharge activation signal DLEQB. Specifically, the transistor P3 is coupled between the data line DL 138 and the voltage terminal VDDM, and the transistor P4 is coupled between the data line DLB 140 and the voltage terminal VDDM. The transistor P5 is coupled between the data line DL 138 and the data line DLB 140. The second latch 106 (e.g., an output latch circuit) may include P-type transistors P6 to P9, N-type transistors N5 to N8, and a NAND gate 222. When signaled, the second latch 106 may transfer the output state from the latch circuit 252 to the inverter 212 (e.g., read mode or DFT test mode), and the second latch 106 may even maintain the output state (e.g., the output state from the latch circuit 252) after removing the input. In the embodiment of FIG. 2, the second latch 106 may further include the inverter 212. In some embodiments, the transistor P6 is coupled between the voltage terminal VDDM and the transistor P7. The transistor P7 is coupled to the transistors N5, N7, P9, the input terminal of the inverter 212, and the first input terminal of the NAND gate 222 at the node n1. The transistor N6 is coupled between the voltage terminal VSS and the transistor N5. The transistor P8 is coupled between the voltage terminal VDDM and the transistor P9. The transistor N8 is coupled between the voltage terminal VSS and the transistor N7. The transistors N6 and P8 have control terminals coupled to the data wire DLB 140 and are operative in response to the data signal DS generated by the first latch 104. The transistors P7 and N7 are operative to switch in response to the enable signal SAEB. The transistors P9 and N5 are operative to switch in response to the enable signal SAE, and at the same time, the control terminal of the transistor N5 is coupled to the control terminal of the transistor N3. The control terminals of the transistors P8 and N8 are coupled to the output of the NAND gate 222. The NAND gate 222 may receive an enable control signal PMB (having a logic state different from the enable control signal PM). In some embodiments, the memory device 100 further includes a write control circuit 251, and this write control circuit 251 is coupled to the latch circuit 252 for operation in different operation modes. The write control circuit 251 can capture data from a temporary storage source (e.g., the latch circuit 252 or the second latch 106) via the complementary DLB input and the DL input. The latch circuit 252 can provide signals via the complementary DLB input and the DL input. These signals can control the transistor rows, thereby affecting the voltages BL and BLB, which are converted into binary signals for the write control single path 251. In this configuration, during the clock cycle for writing to the memory cell, the write latch holds the DL data. During a read operation (e.g., write clock (WCLK) = 1 (non-write mode)), the write latch is largely inactive. The write control circuit 251 can include a first NOR gate N1, a second NOR gate N2, a write truth (WT) transistor, and a write complement (WC) transistor. The first NOR gate N1 can obtain the write clock and the DLB input, and thereby generate a WC drive signal via a NOR operation. The second NOR gate N2 can also use the write clock, but pairs the write clock with the DL input to generate a WT drive signal. These signals activate the WC transistor and the WT transistor respectively, and thereby write to the voltages BL and BLB, which are complementary signals. This configuration facilitates the write operation based on the input, thereby enabling data to be stored in the corresponding location. The memory device 100 further includes a clock generator 210, which includes inverters 236, 238, 242 and NOR gates 240, 244. The NOR gate 240 is coupled between the inverter 238 and the inverter 242 (or the NOR gate 244). Specifically, the inverter 236 is used to invert the signal GLB_SAE 306 to generate the enable signal SAEB. The inverter 238 is used to invert the enable signal SAEB to generate the enable signal SAE. The NOR gate 240 is used to generate the enable signal D_SAEB based on the enable signal SAE and the signal GLB_DCK 302. In some embodiments, the signal GLB_DCK 302 has a low logic state ("0") during the test mode and a high logic state ("1") in other operating modes (e.g., read mode). The inverter 242 is used to generate the enable signal D_SAE based on the enable signal D_SAEB. In the test mode, the enable signal D_SAEB is referred to as a delayed signal associated with the enable signal SAEB, and the enable signal D_SAE is referred to as a delayed signal associated with the enable signal SAE. In some embodiments, the NOR gate 240 is used to generate the enable signal D_SAEB based on the enable signal SAE and the signal GLB_DCK 302. The NOR gate 244 is used to generate the clock signal DCK based on the enable signal D_SAEB and the signal IWEB 304. The clock generator 210 can be an electronic circuit that generates a regular and repetitive electrical signal referred to as a clock signal (e.g., D_SAE signal, DCK signal). This signal can be used to synchronize the operation of digital components in various devices (e.g., the latch circuit 252 or the second latch 106). The clock generator 210 ensures that different parts of the system operate together in a coordinated manner. The memory device 100 may further include a NOR gate 224 and inverters 226, 228. The NOR gate 224 may have a first input coupled to the second latch 106 at node n2 and a second input receiving the test enable signal DFTB. In some embodiments, the latch circuit 252 and the second latch 106 (e.g., output latch circuit) are referred to as read path D flip-flops. Thus, for scan-based testing during the shift mode of the test mode, the data output signal generated by the second latch 106 is transmitted via the NOR gate 224 and the inverters 226, 228 as an input signal (e.g., data signal D 132) in the subsequent memory device 100. The memory device 100 may further include transmission gates 230, 232 that operate in response to control signals HIT and HITB having different logic states. In some embodiments, the transmission gate 230 is coupled to the second latch 106 at node n2 and to an output driver circuit including a NOR gate 234 at node n3. The NOR gate 234 has a first input terminal receiving a signal from the transmission gate 230 and a second input terminal receiving an activation control signal PM, and is configured to generate an output signal Q 142. The configuration of FIG. 2 is given for illustrative purposes. Various embodiments are within the scope of the present disclosure. The operation of the circuit 100 in FIG. 2 is substantially similar to the operation of the circuit 100 in FIG. 1. The detailed operation configurations of the memory device 100 in FIGS. 1 and 2 will be described in the following paragraphs with reference to FIGS. 3 to 7. FIG. 5 illustrates waveforms of signals in the memory device 100 in FIGS. 1 to 4 according to some embodiments of the present disclosure. FIG. 7 illustrates waveforms of signals of the memory device 100 in FIGS. 1, 2, and 6 according to some embodiments of the present disclosure. FIG. 3 illustrates a detailed schematic diagram of the memory device 100 in FIGS. 1 and 2 in a read mode according to some embodiments of the present disclosure. In the read mode, the test activation signal DFTB 148 may be set to “1”, which may cause the NOR gate 120 to output “0”. The XOR gate 103 may receive the data signal D 132 and the output “0” of the NOR gate 120. In this situation, the XOR gate 103 may generate a bypass data signal SXOR 136 (data signal D 132), and may transmit the bypass data signal SXOR 136 (data signal D 132) to the first latch 104. When the memory device 100 is in the read mode, the second transistor 110 (e.g., a sense amplifier pull-down transistor N4), the first switch 112, and the second switch 114 are deactivated, and the first transistor 108 is activated. In the read mode, the signal GLB_DCK 302, the signal IWEB 304, and the test start signal DFTB 148 are set to the logic high state ("1"), and the signal GLB_SAE 306 can be bistable toggled to simulate the normal operation mode. In the read mode, the first latch 104, which is an sense amplifier, is triggered at the accurate timing as in a normal read operation. The D latch circuit 116 (BWEB latch) can be latched during the read operation. The data wiring pair (the first data wiring 138 and the second data wiring 140) is precharged first in response to the precharge start signal DLEQB. Specifically, the voltage BL is enabled, and then the read-column-select is activated to transfer data to the first data wiring 138 (e.g., the data wiring DL). FIG. 4 illustrates a detailed schematic diagram of the memory device 100 in FIGS. 1 and 2 in the write mode according to some embodiments of the present disclosure. In the write mode, the test start signal DFTB 148 can be set to "1", which can cause the NOR gate 120 to output "0". The XOR gate 103 can receive the data signal D 132 and the output "0" of the NOR gate 120. In this situation, the XOR gate 103 can generate the bypass data signal SXOR 136 (data signal D 132), and can transfer the bypass data signal SXOR 136 (data signal D 132) to the first latch 104. When the memory device 100 is in the write mode, the first transistor 108 is deactivated, and the second transistor 110, the first switch 112, and the second switch 114 are activated. The first switch 112 and the second switch 114, which are gated by the activation signal D_SAE and / or the activation signal D_SAEB respectively, can transfer the data signal D and the data signal bus bar DB to the first latch (sense amplifier) 104. In the write mode, the signal GLB_SAE 306 and the signal IWEB 304 are set to the low logic state ("0"), while the test start signal DFTB 148 is set to the high logic state ("1"). The signal GLB_DCK 302 can be bistable toggled to simulate the normal write operation. In the write mode, the sense start signal SAE 144 is set to 0, and the activation signal SAEB is set to 1. The second latch 106 (e.g., Q latch) can hold / latch the readout data from the previous read cycle to ensure its preservation. The precharge circuit 254 (e.g., DL precharger) is turned off in response to the precharge start signal DLEQB being set to "1". The first latch 104 (sense amplifier) can act as an incoming data latch during the write operation. The output of the D-latch circuit 116 (e.g., BWEB latch) and the data line DL 138 / data line DLB 140 (IBWE) can form a write circuit, which is gated by a write clock to control the writing of data to the BL pair of the write control circuit 251. FIG. 5 illustrates the waveforms of signals in the memory device 100 in FIGS. 3 and 4 according to some embodiments of the present disclosure. The operating principle of the memory circuit 100 can be explained by using the timing diagram as illustrated in FIG. 5. Generally, a cycle can include a read operation and a subsequent write operation, and the transistors (e.g., transistors P1, P2, N1, N3) of the latch circuit 252 are precharged first before each read operation. At time T1, when the sense activation signal SAE 144 has a low logic state, the precharge circuit 254 precharges the data signal DL 138 and the data signal DLB 140 in response to the precharge enable signal DLEQB 520 having a high logic state. After the precharge period, a signal (e.g., the sense activation signal SAE 144 or the clock signal DCK 146) can turn on the transistors 108, 110 because the transistors 108, 110 may take time to recharge. During the period when the Din latch is disabled, the activation signal D_SAEB 510 is set to low. During the rising clock edge 502, the voltage level of the write enable signal (WEB) 530 triggers the start of a read operation or a write operation. In the example of FIG. 5, at the first rising clock edge 502, WEB 530 is set to high to trigger a read operation, and during the read operation, the transistors of the first latch 104 (sense amplifier circuit) are activated. At time T2, the precharge start signal DLEQB 520 is set low after the precharge ends. During a read operation, the clock signal DCK 146 and the start signal D_SAEB 510 can remain low. The sense start signal SAE 144 can temporarily rise to activate the sensing function of the first latch 104 (sense amplifier circuit). After performing the sensing function, the sense start signal SAE 144 can fall and remain low during a write operation. The clock signal DCK 146 is low during a read operation, and the sense start signal SAE 144 is also set low at the start of a read cycle. During the rising clock edge 502, the voltage level of the write enable signal (WEB) 530 triggers the start of the read operation. At the end of the read operation, the sense start signal SAE 144 is then temporarily set high to perform the sensing of differential signals (e.g., data signals DL, DLB) in order to sense a binary value. As the sense start signal SAE 144 falls to a low voltage, the start signal D_SAEB 510 is set high while the Din latch is in the transparent phase. After the read operation ends, a write operation can start. At the second rising clock edge 504, WEB 530 is set low to trigger the write operation, and during the write operation, the transistors of the first latch 104 (sense amplifier circuit) are always deactivated. At time T3, before the data is latched during a write operation, the Din signal can persist during the period when the Din latch is considered transparent and the start signal D_SAEB 510 is set high. More specifically, the precharge start signal DLEQB 520 is first set high to turn on the voltage precharge circuit 254 (e.g., transistors P3, P4, P5) to equalize and precharge the first latch 104 (sense amplifier circuit). The start signal D_SAEB 510 is set high during the phase when the Din latch is transparent. During the period from the end of the read operation to the start of the write operation, the precharge start signal DLEQB 520 can become a high voltage to turn on the voltage precharge circuit 254 throughout the write operation and precharge the first latch 104 (sense amplifier circuit). The precharge start signal DLEQB 520 remains high until the start of the next cycle, and the sense start signal SAE 144 also remains low throughout the write operation because during the write operation, the first latch 104 (sense amplifier circuit) may not be needed except to latch the data received via the Din latch and the DinB latch. To latch the data received from the Din latch and the DinB latch, the clock signal DCK 146 can be temporarily set high to perform the sensing of differential signals (e.g., data signals DL, DLB) in order to sense a binary value and latch the binary value stored in the latch circuit 252. At time T4, while the Din signal is being latched, the clock signal DCK 146 is set high. At the start of a write operation, the start signal D_SAEB 510 is set high while the Din latch is in the transparent phase. The start signal D_SAEB 510 can go low while data received from the Din latch and the DinB latch is being latched, because the relationship between the start signal D_SAEB 510 and the clock signal DCK 146 is complementary during the write operation. After the write operation is completed, another cycle of a read operation following the write operation can be started. FIG. 6 illustrates a detailed schematic diagram of the memory device 100 of FIGS. 1 and 2 in write mode according to some embodiments of the present disclosure. In the DFT test mode, the test start signal DFTB 148 can be set to '0', which can cause the NOR gate 120 to output the write start signal BWEB 134. The XOR gate 103 can receive the data signal D 132 and the write start signal BWEB 134. In this situation, the XOR gate 103 can generate a bypass data signal SXOR 136 (data signal XOR), and can transmit the bypass data signal SXOR 136 (data signal XOR) to the first latch 104. When the memory device 100 is in the DFT test mode, the first transistor 108, the first switch 112, and the second switch 114 are activated, and the second transistor 110 (e.g., sense amplifier pull-down transistor N4) is deactivated. The first switch 112 and the second switch 114 gated by the start signal D_SAE and / or the start signal D_SAEB respectively can transmit the data signal XOR and the data bus bar XORB to the first latch 104 (sense amplifier). In the DFT test mode, the signals GLB_DCK 302 and the test start signal DFTB 148 are set to the low logic state ('0'), while the signal IWEB 304 is set to the high logic state ('1'). The signal GLB_SAE 306 can be used as a single clock source for the DFT D flip-flop for two-state toggling. The precharge start signal DLEQB is set to 1, thereby deactivating the precharger of the data wiring. Although the D latch circuit 116 (e.g., BWEB latch) can perform two-state toggling, the write operation is deactivated. The first latch 104 (sense amplifier) can act as the main latch during the DFT operation. The second latch 106 can act as a shadow latch in the DFT D flip-flop. The first latch 104 and the second latch 106 operate together as data flip-flops (e.g., D flip-flops) in the DFT test mode. During the DFT test mode, it may not be necessary to hold the previously read data. FIG. 7 illustrates waveforms of signals of the memory device 100 in FIG. 6 according to some embodiments of the present disclosure. The principle of the DFT test operation of the memory circuit 100 can be explained by using the timing diagram illustrated in FIG. 7. In the DFT test mode, the test start signal DFTB 148 can be set to low (“0”). When the data signal D 132 has a low logic state, the write enable signal BWEB 134 changes to a low logic state, so the XOR gate 103 generates a bypass data signal XOR 136 with a low logic state. At time T1, as the global clock signal CLK 302 of the memory device 100 rises, in response to the sense enable signal SAE 144 rising to have a high logic state and the test start signal DFTB 148 having a low logic state, the NOR gate 120 generates a start signal D_SAEB 510 with a low logic value. The inverter 242 can invert the start signal D_SAEB 510 to generate a start signal D_SAE 144 with a high logic state. During the period from time T1 to T2, the data signal D 132 is input and rises to have a high logic state. The XOR gate 103 generates and transmits a bypass data signal XOR 136 with a high logic state at time T2 to the first latch 104 (sense amplifier). At time T3, in the test mode, when the second latch 106 (e.g., referred to as a high-pass latch circuit) has a low logic state in response to the sense enable signal SAE 144 and the start signal SAEB 510 has a high logic state, the read gate control circuit 250 is turned on in response to the start signal D_SAEB 510 having a logic high state and the start signal D_SAE 144 having a low logic state to transmit the bypass data signal XOR 136 to the latch circuit 252. Specifically, the bypass data signal XOR 136 with a logic high state is transmitted to the data wire DL 138 via the transmission gate 112, and the bypass data signal XORB 262 with a low logic state is transmitted to the data wire DLB 140 via the transmission gate 114. Therefore, during the test mode, in response to the sense enable signal SAE 144 having a low logic state and the start signal D_SAEB 510 having a high logic state, the first latch 104 adjusts the voltage levels of the data wires DL 138 and DLB 140 according to the bypass data signal XOR 136 corresponding to the data signal D 132. At time T4, the second latch 106 output by Qualcomm turns on in response to the rising of the sense activation signal SAE 144 having a high logic state and the activation signal SAEB 510 having a low logic state. Specifically, the transistor P6 turns on in response to the DLB 140 of the data wiring having a low voltage level corresponding to the bypass data signal XORB 262, and in response to the activation signal SAEB 510, supplies the supply voltage VDDM to the node n1 via the turned-on transistor P7. Accordingly, the second latch 106 generates a data output signal SQ by the inverter 212 therein, where the data output signal SQ has a low logic state. At time T5, the transmission gate 230 transmits the data output signal SQ to the NOR gate 234 in response to the control signal HIT having a high logic state and the control signal HITB having a low logic state. The NOR gate 234 generates an output signal Q 142 having a high logic state in response to the activation control signal PM having a low logic state and the data output signal SQ having a low logic state. Accordingly, the output signal Q 142 and the data signal D 132 have the same logic state. In other words, the data of the data signal D 132 is latched by the first latch 104 and the second latch 106 and transmitted to the output signal Q 142 in the test mode. Under the configuration of the present disclosure, the first latch (sense amplifier) 104 that reads data from the memory cell in the read mode and the second latch (Q-latch circuit 106) that temporarily latches the read data for further operations are used to scan, capture, or hit the test data in the test mode, which achieves area and power savings because there is no need to provide additional D flip-flop circuits, shadow latches, and / or other related logic circuits. In addition, for the above reasons, the leakage current in the memory device is improved by reducing the number of circuits and logic gates. FIG. 8 illustrates a detailed schematic diagram of the memory device 100 of FIG. 1 according to some embodiments of the present disclosure. The memory device 800 may include an input circuit 109, a bypass circuit 102, a first latch 104, a second latch 106, a first transistor 108, and a second transistor 110. The memory device 800 of FIG. 8 is substantially similar to the memory device 100 of FIGS. 1 and 2, except that both the first switch 802 and the second switch 804 are replaced by N-type transistors. For simplicity, the specific operations of the similar components that have been described in detail in the previous paragraphs are omitted, unless it is necessary to introduce the common operating relationship with the components illustrated in FIG. 8. Compared with FIG. 2, the read gate control circuit 810 in FIG. 8 includes a plurality of N-type transistors instead of transmission gates 112 and 114 for transmitting bypass data signals SXOR and SXORB. For ease of explanation, transistor 802 is coupled to data wire DL 138 and is turned on in response to activation signal D_SAEB to transmit bypass data signal SXOR to data wire DL 138. Transistor 804 is coupled to data wire DLB 140 and is turned on in response to activation signal D_SAEB to transmit bypass data signal SXORB to data wire DLB 140. The read gate control circuit 810 is coupled between data wire DL 138, data wire DLB 140, bypass circuit 102, and inverter 220 of the first latch 104. In addition, the first latch 104 includes a P-type transistor 806 coupled between the precharge circuit 254 and the latch circuit 252. Specifically, transistor 806 has a first terminal coupled between transistors P3 and P4 at voltage terminal VDDM and a second terminal coupled between transistors P1 and P2. During test mode operation, transistor 806 is turned off to prevent data wires DL 138 and DLB 140 from being affected by other signals in memory device 100. In other words, the voltage levels of data wires DL 138 and DLB 140 are modulated only based on bypass data signals SXOR and SXORB. FIG. 9 illustrates a detailed schematic diagram of the memory device 100 of FIG. 1 according to some embodiments of the present disclosure. Memory device 900 may include an input circuit 909, a bypass circuit 102, a first latch 104, a second latch 106, a first transistor 108, and a second transistor 110. The memory device 900 of FIG. 9 is substantially similar to the memory device 100 of FIGS. 1 and 2, except for the input circuit 909. For brevity, the specific operations of similar components that have been described in detail in the previous paragraphs are omitted, unless it is necessary to introduce the common operating relationships with the components illustrated in FIG. 9. In the memory device 900, the bypass circuit 102 can be used to directly receive the write enable signal BWEB 134 and indirectly receive the data signal D 132. The operation of the memory device 900 in FIG. 9 is substantially similar to the operation of the memory devices 100 in FIGS. 1 and 2. The input circuit 909 can be used to eliminate the need for circuits related to the BWEB latch and the shadow latch. In the DFT test mode, the first latch 104 and the second latch 106 jointly operate as a data flip-flop (e.g., D flip-flop), where the clock signal (e.g., clock signal DCK 146) is disabled and the sense enable signal (e.g., sense enable signal SAE 144) is used as the clock source of the data flip-flop for bistable toggling. FIG. 10 is a flowchart of an example method 1000 for operating the memory device 100 in FIGS. 1 and 2 according to some embodiments of the present disclosure. The method 1000 can be used to operate the memory device 100. For example, for the memory device 100, at least some of the operations described in the method 1000 can be performed during the test mode. It should be noted that the method 1000 is only an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional operations can be provided before, during, and after the method 1000 in FIG. 10, and other operations may only be briefly described herein. The method 1000 starts with operation 1002, in which the memory circuit 100 can directly receive the data signal 132 and indirectly receive the write enable signal 134 to generate a bypass data signal 136. For example, in FIG. 2, the bypass circuit 102 can directly receive the data signal D 132 and indirectly receive the write enable signal BWEB 134. The bypass circuit 102 can generate an XOR output 136 based on the directly received data signal D 132 and the indirectly received write enable signal BWEB 134. The method 1000 then proceeds to operation 1004, in which the memory circuit 100 can transfer the bypass data signal 136 to the first latch (master latch) 104. The first latch 104 is coupled to the memory cell via the first data wire 138 and the second data wire 140. Continuing with the foregoing example in FIG. 2, the XOR gate 103 can transfer the bypass data signal SXOR 136 to the first latch 104. Method 1000 then proceeds to operation 1006, in which memory circuit 100 may transmit a logic inverted signal of bypass data signal 262 to the first latch (master latch) 104. The master latch 104 includes a sense amplifier coupled to a first transistor 108 and a second transistor 110. The first transistor 108 is gated by a sense activation signal 144, and the second transistor 110 is gated by a clock signal 146. Continuing with the foregoing example of FIG. 2, an inverter 118 of the first latch 104 may generate an inverted bypass data signal XORB 262 according to a bypass data signal SXOR 136 (data signal XOR). The second switch 114 may transmit the inverted bypass data signal XORB 262 from the inverter 220 to the data wire DLB 140. The first transistor 108 may be coupled to the first latch 104 and is gated by a sense activation signal SAE 144. The second transistor 110 may be coupled to the first latch 104 and is gated by a clock signal DCK 146. Method 1000 then proceeds to operation 1008, in which memory circuit 100 may generate an output signal Q 142 based on a voltage level present on a second data wire 140 and coming from a second latch (shadow latch) 106. The shadow latch 106 includes a Q latch. The master latch 104 and the shadow latch 106 together and operably act as a data flip-flop. Operations 1002-1008 are performed during a test mode for the memory circuit 100. Continuing with the foregoing example in FIG. 2, the second latch 106 may be used to generate an output signal Q 142 based on the voltage level present on the second data wire 140. The first latch 104 may use the bypass data signal SXOR 136 (data signal XOR) and the inverted bypass data signal XORB 262 as inputs to operate as a DFT D flip-flop. This disclosure relates to removing components from a circuit, such as write latches, shadow latches, 3-to-1 multiplexers, PM ISO clamp circuits, and power saving logic. The removal of the components brings about a significant improvement in the utilization of the layout area within each IO. In addition, eliminating the extra devices, transistors for write and shadow latches, and their associated logic schemes helps to significantly reduce leakage current. The absence of these extra circuits minimizes power consumption because there is no extra signal bi-state switching activity. Even though these components are removed, the functions of read, write, and DFT operations can still continue to function effectively. The Q latch can hold the last read data even during the write mode, thus ensuring that the performance is not affected. The memory design provides good results for DFT-related problems. In addition, it is expected that the layout will benefit from the improved IO area saving ratio in the implementation. This method provides improved layout area utilization, reduced leakage current, reduced power consumption, and maintains the inherent operating functions without degrading performance. As used herein, the terms "about" and "approximately" generally indicate plus or minus 10% of the stated value. For example, about 0.5 would include from 0.45 to 0.55, about 10 would include from 9 to 11, and about 1000 would include from 900 to 1100. The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may be made herein without departing from the spirit and scope of the present disclosure by making various changes, substitutions, and alternations. 100: Memory device 102: Bypass circuit 103: Exclusive OR (XOR) gate 104: First latch 106: Second latch 108: First transistor 109: Input circuit 110: Second transistor 112: First switch 114: Second switch 116: D latch circuit 118: Inverter 120: NOR gate 132: Data signal D 134: Write enable signal BWEB 136: Bypass data signal SXOR / XOR output 138: Data wire DL / First data wire 140: Data wire DLB / Second data wire 142: Output signal Q 144: Write enable signal BWE / Sense enable signal SAE 146: Clock signal DCK 148: Control signal / Test enable signal DFTB 150: Memory array 160: Input / Output circuit 210: Clock generator 212, 220: Inverter 222: NAND gate 224: NOR gate 226, 228: Inverter 230, 232: Transmission gate 234: NOR gate 236, 238: Inverter 240: NOR gate 242: Inverter 244: NOR gate 250: Read gate control circuit 251: Write control circuit 252: Latch circuit 254: Precharge circuit 262: Inverted bypass data signal XORB / Inverted bypass data signal 302: Signal GLB_DCK / Global clock signal CLK 304: Signal IWEB 306: Signal GLB_SAE 502: Rising clock edge 504: Second rising clock edge 510: Enable signal D_SAEB 520: Precharge enable signal DLEQB 530: Write enable signal (WEB) 800: Memory device 802: First switch / Transistor 804: Second switch / Transistor 806: P-type transistor 810: Read gate control circuit 900: Memory device 909: Input circuit 1000: Example method for operating a memory device 1002, 1004: Operations 1006, 1008: Operations BL: Voltage BLB: Voltage BWE, BWEB: Write enable signal CLK: Global clock signal DB: Data signal bus DCK: Clock signal DFTB: Test enable signal DL, DLB: Data wires DLEQB: Precharge enable signal D_C, D_T: Signals D_SAEB: Enable signal D_SAE: Enable signal D, DS: Data signals GLB_DCK: Signal GLB_SAE: Signal HIT, HITB: Control signals IBWE, IBWBE: Outputs N1: First NOR gate N2: Second NOR gate N3~N8: N-type transistors n1~n3: Nodes P3~P9: P-type transistors PM, PMB: Enable control signals Q: Output signal SAE,SAEB: Start signal SQ: Data output signal SXOR: Bypass data signal T1~T5: Time VSS, VDDM: Power supply voltage / voltage terminal WC: Write complement WCLK: Signal / write clock WT: Write true value XOR: Data signal / bypass data signal XORB: Inverted bypass data signal / data signal bus bar, As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, aspects of embodiments of the present disclosure will be best understood. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of each feature may be arbitrarily increased or decreased. FIG. 1 illustrates a block diagram of a memory device according to some embodiments of the present disclosure; FIG. 2 illustrates a detailed schematic diagram of the memory device of FIG. 1 according to some embodiments of the present disclosure; FIG. 3 illustrates a detailed schematic diagram of the memory device of FIG. 1 in a read mode according to some embodiments of the present disclosure; FIG. 4 illustrates a detailed schematic diagram of the memory device of FIG. 1 in a write mode according to some embodiments of the present disclosure; FIG. 5 illustrates waveforms of signals in the memory device in FIGS. 3 and 4 according to some embodiments of the present disclosure; FIG. 6 illustrates a detailed schematic diagram of the memory device of FIG. 1 in a test mode according to some embodiments of the present disclosure; FIG. 7 illustrates waveforms of signals in the memory device in FIG. 6 according to some embodiments of the present disclosure; FIG. 8 illustrates a detailed schematic diagram of the memory device of FIG. 1 according to some embodiments of the present disclosure; FIG. 9 illustrates a detailed schematic diagram of the memory device of FIG. 1 according to some embodiments of the present disclosure; and FIG. 10 is a flowchart of an example method for operating the memory device of FIG. 1 according to some embodiments of the present disclosure. Domestic registration information (please note in the order of registration institution, date, number) None Foreign registration information (please note in the order of registration country, institution, date, number) None 100: Memory device 102: Bypass circuit 103: Exclusive OR (XOR) gate 104: First latch 106: Second latch 108: First transistor 109: Input circuit 110: Second transistor 112: First switch 114: Second switch 116: D latch circuit 118: Inverter 120: NOR gate 132: Data signal D 134: Write enable signal BWEB 136: Bypass data signal SXOR / XOR output 138: Data connection DL / First data connection 140: Data connection DLB / Second data connection 142: Output signal Q 144: Write enable signal BWE / Sensing enable signal SAE 146: Clock signal DCK 148: Control signal / Test enable signal DFTB 150: Memory array 160: Input / output circuit BWEB: Write enable signal DL, DLB: Data connections D: Data signal SXOR: Bypass data signal Q: Output signal
Claims
1. An input / output circuit comprising: a bypass circuit for directly receiving a data signal and indirectly receiving a write start signal via a mutex or gate, wherein the mutex or gate generates a bypass data signal based on the data signal and the write start signal; a first latch coupled between a first data line and a second data line, and including a first switch and a second switch, wherein the first switch is coupled between the first data line and an output of the bypass circuit, and wherein the second switch is coupled between the second data line and the output of the bypass circuit; a second latch operatively coupled to the first latch and for generating a data output signal based on a voltage level present on the second data line; a first transistor coupled to the first latch and gated by a sensed start signal; and a second transistor coupled to the first latch and gated by a clock signal. The first transistor and the second transistor are activated alternately in each of the multiple operating modes of the input / output circuit.
2. The input / output circuit as described in claim 1, wherein in at least one of the plurality of operating modes, the first latch and the second latch jointly operate as a data flip-flop, the clock signal is deactivated, and the sensing start signal acts as a clock source for the data flip-flop toggle.
3. The input / output circuit as claimed in claim 1, wherein the bypass circuit includes the XOR gate, the XOR gate causing one of the plurality of inputs of the XOR gate to receive the write start signal at least via an inverter and an NOR gate.
4. The input / output circuit as described in claim 3, wherein the inverse OR gate causes one of the plurality of inputs of the inverse OR gate to receive a control signal, and wherein the input / output circuit is set to a non-test mode when the control signal is in a first logic state, and is set to a test mode when the control signal is in a second logic state.
5. The input / output circuit as claimed in claim 1, wherein when the input / output circuit is in a read mode, the second transistor, the first switch, and the second switch are deactivated, and the first transistor is activated.
6. The input / output circuit as claimed in claim 1, wherein when the input / output circuit is in a write mode, the first transistor is deactivated, and the second transistor, the first switch, and the second switch are activated.
7. The input / output circuit as claimed in claim 1, wherein when the input / output circuit is in a test mode, the first transistor, the first switch and the second switch are activated, and the second transistor is deactivated.
8. The input / output circuitry as claimed in claim 1, wherein the first latch is coupled to a memory array via the first data line and the second data line.
9. A memory circuit comprising: a memory array including a memory bit cell coupled between a first data line and a second data line; and an input / output circuit operatively coupled to the memory array and comprising: a bypass circuit for directly receiving a data signal and indirectly receiving a write-in signal via a mutex gate, wherein the mutex gate generates a bypass data signal based on the data signal and the write-in signal; a first latch coupled to the first data line and the second data line, and including a first switch and a second switch, wherein the first switch is configured to selectively couple the bypass data signal to the first data line, and the second switch is configured to selectively couple an inverted signal of the bypass data signal to the second data line; and a second latch operatively coupled to the first latch and configured to generate a data output signal based on a voltage level present on the second data line.
10. A method of operating a memory circuit, comprising the following steps: directly receiving a data signal and indirectly receiving a write start signal via a mutex gate, wherein the mutex gate generates a bypass data signal based on the data signal and the write start signal; transmitting the bypass data signal to a main latch, wherein the main latch is coupled to a memory bit cell via a first data line and a second data line; transmitting a logic inverted signal of the bypass data signal to the main latch; and generating a data output signal from a shadow latch based on a voltage level present on the second data line.