Manufacturing method of package substrate

Abstract

A method for manufacturing a packaging substrate includes forming a first circuit layer and a first augmentation circuit on opposite first and second surfaces of a first dielectric layer, and forming a plurality of first conductive blind vias electrically connecting the first circuit and the first augmentation circuit from the second surface, and then forming a plurality of second conductive blind vias electrically connecting the first augmentation circuit from the first surface, thereby solving the problem that the prior art cannot meet the requirements of high-density and fine-pitch circuits.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a packaging substrate in which corresponding conductive blind vias are formed on both sides of a self-dielectric layer. [Previous Technology]

[0002] With the advancement of manufacturing technology in the electronics industry, in recent years, electronic products have been developing towards thinner, lighter, and smaller forms, and towards higher performance, higher functionality, and higher speeds. Therefore, in order to meet the requirements of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch lines are often used in the packaging process.

[0003] As shown in FIG1, the conventional packaging substrate 1 includes a dielectric layer 11 having opposing first surfaces 111 and second surfaces 112, a first circuit layer 12 formed on the first surface 111, a second circuit layer 13 formed on the second surface 112, and a plurality of conductive blind vias 14 formed in the dielectric layer 11 and electrically connecting the first circuit layer 12 and the second circuit layer 13. Subsequently, an insulating protective layer 15 having an opening with an exposed portion of the first circuit layer 12 and the second circuit layer 13 can be formed on the first surface 111 and the second surface 112, and a plurality of conductive blocks 16, 16' are formed in each of the openings, so that the chip 9 can be electrically connected to the second circuit layer 13 through the plurality of conductive blocks 16' of the openings of the insulating protective layer 15 on the second circuit layer 13. The packaging substrate 1 can also be disposed on a printed circuit board (PCB) 8 through each of the conductive blocks 16 located on the first circuit layer 12.

[0004] However, in the conventional packaging substrate 1, after forming a hole through the dielectric layer 11 from the first surface 111 to the second surface 112, a conductive material is then filled into the hole to form each conductive blind via 14. Therefore, as shown in the figure, each conductive blind via 14 is usually limited by the relatively wide line diameter at the first surface 111. As a result, a relatively wide spacing must usually be maintained between adjacent conductive blind vias 14, which cannot meet the requirements of high density and fine pitch lines.

[0005] Therefore, how to overcome the various problems of the aforementioned conventional methods has become an urgent issue to be addressed. [Summary of the Invention]

[0006] In view of the various deficiencies of the prior art, the present invention provides a method for manufacturing a packaging substrate, comprising: forming a first circuit layer on a first metal layer; forming a first dielectric layer on the first metal layer and the first circuit layer, wherein the first dielectric layer has a first surface and a second surface opposite to each other, and the first surface contacts the first metal layer; forming a first augmentation circuit on the second surface of the first dielectric layer, and forming a plurality of first conductive blind vias in the first dielectric layer to electrically connect the first circuit layer and the first augmentation circuit; forming a plurality of second conductive blind vias from the first surface in the first dielectric layer to electrically connect the first augmentation circuit; and removing the first metal layer to expose the first surface of the first dielectric layer, each of the first conductive blind vias and each of the second conductive blind vias.

[0007] In one specific embodiment of the aforementioned method for manufacturing a packaging substrate, the first metal layer is bonded to a carrier plate.

[0008] In one specific embodiment of the aforementioned method for manufacturing a packaging substrate, the carrier plate is a copper foil substrate.

[0009] In one specific embodiment of the aforementioned method for manufacturing a packaging substrate, the fabrication of the first conductive blind via includes forming a second metal layer on the second surface of the first dielectric layer; forming a plurality of first holes penetrating the first dielectric layer from the second metal layer and the second surface of the first dielectric layer using a laser; and filling the plurality of first holes with conductive material to form the first conductive blind via.

[0010] In one specific embodiment of the aforementioned method for manufacturing a packaging substrate, the formation of the first augmentation layer includes forming a plurality of first holes penetrating the first dielectric layer, forming a patterned resist layer on the second metal layer to expose a portion of the second metal layer and the plurality of first holes; forming the conductive material on the exposed portion of the second metal layer and filling the plurality of first holes with the conductive material to form the first augmentation layer, and forming the plurality of first conductive blind vias electrically connecting the first circuit layer and the first augmentation layer.

[0011] In one specific embodiment of the aforementioned method for manufacturing a packaging substrate, the fabrication of the second conductive blind via includes forming a plurality of second holes penetrating the first dielectric layer from the first surface of the first metal layer and the first dielectric layer using a laser; and filling the plurality of second holes with conductive material to form the second conductive blind via.

[0012] In one specific embodiment of the aforementioned method for manufacturing a packaging substrate, the first conductive blind via and the second conductive blind via exposed on the first surface of the first dielectric layer have the same linewidth.

[0013] In one specific embodiment of the aforementioned method for manufacturing a packaging substrate, a second dielectric layer is formed on the second surface of the first dielectric layer, a second augmentation line is formed on the surface of the second dielectric layer, and a plurality of third conductive blind vias are formed in the second dielectric layer to electrically connect the first augmentation line and the second augmentation line.

[0014] One specific embodiment of the aforementioned method for manufacturing a packaging substrate further includes forming an insulating protective layer on the first surface of the first dielectric layer and the surface of the second dielectric layer, wherein the insulating protective layer has a plurality of openings to expose portions of the second augmented layer circuitry and each of the first conductive blind vias and each of the second conductive blind vias.

[0015] The aforementioned method for manufacturing a packaging substrate further includes forming conductive blocks in each of the openings.

[0016] As can be seen from the above, in the manufacturing method of the packaging substrate of the present invention, the second conductive blind hole and the first conductive blind hole are formed respectively from the first surface and the second surface of the first dielectric layer to achieve the purpose of increasing the line density. [Simplified Explanation of the Diagram]

[0017] Figure 1 is a cross-sectional schematic diagram of a conventional packaging substrate.

[0018] Figures 2A to 2M are cross-sectional schematic diagrams of the manufacturing method of the packaging substrate of the present invention.

[0019] Figure 3 is a schematic diagram of the actual application of the packaging substrate of the present invention.

Implementation Method

[0020] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0021] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only used to complement the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention. At the same time, the terms such as "above," "first," "second," and "a" used in this specification are only for the clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0022] Figures 2A to 2M are cross-sectional schematic diagrams of the manufacturing method of the packaging substrate of the present invention.

[0023] As shown in Figure 2A, a carrier plate 20 is provided, wherein the carrier plate may be a copper foil substrate.

[0024] In detail, the carrier plate 20 includes an insulating plate body 200 and copper foil 201 formed on two opposing surfaces of the insulating plate body 200. In addition, at least one first metal layer 202 is bonded to the copper foil 201 on at least one side of the insulating plate body 200.

[0025] In this embodiment, as shown in the figure, the first metal layer 202 is formed on both the upper and lower sides of the insulating plate 200. The process performed on each of the first metal layers 202 is the same. Therefore, the following description will only take the first metal layer 202 on one side as an example.

[0026] As shown in Figure 2B, a first circuit layer 21 is formed on the first metal layer 202.

[0027] As shown in FIG2C, a first dielectric layer 22 is formed on the first metal layer 202 and the first circuit layer 21 to cover the first metal layer 202 and the first circuit layer 21. The first dielectric layer 22 has a first surface 221 and a second surface 222 opposite to each other. Accordingly, the first surface 221 contacts the first metal layer 202, and the first circuit layer 21 is embedded in the first dielectric layer 22. The first circuit layer 21 is flush with the first surface 221 of the first dielectric layer 22, and a portion of the first circuit layer 21 is exposed outside the first dielectric layer 22.

[0028] Next, as shown in Figures 2C to 2F, a first layered circuit 25 is formed on the second surface 222 of the first dielectric layer 22, and a plurality of first conductive blind vias 224 are formed in the first dielectric layer 22 to electrically connect the first circuit layer 21 and the first layered circuit 25, as detailed below.

[0029] As shown in FIG2C, a second metal layer 23 is formed on the second surface 222 of the first dielectric layer 22.

[0030] As shown in FIG2D, a first hole 223 is formed in the second metal layer 23 and the first dielectric layer 22 to expose the first metal layer 202 and the first circuit layer 21.

[0031] As shown in FIG2E, after forming a plurality of first holes 223 penetrating the first dielectric layer 22, a patterned resist layer 24 is formed on the second metal layer 23. The patterned resist layer 24 has an opening 241 exposing the second metal layer 23, thereby exposing a portion of the second metal layer 23 and the plurality of first holes 223.

[0032] As shown in FIG2F, the conductive material is formed on the exposed portion of the second metal layer 23 and filled into the plurality of first holes 223 to form a first augmentation line 25 on the second metal layer 23 (as shown in FIG2E), and a plurality of first conductive blind vias 224 are formed in the first dielectric layer 22 to electrically connect the first circuit layer 21 (as shown in FIG2D) and the first augmentation line 25. Afterwards, the patterned resist layer 24 is removed.

[0033] In this embodiment, a first hole 223 penetrating the first dielectric layer 22 can be formed from the second surface 222 of the second metal layer 23 and the first dielectric layer 22 using a laser process (as shown in FIG2D), and a conductive material is electroplated in the first hole 223 to form the first conductive blind hole 224.

[0034] As shown in FIG2G, a second dielectric layer 26 is formed on the second surface 222 of the first dielectric layer 22, and a second augmentation line 27 is formed on the surface of the second dielectric layer 26. In addition, a plurality of third conductive blind vias 261 may be formed in the second dielectric layer 26 to electrically connect the first augmentation line 25 and the second augmentation line 27.

[0035] In other embodiments, multiple dielectric layers and additional circuitry may be omitted or added as needed, such as a third dielectric layer and a third additional circuitry (figure omitted).

[0036] As shown in Figure 2H, the insulating plate 200 and copper foil 201 are removed to expose the first metal layer 202.

[0037] As shown in FIG2I, a plurality of second holes 225 are formed from the first surface 221 of the first metal layer 202 and the first dielectric layer 22 to the second surface 222.

[0038] As shown in FIG2J, a plurality of second conductive blind holes 226 are formed in each of the second holes 225 (as shown in FIG2H), that is, a plurality of second conductive blind holes 226 are formed from the first surface 221 in the first dielectric layer 22 to electrically connect the second circuit layer 25.

[0039] In this embodiment, a reverse laser process can be used to form a second hole 225 penetrating the first dielectric layer 22 from the first surface 221 of the first metal layer 202 and the first dielectric layer 22, and a conductive material is filled into the second hole 225 to form a second conductive blind via 226. Accordingly, the present invention further forms a second conductive blind via 226 between two adjacent first conductive blind vias 224 by performing a reverse laser process on the first surface 221, thereby increasing the line density.

[0040] As shown in FIG2K, the first metal layer 202 is removed to expose the first surface 221 of the first dielectric layer 22, each of the first conductive blind vias 224 and each of the second conductive blind vias 226.

[0041] In one embodiment, the first conductive blind via 224 and the second conductive blind via 226 exposed on the first surface 221 of the first dielectric layer 22 have the same linewidth, that is, the linewidth Φ1 of the first conductive blind via 224 is equal to the linewidth Φ2 of the second conductive blind via 226. Furthermore, the end width of each of the second conductive blind vias 226 on the second surface 222 is thinner than the end width of the first conductive blind via 224 on the second surface 222.

[0042] As shown in FIG2L, insulating protective layers 28 are formed on the first surface 221 of the first dielectric layer 22 and the surface of the second dielectric layer 26 to form the packaging substrate 2 of the present invention. The insulating protective layer 28 on the first surface 221 has a plurality of openings 281 to expose each of the first conductive blind vias 224 and each of the second conductive blind vias 226. The insulating protective layer 28 on the surface of the second dielectric layer 26 has a plurality of openings 281' to expose the second added-layer circuitry 27. In one embodiment, the packaging substrate 2 of the present invention may optionally not form the insulating protective layer 28. Furthermore, in a specific embodiment, the insulating protective layer 28 may be formed of a photosensitive polyimide (PSPI) solder resist material.

[0043] As shown in Figure 2M, after forming each of the openings 281, 281', conductive blocks 29, 29' can be formed in each of the openings 281, 281'.

[0044] As shown in Figure 3, in practical applications, the packaging substrate 2 obtained by the above process can allow the chip 9 to be disposed on the first surface 221 through each of the conductive blocks 29, and disposed on a printed circuit board (PCB) 8 through each of the conductive blocks 29' on the third circuit layer 27. Accordingly, since the packaging substrate 2 of the present invention provides dense lines through each of the first conductive blind holes 224 and each of the second conductive blind holes 226, it can cope with the higher density solder ball arrangement design on the chip 9. Furthermore, with the use of an insulating protective layer 28 with high resolution openings, it can achieve the purpose of being suitable for packaging substrates such as chiplets.

[0045] In summary, after forming a first conductive blind via on the second surface of the first dielectric layer, the present invention further opens a second hole on the first surface and forms a second conductive blind via, thus providing finer circuitry. Therefore, a high-density circuit design can be formed on the die-placement side (such as the first surface). Thus, the present invention can form high-density circuitry through a simple process, thereby achieving the purpose of forming high-density and fine-pitch circuitry. In addition, the present invention forms each of the second conductive blind vias on the first surface through a reverse laser process, thereby achieving the purpose of forming pads of consistent size and higher density on the die-placement side.

[0046] The above embodiments are used to illustrate the principles and effects of the present invention, and are not intended to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following claims.

Claims

1. A method for manufacturing a packaging substrate, comprising: A first circuit layer is formed on the first metal layer; A first dielectric layer is formed on the first metal layer and the first circuit layer, wherein the first dielectric layer has a first surface and a second surface opposite to each other, and the first surface contacts the first metal layer; a first add-on circuit is formed on the second surface of the first dielectric layer, and a plurality of first conductive blind vias are formed in the first dielectric layer to electrically connect the first circuit layer and the first add-on circuit; a plurality of second conductive blind vias are formed from the first surface in the first dielectric layer to electrically connect the first add-on circuit. And remove the first metal layer to expose the first surface of the first dielectric layer, each of the first conductive blind vias and each of the second conductive blind vias.

2. The method for manufacturing the packaging substrate as described in claim 1, wherein, The first metal layer is bonded to at least one side of an insulating plate so that the first metal layer and the insulating plate form a support plate.

3. The method for manufacturing the packaging substrate as described in claim 2, wherein, The substrate is a copper foil substrate.

4. The method for manufacturing the packaging substrate as described in claim 1, wherein, The fabrication of the first conductive blind via includes forming a second metal layer on the second surface of the first dielectric layer; forming a plurality of first holes penetrating the first dielectric layer from the second metal layer and the second surface of the first dielectric layer by laser; and filling the plurality of first holes with conductive material to form the first conductive blind via.

5. The method for manufacturing the packaging substrate as described in claim 4, wherein, The formation of the first augmentation layer includes forming a plurality of first holes penetrating the first dielectric layer, forming a patterned resist layer on the second metal layer, exposing a portion of the second metal layer and the plurality of first holes; forming a conductive material on the exposed portion of the second metal layer and filling the plurality of first holes with the conductive material to form the first augmentation layer, and forming a plurality of first conductive blind vias electrically connecting the first circuit layer and the first augmentation layer.

6. The method for manufacturing the packaging substrate as described in claim 1, wherein, The fabrication of the second conductive blind via includes forming a plurality of second holes penetrating the first dielectric layer from the first surface of the first metal layer and the first dielectric layer using a laser; and filling the plurality of second holes with conductive material to form the second conductive blind via.

7. The method for manufacturing the packaging substrate as described in claim 1, wherein, The first conductive blind via and the second conductive blind via exposed on the first surface of the first dielectric layer have the same linewidth.

8. The method for manufacturing a packaging substrate as described in claim 1 further includes forming a second dielectric layer on the second surface of the first dielectric layer, forming a second augmentation circuit on the surface of the second dielectric layer, and forming a plurality of third conductive blind vias in the second dielectric layer to electrically connect the first augmentation circuit and the second augmentation circuit.

9. The method for manufacturing a packaging substrate as described in claim 8 further includes forming insulating protective layers on the first surface of the first dielectric layer and the surface of the second dielectric layer, respectively, wherein, The insulating protective layer has a plurality of openings to expose the second additional layer circuitry and each of the first conductive blind vias and each of the second conductive blind vias.

10. The method for manufacturing the packaging substrate as described in claim 9 further includes forming conductive blocks in each of the openings.

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