Power inductor

Abstract

A power inductor includes a coil and a magnetizing element. The coil includes two outer loop circuit layers and a plurality of insulating spacer layers. These outer loop circuit layers are stacked on top of each other and electrically connected. Each outer loop circuit layer has an external connection terminal. At least one insulating spacer layer is located between these outer loop circuit layers. The magnetizing element covers the coil and exposes the external connection terminals of each outer loop circuit layer. The magnetizing element includes a plurality of ferromagnetic particles. Each ferromagnetic particle includes iron-based alloy particles and an insulating film covering the iron-based alloy particles.

Description

[Technical Field]

[0001] This invention relates to an electronic component, and more particularly to a power inductor. [Previous Technology]

[0002] Most common power inductors have the problem of low insulation resistance, which makes them prone to short circuits in high current and voltage circuits, such as automotive circuits and high-power 3C product circuits, causing abnormal operation or even permanent failure of the power inductor. [Summary of the Invention]

[0003] This invention proposes a power inductor with high insulation resistance.

[0004] The power inductor proposed in this invention includes a coil and a magnetizing element. The coil includes two outer loop circuit layers and a plurality of insulating spacer layers, wherein these outer loop circuit layers are stacked on top of each other and electrically connected. Each outer loop circuit layer has an external connection terminal, wherein at least one insulating spacer layer is located between these outer loop circuit layers. The magnetizing element covers the coil and exposes the external connection terminals of each outer loop circuit layer. The magnetizing element includes a plurality of ferromagnetic particles, and each ferromagnetic particle includes iron-based alloy particles and an insulating film, wherein the insulating film covers the iron-based alloy particles.

[0005] In at least one embodiment of the present invention, an outer loop circuit layer is located between two adjacent insulating spacer layers.

[0006] In at least one embodiment of the present invention, the power inductor further includes a plurality of external electrodes. These plurality of external electrodes partially cover the outer surface of the magnetor and are connected to the external connection terminals of the outer loop circuit layers.

[0007] In at least one embodiment of the present invention, the coil further includes an inner loop circuit layer. The inner loop circuit layer is disposed between the outer loop circuit layers and electrically connected to the outer loop circuit layers, wherein the inner loop circuit layer is located between two insulating spacer layers.

[0008] In at least one embodiment of the present invention, each outer loop circuit layer further has a first internal connection terminal relative to the external connection terminal, while the inner loop circuit layer has two second internal connection terminals opposite to each other, wherein the first internal connection terminal of each outer loop circuit layer is connected to one of the second internal connection terminals.

[0009] In at least one embodiment of the present invention, each insulating spacer layer is strip-shaped. Two of these insulating spacers respectively cover and directly contact the outer loop circuit layers, and extend along the outer loop circuit layers. Each outer loop circuit layer has a pair of opposing first sidewalls, and two insulating spacers extending along the outer loop circuit layers respectively protrude from these first sidewalls.

[0010] In at least one embodiment of the present invention, a first internal connection end of an outer loop circuit layer protrudes from the end of an insulating spacer layer.

[0011] In at least one embodiment of the invention, one of these insulating spacers directly contacts the inner loop circuit layer and extends along the inner loop circuit layer. The inner loop circuit layer has a pair of opposing second sidewalls, and the insulating spacers extending along the inner loop circuit layer protrude from these second sidewalls.

[0012] In at least one embodiment of the present invention, one of the second internal connection ends of the inner loop circuit layer protrudes from the end of the insulating spacer layer extending along the inner loop circuit layer.

[0013] In at least one embodiment of the present invention, each insulating spacer layer protrudes from the edge of any of these outer loop circuit layers.

[0014] Based on the above, by utilizing these insulating spacer layers, the insulation resistance between the outer loop circuit layer and the inner loop circuit layer can be effectively improved to avoid short circuits, thereby facilitating the application of power inductors in high-current and high-voltage circuits such as automotive circuits and high-power 3C product circuits.

Implementation Method

[0016] In the following text, in order to clearly present the technical features of this application, the dimensions (e.g., length, width, thickness, area, or depth) of the elements (e.g., layers, films, substrates, and regions) in the drawings will be enlarged proportionally, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the size and shape of the elements, but should cover the size, shape, and deviations of both caused by actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the drawings of this application are mainly for illustration and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of the claims of this application.

[0017] FIG1A is a top view schematic diagram of a power inductor according to at least one embodiment of the present invention. Referring to FIG1A, the power inductor 100 includes a coil 110, a magnetizing element 120, and a plurality of external electrodes 130, wherein the magnetizing element 120 covers the coil 110. These external electrodes 130 partially cover the outer surface of the magnetizing element 120 and are connected to the coil 110. Taking FIG1A as an example, these external electrodes 130 may respectively cover the left and right sides of the magnetizing element 120, so that these external electrodes 130 partially cover the outer surface of the magnetizing element 120, but do not cover the entire outer surface of the magnetizing element 120.

[0018] Figure 1B is a top view of the power inductor in Figure 1A after the external electrodes have been removed, and Figure 1C is a cross-sectional view drawn along line 1C-1C in Figure 1A. Referring to Figures 1B and 1C, the coil 110 includes two outer loop circuit layers 111a, at least one inner loop circuit layer 111b, and multiple insulating spacer layers 112. The insulating spacer layer 112 may be a ceramic material layer or a ferromagnetic material, and the outer loop circuit layer 111a and the inner loop circuit layer 111b may be made of copper, silver, or gold, or an alloy material.

[0019] An inner loop circuit layer 111b is disposed between these outer loop circuit layers 111a. The two outer loop circuit layers 111a are stacked on top of each other and electrically connected. For example, the inner loop circuit layer 111b is electrically connected to these outer loop circuit layers 111a, so that the two outer loop circuit layers 111a are electrically connected to each other through the inner loop circuit layer 111b. Furthermore, in this embodiment, at least one insulating spacer layer 112 is located between these outer loop circuit layers 111a, and one of the outer loop circuit layers 111a may be located between two adjacent insulating spacer layers 112.

[0020] Taking Figure 1C as an example, the upper outer loop circuit layer 111a is sandwiched between two adjacent insulating spacer layers 112, but the lower outer loop circuit layer 111a is only covered by the insulating spacer layer 112 on its upper surface, while the lower surface of the lower outer loop circuit layer 111a is not covered by any insulating spacer layer 112. Furthermore, the inner loop circuit layer 111b is located between two of the insulating spacer layers 112, such that two of the insulating spacer layers 112 are located between these outer loop circuit layers 111a.

[0021] However, in other embodiments, each outer loop circuit layer 111a may not be located between two adjacent insulating spacers 112. For example, in FIG1C, the uppermost insulating spacer 112 may be omitted so that the upper surface of the upper outer loop circuit layer 111a is not covered by the insulating spacer 112. In this way, the magnetizer 120 exposes not only the upper surface of the upper outer loop circuit layer 111a, but also the lower surface of the lower outer loop circuit layer 111a. In other words, the magnetizer 120 may not cover the upper surface of the upper outer loop circuit layer 111a and the lower surface of the lower outer loop circuit layer 111a.

[0022] Each outer loop circuit layer 111a has an external connection terminal Pa1, which is essentially a pad and is used to electrically connect to an external electrode 130 (shown in FIG. 1A) so that external electrical energy can be input to the external connection terminal Pa1 via the external electrode 130. In this way, the power inductor 100 can operate, thereby enabling the circuit in which the power inductor 100 is installed (e.g., automotive circuit or high-power 3C product circuit) to function.

[0023] It is worth mentioning that the power inductor 100 includes two outer loop circuit layers 111a, and each outer loop circuit layer 111a has at least one external connection terminal Pa1, so the power inductor 100 will have at least two external connection terminals Pa1. In addition, in the embodiment shown in FIG1B, the external connection terminal Pa1 located on the left half is covered by the rectangular insulating spacer layer 112 on the left, so FIG1B only depicts a single external connection terminal Pa1.

[0024] Additionally, it should be noted that in this embodiment, the power inductor 100 includes an inner loop circuit layer 111b, so the power inductor 100 has three circuit layers, namely two outer loop circuit layers 111a and one inner loop circuit layer 111b. However, in other embodiments, the power inductor 100 may not include the inner loop circuit layer 111b, so that the power inductor 100 has only two circuit layers, namely two outer loop circuit layers 111a. Therefore, the inner loop circuit layer 111b in FIG. 1C can be omitted.

[0025] Based on the above, the power inductor 100 of this embodiment is not limited to including an inner loop circuit layer 111b. In addition, the power inductor 100 may have four or more circuit layers, wherein the power inductor 100 may include multiple inner loop circuit layers 111b. Therefore, the power inductor 100 of this embodiment is not limited to including only a single inner loop circuit layer 111b.

[0026] It is worth mentioning that the power inductor 100 may further include multiple cover layers 140a and 140b, wherein these cover layers 140a and 140b respectively cover the opposite sides of the magnetizing element 120 and the coil 110, and can directly contact the magnetizing element 120. That is, the magnetizing element 120 and the coil 110 are both located between the cover layers 140a and 140b. Therefore, the cover layers 140a and 140b will cover these outer loop circuit layers 111a and at least one insulating spacer layer 112 (e.g., the uppermost insulating spacer layer 112 in FIG. 1E). In addition, it is particularly worth mentioning that the power inductor 100 shown in FIG. 1B is also drawn after the cover layers 140a and 140b have been removed.

[0027] Figure 1D is a partially enlarged cross-sectional view of the magnetizing element in Figure 1C. Referring to Figure 1D, the magnetizing element 120 includes multiple ferromagnetic particles (not shown), each of which includes iron-based alloy particles 121 and an insulating film 122, with the insulating film 122 covering the iron-based alloy particles 121. The insulating film 122 can be an oxide film, and its material can be silicon dioxide. Alternatively, the insulating film 122 can also be formed from iron oxide-based alloy particles 121. For example, the iron-based alloy particles 121 are placed in a high-temperature furnace containing oxygen to oxidize the surface of the iron-based alloy particles 121, thereby forming the insulating film 122.

[0028] Because each iron-based alloy particle 121 is coated by the insulating film 122, the conductivity of the magnetoresistive element 120 decreases, that is, the resistance of the magnetoresistive element 120 increases. Therefore, even though the magnetoresistive element 120 contains conductive iron-based alloy particles 121, the overall conductivity of the magnetoresistive element 120 is not as good as that of ordinary metals, and can even be equivalent to that of an insulator. Secondly, since the magnetoresistive element 120 includes multiple iron-based alloy particles 121, the magnetoresistive element 120 is ferromagnetic.

[0029] It can be seen that when the outer loop circuit layer 111a and the inner loop circuit layer 111b in Figure 1C transmit current, the current will not be transmitted in the high-resistance magnet 120, but the magnet 120 can induce a magnetic field through the current transmitted in the outer loop circuit layer 111a and the inner loop circuit layer 111b, thereby achieving the function of an inductor.

[0030] Referring to Figure 1C, among these insulating spacer layers 112, only one insulating spacer layer 112 is disposed on one side of the outer loop circuit layer 111a, and each of the other insulating spacer layers 112 is disposed between two adjacent layers of the outer loop circuit layer 111a and the inner loop circuit layer 111b. Thus, when the power inductor 100 is used in high-current and high-voltage circuits such as automotive circuits or high-power 3C product circuits, the insulating spacer layer 112 sandwiched between two adjacent layers of the outer loop circuit layer 111a and the inner loop circuit layer 111b can effectively block the current penetrating the magnetic inductor 120, thereby preventing short circuits from occurring.

[0031] It is worth mentioning that both cover layers 140a and 140b have electrical insulating properties. For example, cover layers 140a and 140b can be made of ceramic or other insulating materials. Alternatively, at least one of the constituent materials of cover layers 140a and 140b can be the same as the constituent material of the magnetizing element 120, that is, at least one of cover layers 140a and 140b also includes a plurality of ferromagnetic particles in the aforementioned magnetizing element 120 (as shown in Figure 1D). Therefore, the conductivity of both cover layers 140a and 140b is like that of an insulator, that is, both cover layers 140a and 140b have electrical insulating properties.

[0032] In one embodiment, the capping layers 140a, 140b and the magnetizer 120 may have ferromagnetic particles of the same size and composition. That is, the ferromagnetic particles in the capping layers 140a, 140b and the magnetizer 120 are substantially the same size (e.g., diameter) and made of the same material. Therefore, no boundary is formed between either the capping layers 140a and 140b and the magnetizer 120. In other words, when the capping layers 140a, 140b and the magnetizer 120 have ferromagnetic particles of the same size and composition, the boundary between either the capping layers 140a and 140b and the magnetizer 120 will not be clearly visible even using an electron microscope, such as a transmission electron microscope (TEM).

[0033] However, in other embodiments, since the cover layers 140a and 140b can be made of ceramic or other insulating materials, the constituent materials of the cover layers 140a and 140b can be different from the constituent materials of the magnetizer 120, such that either the cover layer 140a or 140b forms a boundary with the magnetizer 120, wherein this boundary can be observed by an optical microscope or an electron microscope (e.g., TEM).

[0034] Furthermore, even if the capping layers 140a and 140b and the magnetizer 120 have ferromagnetic particles made of the same constituent material, a boundary can still be formed between either capping layer 140a or 140b and the magnetizer 120. Specifically, when the ferromagnetic particles in the capping layers 140a and 140b and the magnetizer 120 have substantially different particle sizes, a boundary will still be formed between either capping layer 140a or 140b and the magnetizer 120. For example, when the particle size of the ferromagnetic particles in the magnetizer 120 differs from the average particle size (D50) of the ferromagnetic particles in the capping layers 140a and 140b by more than 2 micrometers (µm), a boundary that can be observed by an electron microscope will still be formed between either capping layer 140a or 140b and the magnetizer 120.

[0035] Figure 1E is a cross-sectional view shown along line 1E-1E in Figure 1A. Referring to Figures 1A and 1E, the magnetor 120 exposes the external connection terminals Pa1 of each outer loop circuit layer 111a so that the external electrodes 130 can connect to these external connection terminals Pa1. Specifically, in the embodiment shown in Figure 1E, two opposite sides (e.g., the left and right sides) of the magnetor 120 expose the sides of these external connection terminals Pa1, and the external electrodes 130 respectively cover the aforementioned two opposite sides of the magnetor 120. Thus, these external electrodes 130 can respectively contact and connect to the external connection terminals Pa1, so that these external electrodes 130 can be electrically connected to these external connection terminals Pa1, thereby allowing the power inductor 100 to receive external electrical energy and function via the external electrodes 130.

[0036] In this embodiment, the power inductor 100 is formed by stacking and laminating multiple substrates, wherein each substrate has only one circuit layer. Therefore, the aforementioned power inductor 100 with three circuit layers can be formed by stacking and laminating three substrates. The manufacturing method of the power inductor 100 will be described below using the power inductor 100 with three circuit layers (refer to FIG. 1C) as an example, and in conjunction with FIG. 2A to 2C, FIG. 3A to 3B and FIG. 4A to 4C.

[0037] Referring to Figures 2A to 2C, in the manufacturing method of the power inductor 100, a first substrate 201 is provided, wherein Figure 2A is a bottom view of the first substrate 201, and Figure 2B is a cross-sectional view drawn along line 2B-2B in Figure 2A. Figure 2C is a top view of the first substrate 201, and is drawn by flipping Figure 2A of the first substrate 201 horizontally. The first substrate 201 includes a release layer 20, an outer loop circuit layer 111a, and an insulating spacer layer 112 disposed between the release layer 20 and the outer loop circuit layer 111a.

[0038] In the fabrication process of the first substrate 201, firstly, an insulating spacer layer 112 and an outer loop circuit layer 111a are sequentially formed on the release layer 20. The material of the release layer 20 can be an organic material, such as polyethylene terephthalate (PET). The insulating spacer layer 112 and the outer loop circuit layer 111a can be formed by printing, exposure and development, spraying, or deposition. The aforementioned deposition can be physical vapor deposition (PVD) or chemical vapor deposition (CVD). Subsequently, a magnetically sensitive layer 120i is formed on the release layer 20. The magnetically sensitive layer 120i can be formed by printing, exposure and development, or spraying.

[0039] The outer loop circuit layer 111a is strip-shaped, resembling an inverted C shape as shown in Figure 2C. The outer loop circuit layer 111a has an external connection terminal Pa1 and a first internal connection terminal Pb1 relative to the external connection terminal Pa1, wherein the external connection terminal Pa1 and the first internal connection terminal Pb1 are both opposite ends of the outer loop circuit layer 111a. The external connection terminal Pa1 of the first substrate 201 is covered by the insulating spacer layer 112, and is also located in the left half of Figure 1B, being the external connection terminal Pa1 covered by the insulating spacer layer 112. The insulating spacer layer 112 extends along the outer loop circuit layer 111a, therefore the insulating spacer layer 112 is also strip-shaped and similar to the shape of the outer loop circuit layer 111a, for example, an inverted C shape.

[0040] However, in other embodiments, each outer loop circuit layer 111a may not be located between two adjacent insulating spacer layers 112. For example, in FIG1C, the uppermost insulating spacer layer 112 may be omitted. The outer loop circuit layer 111a has a pair of opposing first sidewalls S1a, and the insulating spacer layer 112 extending along the outer loop circuit layer 111a protrudes from the pair of first sidewalls S1a, wherein the insulating spacer layer 112 directly contacts the outer loop circuit layer 111a. Secondly, the first internal connection end Pb1 of the outer loop circuit layer 111a protrudes from the end of the insulating spacer layer 112, so the first internal connection end Pb1 is not completely covered by the insulating spacer layer 112 and directly contacts the release layer 20, as shown in FIG2A to FIG2C.

[0041] Referring to Figures 3A and 3B, a second substrate 202 is then provided and stacked and pressed onto the first substrate 201. Before the second substrate 202 is stacked and pressed onto the first substrate 201, the release layer 20 of the first substrate 201 is removed to expose the insulating spacer layer 112 and the magnetically sensitive layer 120i of the first substrate 201. Furthermore, Figure 3A is a top view of the second substrate 202, while Figure 3B shows a cross-sectional view of the second substrate 202 stacked and pressed onto the first substrate 201. The second substrate 202 shown in Figure 3B is drawn along the 3B-3B cross-section in Figure 3A.

[0042] The structure of the second substrate 202 is similar to that of the first substrate 201. Specifically, the second substrate 202 includes a release layer 20, an inner loop circuit layer 111b, and an insulating spacer layer 112 disposed between the release layer 20 and the inner loop circuit layer 111b, wherein the inner loop circuit layer 111b and the outer loop circuit layer 111a can be made of the same material. One of the second internal connection terminals Pb2 of the inner loop circuit layer 111b protrudes from the end of the insulating spacer layer 112, but the other second internal connection terminal Pb2 is covered by the insulating spacer layer 112, as shown in FIG3A. Therefore, the second internal connection terminal Pb2 is not completely covered by the insulating spacer layer 112 and directly contacts the release layer 20.

[0043] Secondly, the inner loop circuit layer 111b is strip-shaped, for example, inverted U-shaped, and has two opposing second internal connection ends Pb2, which are the opposite ends of the inner loop circuit layer 111b. The insulating spacer layer 112 of the second substrate 202 directly contacts the inner loop circuit layer 111b and extends along the inner loop circuit layer 111b, so the insulating spacer layer 112 is also strip-shaped and can be inverted U-shaped. The inner loop circuit layer 111b has a pair of opposing second sidewalls S1b, and the insulating spacer layer 112 extending along the inner loop circuit layer 111b protrudes from these second sidewalls S1b.

[0044] Please refer to Figures 2C and 3A. During the process of stacking and pressing the second substrate 202 onto the first substrate 201, the first substrate 201 (as shown in Figure 2C) is located below, while the second substrate 202 (as shown in Figure 3A) is located above. As seen in Figures 3A and 2C, the second internal connection terminal Pb2 on the left side of the upper inner loop circuit layer 111b is aligned with the first internal connection terminal Pb1 of the lower outer loop circuit layer 111a. The aforementioned second internal connection terminal Pb2 on the left side overlaps with the insulating spacer layer 112 and does not protrude beyond the edge of the insulating spacer layer 112.

[0045] Since the first internal connection terminal Pb1 of the lower outer loop circuit layer 111a protrudes from the end of the insulating spacer layer 112, the first internal connection terminal Pb1 will be exposed after the release layer 20 of the first substrate 201 is removed. Secondly, since the upper second internal connection terminal Pb2 is aligned with the lower first internal connection terminal Pb1, when the second substrate 202 is stacked and pressed onto the first substrate 201, the upper second internal connection terminal Pb2 can directly contact and connect with the lower first internal connection terminal Pb1, so that the outer loop circuit layer 111a and the inner loop circuit layer 111b can be electrically connected to each other.

[0046] During the pressing process of the second substrate 202 and the first substrate 201, the second substrate 202 and the first substrate 201 are heated to bond them together. However, the temperature of the second substrate 202 and the first substrate 201 at this time is not high, approximately below 90°C. Therefore, the magnetically sensitive layers 120i of the second substrate 202 and the first substrate 201 are not fused together, that is, a boundary still exists between the second substrate 202 and the first substrate 201.

[0047] Referring to Figures 4A and 4B, after the second substrate 202 is stacked and pressed onto the first substrate 201, a third substrate 203 is provided, and the third substrate 203 is stacked and pressed onto the second substrate 202. Before the third substrate 203 is stacked and pressed onto the second substrate 202, the release layer 20 of the second substrate 202 is removed to expose the insulating spacer layer 112 and the magnetically sensitive layer 120i of the second substrate 202. Furthermore, Figure 4A is a top view of the third substrate 203, while Figure 4B is a cross-sectional view of the third substrate 203 stacked and pressed onto the second substrate 202, wherein the third substrate 203 shown in Figure 4B is drawn along the cross-section 4B-4B in Figure 4A.

[0048] The third substrate 203 includes a release layer 20, an outer loop circuit layer 111a, and an insulating spacer layer 112 disposed between the release layer 20 and the outer loop circuit layer 111a. The structure of the third substrate 203 is similar to that of the first substrate 201, and the manufacturing methods of the third substrate 203 and the first substrate 201 are the same. For example, in the third substrate 203, both the outer loop circuit layer 111a and the insulating spacer layer 112 are strip-shaped, wherein the insulating spacer layer 112 extends along the outer loop circuit layer 111a and directly contacts the outer loop circuit layer 111a, and the insulating spacer layer 112 also protrudes from a pair of first sidewalls S1a of the outer loop circuit layer 111a. In addition, the outer loop circuit layer 111a also has an external connection terminal Pa1 and a first internal connection terminal Pb1.

[0049] As shown in Figures 2A to 2C and Figures 3A to 3B, the two insulating spacer layers 112 extending along the outer loop circuit layers 111a respectively protrude from the first sidewall S1a of the outer loop circuit layers 111a, and the insulating spacer layer 112 extending along the inner loop circuit layer 111b also protrudes from the second sidewall S1b of the inner loop circuit layer 111b, so that the insulating spacer layers 112 can increase the insulation resistance between the outer loop circuit layers 111a and the inner loop circuit layer 111b, thereby avoiding the occurrence of short circuits.

[0050] Each insulating spacer layer 112 is strip-shaped. Two of these insulating spacers 112 respectively cover and directly contact the outer loop circuit layers 111a, while the other insulating spacers 112 cover and directly contact the inner loop circuit layers 111b. In addition, the first internal connection terminal Pb1 of each outer loop circuit layer 111a is connected to a second internal connection terminal Pb2 of one of the inner loop circuit layers 111b.

[0051] The main difference between the third substrate 203 and the first substrate 201 is that the outer loop circuit layer 111a and the insulating spacer layer 112 are different. The outer loop circuit layer 111a of the first substrate 201 is in the shape of an inverted C (see Figure 2C), while the outer loop circuit layer 111a of the third substrate 203 is in the shape of a C (see Figure 4A). In addition, the external connection terminal Pa1 in the third substrate 203 is the external connection terminal Pa1 located on the right half of Figure 1B.

[0052] Please refer to Figures 3A and 4A. During the process of stacking and pressing the third substrate 203 onto the second substrate 202, the second substrate 202 (as shown in Figure 3A) is located below, while the third substrate 203 (as shown in Figure 4A) is located above. As seen in Figures 3A and 4A, the first internal connection terminal Pb1 of the upper outer loop circuit layer 111a is aligned with the second internal connection terminal Pb2 on the right side of the lower inner loop circuit layer 111b. The first internal connection terminal Pb1 overlaps with the insulating spacer layer 112 and does not protrude beyond the edge of the insulating spacer layer 112.

[0053] Since the second internal connection terminal Pb2 on the right side of the lower inner loop circuit layer 111b protrudes from the end of the insulating spacer layer 112, the second internal connection terminal Pb2 on the right side will be exposed after the release layer 20 of the second substrate 202 is removed. Secondly, since the upper first internal connection terminal Pb1 is aligned with the lower right second internal connection terminal Pb2, when the third substrate 203 is stacked and pressed onto the second substrate 202, the upper first internal connection terminal Pb1 can directly contact and connect with the lower second internal connection terminal Pb2, so that the outer loop circuit layer 111a and the inner loop circuit layer 111b can be electrically connected to each other.

[0054] Based on the above, through the direct contact and connection between the first internal connection terminal Pb1 and the second internal connection terminal Pb2, the outer loop circuit layers 111a of the first substrate 201 and the third substrate 203 are electrically connected to the inner loop circuit layers 111b of the second substrate 202. Furthermore, as can be seen from Figures 2C, 3A, and 4A, after the outer loop circuit layers 111a of the first substrate 201 and the third substrate 203 are electrically connected to the inner loop circuit layers 111b of the second substrate 202, the inner loop circuit layers 111b and these outer loop circuit layers 111a can form a spiral coil 110.

[0055] Referring to FIG4C, after the third substrate 203 is stacked and pressed onto the second substrate 202, the first substrate 201, the second substrate 202, and the third substrate 203, which are connected to each other, are then sequentially burnout and sintered to remove residual organic materials and impurities in the first substrate 201, the second substrate 202, and the third substrate 203, and to fuse the magnetic layers 120i of the three substrates into one to form a magnetizer 120 (as shown in FIG1C). The insulating films 122 of these ferromagnetic particles in the magnetic layers 120i are connected to each other due to sintering, as shown in FIG1D. The sintering process may include introducing oxygen to help the surface of the iron oxide-based alloy particles 121 (see FIG1D) increase the insulation resistance of the magnetizer 120, and the sintering temperature may be below 800°C.

[0056] Referring to Figures 4C and 1C, two cover layers 140a and 140b can be formed on opposite sides of the magnetor 120, for example, on the upper surface of the third substrate 203 and the lower surface of the first substrate 201. When the constituent materials of cover layers 140a and 140b are different from the constituent materials of the magnetor 120, cover layers 140a and 140b can be formed after the aforementioned burn-out and sintering. When the constituent materials of cover layers 140a and 140b are the same as the constituent materials of the magnetor 120, cover layers 140a and 140b can be formed on the upper surface of the third substrate 203 and the lower surface of the first substrate 201, respectively, before the aforementioned burn-out and sintering.

[0057] FIG5 is a cross-sectional schematic diagram of a power inductor according to another embodiment of the present invention. Referring to FIG5, the power inductor 500 of FIG5 is similar to the power inductor 100 of the aforementioned embodiment, wherein power inductors 500 and 100 also include some of the same components, such as the magnetizing element 120, the outer loop circuit layer 111a and the inner loop circuit layer 111b. In addition, power inductor 500 may also include an external electrode 130 and cover layers 140a and 140b not shown in FIG5. The following only describes the differences between power inductors 500 and 100, and the same technical features will not be repeated.

[0058] Unlike the power inductor 100, the power inductor 500 includes multiple insulating spacer layers 512, each of which protrudes beyond the edge of either the outer loop circuit layer 111a or the inner loop circuit layer 111b. Taking Figure 5 as an example, each insulating spacer layer 512 extends to the side of the magnetizing element 120 and completely overlaps with the upper and lower surfaces of the magnetizing element 120, such that each insulating spacer layer 512 protrudes beyond the edge, or even all edges, of either the outer loop circuit layer 111a or the inner loop circuit layer 111b. Thus, the insulating spacer layer 512 can significantly increase the insulation resistance, thereby effectively preventing short circuits between adjacent layers of the outer loop circuit layer 111a and the inner loop circuit layer 111b.

[0059] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0015] FIG1A is a top view schematic diagram of a power inductor according to at least one embodiment of the present invention. FIG1B is a top view schematic diagram of the power inductor in FIG1A after the external electrodes are removed. FIG1C is a cross-sectional schematic diagram drawn along line 1C-1C in FIG1A. FIG1D is a partially enlarged cross-sectional schematic diagram of the magnetizing element in FIG1C. FIG1E is a cross-sectional schematic diagram drawn along line 1E-1E in FIG1A. FIG2A to FIG2C, FIG3A to FIG3B and FIG4A to FIG4C are schematic diagrams of the manufacturing method of the power inductor in FIG1A. FIG5 is a cross-sectional schematic diagram of a power inductor according to another embodiment of the present invention.

Claims

1. A power inductor, comprising: A coil includes: two outer loop circuit layers stacked on top of each other and electrically connected, wherein each outer loop circuit layer has an external connection terminal; a plurality of insulating spacer layers, wherein at least one insulating spacer layer is located between the outer loop circuit layers; a magnetizing element covering the coil and exposing the external connection terminal of each outer loop circuit layer, wherein the magnetizing element includes a plurality of ferromagnetic particles, and each ferromagnetic particle includes: an iron-based alloy particle; and an insulating film covering the iron-based alloy particle.

2. The power inductor as claimed in claim 1, wherein one of the outer loop circuit layers is located between two adjacent insulating spacer layers.

3. The power inductor as described in claim 1, further comprising: Multiple external electrodes partially cover an outer surface of the magnetor and are connected to the external terminals of the outer loop circuit layers.

4. The power inductor as claimed in claim 1, wherein the coil further comprises: An inner loop circuit layer is disposed between the outer loop circuit layers and electrically connected to the outer loop circuit layers, wherein the inner loop circuit layer is located between two of the insulating spacers.

5. The power inductor of claim 4, wherein each of the outer loop circuit layers further has a first internal connection terminal relative to the external connection terminal, and the inner loop circuit layer has two second internal connection terminals opposite to each other, wherein the first internal connection terminal of each of the outer loop circuit layers is connected to one of the second internal connection terminals.

6. The power inductor of claim 5, wherein each of the insulating spacers is strip-shaped, wherein two of the insulating spacers respectively cover and directly contact the outer loop circuit layers and extend along the outer loop circuit layers, wherein each outer loop circuit layer has a pair of opposing first sidewalls, and the two insulating spacers extending along the outer loop circuit layers respectively protrude from the first sidewalls of the outer loop circuit layers.

7. The power inductor as claimed in claim 6, wherein the first internal connection terminal of one of the outer loop circuit layers protrudes from the end of one of the insulating spacer layers.

8. The power inductor of claim 6, wherein one of the insulating spacers directly contacts and extends along the inner loop circuit layer, wherein the inner loop circuit layer has a pair of opposing second sidewalls, and the insulating spacer extending along the inner loop circuit layer protrudes from the second sidewalls.

9. The power inductor of claim 8, wherein one of the second internal connection terminals of the inner loop circuit layer protrudes from the end of the insulating spacer extending along the inner loop circuit layer.

10. The power inductor as claimed in claim 8, wherein each of the insulating spacers protrudes beyond the edge of any of the outer loop circuit layers.

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