Electronic device and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- INNOLUX CORP
- Filing Date
- 2022-06-06
- Publication Date
- 2026-08-01
Smart Images
Figure TWG2TB001903553_001 
Figure TWG2TB001903553_002 
Figure TWG2TB001903553_003
Abstract
Description
Electronic Device and Method for Manufacturing the Same The present disclosure relates to an electronic device and a method for manufacturing the same, and more particularly to an electronic device including a first insulating layer and a second insulating layer and a method for manufacturing the same. Generally, a packaging process is performed on an electronic unit so that the electronic unit can resist contaminants in the external environment, avoid damage to the electronic unit caused by manual operation, achieve fixed functions and / or achieve heat dissipation functions, thereby improving the reliability and / or other electrical performance of the electronic unit. In the current packaging process, the above advantages of performing the packaging process are often achieved by providing a protective layer on the electronic unit. However, as the user's demand for electronic devices increases, the sizes of the electronic unit and its components are gradually reduced. Directly providing a protective layer on a small-sized electronic unit will cause many problems such as insufficient circuit design space, easy disconnection, easy short circuit, and easy generation of leakage current. Therefore, although the existing electronic devices and methods for manufacturing the same have gradually met their intended uses, they still do not completely meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding the electronic device and the method for manufacturing the same. In some embodiments, an electronic device is provided. The electronic device includes an electronic unit, a first insulating layer, a second insulating layer, and a connecting component. The first insulating layer is disposed between the second insulating layer and the electronic unit. The connecting component is electrically connected to the electronic unit, wherein the second insulating layer is disposed between the connecting component and the first insulating layer. Wherein, the thickness of the second insulating layer is greater than the thickness of the first insulating layer and the thermal expansion coefficients of the first insulating layer and the second insulating layer are different. In some embodiments, a method for manufacturing an electronic device is provided. The manufacturing method includes providing a substrate. The substrate includes a plurality of electronic units. Providing a first insulating layer on the plurality of electronic units. Providing a second insulating layer on the first insulating layer. Wherein, the thickness of the second insulating layer is greater than the thickness of the first insulating layer and the thermal expansion coefficients of the first insulating layer and the second insulating layer are different. The electronic device of the present disclosure can be applied to various types of electronic devices. To make the features and advantages of the present disclosure more obvious and understandable, various embodiments are specifically exemplified below and are described in detail in conjunction with the accompanying drawings as follows. The following provides a detailed description of the electronic devices in the embodiments of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simply and clearly describing some embodiments of the present disclosure. Of course, these are only for illustration and not for limiting the present disclosure. In addition, similar and / or corresponding component symbols may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding component symbols is only for simply and clearly describing some embodiments of the present disclosure, and does not represent any connection between the different embodiments and / or structures discussed. It should be understood that in each embodiment, relative terms may be used, for example, "lower" or "bottom" or "higher" or "top", to describe the relative relationship of one component of the figure to another component. It can be understood that if the device in the figure is flipped so that it is upside down, the component described on the "lower" side will become the component on the "higher" side. The embodiments of the present disclosure can be understood in conjunction with the figures, and the figures of the present disclosure are also regarded as part of the disclosure description. Furthermore, when it is mentioned that a first material layer is on or above a second material layer, it may include the case where the first material layer is in direct contact with the second material layer or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, when the first material layer is directly on the second material layer, it means that the first material layer is in direct contact with the second material layer. In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify components, and they do not themselves intend to imply or represent that the component(s) have any previous ordinal numbers, nor do they represent the order of one component and another component, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish a component with a certain name from another component with the same name. The same terms may not be used in the claims and the specification. For example, the first component in the specification may be the second component in the claims. In some embodiments of the present disclosure, terms related to joining and connecting, such as "connect", "interconnect", "join", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, and there are other structures disposed between these two structures. And these terms related to joining and connecting may also include the situation where both structures can move, or both structures are fixed. In addition, the term "electrically connected" or "electrically coupled" includes any direct and indirect electrical connection means. In the text, the terms "about", "approximately", and "substantially" generally mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meanings of "about", "approximately", and "substantially" can still be implied even without specifically stating "about", "approximately", or "substantially". The term "ranging from a first value to a second value" means that the range includes the first value, the second value, and other values therebetween. Furthermore, there may be a certain error between any two values or directions being compared. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction can range from 80 degrees to 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction can range from 0 degrees to 10 degrees. Furthermore, it should be understood that, according to the embodiments of the present disclosure, a scanning electron microscope (SEM), an optical microscope (OM), an α-step, an ellipsometer, or other suitable means can be used to measure the width, thickness, or height of each component, and the spacing or distance between components. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structure image of the components to be measured, and measure the width, thickness, height, or angle of each component, and the spacing or distance between components. Throughout the specification and claims of the present disclosure, certain terms are used to refer to specific components. Those of ordinary skill in the art should understand that electronic equipment manufacturers may use different names to refer to the same component. This document is not intended to distinguish components that have the same function but different names. In the following specification and claims, terms such as "comprising", "including", and "having" are open-ended terms, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the description of the present disclosure uses the terms "comprising", "including", and / or "having", it specifies the existence of corresponding features, regions, steps, operations, and / or components, but does not exclude the existence of one or more corresponding features, regions, steps, operations, and / or components. It should be understood that, without departing from the spirit of the present disclosure, the features in several different embodiments can be replaced, recombined, and combined to complete other embodiments in the following examples. As long as the features between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily combined and used. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that such terms, if defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure. In this document, the respective directions are not limited to the three axes such as the X-axis, Y-axis, and Z-axis of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, hereinafter, the X-axis direction is the first direction D1 (width direction), and the Z-axis direction is the second direction D2 (thickness direction). In some embodiments, the cross-sectional schematic diagrams described herein are schematic diagrams of observing the XZ plane. In this disclosure, the electronic device may include a display device, a lighting device, an antenna device, a sensing device, or a titling device, but is not limited thereto. The electronic device may be a foldable or flexible electronic device. The display device may be a non-self-emitting display device or a self-emitting display device. The antenna device may be an antenna device in a liquid crystal form or a non-liquid crystal form. The sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasonic waves, but is not limited thereto. In this disclosure, the electronic device may include electronic units. The electronic units are, for example, known good dies (KGDs) (i.e., known good wafers), semiconductor wafers, or diodes, but are not limited thereto. The electronic units may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diodes may include light-emitting diodes or photodiodes. The light-emitting diodes may, for example, include organic light-emitting diodes (OLEDs), mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), or quantum dot light-emitting diodes (quantum dot LEDs), but are not limited thereto. The titling device may be, for example, a display titling device or an antenna titling device, but is not limited thereto. It should be noted that the electronic device may be any permutation and combination of the foregoing, but is not limited thereto. Hereinafter, the electronic device including electronic units will be used to illustrate the content of this disclosure, but this disclosure is not limited thereto. In addition, the outer shape of the electronic device can be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device can have peripheral systems such as a processing system, a driving system, a control system, a light source system, a shelf system, etc. to support the electronic device or the splicing device. It should be noted that the electronic device can be any permutation and combination of the foregoing, but is not limited thereto. It should be understood that in some embodiments, additional operation steps can be provided before, during, and / or after the manufacturing method of the electronic device. In some embodiments, some of the described operation steps may be replaced or omitted, and the order of some of the operation steps is interchangeable. In addition, it should be understood that some of the described steps can be replaced or deleted for other embodiments of the method. In some embodiments, the manufacturing method of the electronic device disclosed herein is applicable to the chip first process and the redistribution layer first (RDL first) process. In some embodiments, the manufacturing method of the electronic device disclosed herein is applicable to the face up process and the face down process. For ease of explanation, hereinafter, the face down chip first process is taken as an example, but the present disclosure is not limited thereto. In addition, in the present disclosure, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of the present disclosure. Referring to FIG. 1, which is a cross-sectional schematic diagram of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 1, a substrate SB is provided, and the substrate SB includes a plurality of electronic units 10. In some embodiments, the substrate SB can be a wafer such as silicon, a semiconductor-on-insulator (SOI) substrate, other suitable substrates, or a combination of the foregoing, but the present disclosure is not limited thereto. The individual electronic units 10 are isolated from each other by a virtual line CL1, where the virtual line CL1 is, for example, a virtual first cutting line CL1, and in subsequent processes, a cutting process will be used to separate each electronic unit 10 and the remaining components formed subsequently along the virtual first cutting line CL1. In some embodiments, each of the plurality of electronic units 10 may include a light-emitting element such as a pixel, a light-emitting diode, or a photodiode; a conductive element such as a metal layer, a wire, a via, or a bonding pad; a driving element such as a transistor; a functional layer such as an insulating layer, an interlayer dielectric layer, a passivation layer, a planarization layer, or a dielectric material; other suitable components, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the electronic unit 10 may be a die, a chip unit, other suitable units, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the electronic unit 10 may include a bottom surface 10B (first surface), a top surface 10T (second surface) opposite to the bottom surface 10B, and a side surface 10S connecting the bottom surface 10B and the top surface 10T. In some embodiments, as shown in FIG. 1, the substrate SB may include at least two electronic units 10, but the present disclosure is not limited thereto. For example, the substrate SB may include any natural number greater than 2 of electronic units 10. In some embodiments, the electronic units 10 may be arranged in a matrix in the substrate SB. In some embodiments, each of the plurality of electronic units 10 may include a connection pad 12 for electrically connecting to other components. In some embodiments, the connection pad 12 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a semiconductor material, any other suitable conductive material, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the conductive material may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), its alloy or its compound, other suitable conductive materials, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the conductive material may include a transparent conductive oxide (TCO). For example, it may include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the connection pads 12 can be formed by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), other suitable deposition processes, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, a single electronic unit 10 can include a plurality of connection pads 12. For example, as shown in FIG. 1, a single electronic unit 10 can include four connection pads 12, but the present disclosure is not limited thereto. According to electrical requirements, the electronic unit 10 can include any natural number of connection pads 12. In some embodiments, for ease of illustration, FIG. 1 shows the top surface of the connection pads 12 flush with the top surface 10T of the electronic unit 10, but it is not limited thereto. The top surface of the connection pads 12 can be higher than the top surface 10T of the electronic unit 10. As shown in FIG. 1, in some embodiments, a first insulating layer 20 is provided on the substrate SB. In some embodiments, the first insulating layer 20 is provided on the top surface 10T of the electronic unit 10 such that the bottom surface 20B of the first insulating layer 20 contacts the top surface 10T of the electronic unit 10. In some embodiments, the first insulating layer 20 can be formed on the electronic unit 10 by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, other suitable deposition methods, or a combination of the foregoing. In some embodiments, the first insulating layer 20 can be or can include an organic material, an inorganic material, other suitable insulating materials, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the first insulating layer 20 can be or can include a polymer-based dielectric film such as an organic polymer film. In some embodiments, the first insulating layer 20 can be or can include an Ajinomoto Build-up Film (ABF), an epoxy resin, a silicone resin, a benzocyclobutene (BCB), a polyimide (PI) such as a photosensitive polyimide (PSPI), a polybenzoxazole (PBO), an oxide such as silicon oxide (SiO x )), a nitride such as silicon nitride (SiN x ) nitrides, such as silicon oxynitride (SiO x N y ) nitrogen oxides, other suitable capping materials, other suitable insulating materials, or combinations thereof, although the present disclosure is not limited thereto. In some embodiments, the first insulating layer 20 may be or may include a molding material. In some embodiments, a side surface 20S of the first insulating layer 20 is spaced apart from an outermost surface 10S of the plurality of electronic units 10 by a distance d. Specifically, referring to FIG. 1, which is a cross-sectional schematic view, the distance d is the width from the bottom of the side surface 20S of the first insulating layer 20 to the outermost surface 10S of the plurality of electronic units 10 in a first direction D1. In some embodiments, the side surface 20S of the first insulating layer 20 and the outermost surface 10S of the electronic unit 10 are not aligned in the first direction D1. In some embodiments, the area of the bottom surface 20B of the first insulating layer 20 is smaller than the area of the top surface 10T of the plurality of electronic units 10. In other words, the projection of the first insulating layer 20 onto the top surface 10T of the plurality of electronic units 10 may fall within the top surface 10T of the plurality of electronic units 10. In some embodiments, by providing the first insulating layer 20 with an area smaller than the top surface 10T of the plurality of electronic units 10, the cutting difficulty of the subsequent first cutting process can be reduced, and the margin of the first cutting process can be improved, but not limited thereto. In some embodiments, the side surface 20S of the first insulating layer 20 is an inclined side surface. In some embodiments, an angle a20 is formed between the side surface 20S of the first insulating layer 20 and the bottom surface 20B of the first insulating layer 20. In some embodiments, the angle a20 may be greater than or equal to about 45 degrees and less than about 90 degrees. For example, the angle a20 may be 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, 85 degrees, 89 degrees, or any value or range of values between the foregoing values. In some embodiments, since the side surface 20S of the first insulating layer 20 has the angle a20, it is beneficial to improve the adhesion and / or reliability between the component disposed above the first insulating layer 20 and the first insulating layer 20. Referring to FIG. 2, which is a schematic cross-sectional view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 2, the first insulating layer 20 is patterned to form first openings (or vias) 22 and 24, and a part of the top surface 10T of the electronic unit 10 is exposed. In some embodiments, the corresponding patterning process can be selected according to the material of the first insulating layer 20. For example, when the first insulating layer 20 is a photoresist material, the first insulating layer 20 can be patterned by an exposure process and a development process. For example, when the first insulating layer 20 is a non-photoresist material, the first insulating layer 20 can be patterned by laser drilling, or a photoresist pattern can be further additionally provided on the first insulating layer 20 to pattern the first insulating layer 20, or other suitable process methods can be adopted, but not limited thereto. In some embodiments, the first insulating layer 20 can be patterned according to the setting positions of the connection pads 12 on the electronic unit 10. For example, each of the plurality of connection pads 12 can correspond to a first opening 22, but the present disclosure is not limited thereto. In some embodiments, along the first direction D1, the width of the first opening 24 located between adjacent electronic units 10 can be greater than the width of the first opening 22, so as to facilitate separating the adjacent electronic units 10 from each other when performing the subsequent first cutting process. As shown in FIG. 2, the first opening 22 can have an angle a22. In some embodiments, the angle a22 can be greater than or equal to approximately 90 degrees and less than approximately 180 degrees. For example, the angle a22 can be 90 degrees, 100 degrees, 110 degrees, 120 degrees, 130 degrees, 140 degrees, 150 degrees, 160 degrees, 170 degrees, 179 degrees, or any value or value range between the foregoing values. In some embodiments, the angle a22 can be adjusted by adjusting the process parameters of the patterning process. Referring to FIG. 3, which is a schematic cross-sectional view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 3, a first conductive layer 30 is provided on a first insulating layer 20. In some embodiments, the material and formation method of the first conductive layer 30 may be the same as or different from those of the connection pad 12. In some embodiments, the first conductive layer 30 may be conformally formed on the first insulating layer 20 and the first conductive layer 30 extends into the first openings 22, 24. Then, the first conductive layer 30 may be patterned to expose a part of the top surface 10T of the electronic unit 10 and a part of the side surface 20S and the top surface 20T of the first insulating layer 20. For example, the first conductive layer 30 is conformally disposed and extends into the first openings 22, 24. According to some embodiments, the top surface of the first conductive layer 30 corresponding to the first openings 22, 24 may have a recess R. Further, in the second direction D2, the top surface of the first conductive layer 30 corresponding to the first openings 22, 24 is higher than the top surface 20T of the first insulating layer 20 and the top surface of the first conductive layer 30 corresponding to the first openings 22, 24 is lower than the top surface of the first conductive layer 30 corresponding to the first insulating layer 20. The first conductive layer 30 described in the present disclosure may be a single-layer conductive material or a multi-layer conductive material, and the first conductive layer 30 may include copper, titanium, aluminum, molybdenum, indium tin oxide, other suitable materials, or a combination of the foregoing, but is not limited thereto. In some embodiments, the patterned first conductive layer 30 may correspond to one of the plurality of first openings 22 in the first insulating layer 20. In other embodiments, the patterned first conductive layer 30 may correspond to a plurality of the first openings 22 in the first insulating layer 20. For example, the patterned first conductive layer 30 may correspond to two first openings 22. However, the present disclosure is not limited thereto, and the patterned first conductive layer 30 may correspond to any natural number of first openings 22 to improve the fan-out characteristics and / or fan-out range of the first conductive layer 30. Among them, the improvement of the fan-out characteristics may include increasing the number of components and bonding ability for bonding with other components, and the improvement of the fan-out range represents increasing the fan-out area to avoid space constraints in circuit design, but is not limited thereto. In some embodiments, the first conductive layer 30 may be between the first insulating layer 20 and a subsequently formed second insulating layer 40 (shown in FIG. 4). Through one of the plurality of first openings 22, the first conductive layer 30 is electrically connected to the connection pad 12 of the electronic unit 10. In some other embodiments, a seed layer (not shown) may be conformally formed on the first insulating layer 20 and within the first openings 22 and 24, and then a metal layer is formed on the seed layer. Materials of the seed layer and the metal layer may include, for example, titanium and copper, but are not limited thereto. Subsequently, the metal layer and the seed layer are patterned to remove a portion of the metal layer and a portion of the seed layer, thereby exposing a portion of the top surface 10T of the electronic unit 10. Referring to FIG. 4, which is a cross-sectional schematic view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 4, a second insulating layer 40 is provided on a substrate SB (as shown in FIG. 1). Specifically, the second insulating layer 40 is formed on the top surface 10T of the electronic unit 10, the top surface 20T and the side surface 20S of the first insulating layer 20, the first opening 24, and the first conductive layer 30. In some embodiments, the second insulating layer 40 may include a bottom surface 40B (the third surface), a top surface 40T (the fourth surface) opposite to the bottom surface 40B, and a side surface 40S (the second side surface) connecting the bottom surface 40B and the top surface 40T. In some embodiments, the top surface 40T of the second insulating layer 40 is farther from the electronic unit 10 than the bottom surface 40B of the second insulating layer 40. In some embodiments, the material and the formation method of the second insulating layer 40 may be the same as or different from those of the first insulating layer 20. In some embodiments, since the materials of the first insulating layer 20 and the second insulating layer 40 are different, the first insulating layer 20 and the second insulating layer 40 may substantially have an interface. Hereinafter, the case where the materials of the first insulating layer 20 and the second insulating layer 40 are different will be taken as an example for description. In some embodiments, as shown in FIG. 4, the first insulating layer 20 may have a first thickness T1, and the second insulating layer 40 may have a second thickness T2. In some embodiments, the first thickness T1 of the first insulating layer 20 is the distance between the bottom surface 20B and the top surface 20T of the first insulating layer 20 in the second direction D2. In some embodiments, the second thickness T2 of the second insulating layer 40 is the distance between the top surface 20T of the first insulating layer 20 and the top surface 40T of the second insulating layer 40 in the second direction D2. In some embodiments, the first thickness T1 of the first insulating layer 20 may be greater than or equal to approximately 2 um and less than or equal to approximately 10 um. For example, the first thickness T1 may be 2 um, 3 um, 4 um, 5 um, 6 um, 7 um, 8 um, 9 um, 10 um, any value or range of values between the foregoing values. In some embodiments, the second thickness T2 of the second insulating layer 40 may be greater than or equal to approximately 13 um and less than or equal to approximately 50 um. For example, the second thickness T2 may be 13 um, 15 um, 20 um, 25 um, 30 um, 35 um, 40 um, 45 um, 50 um, any value or range of values between the foregoing values. In some embodiments, the first thickness T1 of the first insulating layer 20 may be less than the second thickness T2 of the second insulating layer 40. In some embodiments, the ratio (T1 / T2) of the first thickness T1 of the first insulating layer 20 to the second thickness T2 of the second insulating layer 40 may be greater than or equal to approximately 0.02 to less than or equal to approximately 0.85. For example, the ratio (T1 / T2) may be 0.02, 0.04, 0.08, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.75, 0.8, 0.85, any value or range of values between the foregoing values. In some embodiments, since the first thickness T1 of the first insulating layer 20 may be less than the second thickness T2 of the second insulating layer 40, the connection pad 12 can be gradually fan - out by stacking the first insulating layer 20 and the second insulating layer 40. For example, the connection pad 12 can be initially fan - out by the first opening 22 of the first insulating layer 20, and then further fan - out by the second opening 42 (refer to FIG. 5 below) of the second insulating layer 40, thereby enhancing the fan - out effect and / or the fan - out range. In other embodiments, the electronic device can further dispose other insulating layers with openings between the top surface 10T of the electronic unit 10 and the subsequently formed connection component 60 (refer to FIG. 13 below), thereby enhancing the fan - out effect and / or the fan - out range. It should be particularly noted that since the first insulating layer 20 and the second insulating layer 40 can simultaneously serve as the protective layer of the electronic unit 10, the electronic unit 10 can be fully protected from damage. Furthermore, by sequentially disposing the first insulating layer 20 and the second insulating layer 40 on the electronic unit 10, the problems of easy cracking and / or edge warping of a single protective layer during the subsequent cutting process can be reduced. In addition, since the present disclosure stacks the first insulating layer 20 and the second insulating layer 40 multiple times, the problem of difficultly and accurately forming an opening penetrating the single insulating layer in a relatively thick single insulating layer can be avoided. It should be particularly noted that, as shown in FIGS. 3 and 4, since a part of the top surface 10T of the patterned first conductive layer 30 exposes the electronic unit 10, the bottom surface 40B of the second insulating layer 40 is in direct contact with the top surfaces 10T of the plurality of electronic units 10, so as to improve the reliability of the subsequent cutting process. For example, since there are fewer components intersecting the virtual first cutting line CL1 described below, problems such as uneven cutting edges, cracking, and / or warping can be reduced after cutting along the virtual first cutting line CL1. In some embodiments, as shown in FIG. 4, the second insulating layer 40 is in direct contact with the side surface 20S of the first insulating layer 20. In some embodiments, since the inclined side surface 20S of the first insulating layer 20 has the above-mentioned angle a20, the first insulating layer 20 and the second insulating layer 40 can be more easily joined. Furthermore, when the materials of the first insulating layer 20 and the second insulating layer 40 are different, the angle a20 can disperse the stress between the heterogeneous interfaces of the first insulating layer 20 and the second insulating layer 40 and / or improve the reliability of the heterogeneous interfaces of the first insulating layer 20 and the second insulating layer 40. In some embodiments, the coefficients of thermal expansion (CTEs) of the first insulating layer 20 and the second insulating layer 40 can be the same or different. In some embodiments, the coefficients of thermal expansion of the first insulating layer 20 and / or the second insulating layer 40 can be greater than or equal to approximately 3 ppm / K to less than or equal to approximately 60 ppm / K. For example, the coefficients of thermal expansion of the first insulating layer 20 and / or the second insulating layer 40 can be 3 ppm / K, 5 ppm / K, 10 ppm / K, 15 ppm / K, 20 ppm / K, 25 ppm / K, 30 ppm / K, 35 ppm / K, 40 ppm / K, 45 ppm / K, 50 ppm / K, 55 ppm / K, 60 ppm / K, any value or value range between the foregoing values. In some embodiments, when the coefficients of thermal expansion of the first insulating layer 20 and the second insulating layer 40 are different, the warping degree of the electronic device can be reduced. In some embodiments, the coefficient of thermal expansion of the first insulating layer 20 is less than that of the second insulating layer 40, so the effect of reducing the warping of the electronic device can be achieved, but not limited thereto. In some embodiments, the first insulating layer 20 and the second insulating layer 40 can be reverse warping layers with respect to each other. In other words, because the warping directions of the first insulating layer 20 and the second insulating layer 40 are different, the warping phenomenon can be offset from each other, thereby reducing the warping degree of the electronic device. For example, the first insulating layer 20 can be an insulating layer warping upward (with the opening upward) in the second direction D2, and the second insulating layer 40 can be an insulating layer warping downward (with the opening downward) away from the second direction D2. Therefore, when the combination of the first insulating layer 20 and the second insulating layer 40 is provided, the warping that can be offset from each other can be achieved. In some embodiments, the Young's modulus of the first insulating layer 20 and / or the second insulating layer 40 can be greater than or equal to about 1000 MPa and less than or equal to about 20000 MPa. For example, the Young's modulus of the first insulating layer 20 and / or the second insulating layer 40 can be 1000 MPa, 2000 MPa, 4000 MPa, 6000 MPa, 8000 MPa, 10000 MPa, 12000 MPa, 14000 MPa, 16000 MPa, 18000 MPa, 20000 MPa, any value or value range between the foregoing values. In some embodiments, the Young's modulus of the first insulating layer 20 is less than that of the second insulating layer 40. Therefore, forming the second insulating layer 40 on the top surface 10T of the electronic unit 10, the top surface 20T and the side surface 20S of the first insulating layer 20, the first opening 24, and the first conductive layer 30 can avoid or reduce the risk of damage such as scratching to the electronic unit 10, the first insulating layer 20, or the first conductive layer 30, but not limited thereto. In some embodiments, since the water and oxygen resistance characteristics of the second insulating layer 40 can be superior to those of the first insulating layer 20, the water and oxygen resistance characteristics of the electronic device disclosed herein can be further improved by providing the second insulating layer 40. In some embodiments, since the hardness of the second insulating layer 40 can be greater than that of the first insulating layer 20, the hardness of the electronic device disclosed herein can be further improved by providing the second insulating layer 40. In these embodiments, even if the water and oxygen resistance characteristics and / or the hardness of the first insulating layer 20 are slightly lower than those of the second insulating layer 40, the first insulating layer 20 can be accurately and easily formed on the electronic unit 10 and helps to form the first opening 22. Therefore, the combination of the first insulating layer 20 and the second insulating layer 40 can effectively improve various characteristics of the electronic device. In some embodiments, since the first thickness T1 of the first insulating layer 20 is less than the second thickness T2 of the second insulating layer 40, the first insulating layer 20 may include PSPI that is more conducive to performing an accurate patterning process, and the second insulating layer 40 may include ABF, so as to improve the fan-out effect and / or fan-out range through the thickness ratio and material selection between the first insulating layer 20 and the second insulating layer 40. Referring to FIG. 5, which is a cross-sectional schematic diagram of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 5, the second insulating layer 40 is patterned to form a second opening 42, and the top surface of the first conductive layer 30 is exposed. In some embodiments, the second opening 42 may have an angle a42. In some embodiments, the angle a42 may be greater than or equal to 90 degrees and less than 180 degrees. For example, the angle a42 may be 90 degrees, 100 degrees, 110 degrees, 120 degrees, 130 degrees, 140 degrees, 150 degrees, 160 degrees, 170 degrees, 179 degrees, or any value or range of values between the foregoing values. In some embodiments, the angle a42 can be adjusted by adjusting the process parameters of the patterning process. In some embodiments, the angle a22 of one of the plurality of first openings 22 is different from the angle a42 of one of the plurality of second openings 42. In some embodiments, the angle a22 of the first opening 22 is greater than the angle a42 of the second opening 42. For example, this can enable the heat energy generated by the electronic unit 10 to be quickly导出, but not limited thereto. In some embodiments, the roughness of the first sidewall 22S of one of the plurality of first openings 22 may be less than that of the second sidewall 42S of one of the plurality of second openings 42. In the present disclosure, the roughness can be surface roughness, and can be obtained by, for example, arithmetic mean roughness (Ra), maximum height (Ry), ten-point mean roughness (Rz), other similar measurement methods, or a combination of the foregoing. In some embodiments, since the first thickness T1 of the first insulating layer 20 may be less than the second thickness T2 of the second insulating layer 40, the thickness of the conductive component (for example, the first conductive layer 30) disposed in the first opening 22 of the first insulating layer 20 is correspondingly less than the thickness of the conductive component (for example, the subsequent connection element 60) disposed in the second opening 42 of the second insulating layer 40. Therefore, when the roughness of the first sidewall 22S of the first opening 22 is small, thus having a relatively smooth sidewall, it helps to accurately form the first conductive layer 30 in the first opening 22, thereby improving the reliability of the first conductive layer 30. In addition, since the first thickness T1 of the first insulating layer 20 is less than the second thickness T2 of the second insulating layer 40, the formation accuracy of the first opening 22 is greater than the formation accuracy of the second opening 42. On the other hand, when the roughness of the second sidewall 42S of the second opening 42 is relatively large, resulting in a relatively uneven sidewall, the frictional force of the rough sidewall can help form a connection element 60 with a relatively large thickness and / or width in the second opening 42, thereby improving the reliability of the connection element 60. For example, it can improve the reliability of forming the connection element 60 by means of an electroplating process subsequently. In some embodiments, at least one of the plurality of first openings 22 and at least one of the plurality of second openings 42 do not overlap in the normal direction of the electronic unit 10 (i.e., the second direction D2), so as to improve the fan-out effect and / or fan-out range or reduce the risk of cracking of the metal layer of the electronic device, but not limited thereto. In some other embodiments, each of the plurality of first openings 22 and each of the plurality of second openings 42 do not overlap in the normal direction of the electronic unit 10 (i.e., the second direction D2). In some embodiments, at least one of the plurality of first openings 22 and at least one of the plurality of second openings 42 overlap in the normal direction of the electronic unit 10 (i.e., the second direction D2), thereby increasing the margin for performing the patterning process of the second insulating layer 40. In some other embodiments, each of the plurality of first openings 22 and each of the plurality of second openings 42 overlap in the normal direction of the electronic unit 10 (i.e., the second direction D2). In some embodiments, following the above, a first cutting process may be performed to cut the substrate SB so that the plurality of electronic units 10 are separated into a plurality of first electronic devices. In some embodiments, the first cutting process may include a blade saw process, a die break dicing process, a laser cutting process, other suitable cutting processes, or a combination of the foregoing. As shown in FIG. 5, the first cutting process may be performed along the virtual first cutting line CL1. Referring to FIG. 6, which is a cross-sectional schematic view of the first electronic device 1 after the first cutting process according to some embodiments of the present disclosure. In some embodiments, the first electronic device 1 may be a known good die (KGD), and the first electronic device 1 may include a first conductive layer 30 that can serve as a redistribution layer for wafer-level packaging. As shown in FIG. 6, after the first cutting process, the side surface 10S of the electronic unit 10 of the first electronic device 1 is aligned with the side surface 40S of the second insulating layer 40, so that the second insulating layer 40 protects the electronic unit 10 of the first electronic device 1. That is, in the first direction D1, the distance between the side surface 10S of the electronic unit 10 and the side surface 40S of the second insulating layer 40 is less than or equal to 5 micrometers. Through the alignment design of the side surface 10S of the electronic unit 10 and the side surface 40S of the second insulating layer 40, it will be beneficial to the subsequent process quality. In addition, it should be understood that, for clarity of illustration, some components of the first electronic device 1 are omitted in FIG. 6, and some components are schematically illustrated. In some embodiments, additional components may be added to the first electronic device 1 described above. In other embodiments, some components of the first electronic device 1 described above may be replaced or omitted. Referring to FIG. 7, which shows a cross-sectional schematic view of the second electronic device 2 in an intermediate manufacturing stage according to some embodiments of the present disclosure. As shown in FIG. 7, a plurality of first electronic devices 1 are provided on a first carrier substrate CP1. For ease of illustration, two first electronic devices 1 are shown provided on the first carrier substrate CP1 in FIG. 7, but the present disclosure is not limited thereto. Specifically, in some embodiments, as shown in FIG. 7, a first carrier substrate CP1 is provided, and a first adhesive layer AL1 is disposed on the first carrier substrate CP1. In some embodiments, the first carrier substrate CP1 may be or may include a wafer, a chip, glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET) substrate, polypropylene (PP) substrate, a temporary substrate, other suitable substrates, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the first adhesive layer AL1 may serve as a peeling layer or a release layer. In some embodiments, the first adhesive layer AL1 may be or may include a thermal release adhesive, an ultraviolet (UV) adhesive layer, a light-to-heat conversion (LTHC) adhesive layer, other suitable cleavage-type adhesive layers, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the first adhesive layer AL1 may be formed by a coating process or other suitable forming processes. Then, the first electronic device 1 shown in FIG. 6 is turned upside down along the second direction D2, such that the top surface 40T of the second insulating layer 40 of the first electronic device 1 is in direct contact with and bonded to the first adhesive layer AL1. As shown in FIG. 7, in some embodiments, a third insulating layer 50 is provided on a plurality of first electronic devices 1. In some embodiments, the third insulating layer 50 may surround the electronic units 10 in the first electronic device 1. For example, the third insulating layer 50 may surround the side surface 10S and the bottom surface 10B of the electronic unit 10. In some embodiments, the third insulating layer 50 may be disposed on the first adhesive layer AL1 and between adjacent first electronic units 10. In some embodiments, the third insulating layer 50 may be disposed on the side surface 40S of the second insulating layer 40, the side surface 10S of the electronic unit 10, and the bottom surface 10B of the electronic unit 10. In some embodiments, the third insulating layer 50 may expose a part of the side surface 40S of the second insulating layer 40 and / or a part of the side surface 10S of the electronic unit 10. By aligning the side surface 10S of the electronic unit 10 with the side surface 40S of the second insulating layer 40, for example, the risk of cracking of the side surface 10S, the side surface 40S, and the third insulating layer 50 can be reduced, but not limited thereto. In some embodiments, the third insulating layer 50 may be or may include an organic material, an inorganic material, other suitable encapsulation materials, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the foregoing inorganic materials may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the foregoing organic materials may include epoxy resin, silicone resin, acrylic resins, other suitable materials, or a combination of the foregoing, but the present disclosure is not limited thereto. For example, the foregoing acrylic resins may include polymethylmetacrylate (PMMA), benzocyclobutene (BCB), polyimide, polyester, polydimethylsiloxane (PDMS), polyfluoroalkoxy (PFA). In some embodiments, the third insulating layer 50 may include ABF. In some embodiments, the third insulating layer 50 may be a light-transmitting, semi-light-transmitting, or light-impermeable material. In some embodiments, as shown in FIG. 7, the third insulating layer 50 may have a fifth thickness T5. In some embodiments, the fifth thickness T5 may be the distance between the top surface 50T and the bottom surface 50B of the third insulating layer 50. In some embodiments, the fifth thickness T5 of the third insulating layer 50 may be greater than the second thickness T2 of the second insulating layer 40. In some embodiments, the fifth thickness T5 of the third insulating layer 50 may be greater than the first thickness T1 of the first insulating layer 20. In some embodiments, the fifth thickness T5 of the third insulating layer 50 may be greater than the sum of the second thickness T2 of the second insulating layer 40 and the first thickness T1 of the first insulating layer 20. Referring to FIG. 8, which shows a cross-sectional schematic view of the second electronic device 2 in an intermediate manufacturing stage according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 8, a second carrier plate CP2 is provided, and a second adhesive layer AL2 is disposed on the second carrier plate CP2. In some embodiments, the material of the second carrier plate CP2 may be the same as or different from the material of the first carrier plate CP1. In some embodiments, the material and formation method of the second adhesive layer AL2 may be the same as or different from the material and formation method of the first adhesive layer AL1. Then, the structure shown in FIG. 7 is turned upside down along the second direction D2, such that the bottom surface 50B of the third insulating layer 50 is in direct contact with and bonded to the second adhesive layer AL2. Referring to FIG. 9, which shows a cross-sectional schematic view of the second electronic device 2 in an intermediate manufacturing stage according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 9, according to the material of the first adhesive layer AL1, a corresponding cleavage process may be used to release or remove the first adhesive layer AL1 and the first carrier plate CP1, thereby exposing the top surface 50T of the third insulating layer 50. Referring to FIG. 10, which shows a cross-sectional schematic view of the second electronic device 2 in an intermediate manufacturing stage according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 10, a first photoresist 52 is formed on the top surface 50T of the third insulating layer 50 and the top surface 40T of the second insulating layer 40. In some embodiments, the first photoresist 52 can be formed by a spin coating process, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition (ALD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, other suitable methods, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first photoresist 52 can be a dry film photoresist. In some embodiments, the first photoresist 52 can have an opening 53, and the opening 53 corresponds to the second opening 42 of the second insulating layer 40 to expose at least a portion of the top surface of the first conductive layer 30. In some embodiments, one opening 53 of the first photoresist 52 can correspond to one of the second openings 42 of the second insulating layer 40, but the present disclosure is not limited thereto. Referring to FIG. 11, which shows a cross-sectional schematic view of the second electronic device 2 in an intermediate manufacturing stage according to some embodiments of the present disclosure. In some embodiments, a second conductive layer 62 is disposed in the opening 53 of the first photoresist 52. In some embodiments, the second conductive layer 62 can be disposed on the top surface 50T of the third insulating layer 50 and the top surface 40T of the second insulating layer 40. In some embodiments, a portion of the second conductive layer 62 is in contact with the top surface 50T of the third insulating layer 50. In some embodiments, the second conductive layer 62 can include a conductive material. For example, the conductive material can include a metal, a metal nitride, a semiconductor material, or a combination thereof, or any other suitable conductive material, but the present disclosure is not limited thereto. In some embodiments, the conductive material can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), its alloy, its compound, other suitable conductive materials, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the second conductive layer 62 can be formed by, for example, electroplating, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, other suitable deposition methods, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the first conductive layer 30 may have a third thickness T3 in the second direction D2. As shown in FIG. 11, the third thickness T3 of the first conductive layer 30 may be between the bottom surface of the second conductive layer 62 and the top surface 20T of the first insulating layer 20. In some embodiments, the second conductive layer 62 may have a fourth thickness T4 in the second direction D2. As shown in FIG. 11, the fourth thickness T4 of the second conductive layer 62 may be the thickness of the second conductive layer 62 located on the third insulating layer 50. In some embodiments, since the first conductive layer 30 may be a conductive layer in a Wafer Level Package (WLP) process and the second conductive layer 62 may be a conductive layer in a Panel Level Package (PLP) process, the fourth thickness T4 of the second conductive layer 62 may be greater than the third thickness T3 of the first conductive layer 30. In some embodiments, the second conductive layer 62 may include a multi-layer structure, where the multi-layer structure may include a seed layer and a metal layer. For example, a seed layer (not shown) may be conformally formed first on the top surface 50T of the third insulating layer 50, the top surface of the second insulating layer 40, and in the second opening 42. Then, a metal layer (not shown) is formed on the seed layer to enhance the reliability of the metal layer by means of the seed layer. In some embodiments, the seed layer and the metal layer may be formed by physical vapor deposition (PVD), electroplating, or other suitable forming processes, but the present disclosure is not limited thereto. In some embodiments, the seed layer may be a titanium copper alloy (TiCu), and the metal layer may include copper. Referring to FIG. 12, which shows a cross-sectional schematic view of the second electronic device 2 in an intermediate manufacturing stage according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 12, a second photoresist 54 is formed on the first photoresist 52. Specifically, the second photoresist 54 may be formed on the top surfaces of the first photoresist 52 and the second conductive layer 62. In some embodiments, the material and formation method of the second photoresist 54 may be the same as or different from those of the first photoresist 52. In some embodiments, the second photoresist 54 may be a dry film photoresist. In some embodiments, the second photoresist 54 may have an opening 55, and the opening 55 corresponds to the second conductive layer 62 to expose at least a portion of the top surface of the second conductive layer 62 through the opening 55 of the second photoresist 54. Referring to FIG. 13, which shows a cross-sectional schematic view of the second electronic device 2 in an intermediate manufacturing stage according to some embodiments of the present disclosure. In some embodiments, a third conductive layer 64 is disposed in the opening 55 of the second photoresist 54. In some embodiments, the material and formation method of the third conductive layer 64 may be the same as or different from the material and formation method of the third conductive layer 64. In some embodiments, the third conductive layer 64 and the second conductive layer 62 may have an interface. In other embodiments, the third conductive layer 64 and the second conductive layer 62 may substantially not have an interface. In some embodiments, the third conductive layer 64 may also include a seed layer and a metal layer to improve the reliability of the metal layer by means of the seed layer. In some embodiments, in the second direction D2, the thickness of the third conductive layer 64 may be greater than that of the second conductive layer 62. Referring to FIG. 14, which shows a cross-sectional schematic view of the second electronic device 2 in an intermediate manufacturing stage according to some embodiments of the present disclosure. In some embodiments, the second photoresist 54 and the first photoresist 52 are removed to expose the top surface 40T of the second insulating layer 40. In some embodiments, the second photoresist 54 and the first photoresist 52 may be removed by an ashing process, other suitable removal processes, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the second photoresist 54 and the first photoresist 52 may be removed in the same process. In other embodiments, the second photoresist 54 and the first photoresist 52 may be removed separately in different processes. In some embodiments, due to the selectivity of the removal process, the removal process substantially does not damage the structures of the third conductive layer 64 and the second conductive layer 62. In some embodiments, the third conductive layer 64 and the second conductive layer 62 may jointly serve as a connection element 60 disposed on the second insulating layer 40. In other words, the connection element 60 may include, for example, the second conductive layer 62 and the third conductive layer 64. In some embodiments, the connection element 60 may serve as a redistribution line element of an electronic device in a panel-level process. In some embodiments, the connection element 60 is connected to the connection pad 12 of the electronic unit 10 through the first conductive layer 30. In some embodiments, since the third conductive layer 64 is in direct contact and electrical connection with the second conductive layer 62, the second conductive layer 62 is in direct contact and electrical connection with the first conductive layer 30, and the first conductive layer 30 is in direct contact and electrical connection with the connection pad 12, the fan-out effect and / or the fan-out range can be effectively improved. Referring to FIG. 15, which shows a cross-sectional schematic view of the second electronic device 2 in an intermediate manufacturing stage according to some embodiments of the present disclosure. In some embodiments, a fourth insulating layer 70 is provided on the connecting element 60, the third insulating layer 50, and the second insulating layer 40. In some embodiments, the fourth insulating layer 70 covers the side surfaces of the connecting element 60. In some embodiments, the fourth insulating layer 70 is in direct contact with the third insulating layer 50 and the second insulating layer 40. In some embodiments, the material and formation method of the fourth insulating layer 70 may be the same as or different from those of the third insulating layer 50. In some embodiments, the fourth insulating layer 70 and the third insulating layer 50 may have an interface. In other embodiments, the fourth insulating layer 70 and the third insulating layer 50 may substantially have no interface. In some embodiments, the hardness of the third insulating layer 50 and / or the fourth insulating layer 70 is different from that of the first insulating layer 20 and / or the second insulating layer 40. For example, the hardness of the third insulating layer 50 and / or the fourth insulating layer 70 may be greater than that of the first insulating layer 20 and / or the second insulating layer 40. Next, in some embodiments, a second cutting process may be performed to separate the plurality of first electronic devices 1 into a plurality of second electronic devices 2. In some embodiments, the second cutting process and the first cutting process may be the same or different. As shown in FIG. 15, the second cutting process may be performed along the virtual second cutting line CL2. In other embodiments, the fourth insulating layer 70 may include a first sub-insulating layer and a second sub-insulating layer formed in different processes. In this embodiment, continuing with FIG. 9, a patterned first sub-insulating layer may be first formed on the third insulating layer 50. Then, a second conductive layer 62 is formed in the openings of the first sub-insulating layer and on the third insulating layer 50 and the second insulating layer 40. Then, a patterned second sub-insulating layer is formed on the patterned first sub-insulating layer. After that, a third conductive layer 64 is formed in the openings of the second sub-insulating layer and on the third conductive layer 64 on the second conductive layer 62, thereby obtaining the connecting element 60. Referring to FIG. 16, which shows a schematic cross-sectional view of the second electronic device 2 after the second cutting process according to some embodiments of the present disclosure. As shown in FIG. 16, in the first direction D1, the side surface 50S of the third insulating layer 50 of the second electronic device 2 is aligned with the side surface 70S of the fourth insulating layer 70 to protect the electronic unit 10 of the second electronic device 2 by means of the fourth insulating layer 70 and the third insulating layer 50. As shown in FIG. 16, in some embodiments, a connection pad 66 may be further provided on the third conductive layer 64. Therefore, the second electronic device 2 can be electrically connected to a printed circuit board (PCB) or other components through the connection pad 66. In some embodiments, the material and formation method of the connection pad 66 may be the same as or different from those of the connection pad 12. The redistribution layer of the second electronic device 2 is formed by alternately stacking the second conductive layer 62, the third conductive layer 64 and the fourth insulating layer 70, improving the fan out characteristics and / or fan out range of the electronic device. In summary, according to the embodiments of the present disclosure, an electronic device including a first insulating layer and a second insulating layer and a manufacturing method thereof are provided to avoid problems such as limited circuit design space for vias, wires, redistribution layers, etc. by setting the insulating layers in batches. In addition, by adjusting the thickness ratio and / or material properties (e.g., material type, coefficient of thermal expansion, warping direction) of the first insulating layer and the second insulating layer, the fan out characteristics and / or fan out range of the electronic device are improved, the compatibility with the fine line diameter process is improved, the warpage probability is reduced, the reliability and / or the electrical performance are improved. Furthermore, the electronic device and the manufacturing method of the present disclosure can also be compatible with the prior wafer process and the prior redistribution layer process. Components between the embodiments of the present disclosure can be arbitrarily mixed and used as long as they do not violate the inventive spirit or conflict with each other. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the technical field can understand the processes, machines, manufactures, compositions of matter, devices, methods and steps developed currently or in the future from the disclosure of the present disclosure. As long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the protection scope of the present disclosure includes the above processes, machines, manufactures, compositions of matter, devices, methods and steps. Any embodiment or claim scope of the present disclosure does not have to achieve all the purposes, advantages and / or features disclosed in the present disclosure. The foregoing outlines several embodiments so that those of ordinary skill in the art to which this disclosure pertains can better understand the viewpoints of the embodiments of this disclosure. Those of ordinary skill in the art to which this disclosure pertains should understand that they can design or modify other processes and structures based on the embodiments of this disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those of ordinary skill in the art to which this disclosure pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure. 1: First electronic device 10: Electronic unit 10B, 20B, 40B, 50B: Bottom surface 10T, 20T, 40T, 50T: Top surface 10S, 20S, 40S, 50S, 70S: Side surface 12, 66: Connection pad 2: Second electronic device 20: First insulating layer 22, 24: First opening 22S: First side wall 30: First conductive layer 40: Second insulating layer 42: Second opening 42S: Second side wall 50: Third insulating layer 52: First photoresist 53, 55: Opening 54: Second photoresist 60: Connection element 62: Second conductive layer 64: Third conductive layer 70: Fourth insulating layer AL1: First adhesive layer AL2: Second adhesive layer a20, a22, a42: Angle CL1: First cutting line CL2: Second cutting line CP1: First carrier plate CP2: Second carrier plate d: Distance D1: First direction D2: Second direction R: Recess SB: Substrate T1: First thickness T2: Second thickness T3: Third thickness T4: Fourth thickness T5: Fifth thickness When read in conjunction with the accompanying drawings, this disclosure can be more fully understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, for clarity, the dimensions of the various features may be arbitrarily enlarged or reduced. FIGS. 1 to 6 are respectively cross-sectional schematic views showing the first electronic device 1 at different manufacturing stages according to some embodiments of this disclosure. FIGS. 7 to 16 are respectively cross-sectional schematic views showing the second electronic device 2 at different manufacturing stages according to some embodiments of this disclosure. 1: First electronic device 10: Electronic unit 10B,40B: Bottom surface 10T,40T: Top surface 10S,20S,40S: Side surface 12: Connection pad 20: First insulating layer 30: First conductive layer 40: Second insulating layer 42: Second opening D1: First direction D2: Second direction T1: First thickness T2: Second thickness T3: Third thickness
Claims
1. An electronic device comprising: One electronic unit; First insulating layer; A second insulating layer, wherein the first insulating layer is disposed between the second insulating layer and the electronic unit; And a connecting element electrically connected to the electronic unit, wherein the second insulating layer is disposed between the connecting element and the first insulating layer, wherein the thickness of the second insulating layer is greater than the thickness of the first insulating layer, the ratio of the thickness of the first insulating layer to the thickness of the second insulating layer is greater than or equal to 0.04 and less than or equal to 0.4, and the coefficients of thermal expansion of the first insulating layer and the second insulating layer are different.
2. The electronic device as claimed in claim 1, further comprising: A first conductive layer is disposed between the first insulating layer and the second insulating layer.
3. The electronic device as claimed in claim 2, wherein the first insulating layer includes a first opening, and the first conductive layer is electrically connected to the electronic unit through the first opening.
4. The electronic device as claimed in claim 3, further comprising: A second conductive layer, wherein the second insulating layer is disposed between the first conductive layer and the second conductive layer.
5. The electronic device as claimed in claim 4, wherein the second insulating layer includes a second opening, and the second conductive layer is electrically connected to the first conductive layer through the second opening.
6. The electronic device as claimed in claim 5, wherein the angle of the first opening is different from the angle of the second opening.
7. The electronic device as claimed in claim 5, wherein the first opening has a first sidewall, the second opening has a second sidewall, and the roughness of the first sidewall is different from the roughness of the second sidewall.
8. The electronic device as claimed in claim 7, wherein the roughness of the first sidewall is less than the roughness of the second sidewall.
9. A method for manufacturing an electronic device, comprising: A substrate is provided, and the substrate includes a plurality of electronic units; A first insulating layer is provided on the plurality of electronic units; The first insulating layer is provided on the first insulating layer, wherein the thickness of the second insulating layer is greater than the thickness of the first insulating layer, the ratio of the thickness of the first insulating layer to the thickness of the second insulating layer is greater than or equal to 0.04 and less than or equal to 0.4, and the coefficients of thermal expansion of the first insulating layer and the second insulating layer are different.
10. The method of manufacturing an electronic device as described in claim 9, further comprising: A first conductive layer is provided between the first insulating layer and the second insulating layer.
11. A method of manufacturing an electronic device as claimed in claim 10, wherein the first insulating layer includes a first opening, and the first conductive layer is electrically connected to the electronic unit through the first opening.
12. The method of manufacturing an electronic device as described in claim 11 further comprises: A second conductive layer is provided, wherein the second insulating layer is disposed between the first conductive layer and the second conductive layer.
13. A method of manufacturing an electronic device as claimed in claim 12, wherein the second insulating layer includes a second opening, and the second conductive layer is electrically connected to the first conductive layer through the second opening.
14. A method of manufacturing an electronic device as claimed in claim 13, wherein the angle of the first opening is different from the angle of the second opening.
15. A method of manufacturing an electronic device as claimed in claim 13, wherein the first opening has a first sidewall, the second opening has a second sidewall, and the roughness of the first sidewall is different from the roughness of the second sidewall.
16. A method of manufacturing an electronic device as claimed in claim 15, wherein the roughness of the first sidewall is less than the roughness of the second sidewall.