Semiconductor device and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2024-06-04
- Publication Date
- 2026-08-01
Smart Images
Figure TWG2TB001903562_001 
Figure TWG2TB001903562_002 
Figure TWG2TB001903562_003
Abstract
Description
Semiconductor device and method for manufacturing the same none Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon. The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that must be addressed. none The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. In addition, the various tasks and processes described herein may be incorporated into more comprehensive programs or processes having additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well known, and therefore, for the sake of brevity, many conventional processes will be only briefly mentioned herein or will be omitted entirely without providing well-known process details. As will be apparent to those skilled in the art after a thorough reading of this disclosure, the structures disclosed herein can be employed with a variety of technologies and can be incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include a varying number of components, and that a single component shown in the figures may represent multiple components. Additionally, for ease of description, spatially relative terms, such as "over," "overlying," "above," "upper," "top," "below," "underlying," "beneath," "lower," "bottom," and the like, may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly. When spatially relative terms, such as those listed above, are used to describe a first element relative to a second element, the first element can be directly on the other element, or intervening elements or layers may be present. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate the relationship between the various embodiments and / or configurations discussed. It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," "example," etc., indicate that the embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to be able to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described. It will be understood that the phrases or terms herein are for the purpose of description rather than limitation, and thus the terms or phrases of this specification are to be interpreted by those skilled in the art based on the teachings herein. The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Throughout the description herein, unless otherwise specified, the same reference numerals in different figures refer to the same or similar components formed by the same or similar methods using the same or similar materials. Semiconductor image sensors are used to sense incident visible or invisible radiation, such as visible light and infrared light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications, such as digital still cameras, mobile phones, tablet computers, and eyewear. These image sensors utilize an array of pixels to absorb (e.g., sense) incident radiation and convert it into an electrical signal. One example of an image sensor is a backside illuminated (BSI) image sensor, which detects radiation from the "backside" of the BSI image sensor's substrate. A backside illuminated (BSI) image sensor is a type of CIS device. A BSI image sensor includes a pixel region formed on a substrate (e.g., a semiconductor substrate) and having a pixel array or radiation-sensing area. The terms "radiation-sensing area" and "pixel" are used interchangeably throughout this disclosure. Pixels are used to convert photons from incident radiation into electrical signals. These signals are then distributed to processing components attached to the BSI image sensor. For this reason, the pixel region is covered with interconnect structures in multiple metallization layers that distribute the electrical signals generated within the pixels to the appropriate processing components. The multiple metallization layers are formed on a first surface of the substrate, referred to as the "front" surface of the substrate. The pixel region is formed on a second surface of the substrate, opposite the front surface. This second surface of the substrate is referred to herein as the "back" surface of the substrate. The pixel region includes a grid structure that provides optical isolation between adjacent pixels. Furthermore, the pixel region includes a color filter layer. The material of the color filter layer can be selected so that light of a desired wavelength passes through the color filter layer, while light of other wavelengths is absorbed by the color filter layer. Components of a BSI image sensor (e.g., pixels, transistors, capacitors, memory structures, or other chips attached to the BSI image detector) can be electrically coupled to external devices (e.g., external circuitry) via wire connectors attached to pad structures formed on the rear surface of the substrate. To achieve this, the pad structures of the BSI image sensor extend from the rear surface of the substrate to the front surface of the substrate and are electrically connected to interconnect structures within the multiple metallization layers of the BSI image sensor. Thus, the interconnect structures within the multiple metallization layers that provide electrical signal connections to the BSI image sensor can be electrically connected to external devices or circuitry via the pad structures. The pad structures can be disposed around the perimeter of the BSI image sensor surrounding the pixel region. Achieving high device reliability is a challenge for BSI image sensors. The device reliability of BSI image sensors can be negatively impacted by stress buildup during manufacturing operations. In a BSI image sensor, a pad structure can be constructed by forming a first cavity portion that terminates at a contact pad opening at a shallow trench isolation (STI) region in a substrate, followed by forming a second cavity portion that extends through the substrate and interlayer dielectric (ILD) layer to the interconnect structure. During pixel construction, silicon (Si) dislocations in the STI region of the substrate can lead to crystal defects due to stress buildup caused by chemical mechanical polishing (CMP) operations, negatively impacting manufacturing yield. According to some embodiments of the present disclosure, the first cavity portion of the contact pad opening extends into the ILD layer rather than terminating in the STI region of the substrate. As a result, an STI region is not required, and crystal defects caused by Si dislocations in the STI region are avoided. Several intermediate stages in the fabrication of an image sensor device are illustrated. Variations of the embodiments are also discussed. Throughout the various figures and illustrative embodiments, the same reference numerals are used to denote the same elements. FIG1 depicts a schematic cross-sectional view of an example portion of an example CIS device 100. The example CIS device 100 includes a CIS system-on-a-chip (SOC) 102 and a carrier substrate, such as an application-specific integrated circuit (ASIC) 104. The example CIS device 100, including the CIS SOC 102 and the ASIC 104, has a plurality of regions, including a pixel array region 106, a peripheral region 108 laterally surrounding the pixel array region 106 (such as a black level correction (BLC) region), and a contact pad (PAD) region 110. The example CIS device 100 may further include other regions, such as, for example, alignment regions, such as a scribe-line primary mark (SPM) region, which are not explicitly shown because their inclusion is not necessary for understanding the various embodiments described herein. The example CIS SOC 102 includes a substrate 112 having a frontside surface 112A and a backside surface 112B, a first layer stack 114 disposed on the backside surface 112B, a second layer stack 116 disposed on the frontside surface 112A, a multi-layer metallization layer 118 disposed within the second layer stack 116, and a contact pad structure 120 disposed within the PAD region 110. The contact pad structure 120 is an input / output (I / O) port of the CIS device 100 and includes a conductive layer electrically coupled to an interconnect structure 121 of the multi-layer metallization layer 118, which is embedded in an ILD layer 122 of the multi-layer metallization layer 118. The example CIS SOC 102 may include additional components, such as microlenses on the first layer stack 114, solder bumps on the contact pad structure 120, metal wiring, active and / or passive devices, insulating layers, etch stop layers, and doped regions, which are not shown for simplicity. The example first layer stack 114 includes a first dielectric layer 126 (e.g., an oxide layer such as AlO, an oxynitride layer, or another suitable material having color filter properties), an ARC (anti-reflection coating) layer 128, a first oxide layer 130, a second oxide layer 132 (e.g., an oxide film such as undoped silicon glass (USG) or another suitable dielectric material), a metal layer 134, and a third oxide layer 135. The example second layer stack 116 includes a fourth oxide layer 143, a contact etch stop layer (CESL) 124, and multiple metallization layers 118. The substrate 112 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, or the like, which can be doped (e.g., with p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate can include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The interconnect structure 121 provides routing and electrical connections between device elements formed in and / or above the substrate 112. The interconnect structure 121 may include one or more conductive features, which in this example include metal wires and / or vias formed therein within the multilayer metallization layer 118. The conductive features may be electrically connected to active and / or passive devices on the substrate 112 via contacts (not shown). In some embodiments, the interconnect structure 121 may be formed using a single and / or dual damascene process, a via-first process, or a metal-first process. The conductive material used for the metal lines and / or vias can be formed from conductive materials such as copper (Cu), aluminum (Al), tungsten (W), nickel, cobalt, silver, combinations thereof, or other suitable materials, and can be formed using electrochemical plating processes, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. After forming the conductive material, excess conductive material can be removed using a planarization process such as chemical mechanical polishing (CMP), for example. The interconnect structure 121 shown in FIG. 1 is for illustrative purposes only. The interconnect structure 121 can include other configurations and may include one or more metal lines and an intermetallic dielectric (IMD) layer. The example pixel array region 106 includes a metal layer 134 having a metal grid structure, wherein grid lines 136 isolate pixels from one another. The example pixel array region 106 is configured to receive an incident radiation beam, which is converted into an electrical signal within the pixel array region 106 via the first layer stack 114. The electrical signal is distributed to the ASIC 104 or external circuitry via the contact pad structure 120 and the interconnect structure 121. The ASIC 104 can be bonded to the multilayer metallization layer 118 via molecular forces (a technique known as direct bonding or optical fusion bonding) or via other bonding techniques known in the art, such as metal diffusion or anodic bonding. In some embodiments, the ASIC 104 can comprise a material similar to the substrate 112 or can comprise a glass substrate. The ASIC 104 can include active devices (e.g., transistor structures) to form logic and memory circuits within the ASIC. Electrical connections between the active devices within the ASIC 104 and the first layer stack 114 are provided by the interconnect structure 121B within the ASIC 104. The peripheral region 108 may include a grounded metal shield 137 in the metal layer 134 to provide optical shielding for active devices (not shown) in the peripheral region 108, thereby keeping the active devices optically dark. The active devices in the peripheral region 108 may be reference pixels used to establish a light intensity baseline for the CIS SOC 102. The PAD region 110 may include one or more conductive bonding pads or solder bumps (not shown) on the contact pad structure 120. Electrical connections between the CIS device 100 and external circuits may be established via the conductive bonding pads or solder bumps. The first layer stack 114 may include a first dielectric layer 126 on the backside surface 112B, an ARC layer 128 disposed on the first dielectric layer 126 to reduce reflection of incident light, a first oxide layer 130 disposed on the ARC layer 128, a metal layer 134 disposed on the first oxide layer 130, a second oxide layer 132 disposed on the metal layer 134, and a third oxide layer 135 disposed on the second oxide layer 132. In some embodiments, the ARC layer 128 may include a first ARC layer 139 and a second ARC layer 141. In various embodiments, the first ARC layer 139 includes a high-k dielectric material, such as hafnium oxide (HfO). 2). In various embodiments, the second ARC layer 141 includes a high-k dielectric material, such as tantalum oxide (Ta 2O 5). In other embodiments, the ARC layer 128 may include a high-k dielectric material such as titanium oxide (TiO 2) Hafnium zirconium oxide (HfZrO), Hafnium silicate (HfSiO 4) Zirconium oxide (ZrO 2), and zirconium silicate (ZrSiO 2) or other suitable high-k dielectric materials. In various embodiments, the third oxide layer 135 may include a plasma-enhanced oxide (PEOX) layer formed using a plasma-enhanced CVD process with a tetraethoxysilane (PETEOS) precursor. In some embodiments, the metal layer 134 includes a titanium nitride (TiN) layer 142. In some embodiments, the metal layer 134 includes tungsten (W) or other suitable metal material formed above the TiN layer 142. In an embodiment, the substrate 112 is formed of Si and has a thickness of about 3 microns; the first dielectric layer 126 is formed of aluminum oxide (AlO) and has a thickness of about 40 angstroms (A); the first ARC layer 139 is formed of HfO 2 is formed to have a thickness of about 60 Å; the second ARC layer 141 is made of Ta 2O 5, having a thickness of approximately 470 Å; the first oxide layer 130 is plasma-enhanced oxide (PEOX) and has a thickness of approximately 700 Å; the metal layer 134 includes a TiN layer 142 of approximately 300 Å and a tungsten (W) layer of approximately 1600 Å; the second oxide layer 132 is formed of undoped silica glass (USG) and has a thickness of approximately 4000 Å; the third oxide layer 135 is low deposited rate resistor protection oxide (LRPO) and has a thickness of approximately 250 Å; the CESL has a thickness of approximately 375 Å; and the fourth oxide layer 143 has a thickness of approximately 385 Å. The contact pad structure 120 is formed in the first cavity portion of the contact pad opening, which extends to the ILD layer 122 without terminating at the STI region of the substrate 112. As a result, no STI region is required in the PAD region 110, and crystal defects caused by Si dislocations in the STI region can be avoided. Figure 2 is a flow chart of an example method 200 for manufacturing a CIS device according to some embodiments. For ease of illustration, the operations shown in Figure 2 will be described with reference to Figures 3A to 3I, which show cross-sectional views of a CIS device at various stages of its manufacturing process according to some embodiments. The operations may be performed in a different order, or not at all, depending on the particular application. It should be noted that method 200 may not produce a complete CIS device. Therefore, it should be understood that additional processes may be provided before, during, and after the method, and some other processes may only be briefly described herein. The elements in Figures 3A to 3I have the same annotations as the elements in Figure 1, as described above. In some figures, some reference numerals in the components or features shown therein may be omitted to avoid obscuring other components or features; this is for ease of depiction of the figures. Method 200 is merely an example and is not intended to limit the present disclosure beyond that expressly recited in the claims. Additional steps may be provided before, during, and after example method 200, and some of the described steps may be moved, replaced, or eliminated for additional embodiments of example method 200. Additional features may be added to the semiconductor devices depicted in the figures, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device. It should be understood that the components of the semiconductor device can be manufactured using typical semiconductor technology process flows, and therefore only some of the processes are briefly described herein. Furthermore, the exemplary semiconductor device may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but these are simplified for a better understanding of the concepts of the present disclosure. In some embodiments, the exemplary device includes a plurality of interconnected semiconductor devices (e.g., transistors), including PFETs (P-channel field-effect transistors), NFETs (N-channel field-effect transistors), and the like. Furthermore, it should be noted that the operations of method 200, including any description given with reference to the figures, are merely exemplary and are not intended to be limiting beyond those specifically enumerated in the following claims. At block 210 , method 200 includes providing a substrate having a front surface, a back surface, a pixel array region, a peripheral region, and a contact pad region. Referring to the example of FIG. 3A , in the embodiment of block 210 , substrate 112 includes front surface 112A, back surface 112B, pixel array region 106 , peripheral region 108 , and contact pad region 110 . At block 212, method 200 includes forming a multi-layer metallization layer adjacent to and below the front side surface of the substrate, the multi-layer metallization layer having an interconnect structure embedded in an interlayer dielectric (ILD) layer. After forming the multi-layer metallization layer on the front side surface, a carrier substrate, such as an ASIC, may then be bonded to the multi-layer metallization layer. Referring to the example of FIG. 3A , in the embodiment of block 212, a multi-layer metallization layer 118 is formed below the front side surface 112A of the substrate 112, the multi-layer metallization layer 118 having an interconnect structure 121 embedded in an ILD layer 122. In the illustrated example, the interconnect structure 121B of the ASIC 104 is bonded to the interconnect structure 121 of the multi-layer metallization layer 118. At block 214 , the method 200 includes forming an anti-reflective coating (ARC) layer on the backside surface of the substrate. Referring to the example of FIG. 3A , in the embodiment of block 214 , the ARC layer 128 is formed on the backside surface 112B of the substrate 112 . At block 216 , the method 200 includes forming a first oxide layer over the ARC layer. Referring to the example of FIG. 3A , in one embodiment of block 216 , the first oxide layer 130 is formed over the ARC layer 128 . At block 218, method 200 includes forming a first cavity portion of a contact pad opening in the contact pad region, the first cavity portion extending from a top surface of the first oxide layer to an interior region of the ILD layer. In various embodiments, the first contact pad opening is formed by depositing a mask, patterning the mask with an opening, and etching the first cavity portion of the contact pad opening based on the patterned mask. In one embodiment, the mask is formed of silicon nitride (SiN) and has a thickness of 880 Å. Referring to the example of FIG. 3B , in the embodiment of block 218, a patterned mask 302 is formed over the first oxide layer 130, and a first cavity portion 304 of the contact pad opening is formed in the contact pad region 110, extending from the patterned mask 302 and the top surface of the first oxide layer 130 to an interior region of the ILD layer 122. Thereafter, the contact pad structure 120 is formed in the first cavity portion 304 of the contact pad opening, which extends to the ILD layer 122 without terminating at the STI region of the substrate 112. As a result, the STI region is not required and crystal defects due to Si dislocations in the STI region can be avoided. At block 220, method 200 includes forming an oxide (e.g., plasma-enhanced oxide (PEOX)) layer on the sidewalls of the substrate and ARC layer exposed by the first contact pad opening and on the top surface of the ILD layer exposed by the first contact pad opening. Forming the oxide layer on the sidewalls of the substrate and ARC layer exposed by the first contact pad opening and on the top surface of the ILD layer exposed by the first contact pad opening involves depositing the oxide and then etching the oxide. Referring to the example of FIG. 3C , in an embodiment of block 220, an oxide (e.g., plasma-enhanced oxide (PEOX)) layer 306 is formed on the sidewalls of the substrate 112 and ARC layer 128 exposed by the first cavity portion 304 of the contact pad opening and on the surface of the ILD layer 122 exposed by the first cavity portion 304 of the contact pad opening. At block 222, method 200 includes forming a contact pad extending from the first cavity portion of the contact pad opening to the interconnect structure. In various embodiments, forming the contact pad extending from the first cavity portion of the contact pad opening to the interconnect structure includes forming a second cavity portion of the contact pad opening and forming the contact pad in the second cavity portion of the contact pad opening, the second cavity portion extending from an oxide layer on a surface of the ILD layer exposed by the first cavity portion of the contact pad opening to the interconnect structure. In one embodiment, the contact pad is formed of aluminum copper (AlCu). In one embodiment, the AlCu contact pad is formed by depositing an AlCu material layer and patterning and etching the AlCu material layer to form a pad structure. Referring to the example of FIG. 3C, in one embodiment of block 222, a second cavity portion 308 of the contact pad opening extending to the interconnect structure 121 is formed. Referring to the example of FIG. 3D, in one embodiment of block 222, the contact pad structure 120 is formed in the second cavity portion 308 of the contact pad opening. At block 224, method 200 includes forming an outer oxide layer in a first cavity portion and a second cavity portion of the contact pad opening above the substrate and above the contact pad. In various embodiments, forming the outer oxide layer involves depositing the oxide layer using a PECVD process. Referring to the example of FIG. 3E , in an embodiment of block 224, an outer oxide layer 310 is formed in a first cavity portion 304 and a second cavity portion 308 of the contact pad opening above the substrate 112 and above the contact pad structure 120. At block 226, method 200 includes planarizing the oxide formed above the substrate. In various embodiments, planarizing the outer layer of oxide formed above the substrate includes removing the oxide above the patterned mask, removing the patterned mask, and removing a portion of the oxide above the ARC layer using a CMP operation. In various embodiments, an etching operation is performed to remove the oxide above the patterned mask, the patterned mask, and the portion of the oxide above the ARC layer, followed by a CMP operation to planarize the top surface of the oxide above the ARC layer. Referring to the example of FIG. 3F , in the embodiment of block 226, the oxide above the patterned mask 302, the patterned mask 302, and the portion of the oxide above the ARC layer 128 have been removed. The oxide 310 above the ARC layer 128 has been planarized using a CMP operation. At block 228, method 200 includes forming a ground opening in the peripheral region. In various embodiments, forming the ground opening in the peripheral region involves an etching operation. Referring to the example of FIG. 3G, in the embodiment of block 228, a ground opening 312 has been formed in the peripheral region 108. At block 230, method 200 includes forming a metal layer including gridlines in the pixel region and a grounded metal shield in the peripheral region. In various embodiments, the metal layer is formed by depositing a TiN layer over the pixel array region and the peripheral region (including in the ground openings), followed by depositing a tungsten (W) layer over the TiN layer. In various embodiments, forming the metal layer including gridlines in the pixel region and the grounded metal shield in the peripheral region also includes depositing a TiN layer and a W layer over the PAD region while the TiN layer and the W layer are deposited over the pixel array region and the peripheral region, wherein portions of the TiN layer and the W layer deposited over the PAD region are removed in a subsequent operation. At block 232, method 200 includes forming a second oxide layer over the metal layer. In various embodiments, the second oxide layer is formed by deposition. In various embodiments, forming the second oxide layer over the metal layer also includes forming the second oxide layer over the metal layer in the PAD region, wherein a portion of the second oxide formed over the PAD region is removed in a subsequent operation. At block 234, method 200 includes forming pixel openings in the second oxide layer, the metal layer, and a portion of the first oxide layer in the pixel array region to define grid lines. In various embodiments, the pixel openings are formed by patterning and etching the metal layer. In various embodiments, forming the pixel openings in the second oxide layer, the metal layer, and a portion of the first oxide layer in the pixel array region also includes removing a portion of the second oxide layer, the metal layer, and the first oxide layer above the PAD region. 3H , in the embodiment of blocks 230, 232, and 234, a metal layer 134 including grid lines 136 in the pixel array region 106 and a ground metal shield 137 in the peripheral region 108 has been formed. A second oxide layer 132 has been formed over the metal layer 134. A pixel opening 313 has been formed in the second oxide layer 132, the metal layer 134, and a portion of the first oxide layer 130 in the pixel array region 106. Furthermore, the PAD region 110 does not have a metal layer 134 or a second oxide layer 132 formed thereon. At block 236, method 200 includes forming a third oxide layer over the second oxide layer. In various embodiments, forming the third oxide layer includes depositing polyethylene oxide (PEOX) using a CVD process. In various embodiments, forming the third oxide layer includes depositing the third oxide layer over the second oxide layer over the pixel array region and the peripheral region, and depositing the third oxide layer over the first oxide layer over the PAD region. At block 238 , method 200 includes forming a scribe line pad opening over the contact pad. Referring to the example of FIG. 3I , in the embodiment of blocks 236 and 238 , a third oxide layer 135 is formed over the second oxide layer 132 , and a scribe line pad opening 314 is formed over the contact pad structure 120 . The aspect ratio of the scribe line pad opening 314 is much higher than that of the scribe line pad opening formed by the process of terminating the first contact pad opening in the STI region of the substrate. Due to the aspect ratio of the scribe line pad opening 314, an anisotropic etching technique can be used to etch the scribe line pad opening 314. FIG4 is a schematic cross-sectional view of an example anisotropically etched wall that can achieve the scribe line liner opening 314. In this example, a technique such as the Bosch plasma etch process (a high aspect ratio plasma etch process) is employed. The Bosch plasma etch process can be used to etch straight walls 410. The Bosch plasma etch process comprises a cyclic process involving isotropic etching followed by protective film deposition using rapid gas switching in the plasma etch chamber. The isotropic etch can involve deep reactive ion etching (DRIE), depositing a protective coating over the etched area, and rapidly switching between etching and deposition steps during the manufacturing process to carve (etch) a small portion of the opening and layer (deposit) material on the walls of the opening to protect the walls during further etching steps. Although the foregoing examples are described with respect to forming a BSI image sensor without STI in a substrate in a PAD region, the foregoing devices, apparatus, and methods can also be used in conjunction with forming a BSI image sensor with STI in a substrate in a PAD region. For example, FIG. 5 depicts a schematic cross-sectional view of an example portion of an example CIS device 500. The example CIS device 500 includes a CIS system-on-a-chip (SOC) 502 and a carrier substrate, such as an application specific integrated circuit (ASIC) 504. The example CIS device 500 has a plurality of regions, including a pixel array region 506, a peripheral region 508 laterally surrounding the pixel array region 506 (such as a black level correction (BLC) region), and a contact pad (PAD) region 510. The example CIS device 500 may further include other regions. The example CIS SOC 502 includes a substrate 512, a multi-layer metallization layer 518, and a pad structure 520 disposed within a PAD region 510. The substrate 512 includes an STI region 524 in the PAD region 510. The pad structure 520 includes a conductive layer electrically coupled to an interconnect structure 521 of the multi-layer metallization layer 518, which is embedded in an ILD layer 522 of the multi-layer metallization layer 518. Interconnect structure 521 provides routing and electrical connections between device elements formed in and / or above substrate 512. Interconnect structure 521 may include one or more conductive features, which in this example include metal wires and / or vias formed therein in multilayer metallization layer 518. The conductive features may be electrically connected to active and / or passive devices on substrate 512 via contacts (not shown). In some embodiments, interconnect structure 521 may be formed using a single and / or dual damascene process, a via-first process, or a metal-first process. The contact pad structure 520 is formed in the first cavity portion 552 of the contact pad opening (e.g., wherein a portion of the oxide layer 523 and the STI region 524 are disposed above the contact pad structure 520 in the first cavity portion 552). The first cavity portion 552 extends to the ILD layer 522 without terminating at the STI region of the substrate 512. As a result, crystal defects caused by Si dislocations in the STI region can be avoided. A scribe line pad opening 514 is formed above the contact pad structure 520. The aspect ratio of the scribe line pad opening 514 is much higher than the aspect ratio of a scribe line pad formed by a process in which the first contact pad opening terminates in the STI region of the substrate. Due to the aspect ratio of the scribe line pad opening 514, an anisotropic etching technique can be used to etch the scribe line pad opening 514. According to another embodiment, the devices, apparatus, and methods described herein may also be used in conjunction with a BSI image sensor that forms a first cavity portion having each of a plurality of contact pad openings extending into the ILD layer without terminating in the STI region of the substrate. FIG6 depicts a schematic cross-sectional view of an example portion of an example CIS device 600. The example CIS device 600 includes a CIS system-on-a-chip (SOC) 602 and a carrier substrate, such as an application specific integrated circuit (ASIC) 604. The example CIS device 600 has a plurality of regions, including a pixel array region 606, a peripheral region 608 laterally surrounding the pixel array region 606 (such as a black level correction (BLC) region), and a contact pad (PAD) region 610. The example CIS device 600 may further include other regions. The example CIS SOC 602 includes a substrate 612, a multi-layer metallization layer 618, and a plurality of first and second contact pad structures 620A and 620B disposed within a PAD region 610. The first and second contact pad structures 620A and 620B each include a conductive layer electrically coupled to an interconnect structure 621 of the multi-layer metallization layer 618, which is embedded in an ILD layer 622 of the multi-layer metallization layer 618. The first contact pad structure 620A is formed in the first cavity portion 652A of the first contact pad opening (e.g., wherein the oxide layer 623 is disposed over the first contact pad structure 620A in the first cavity portion 652A), and the first cavity portion 652A extends to the ILD layer 622 without terminating at the STI region of the substrate 612. Similarly, the second contact pad structure 620B is formed in the first cavity portion 652B of the second contact pad opening (e.g., wherein the oxide layer 623 is disposed over the second contact pad structure 620B in the first cavity portion 652B), and the first cavity portion 652B extends to the ILD layer 622 without terminating at the STI region of the substrate 612. As a result, an STI region is not required, and crystal defects due to Si dislocations in the STI region can be avoided. According to another embodiment, the devices, apparatus, and methods described herein may also be used in conjunction with forming a BSI image sensor having a first cavity portion with a contact pad opening that extends to a carrier substrate, such as an ILD layer of an ASIC, without terminating at the STI region of the substrate. FIG7 depicts a schematic cross-sectional view of an example portion of an example CIS device 700. The example CIS device 700 includes a CIS system-on-a-chip (SOC) 702 and a carrier substrate, such as an application specific integrated circuit (ASIC) 704. The example CIS device 700 has a plurality of regions, including a pixel array region 706, a peripheral region 708 laterally surrounding the pixel array region 706 (such as a black level correction (BLC) region), and a contact pad (PAD) region 710. The example CIS device 700 may further include other regions. The example CIS SOC 702 includes a substrate 712. The example ASIC 704 includes multiple metallization layers 718 and a contact pad structure 720 disposed within the PAD region 710. The contact pad structure 720 includes a conductive layer electrically coupled to an interconnect structure 721 of the multiple metallization layers 718, which is embedded in an ILD layer 722 of the multiple metallization layers 718. The contact pad structure 720 is formed in the first cavity portion 752 of the contact pad opening (e.g., wherein the oxide layer 723 is disposed over the contact pad structure 720 in the first cavity portion 752), and the first cavity portion 752 extends through the CIS SOC 702 to the ILD layer 722 without terminating at the STI region of the substrate 712. As a result, the STI region is not required, and crystal defects due to Si dislocations in the STI region can be avoided. Other configurations are also contemplated in which a contact pad structure is formed in a first cavity portion of a contact pad opening, the first cavity portion extending to the ILD layer without terminating in the STI region of the substrate. For example, FIG. 8 depicts a schematic cross-sectional view of an example portion of an example CIS device 800. The example CIS device 800 includes a CIS system-on-a-chip (SOC) 802 and a carrier substrate, such as an application specific integrated circuit (ASIC) 804. The example CIS device 800 has a plurality of regions including a pixel array region 806, a peripheral region 808 laterally surrounding the pixel array region 806 (such as a black level correction (BLC) region), and a contact pad (PAD) region 810. The example CIS device 800 may further include other regions. The example CIS SOC 802 includes a substrate 812. The example ASIC 804 includes a multi-layer metallization layer 818, and a first contact pad structure 820A and a second contact pad structure 820B disposed within the PAD region 810. The first contact pad structure 820A and the second contact pad structure 820B include conductive layers electrically coupled to an interconnect structure 821 of the multi-layer metallization layer 818, which is embedded in an ILD layer 822 of the multi-layer metallization layer 818. In this example, the first contact pad structure 820A is formed in a first cavity portion 852A of a first contact pad opening (e.g., wherein an oxide layer 823 is disposed over the contact pad structure 820A in the first cavity portion 852A), and the first cavity portion 852A extends through the CIS SOC 802 to the ILD layer 822 without terminating at the STI region of the substrate 812. In addition, a second contact pad structure 820B is formed in the first cavity portion 852B of the second contact pad opening (e.g., wherein the oxide layer 823 is disposed above the contact pad structure 820B in the first cavity portion 852B). The first cavity portion 852B extends through the CIS SOC 802 to the ILD layer 822 without terminating at the STI region of the substrate. As a result, an STI region is not required, and crystal defects caused by Si dislocations in the STI region can be avoided. In another example, FIG. 9 depicts a schematic cross-sectional view of an example portion of another example CIS device 900. The example CIS device 900 includes a CIS system-on-a-chip (SOC) 902 and a carrier substrate, such as an application-specific integrated circuit (ASIC) 904. The example CIS device 900 has a plurality of regions, including a pixel array region 906, a peripheral region 908 laterally surrounding the pixel array region 906 (such as a black level correction (BLC) region), and a contact pad (PAD) region 910. The example CIS device 900 may further include other regions. The example CIS SOC 902 includes a substrate 912. The example CIS SOC 902 includes multiple metallization layers 918A, and the example ASIC 904 includes multiple metallization layers 918B. A first contact pad structure 920A and a second contact pad structure 920B are disposed within the PAD region 910. The first contact pad structure 920A includes a conductive layer electrically coupled to an interconnect structure 921A of a multilayer metallization layer 918A embedded in an ILD layer 922A of a multilayer metallization layer 918A, and the second contact pad structure 920B includes a conductive layer electrically coupled to an interconnect structure 921B of a multilayer metallization layer 918B embedded in an ILD layer 922B of a multilayer metallization layer 918B. In this example, the first contact pad structure 920A can be formed in the first cavity portion 952A of the first contact pad opening that extends to the ILD layer 922A without terminating at the STI region of the substrate 912 (e.g., wherein the oxide layer 923 is disposed above the contact pad structure 920A in the first cavity portion 952A), and the second contact pad structure 920B can be formed in the first cavity portion 952B of the second contact pad opening that extends through the CIS SOC 902 to the ILD layer 922B without terminating at the STI region of the substrate 912 (e.g., wherein the oxide layer 923 is disposed above the contact pad structure 920B in the first cavity portion 952B). As a result, the STI region is not required, and crystal defects due to Si dislocations in the STI region can be avoided. In some aspects, the technology described herein relates to a manufacturing method comprising: providing a substrate having a frontside surface, a backside surface, and a contact pad region; providing an interconnect structure embedded in an interlayer dielectric (ILD) layer below the frontside surface of the substrate; forming a first cavity portion of a contact pad opening in the contact pad region extending from above the backside surface through the substrate to an interior region of the ILD layer below the frontside surface; forming a contact pad extending from the first cavity portion of the contact pad opening to the interconnect structure; forming an oxide layer over the contact pad; and forming a scribe line pad opening through the oxide layer to the contact pad. In some aspects, the technology described herein relates to a manufacturing method in which providing an interconnect structure embedded in an ILD layer includes forming multiple metallization layers below a front surface of a substrate, the multiple metallization layers including the interconnect structure and the ILD layer. In some aspects, the technology described herein relates to a manufacturing method further comprising bonding an application specific integrated circuit (ASIC) to the multiple metallization layers formed below the frontside surface, wherein the interconnect structure and the ILD layer are embedded in the ASIC. In some aspects, the technology described herein relates to a manufacturing method further comprising forming an anti-reflective coating (ARC) layer on a backside surface of a substrate, and forming a first oxide layer on the ARC layer, wherein forming the first cavity portion of the contact pad opening comprises forming the first cavity portion of the contact pad opening to extend from a top surface of the first oxide layer to an interior region of the ILD layer. In some aspects, the technology described herein relates to a manufacturing method further comprising forming an oxide layer on a surface of a sidewall portion of the substrate exposed by a first cavity portion of the contact pad opening, a sidewall portion of the ARC layer exposed by the first cavity portion of the contact pad opening, and a surface of the ILD layer exposed by the first cavity portion of the contact pad opening. In some aspects, the technology described herein relates to a manufacturing method, wherein forming a contact pad includes: forming a contact pad opening free of an oxide layer on a surface of an ILD layer exposed by a first cavity portion of the contact pad opening extending to a second cavity portion of an interconnect structure; and forming the contact pad in the second cavity portion of the contact pad opening. In some aspects, the technology described herein relates to a fabrication method wherein forming a scribe line pad opening through an oxide layer to a contact pad includes performing an anisotropic etching operation to form the scribe line pad opening. In some aspects, the techniques described herein relate to a manufacturing method wherein performing an anisotropic etching operation includes performing a cyclic process involving an isotropic etch followed by a protective film deposition. In some aspects, the technology described herein relates to a semiconductor device comprising: a substrate having a frontside surface, a backside surface, and a contact pad region; an interconnect structure embedded in an interlayer dielectric (ILD) layer below the frontside surface of the substrate; an application-specific integrated circuit (ASIC) bonded to multiple metallization layers formed below the frontside surface; a first contact pad opening in the contact pad region extending from above the backside surface through the substrate to an interior region of the ILD layer below the frontside surface; a contact pad extending from the first contact pad opening to the interconnect structure; an oxide layer formed above the contact pad; and a scribe line pad opening formed through the oxide layer to the contact pad. In some aspects, the technology described herein relates to a semiconductor device wherein multiple metallization layers include an interconnect structure and an ILD layer. In some aspects, the technology described herein relates to a semiconductor device in which interconnect structures and ILD layers are embedded in an ASIC. In some aspects, the technology described herein relates to a semiconductor device wherein the contact pad comprises aluminum copper (AlCu). In some aspects, the technology described herein relates to a semiconductor device further comprising: a second contact pad opening in the contact pad region extending from above the backside surface through the substrate to an inner region of the ILD layer below the frontside surface; a second contact pad extending from the second contact pad opening to an interconnect structure, wherein an oxide layer is formed over the contact pad; and a second scribe lane pad opening formed through the oxide layer to the contact pad. In some aspects, the technology described herein relates to a semiconductor device further comprising: an anti-reflective coating (ARC) layer on a backside surface of a substrate; and a first oxide layer on the ARC layer, wherein a first contact pad opening extends from a top surface of the first oxide layer to an interior region of the ILD layer. In some aspects, the technology described herein relates to a fabrication method comprising: providing a semiconductor structure having a plurality of regions, the regions including a contact pad region, the semiconductor structure comprising a substrate having a shallow trench isolation (STI) region in the contact pad region and a multi-layer metallization layer having an interconnect structure embedded in an interlayer dielectric (ILD) layer; forming a first contact pad opening in the contact pad region, the opening in the first contact pad extending through the STI region to an interior region of the ILD, wherein the first contact pad opening does not terminate in the STI region; forming a contact pad extending from the first contact pad opening to the interconnect structure; forming an oxide layer over the contact pad; and forming a scribe line pad opening through the oxide layer to the contact pad. In some aspects, the technology described herein relates to a manufacturing method further comprising forming an anti-reflective coating (ARC) layer on a backside surface of a substrate and forming a first oxide layer on the ARC layer, wherein forming the first contact pad opening comprises forming the first contact pad opening extending from a top surface of the first oxide layer to an interior region of the ILD layer. In some aspects, the technology described herein relates to a manufacturing method further comprising forming an oxide layer on a sidewall portion of the substrate exposed by the first contact pad opening, a sidewall portion of the ARC layer exposed by the first contact pad opening, and a surface of the ILD layer exposed by the first contact pad opening. In some aspects, the technology described herein relates to a manufacturing method, wherein forming a contact pad includes: forming a first contact pad opening extending from an oxide layer on a surface of an ILD layer exposed by the first contact pad opening to a second cavity portion of an interconnect structure; and forming the contact pad in the second cavity portion of the first contact pad opening. In some aspects, the technology described herein relates to a fabrication method wherein forming a scribe line pad opening through an oxide layer to a contact pad includes performing an anisotropic etching operation to form the scribe line pad opening. In some aspects, the techniques described herein relate to a manufacturing method wherein performing an anisotropic etching operation includes performing a cyclic process involving an isotropic etch followed by a protective film deposition. Although at least one exemplary embodiment has been presented in the foregoing detailed description of the present disclosure, it should be understood that a vast number of variations exist. It should also be understood that the one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. Instead, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing the exemplary embodiments of the present disclosure. It should be understood that various changes may be made to the functions and configurations of the components described in the exemplary embodiments without departing from the scope of the present disclosure as set forth in the appended claims. 100: CIS device 102: CIS SOC 104: ASIC 106: pixel array area 108: peripheral area 110: PAD area 112: substrate 112A: front side surface 112B: back side surface 114: first layer stack 116: second layer stack 118: multi-layer metallization layer 120: contact pad structure 121: interconnect structure 121B: interconnect structure 122: ILD layer 124: CESL layer 126: first dielectric layer 128: ARC layer 130: first oxide layer 132: second oxide layer 134: metal layer 135: second Three oxide layers 136: grid lines 137: ground metal shield 139: first ARC layer 141: second ARC layer 142: TiN layer 143: fourth oxide layer 200: methods 210-238: blocks 302: patterned mask 304: first cavity portion 306: oxide layer 308: second cavity portion 310: oxide 312: ground opening 313: pixel opening 314: scribe line pad opening 410: straight wall 500: CIS device 502: CIS SOC 504: ASIC 506: pixel array area 508: peripheral area 510: PAD area 512: substrate 514: scribe line pad opening 518: multi-layer metallization layer 520: contact pad structure 521: interconnect structure 522: ILD layer 523: oxide layer 524: STI region 552: first cavity portion 600: CIS device 602: CIS SOC 604: ASIC 606: pixel array area 608: peripheral area 610: PAD area 612: substrate 618: multi-layer metallization layer 620A: first contact pad structure 620B: second contact pad structure 621: interconnect structure 622: ILD layer 623: oxide layer 652A~652B: first cavity portion 700: CIS device 702: CIS SOC 704: ASIC 706: Pixel array region 708: Peripheral region 710: PAD region 712: Substrate 718: Multi-layer metallization layer 720: Contact pad structure 721: Interconnect structure 722: ILD layer 723: Oxide layer 752: First cavity portion 800: CIS device 802: CIS SOC 804: ASIC 806: Pixel array region 808: Peripheral region 810: PAD region 812: Substrate 818: Multi-layer metallization layer 820A: First contact pad structure 820B: Second contact pad structure 821: Interconnect structure 822: ILD layer 823: Oxide layers 852A~852B: First cavity portion 900: CIS device 902: CIS SOC 904: ASIC 906: Pixel array region908: Peripheral area 910: PAD area 912: Substrate 918A-918B: Multi-layer metallization layer 920A: First contact pad structure 920B: Second contact pad structure 921A-921B: Interconnect structure 922A-922B: ILD layer 923: Oxide layer 952A-952B: First cavity portion The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard specifications in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. FIG1 depicts a cross-sectional view of an example portion of a semiconductor device according to some embodiments. FIG2 is a flow chart of an example method for manufacturing a CMOS image sensor (CIS) device according to some embodiments. FIG3A to FIG3I depict cross-sectional views of a CIS device according to some embodiments at various stages of its manufacturing process. FIG4 illustrates a cross-sectional schematic view of an example anisotropic etched wall that can achieve scribe line pad openings according to some embodiments. FIG5 depicts a schematic cross-sectional view of an example portion of an example CIS device according to some embodiments. FIG6 depicts a schematic cross-sectional view of an example portion of an example CIS device according to some embodiments. FIG7 depicts a schematic cross-sectional view of an example portion of an example CIS device according to some embodiments. FIG8 depicts a schematic cross-sectional view of an example portion of an example CIS device according to some embodiments. FIG. 9 depicts a schematic cross-sectional view of an example portion of an example CIS device, according to some embodiments. Domestic deposit information (please note in the order of deposit organization, date, and number) None Foreign deposit information (please note in the order of deposit country, organization, date, and number) None 100:CIS device 102:CIS SOC 104:ASIC 106: Pixel array area 108: Surrounding area 110:PAD area 112:Substrate 112A: front surface 112B: Back surface 114: First layer stacking 116: Second layer stack 118:Multi-layer metallization layer 120: Contact pad structure 121: Interconnection structure 121B: Interconnection structure 122:ILD layer 124:CESL layer 126: first dielectric layer 128:ARC layer 130: first oxide layer 132: Second oxide layer 134:Metal layer 135: Third oxide layer 136: Grid lines 137: Grounded metal shield 139: First ARC layer 141: Second ARC layer 142:TiN layer 143: Fourth oxide layer
Claims
1. A method of manufacturing a semiconductor device, comprising: providing a substrate having a front surface, a rear surface, and a contact pad region; providing an interconnect structure embedded in an interlayer dielectric layer beneath the front surface of the substrate; forming a first cavity portion of a contact pad opening in the contact pad region, the first cavity portion extending from the rear surface through the substrate to an internal region of the interlayer dielectric layer beneath the front surface; forming a contact pad extending from the first cavity portion of the contact pad opening to the interconnect structure, wherein the contact pad is completely located beneath the front surface; forming an oxide layer above the contact pad; and forming a scribe line pad opening extending through the oxide layer to the contact pad.
2. A method of manufacturing a semiconductor device as claimed in claim 1, wherein providing an interconnect structure embedded in an interlayer dielectric layer comprises: forming a multilayer metallization layer under the front surface of the substrate, the multilayer metallization layer including the interconnect structure and the interlayer dielectric layer.
3. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising: forming an antireflective coating layer on the rear surface of the substrate, and forming a first oxide layer on the antireflective coating layer, wherein: The first cavity portion forming the contact pad opening includes: the first cavity portion forming the contact pad opening extends from one of the top surfaces of the first oxide layer to the inner region of the interlayer dielectric layer.
4. The method of manufacturing a semiconductor device as claimed in claim 3, further comprising: forming the oxide layer on a plurality of sidewall portions of the substrate exposed by the first cavity portion of the contact pad opening, a plurality of sidewall portions of the antireflective coating layer exposed by the first cavity portion of the contact pad opening, and a surface of one of the interlayer dielectric layers exposed by the first cavity portion of the contact pad opening.
5. A semiconductor device comprising: a substrate having a front surface, a rear surface, and a contact pad region; an interconnect structure embedded in an interlayer dielectric layer beneath the front surface of the substrate; an application-specific integrated circuit bonded to a multilayer metallization layer formed beneath the front surface; a first contact pad opening extending from the rear surface through the substrate to an internal region of one of the interlayer dielectric layers beneath the front surface in the contact pad region; a contact pad extending from the first contact pad opening to the interconnect structure and entirely beneath the front surface; an oxide layer formed above the contact pad; and a scribe line pad opening extending through the oxide layer to the contact pad.
6. The semiconductor device as claimed in claim 5, further comprising: a second contact pad opening extending through the substrate from above the rear surface to an inner region of one of the interlayer dielectric layers below the front surface in the contact pad region; a second contact pad extending from the second contact pad opening to the interconnect structure, wherein the oxide layer is formed above the contact pad; and a second scribe line pad opening extending through the oxide layer to the contact pad.
7. A method of manufacturing a semiconductor device, comprising: providing a semiconductor structure having a plurality of regions, the regions including a contact pad region, the semiconductor structure including a front surface, a rear surface, a substrate having a shallow trench isolation region in the contact pad region, and a multilayer metallization layer having an interconnect structure embedded in an interlayer dielectric layer; forming a first contact pad opening in the contact pad region, the first contact pad opening extending from the rear surface through the shallow trench isolation region to an internal region of one of the interlayer dielectric layers below the front surface, wherein the first contact pad opening does not terminate at the shallow trench isolation region; forming a contact pad extending from the first contact pad opening to the interconnect structure, wherein the contact pad is completely located below the front surface; forming an oxide layer above the contact pad; and forming a scribe line pad opening extending through the oxide layer to the contact pad.
8. The method of manufacturing a semiconductor device as claimed in claim 7, further comprising: forming an antireflective coating layer on the rear surface of the substrate, and forming a first oxide layer on the antireflective coating layer, wherein: Forming the first contact pad opening includes: forming the first contact pad opening extending from one of the top surfaces of the first oxide layer to the inner region of the interlayer dielectric layer.
9. A method of manufacturing a semiconductor device as claimed in claim 8, further comprising: forming the oxide layer on a plurality of sidewall portions of the substrate exposed by the first contact pad opening, a plurality of sidewall portions of the antireflective coating layer exposed by the first contact pad opening, and a surface of one of the interlayer dielectric layers exposed by the first contact pad opening.
10. A method of manufacturing a semiconductor device as claimed in claim 7, wherein forming the scribe line pad opening through the oxide layer to the contact pad comprises: performing a plurality of anisotropic etching operations to form the scribe line pad opening.