Integrated circuit device and method for forming the same

Abstract

A method and apparatus are provided, wherein the method includes forming a stack comprising a nanostructure channel, an interposer, and a hard mask structure by forming source / drain openings; the method further includes forming a sacrificial gate structure on the stack and forming a spacer layer adjacent to the sacrificial gate structure; the method further includes releasing the nanostructure channel by removing the interposer and forming a gate dielectric on the sides of the nanostructure channel and the spacer layer; the method also includes forming a reduced gate dielectric by removing a portion of the gate dielectric from the sides of the spacer layer, the portion being laterally adjacent to the nanostructure channel, and forming a gate metal layer on the exposed portion of the reduced gate dielectric and the spacer layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to integrated circuit devices and methods of forming the same. Prior Art

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each featuring smaller and more complex circuits than the previous one. Throughout the history of IC development, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component or circuit produced during the manufacturing process) has decreased. This process of device miniaturization has provided benefits such as increased production efficiency and reduced associated costs. However, this device miniaturization has also increased the complexity of processing and manufacturing ICs. Summary of the Invention

[0003] In some embodiments, a method for forming an integrated circuit device is provided, the method comprising forming a stack comprising a plurality of nanostructured channels, a plurality of interposers, and a hard mask structure by forming source / drain openings; forming a sacrificial gate structure on the stack; forming a spacer layer adjacent to the sacrificial gate structure; releasing the plurality of nanostructured channels by removing the plurality of interposers; forming a gate dielectric on sides of the plurality of nanostructured channels and the spacer layer; forming a reduced gate dielectric by removing a portion of the gate dielectric from the sides of the spacer layer, the portion being laterally adjacent to the plurality of nanostructured channels; and forming a gate metal layer on the exposed portion of the reduced gate dielectric and the spacer layer.

[0004] In some embodiments, a method for forming an integrated circuit device is provided, the method comprising forming a stack comprising alternating nanostructured channels and a plurality of interposers by forming source / drain openings extending through alternating first and second semiconductor layers; releasing the plurality of nanostructured channels by removing the plurality of interposers; forming a gate dielectric over the plurality of nanostructured channels and on side surfaces of a spacer extending from a first level above the plurality of nanostructured channels to a second level below the plurality of nanostructured channels; forming a plurality of protection plugs between the plurality of nanostructured channels; selectively growing a protection structure on exposed surfaces of the plurality of protection plugs; and removing a portion of the gate dielectric exposed through the plurality of protection plugs.

[0005] In some other embodiments, an integrated circuit device is provided, comprising a first stack of a plurality of nanostructures; a second stack of a plurality of nanostructures adjacent to the first stack of the plurality of nanostructures along a first direction; a source / drain adjacent to the first stack of the plurality of nanostructures along a second direction transverse to the first direction; and a gate structure surrounding the first stack of the plurality of nanostructures, the gate structure comprising: a gate dielectric comprising: a first portion extending between the first stack of the plurality of nanostructures; and a second portion extending between the second stack of the plurality of nanostructures, the first portion and the second portion being discontinuous in a region between the first stack of the plurality of nanostructures and the second stack of the plurality of nanostructures along the first direction; and a gate metal located on the gate dielectric, the gate metal extending between the first stack of the plurality of nanostructures, between the second stack of the plurality of nanostructures, and continuously between the first stack of the plurality of nanostructures and the second stack of the plurality of nanostructures in this region. Simple diagram description

[0006] The following detailed description, combined with the accompanying drawings, will provide a better understanding of the embodiments of the present invention. It should be noted that, in accordance with standard industry practice, the various features shown in the figures are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of illustration. 1A and 1B are schematic cross-sectional views of a portion of an integrated circuit device according to various embodiments of the present invention. Figures 2A, 2B, 3A, 3B, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 9C, 10A, 10B, 11A, 11B, 12A, 12B, 12C, 12D, 13A, 13B, 13C, 13D, 14A, 14B, 14C, 14D, 14E, 14F, 15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H, 15I, 16, and 17 are schematic diagrams of various embodiments of integrated circuit devices at various stages of manufacture according to various embodiments of the present invention. FIG. 18 is a flow chart of a method for forming an integrated circuit device according to various embodiments. Implementation Method

[0007] It should be understood that the following description provides many different embodiments or examples for implementing various components of the provided subject matter. Specific examples of various components and their arrangements are described below to simplify the description. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, component dimensions are not limited to the ranges or values ​​of one embodiment of the present disclosure but may depend on the processing conditions and / or desired properties of the component. Furthermore, the following description of forming a first component above or on a second component includes embodiments in which the first and second components are formed in direct contact, as well as embodiments in which additional components may be formed between the first and second components, eliminating the need for direct contact. Furthermore, the various examples in the present description may use repeated reference symbols and / or terms. This repeated reference symbol or terminology is for simplicity and clarity and is not intended to limit the relationship between the various embodiments and / or the described structures.

[0008] Spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and similar terms, may be used to conveniently describe the relationship of one element or component to another element or component in the drawings. Spatially relative terms encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the description using spatially relative terms interpreted accordingly.

[0009] Terms indicating relative degrees (eg, "about," "substantially," and the like) should be interpreted as understood by one of ordinary skill in the art in light of the prior art.

[0010] The terms "first," "second," "third," and the like may be used herein to describe a sequence of events or a sequential order of elements, but may be interchangeable or varied in some contexts. For example, a second layer may be formed on a first layer (e.g., sequentially after the first layer), but in some contexts, the first layer may be referred to as the "second layer," "third layer," "fourth layer," or similar terms, while the second layer may be referred to as the "first layer," "third layer," "fourth layer," or similar terms.

[0011] The term "surround" may be used herein to describe a structure that fully or partially encloses another element or structure, such as in three dimensions. For example, a first structure may "surround" a second structure on four sides (e.g., left, right, front, and back) but not on two perpendicular sides (e.g., top and bottom). In another example, a first structure may partially surround a second structure, such as by surrounding three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0012] Depending on the context, the source / drain regions may individually or collectively represent a source or a drain.

[0013] This article relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured FETs, such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), and the like.

[0014] Improving the performance of nanostructured devices in nanochip field-effect transistors (NFVs) is challenging given the complex device architectures and extreme scaling requirements. For example, reducing gate-to-drain capacitance (Cgd) can improve device speed and power efficiency. Including sidewall spacers with low dielectric constants can help reduce capacitance (Ceff) and improve device performance. However, during gate-last processing, forming an active replacement gate after forming the sidewall spacers can introduce significantly increased gate-to-drain capacitance (Cgd). For example, a high-k gate dielectric layer formed over the active semiconductor channel is also formed to cover the entire sidewall spacer.

[0015] In an embodiment of the present invention, the high-k gate dielectric layer is selectively removed from the sidewall spacers to reduce gate-to-drain capacitance (Cgd), while retaining the high-k gate dielectric layer on the sidewall spacers to reduce or eliminate gate leakage and reliability degradation. Removing the high-k gate dielectric layer from the sidewall spacers improves cell size reduction by increasing the top gate length. The increased volume of the gate metal gapfill reduces gate resistance Rg.

[0016] Nanostructured transistor structures can be patterned using any suitable method. For example, these structures can be patterned using one or more photolithography processes, including double or multiple patterning processes. Generally, double or multiple patterning processes combine photolithography with self-aligned processes to create patterns with smaller pitches, for example, than can be achieved using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructured transistor structures.

[0017] Figures 1A and 1B are schematic cross-sectional views of a portion of a nanostructure device 10 according to various embodiments. Figure 1A illustrates a schematic view taken along the XZ plane. Figure 1B illustrates a schematic view taken along the YZ plane, which is perpendicular to the XZ plane. The nanostructure device 10 of Figures 1A and 1B is described in detail below to provide a background for understanding the technical features and advantages of the various embodiments shown in Figures 2A through 18.

[0018] Referring to FIG. 1A , nanostructure devices 20A and 20B may be or include one or more n-type field-effect transistors (NFETs) or p-type field-effect transistors (PFETs). For example, nanostructure device 20A may be a PFET, while nanostructure device 20B may be an NFET. Nanostructure devices 20A and 20B are formed above and / or in substrate 110 and generally include a gate structure 200 that spans and / or surrounds channels 22A, 22B, and 22C (sometimes referred to as semiconductor channels). Channels 22A, 22B, and 22C are also referred to as "nanostructures." Channels 22A, 22B, and 22C are located above fins 32 (sometimes referred to as fin structures or semiconductor fins). Fins 32 protrude from and are isolated by isolation structures 36 (see FIG. 1B ). The channels 22A, 22B, and 22C may also be collectively referred to as channels 22. The gate structure 200 controls the flow of current through the channels 22A, 22B, and 22C.

[0019] The illustrated nanostructure devices 20A and 20B include three channels 22A, 22B, and 22C. Channels 22A, 22B, and 22C are laterally adjacent to source / drain components 82N and 82P and are covered and surrounded by a gate structure 200. Generally, there are two or more channels 22, such as three or four or more. However, in some embodiments, there may be only one channel 22. Depending on the voltages applied to the gate structure 200 and the source / drain components 82N and 82P, the gate structure 200 controls the current flowing through the channels 22A, 22B, and 22C, as well as the current flowing from the source / drain components 82N and 82P.

[0020] In some embodiments, fin 32 comprises silicon. In some embodiments, nanostructure device 20B comprises an n-type field-effect transistor (FET), and the source / drain components 82N of the n-type FET comprise silicon phosphide (SiP), SiAs, SiSb, SiPAs, SiP:As:Sb, SiGe, combinations thereof, or the like. In some embodiments, nanostructure device 20A comprises a p-type FET, and the source / drain components 82P of the p-type FET comprise undoped or doped silicon germanium (SiGe), such as SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or other suitable semiconductor materials. In general, source / drain components 82N and 82P may comprise any combination of suitable semiconductor materials and suitable dopants.

[0021] Channels 22A, 22B, and 22C each comprise a semiconductor material, such as silicon or a silicon compound, such as silicon germanium or the like. In some embodiments, channel 22 is or comprises one or more semiconductors or semiconductor alloys, such as Si, SiGe, Ge, GaAs, InGaAs, SiGeSn, GeSn, one or more two-dimensional materials with semiconductor properties, such as MoS2, WS2, combinations thereof, and the like. Channels 22A, 22B, and 22C are nanostructures (having dimensions in the range of a few nanometers) and may each have an elongated shape and extend in the X-direction. In some embodiments, channels 22A, 22B, and 22C each have a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of channels 22A, 22B, and 22C may be rectangular, circular, square, annular, elliptical, hexagonal, or a combination thereof.

[0022] In some embodiments, the lengths of channels 22A, 22B, and 22C (e.g., measured in the X-direction) may differ from one another, for example, due to tapering during the fin etching process (see Figures 3A and 3B). In some embodiments, the length of channel 22C may be less than that of channel 22B, and the length of channel 22B may be less than that of channel 22A. Channels 22A, 22B, and 22C may not have uniform thickness (e.g., along the X-axis), for example, due to a channel trimming process used to increase the spacing between channels 22A, 22B, and 22C (e.g., measured in the Z-axis) to increase gate structure manufacturing process margins. For example, the middle portion of each channel 22A, 22B, and 22C may be thinner than the ends of each channel 22A, 22B, and 22C. This shape may be referred to as a "dogbone" shape.

[0023] In some embodiments, the spacing between channels 22A, 22B, and 22C (e.g., between channel 22B and channel 22A or channel 22C) is in a range of between about 1 nm and about 15 nm, such as between about 5.5 nm and about 10 nm, although ranges greater than or less than this range may also be beneficial and are contemplated herein. In some embodiments, the thickness of each of channels 22A, 22B, and 22C (e.g., measured in the Z direction) is in a range of between about 1 nm and about 10 nm, although ranges greater than or less than this range may also be beneficial and are contemplated herein. In some embodiments, the width of each of channels 22A, 22B, and 22C (e.g., measured in the Y direction, perpendicular to the XZ plane, as shown in FIG. 3B ) is at least about 8 nm, although in some embodiments, this width may be less than 8 nm.

[0024] The gate structure 200 is disposed above and between channels 22A, 22B, and 22C. Channels 22A, 22B, and 22C are silicon channels for n-type devices or silicon-germanium channels for p-type devices. In some embodiments, the gate structure 200 includes an interfacial layer (IL) 210, one or more gate dielectric layers 600 on the IL 210, and a metal core layer 290 on the gate dielectric layer 600. Additional layers, such as one or more work function metal layers 900 (see FIG. 16 ), sometimes referred to as work function adjustment layers or work function layers, may be present on the gate dielectric layer 600 and between the gate dielectric layer 600 and the metal core layer 290.

[0025] An interfacial layer 210 (which may be the oxide of channels 22A, 22B, 22C) is formed on the exposed areas of channels 22A, 22B, 22C and on the top surface of fin 32. Interfacial layer 210 promotes adhesion of gate dielectric layer 600 to channels 22A, 22B, 22C. In some embodiments, interfacial layer 210 has a thickness of approximately 5 Å to approximately 50 Å. In some embodiments, interfacial layer 210 has a thickness of approximately 10 Å. An interfacial layer 210 that is too thin may result in voids or insufficient adhesion. An interfacial layer 210 that is too thick may deplete gate fill margin, which is related to threshold voltage adjustment and resistance. In some embodiments, interfacial layer 210 is doped with a dipole, such as lanthanum, for threshold voltage adjustment.

[0026] In some embodiments, the gate dielectric layer 600 comprises at least one high-k gate dielectric material, which may be a high-k dielectric material having a dielectric constant greater than that of silicon oxide (k ≈ 3.9). Example high-k dielectric materials may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer 600 has a thickness of approximately 5 Å to approximately 100 Å. The gate dielectric layer 600 may be a single layer or multiple layers.

[0027] In an embodiment of the present invention, the gate dielectric layer 600 may be a reduced gate dielectric layer 600S that covers only a portion of the gate spacer 41, as will be described with reference to FIG. 2A to FIG. 18. Reducing the area of ​​the gate dielectric layer 600 covering the gate spacer 41 can reduce the effective capacitance and increase the speed of the nanostructure device 10.

[0028] The gate structure 200 also includes a metal core layer 290. The metal core layer 290 may include a conductive material such as Co, W, Ru, combinations thereof, or the like. In some embodiments, the metal core layer 290 is or includes a Co-based compound, a W-based compound, a Ru-based compound, or an alloy containing one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, or the like. Between the channels 22A, 22B, and 22C, the metal core layer 290 circumferentially surrounds one or more work function metal layers 900 (in the cross-sectional schematic). The work function metal layers 900, in turn, circumferentially surround the gate dielectric layer 600. The gate dielectric layer 600 circumferentially or partially surrounds the interface layer 210.

[0029] As shown in FIG. 1A , nanostructure devices 20A and 20B may further include source / drain contacts 120 formed above source / drain features 82N and 82P. Source / drain contacts 120 may include a core layer that is or includes a conductive material, such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, yttrium, molybdenum, nickel, aluminum, or a combination thereof. The core layer may be surrounded by one or more liner layers (or barrier layers), such as SiN or TiN, which help prevent or reduce diffusion of material from or into source / drain contacts 120. In some embodiments, the height of source / drain contacts 120 may be in the range of approximately 1 nm to approximately 50 nm.

[0030] A silicide layer 118 may be located between the source / drain features 82N, 82P and the source / drain contacts 120 to at least reduce the source / drain contact resistance. In some embodiments, the silicide layer 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, or the like. In some embodiments, the silicide layer 118 is or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, or the like. The silicide layer 118 may have a thickness in a range from about 1 nm to about 10 nm. A thickness less than about 1 nm may result in insufficient reduction in contact resistance. A thickness greater than about 10 nm may result in an electrical short to the channel 22. In some embodiments, the silicide layer 118 shown below contacts the etch stop layer 131 .

[0031] As shown in FIG. 1B , the nanostructure devices 20A and 20B may further include an interlayer dielectric (ILD) 130. The ILD 130 provides electrical isolation between various components of the nanostructure devices 20A and 20B, such as between adjacent pairs of source / drain contacts 120. An etch stop layer 131 may be formed before forming the ILD 130. The etch stop layer 131 may be laterally positioned between the ILD 130 and the gate spacers 41 and vertically positioned between the ILD 130 and the source / drain features 82N and 82P. In some embodiments, the etch stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO₂, ZrO₂, ZrAlO₂, HfAlO₂, HfSiO₂, Al₂O₃, or other suitable materials. In some embodiments, the thickness of the etch stop layer 131 ranges from approximately 1 nm to approximately 5 nm. In some embodiments, when the interlayer dielectric 130 is not present (e.g., the interlayer dielectric 130 is completely removed before forming the source / drain contacts 120), the etch stop layer 131 may contact the source / drain contacts 120. Before forming the source / drain contacts 120, the etch stop layer 131 may be trimmed, for example, in the X-axis direction, to improve the fill quality of the source / drain contacts 120.

[0032] Nanostructure devices 20A and 20B include gate spacers 41 disposed on the sidewalls of the metal core layer 290 above the channel 22C, and inner spacers 74 disposed on the sidewalls of the interface layer 210 and / or the gate dielectric layer 600 between the channels 22A, 22B, and 22C. The inner spacers 74 are also disposed between the channels 22A, 22B, and 22C. In the embodiment shown in FIG. 1A , the gate spacers 41 include a first spacer 41A and a second spacer 41B disposed on the first spacer 41A. The first spacer 41A and the second spacer 41B can each comprise a dielectric material, such as a low-k material, such as SiOCN, SiON, SiN, SiCN, SiOC, or the like. In some embodiments, the second spacer 41B is absent. The materials of the first spacer 41A and the second spacer 41B can be the same or different. In some embodiments, the upper portion of the second spacer layer 41B (or the first spacer layer 41A when the second spacer layer is not present) may be partially or completely removed to increase the aspect ratio of the opening formed through the source / drain features 82N and 82P. FIG. 1A illustrates an embodiment in which the upper portion of the second spacer layer 41B is not thinned.

[0033] In an embodiment of the present invention, the side surfaces of the gate spacer 41 may be substantially free of the gate dielectric layer 600. For example, a certain percentage of the side surface of the gate spacer 41 may be covered by the gate dielectric layer 600, rather than being completely or mostly covered by the gate dielectric layer 600. This percentage may be in the range of approximately 2% to approximately 20%. Methods for reducing the area of ​​the gate dielectric layer 600 covering the side surfaces of the gate spacer 41 according to various embodiments are described with reference to FIG. 2A through FIG. 18.

[0034] FIG18 illustrates a flowchart of method 1000 for forming an integrated circuit device or a portion thereof, according to one or more aspects of an embodiment of the present invention. Method 1000 is merely an example and is not intended to limit embodiments of the present invention to the content explicitly shown in method 1000. Additional operations may be provided before, during, and after method 1000, and some described operations may be replaced, eliminated, or moved for other embodiments of the method. For the sake of simplicity, not all operations are described in detail herein. Method 1000 is described below with reference to partial perspective views and / or schematic cross-sectional views of a workpiece (as shown in FIG2A through FIG17 ) at various stages of fabrication according to an embodiment of method 1000. For the avoidance of doubt, in all figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X and Y directions. It should be noted that since the workpiece can be fabricated into a semiconductor device, the workpiece may be referred to as a semiconductor device, depending on the context.

[0035] 2A to 17 are schematic diagrams illustrating intermediate stages of fabricating a field effect transistor (eg, a nanostructured field effect transistor) according to some embodiments.

[0036] In Figures 2A and 2B, a substrate 110 is provided. Substrate 110 can be a semiconductor substrate, such as a bulk semiconductor or the like, and can be doped (e.g., p-type or n-type) or undoped. The semiconductor material of substrate 110 can include silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or combinations thereof. Other substrates can also be used, such as single-layer, multi-layer, or graded substrates.

[0037] In Figures 2A and 2B, a multilayer stack 25, or "lattice," is formed over a substrate 110. The multilayer stack 25 comprises alternating layers of first semiconductor layers 21A, 21B, and 21C (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23. In some embodiments, the first semiconductor layers 21 may be formed of a first semiconductor material, such as Si, SiGe, Ge, GaAs, InGaAs, GeSn, SiGeSn, MoS, WS2, or the like, while the second semiconductor layers 23 may be formed of a second semiconductor material, such as SiGe, Ge, Si, InGaAs, AlGaAs, GeSn, SiGeSn, or the like. Each of the first and second semiconductor layers 21 and 23 of the multilayer stack 25 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), and the like. Each of the first semiconductor layer 21 and the second semiconductor layer 23 that may form the multilayer stack 25 has a thickness in a range of about 1 nm to about 10 nm.

[0038] 2A and 2B show three first semiconductor layers 21 and four second semiconductor layers 23. In some embodiments, the multilayer stack 25 may include fewer or more first semiconductor layers 21 and second semiconductor layers 23. Although the multilayer stack 25 is shown as including the second semiconductor layer 23 as the bottommost and topmost layers, in some embodiments, the bottommost and / or topmost layers of the multilayer stack 25 may be the first semiconductor layer 21.

[0039] Due to the high etch selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form the channel region of the nanofield-effect transistor. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form the channel region. The high etch selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form the channel region of the nanofield-effect transistor.

[0040] In Figures 2A and 2B, a hard mask layer 28L is formed. The hard mask layer 28L can be a dielectric layer comprising one or more dielectric materials, such as SiO2, Si3N4, SiON, SiCN, SiCON, or the like. The hard mask layer 28L can be formed on the uppermost second semiconductor layer 23 using a suitable deposition process, such as chemical vapor deposition (CVD), including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or the like. The hard mask layer 28L can be or include one or more layers of SiO, SiN, SiON, SiCN, SiOCN, or the like, and can be formed to a thickness ranging from approximately 1 nm to approximately 10 nm.

[0041] In Figures 3A and 3B, fin 32 is formed in substrate 110, nanostructures (channel 22, nanostructure 24) are formed in multilayer stack 25, and hard mask structure 28 is also formed, corresponding to operation 1100 in Figure 18. In some embodiments, channel 22, nanostructure 24, and fin 32 can be formed by etching trenches in multilayer stack 25, hard mask layer 28L, and substrate 110. This etching process can be any suitable etching process, such as reactive ion etching (RIE), neutron beam etching (NBE), similar methods, or combinations thereof. This etching process can be anisotropic. The first nanostructure (channels 22A, 22B, 22C) (hereinafter also referred to as channel 22) is formed from first semiconductor layer 21, while the second nanostructure (nanostructure 24) is formed from second semiconductor layer 23, and hard mask structure 28 is formed from hard mask layer 28L. The distance CD1 between adjacent fins 32 and nanostructures (channels 22 and nanostructures 24) can be between approximately 18 nm and approximately 100 nm, although distances smaller or larger than these ranges may also be beneficial and are embodiments herein. For simplicity, the nanostructure device 10 shown in Figures 3A and 3B includes two fins 32. The method 1000 shown in Figure 18 can be extended to any number of fins, not just the two fins 32 shown in Figures 3A through 17.

[0042] Fins 32 and nanostructures (channels 22 and nanostructures 24) can be patterned using any suitable method. For example, fins 32 and nanostructures (channels 22 and nanostructures 24) can be patterned using one or more photolithography processes, including double or multiple patterning processes. Generally, double or multiple patterning processes combine photolithography with self-aligned processes to create patterns with smaller pitches, for example, than can be achieved using a single direct photolithography process. In one example of a multiple patterning process, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 32.

[0043] Figures 3A and 3B illustrate fins 32 having tapered sidewalls, such that the width of each of the fins 32 and / or nanostructures (channels 22 and nanostructures 24) continuously increases toward substrate 110. In these embodiments, each of the fins 32 and / or nanostructures (channels 22 and nanostructures 24) may have different widths and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of the fins 32 and / or nanostructures (channels 22 and nanostructures 24) are substantially similar, and each of the nanostructures (channels 22 and nanostructures 24) is rectangular.

[0044] In Figures 3A and 3B, an isolation region, a spacer feature, or an isolation structure 36 (which may be a shallow trench isolation (STI) region, a STI feature, or a STI structure) is formed adjacent to the fin 32. The isolation structure 36 may be formed by depositing an insulating material over the substrate 110, the fin 32, and the nanostructures (channel 22, nanostructure 24), and the hard mask structure 28, as well as between adjacent fins 32, nanostructures (channel 22, semiconductor layer 24), and the hard mask structure 28. The isolation material may be an oxide, such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. In some embodiments, a liner (not shown) may first be formed along the surfaces of substrate 110, fins 32, nanostructures (channels 22, nanostructures 24), and hard mask structure 28. Subsequently, a core material (such as discussed above) may be formed over the liner.

[0045] The insulating material undergoes a removal process (e.g., chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like) to remove excess insulating material above the nanostructures (channel 22, nanostructure 24) and hard mask structure 28. After the removal process is completed, the top surface of hard mask structure 28 is exposed and flush with the insulating material.

[0046] Next, the insulating material is recessed to form isolation structures 36. After the recessing, the upper portions of the nanostructures (channels 22 and nanostructures 24), hard mask structures 28, and fins 32 may protrude from between adjacent isolation structures 36. Isolation structures 36 may have top surfaces that are planar, convex, concave, or a combination thereof, as shown. In some embodiments, isolation structures 36 are recessed using a suitable etching process, such as oxide removal using dilute hydrofluoric acid (dHF), which is selective to the insulating material and leaves the fins 32, hard mask structures 28, and nanostructures (channels 22 and nanostructures 24) substantially unchanged.

[0047] Figures 2A-3B illustrate one embodiment of forming fins 32, hard mask structure 28, and nanostructures (channels 22 and nanostructures 24) (post-etching). In some embodiments, fins 32, hard mask structure 28, and / or nanostructures (channels 22 and nanostructures 24) are epitaxially grown or deposited in trenches in a dielectric layer (e.g., prior to etching). The epitaxial structure may include alternating semiconductor materials, such as a first semiconductor material and a second semiconductor material.

[0048] In Figures 3A and 3B, suitable well regions (not individually shown) may be formed in fin 32, nanostructures (channel 22, nanostructure 24), and / or isolation structure 36. Using a mask, n-type impurity implantation may be performed in the p-type region of substrate 110, while p-type impurity implantation may be performed in the n-type region of substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, or the like. Exemplary p-type impurities may include boron, boron fluoride, indium, or the like. Following implantation, an annealing step may be performed to repair implantation damage and activate the p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of fin 32 and nanostructures (channel 22, nanostructure 24) may eliminate the need for individual implantation, although both in-situ and implantation doping may also be used.

[0049] In Figures 4A through 4C , a dummy gate structure 40 (sometimes referred to as a sacrificial gate structure) is formed over the fin 32, nanostructures (channel 22, nanostructure 24), and hard mask structure 28, corresponding to operation 1200 in Figure 18 . A dummy gate layer 45 (sometimes referred to as a sacrificial gate layer) is formed over the fin 32 and / or nanostructures (channel 22, nanostructure 24). The dummy gate layer 45 can be or include a material having a high etch selectivity relative to the isolation structure 36. The dummy gate layer 45 can be a conductive, semiconducting, or non-conductive material, and can be or include amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 45 can be deposited by physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition, or other techniques suitable for depositing the selected material. A mask layer 47 is formed over the dummy gate layer 45 and can include, for example, silicon nitride, silicon oxynitride, or the like. In some embodiments, prior to forming the dummy gate layer 45, a dummy gate dielectric layer 43 (sometimes referred to as a liner layer) is formed between the dummy gate layer 45 and the fin 32 and nanostructure (channel 22, nanostructure 24). In some embodiments, the dummy gate dielectric layer 43 is or includes one or more dielectric materials (e.g., Si3N4, SiO2, SiON, or the like), one or more semiconductors (including Si, SiGe, combinations thereof, or the like). The thickness of the dummy gate dielectric layer 43 can be in a range from approximately 0.5 nm to approximately 10 nm. In some embodiments, mask layer 47 includes a first mask layer 47A contacting dummy gate layer 45 and a second mask layer 47B contacting and overlying first mask layer 47A. First mask layer 47A may be made of or include the same material as or a different material than second mask layer 47B. In some embodiments, nanostructure 24 may be removed before forming dummy gate dielectric layer 43, and then a dielectric layer or oxide layer may be gapfilled in place of nanostructure 24.

[0050] Gate spacers 41 are formed on the sidewalls of the mask layer 47 and the dummy gate layer 45. As shown in FIG. 4A , the lower portion of the gate spacers 41 extends downward between adjacent stacks of nanostructures (channel 22, nanostructure 24) and rests on the upper surface of the isolation structure 36. In some embodiments, the gate spacers 41 are or include an insulating material such as SiCON, SiON, SiOC, Si3N4, SiO2, or the like, and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The gate spacers 41 may be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. In some embodiments, an anisotropic etching process is used to remove the portion of the spacer material layer between the dummy gate structures 40. In some embodiments, as shown in Figures 4B and 4C, the gate spacer 41 includes a first spacer 41A that contacts the channel 22C, a dummy gate dielectric layer 43, a dummy gate layer 45, and first and second mask layers 47A and 47B. The second spacer 41B of the gate spacer 41 may contact the first spacer 41A. The first spacer 41A may be made of or include a material that is the same as or similar to that of the second spacer 41B. The thickness of the gate spacer 41 may be in a range from approximately 2 nm to approximately 20 nm.

[0051] In Figures 5A through 5C , source / drain openings 59 are formed by performing an etching process to etch the portions of the protruding fin 32, hard mask structure 28, and / or nanostructures (channel 22, nanostructure 24) not covered by the dummy gate structure 40. This etching process can be anisotropic, so that the portion of the fin 32 directly beneath the dummy gate structure 40 and gate spacer 41 is protected and substantially unetched. In some embodiments, the top surface of the recessed fin 32 can be substantially coplanar with the top surface of the isolation structure 36. In some other embodiments, as shown in Figures 5A and 5C , the top surface of the recessed fin 32 can be lower than the top surface of the isolation structure 36. For simplicity, Figure 5A shows a vertical stack of three nanostructures (channel 22, nanostructure 24) before performing the etching process. In general, the etching process can be used to form fewer or more vertical stacks of nanostructures (channel 22, nanostructure 24) above the fin 32 than shown. In some embodiments, the second mask layer 47B is exposed after the etching process because the upper portions of the first and second spacers 41A, 41B are removed during the etching process. FIG. 8C shows a fin spacer 41F, which is the portion of the first and / or second spacers 41A, 41B above the isolation structure 36 adjacent to the corresponding fin 32.

[0052] In Figures 6A and 6B, recess 64 is formed by removing the end of nanostructure 24. For example, a selective etching process is performed to recess the end of nanostructure 24 exposed by source / drain openings 59 while substantially leaving channel 22 untouched or slightly thinning the end of channel 22. After the selective etching process, recess 64 is formed in nanostructure 24 at the location where the removed end was previously located. Next, after recess 64 is formed, an internal spacer layer 74L is formed to (partially or completely) fill the recess in nanostructure 24 previously formed by the selective etching process. Internal spacer layer 74L can be a suitable dielectric material, such as SiO2, Si3N4, SiON, SiCN, SiCON, or the like, and can be formed by a suitable deposition method, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like.

[0053] In Figures 7A and 7B , after forming the inner spacer layer 74L, an anisotropic etching process is performed to remove portions of the inner spacer layer 74L disposed outside the recess (e.g., portions on the sidewalls of the channel 22 and the fin 32). The remaining portions of the inner spacer layer 74L (e.g., portions disposed within the recess in the nanostructure 24) form inner spacers 74. The thickness of the inner spacers 74 can range from approximately 1 nm to approximately 10 nm. This thickness can represent the thickness in the X-axis direction shown in Figure 7A , the thickness in the Z-axis direction shown in Figure 7A , or both.

[0054] In the description of forming the inner spacers 74 provided with reference to Figures 6A-7B, the inner spacers 74 are formed in the recess 64 adjacent to the nanostructures 24 between the channels 22 and between the topmost channel 22C and the hard mask structure 28. In some embodiments, before forming the inner spacer 74L, the hard mask structure 28 may be recessed (e.g., the ends of the hard mask structure 28 are removed) in the same or different etch process used to form the recess 64. Subsequently, during the formation of the inner spacers 74 adjacent to the recessed nanostructures 24, additional inner spacers may be formed adjacent to the recessed hard mask structure 28. The inner spacers adjacent to the hard mask structure 28 have a different etch selectivity than the hard mask structure 28, which may be beneficial in providing electrical isolation between the gate structure 200, which may replace the hard mask structure 28, and the adjacent source / drain features 82P and 82N. The locations of the recesses and inner spacers adjacent to the hard mask structure 28 are shown in dashed lines in Figures 6A and 7A.

[0055] In FIG. 8A , a first semiconductor layer 110A is formed in the source / drain openings 59 . In some embodiments, the first semiconductor layer 110A is an undoped silicon layer that can be deposited or epitaxially grown on the exposed surfaces of the fins 32 . This deposition can include one or more operations, such as chemical vapor deposition (which can be ultra-high vacuum chemical vapor deposition (UHV-CVD)), which allows for improved control of the deposition rate and purity of the first semiconductor layer 110A. In some embodiments, a silicon-containing precursor gas can be introduced into the processing chamber, and a reaction therebetween forms a silicon material that is deposited in the source / drain openings 59 . In some embodiments, the first semiconductor layer 110A has an upper surface that is substantially coplanar with the upper surface of the fins 32 .

[0056] In FIG. 8A , source / drain features 82 (sometimes referred to as source / drains) are formed. In the illustrated embodiment, source / drain features 82 are epitaxially grown from epitaxial material. In some embodiments, source / drain features 82 impart stress in corresponding channels 22A, 22B, and 22C, thereby improving performance. Source / drain features 82 are formed such that each dummy gate structure 40 is disposed between adjacent pairs of source / drain features 82. In some embodiments, gate spacers 41 separate source / drain features 82 from dummy gate layer 45 by a suitable lateral distance to prevent electrical bridging to the gate of the subsequently formed final device. Source / drain features 82 may be or include Si:B, Si:Ga, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or the like. Source / drain features 82 may be or include SiP, SiAs, SiSb, SiPAs, SiP:As:Sb, or the like. The source / drain features 82 can apply compressive or tensile stress to the channel region. The source / drain features 82 can have surfaces that protrude from corresponding surfaces of the first semiconductor layer 110A and can have facets. In some embodiments, adjacent source / drain features 82 can be merged to form a single source / drain feature 82 adjacent to two adjacent fins 32.

[0057] In Figures 8A and 8B, after forming the source / drain features 82, an interlayer dielectric 130 may be formed covering the source / drain features 82 and adjacent to the gate spacers 41. In some embodiments, an etch stop layer 131 is formed before forming the interlayer dielectric 130. The etch stop layer 131 may be formed by depositing a compliant thin layer of a dielectric material different from that of the interlayer dielectric 130, such as one or more of SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlOx, HfAlOx, HfSiOx, Al2O3, or other suitable materials. After depositing the etch stop layer 131, the interlayer dielectric 130 may be deposited using a suitable process, such as a blanket deposition process including physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. The material of the interlayer dielectric 130 may include silicon dioxide or a low-k dielectric material, such as a material having a dielectric constant (k value) lower than the k value of silicon dioxide (approximately 3.9). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y), spin-on-glass (SOG), or a combination thereof. The interlayer dielectric 130 may be deposited by spin coating, chemical vapor deposition, flowable chemical vapor deposition (FCVD), plasma-assisted chemical vapor deposition, physical vapor deposition, or other deposition processes.

[0058] 9A to 15F illustrate the formation of the gate structure 200 having a gate dielectric layer 600S having dimensions reduced by a selective etching process that removes a portion of the gate dielectric layer 600 from the sides of the gate spacer 41.

[0059] In Figures 9A to 9C , after forming the source / drain features 82, the etch stop layer 131, and the interlayer dielectric 130, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the interlayer dielectric 130 and the etch stop layer 131. The planarization process also removes portions of the first and second mask layers 47A, 47B, and the gate spacers 41. After the planarization process, the dummy gate layer 45 is exposed. The top surfaces of the interlayer dielectric 130 and the etch stop layer 131 may be coplanar with the top surfaces of the dummy gate layer 45 and the gate spacers 41.

[0060] Next, as shown in Figures 9A to 9C , the dummy gate layer 45 is removed in an etching process to form a gate opening 92. In some embodiments, the dummy gate layer 45 is removed using an anisotropic dry etching process. For example, the etching process may include a wet etching process or a dry etching process using a reactive gas that selectively etches the dummy gate layer 45 without etching the gate spacers 41. The dummy gate dielectric layer 43 (if present) may serve as an etch stop when etching the dummy gate layer 45. After removing the dummy gate layer 45, the dummy gate dielectric layer 43 may be removed. Figure 9B is a perspective view taken along line B'-B' of Figure 9A.

[0061] Next, nanostructure 24 is removed to release the nanostructure (channel 22), corresponding to operation 1300 in FIG. 18 . After nanostructure 24 is removed, the nanostructure (channel 22) forms a plurality of nanosheets extending horizontally (e.g., parallel to the major upper surface of substrate 110, e.g., in the XY plane). In some embodiments, nanostructure 24 is removed by a selective etching process using an etchant selective for the material of nanostructure 24, such that nanostructure 24 is removed without substantially attacking the nanostructure (channel 22). In some embodiments, the etching process is an isotropic etching process using an etching gas and a selective carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, combinations thereof, or the like.

[0062] In some embodiments, nanostructure 24 is removed and the nanostructure (channel 22) is patterned to form the channel regions of the p-type field-effect transistor and the n-type field-effect transistor. However, in some embodiments, nanostructure 24 may be removed and the nanostructure (channel 22) patterned to form the channel region of the n-type field-effect transistor, and the nanostructure (channel 22) may be removed and the nanostructure 24 patterned to form the channel region of the p-type field-effect transistor. In some embodiments, nanostructure (channel 22) may be removed and the nanostructure 24 patterned to form the channel region of the n-type field-effect transistor, and the nanostructure 24 may be removed and the nanostructure (channel 22) patterned to form the channel region of the p-type field-effect transistor. In some embodiments, nanostructure (channel 22) is removed and the nanostructure 24 patterned to form the channel region of the p-type field-effect transistor and the n-type field-effect transistor.

[0063] In some embodiments, channel 22 (nanosheet) is further etched to reshape (e.g., thin) the channel 22 to improve gate fill margin. This reshaping can be performed using an isotropic etch process that is selective for channel 22. After reshaping, channel 22 may exhibit a dog-bone shape, where the middle portion of channel 22 is thinner than the edges of channel 22 along the X-direction.

[0064] In Figures 10A to 15G , a gate structure 200 is formed in the gate opening 92. To provide context for understanding the embodiment of reducing the gate dielectric layer 600 to form a reduced gate dielectric layer 600S, a description of the materials and processes used to form the various layers of the gate structure 200 is provided with reference to Figure 16 .

[0065] FIG16 is a detailed schematic diagram of a portion of a gate structure 200 (sometimes referred to as a replacement gate) between channel 22B and channel 22C. Gate structure 200 generally includes an interfacial layer (IL) 210 (hereinafter also referred to as a first interfacial layer), at least one gate dielectric layer 600, a work function metal layer 900, and a metal core layer 290 (sometimes referred to as a gate fill layer). In some embodiments, each gate structure 200 further includes at least one of a second interfacial layer 240 or a second work function metal layer 700.

[0066] Referring to FIG. 16 , in some embodiments, the interfacial layer 210 comprises an oxide of the semiconductor material of the substrate 110, such as silicon oxide. In other embodiments, the interfacial layer 210 may comprise other suitable dielectric materials. The interfacial layer 210 has a thickness ranging from approximately 5 Å to approximately 50 Å. The interfacial layer 210 may be formed by thermal oxidation, chemical vapor deposition, atomic layer deposition, or similar methods.

[0067] Referring again to FIG. 16 , a gate dielectric layer 600 is formed above the interfacial layer 210. In some embodiments, an atomic layer deposition (ALD) process is used to form the gate dielectric layer 600, allowing precise control of the thickness of the gate dielectric layer 600. In some embodiments, the ALD process is performed using approximately 40 to 80 deposition cycles at a temperature ranging from approximately 200°C to approximately 300°C. In some embodiments, the ALD process uses HfCl₄ and / or H₂O as precursors. This ALD process can form the gate dielectric layer 600 with a thickness ranging from approximately 10 Å to approximately 100 Å.

[0068] In some embodiments, the gate dielectric layer 600 comprises a high-k dielectric material, which may refer to a dielectric material having a high k dielectric constant greater than that of silicon oxide (k ≈ 3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In other embodiments, the gate dielectric layer 600 may comprise a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 comprises more than one high-k dielectric layer, at least one of which includes a dopant, such as lanthanum, magnesium, yttrium, or the like. The dopant is driven in through an annealing process to alter the threshold voltage of the nanostructure devices 20A, 20B. In some embodiments of the present invention, the gate dielectric layer 600 is reduced to form a reduced gate dielectric layer 600S.

[0069] Referring again to FIG. 16 , an optional second interfacial layer 240 is formed on the gate dielectric layer 600 (or the reduced gate dielectric layer 600S), and a second work function metal layer 700 is formed on the second interfacial layer 240. The second interfacial layer 240 promotes better metal gate adhesion on the gate dielectric layer 600 (or the reduced gate dielectric layer 600S). In many embodiments, the second interfacial layer 240 further provides improved thermal stability for the gate structure 200 and serves to limit the diffusion of metal impurities from the work function metal layer 900 and / or the second work function metal layer 700 (sometimes referred to as a work function barrier layer) into the gate dielectric layer 600. In some embodiments, the second interfacial layer 240 is formed by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer comprises one or more of the following: HfSiON, HfTaO, HfTiO, HfAlON, HfZrO, or other suitable materials. In one embodiment, the high-k capping layer comprises titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited using about 40 to about 100 cycles of atomic layer deposition at a temperature of about 400°C to about 450°C. Subsequently, in some embodiments, an anneal is performed to form a second interfacial layer 240, which may be or include TiSiN. After forming the second interfacial layer 240 via thermal annealing, an atomic layer etch (ALE) process may be performed using artificial intelligence (AI) controlled cycles to remove the high-k capping layer while substantially leaving the second interfacial layer 240 intact. Each cycle may include a first pulse of WCl₂, followed by an Ar purge, followed by a second pulse of O₂, and then another Ar purge. The high-k cap layer is removed to increase the gate fill margin, allowing for further adjustment of multiple threshold voltages through metal gate patterning.

[0070] Furthermore, in FIG. 16 , according to some embodiments, after forming the second interfacial layer 240 and removing the high-k capping layer, a second workfunction metal layer 700 is selectively formed on the intermediate-stage gate structure 200 (e.g., on the second interfacial layer 240 or the reduced gate dielectric layer 600S). The second workfunction metal layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, or the like. In one embodiment, the second workfunction metal layer 700 is TiN. The second workfunction metal layer 700 may have a thickness in a range of approximately 5 Å to approximately 20 Å. The inclusion of the second workfunction metal layer 700 provides additional threshold voltage adjustment flexibility. Generally, the second workfunction metal layer 700 increases the threshold voltage for n-type field-effect transistor devices and decreases the threshold voltage (scale) for p-type field-effect transistor devices.

[0071] In some embodiments, a work function metal layer 900 (which may include at least one of an n-type work function metal layer, an in-situ capping layer, or an oxygen barrier layer) is formed on the second work function metal layer 700. The n-type work function metal layer is or includes an n-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, or the like. The n-type work function metal layer can be formed by one or more deposition methods, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, and / or other suitable methods, and has a thickness between approximately 10 Å and approximately 20 Å. The in-situ capping layer is formed on the n-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN, or other suitable materials, and has a thickness between approximately 10 Å and approximately 20 Å. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the n-type work function metal layer, which could cause an undesirable shift in threshold voltage. The oxygen barrier layer is formed of a dielectric material that prevents oxygen from penetrating into the n-type work function metal layer and protects the n-type work function metal layer from further oxidation. The oxygen barrier layer may comprise an oxide of silicon, germanium, silicon germanium, or other suitable materials. In some embodiments, the oxygen barrier layer is formed using atomic layer deposition and has a thickness between approximately 10 Å and approximately 20 Å.

[0072] FIG. 16 further illustrates metal core layer 290. In some embodiments, an adhesion layer (not shown separately) is formed between the oxygen barrier layer of the work function metal layer and metal core layer 290. The adhesion layer can promote and / or enhance adhesion between metal core layer 290 and work function metal layer 900. In some embodiments, the adhesion layer can be formed using atomic layer deposition from a metal nitride, such as TiN, TaN, MoN, WN, or other suitable materials. In some embodiments, the thickness of the adhesion layer is between approximately 10 Å and approximately 25 Å. Metal core layer 290 can be formed on the adhesion layer and can include a conductive material, such as tungsten, cobalt, ruthenium, yttrium, molybdenum, copper, aluminum, or a combination thereof. In some embodiments, metal core layer 290 can be deposited using methods such as chemical vapor deposition, physical vapor deposition, plating, and / or other suitable processes. In some embodiments, a gap 530 (which can be an air gap) is formed vertically in metal core layer 290 between channels 22A, 22B, and 22C. In some embodiments, the metal core layer 290 is conformally deposited on the work function metal layer 900. The gap 530 may be formed due to merging of the sidewall deposited films during the conformal deposition. In some embodiments, the gap 530 does not exist between adjacent channels 22A, 22B, 22C.

[0073] In some embodiments, one or more metal layers in a p-type field effect transistor device, including the metal core layer 290, the second work function metal layer 700, and the work function metal layer 900, may include Ti, Al, Zn, W, Nb, Co, and the like, and the combined thickness of the metal layers on the gate dielectric layer 600 may be in a range of approximately 0.5 nm to approximately 20 nm. In some embodiments, one or more metal layers in an n-type field effect transistor device, including the metal core layer 290, the second work function metal layer 700, and the work function metal layer 900, may include Ti and / or Al, and the like, and the combined thickness of the metal layers on the gate dielectric layer 600 may be in a range of approximately 0.5 nm to approximately 20 nm. In some embodiments, one or more of the second interface layer 240, the second work function metal layer 700, and the work function metal layer 900 may be omitted.

[0074] In Figures 10A and 10B, an interfacial layer 210 is formed on the exposed surfaces of the channel 22 and the fin 32, similar to the description with reference to Figure 16. In some embodiments, the interfacial layer 210 comprises an oxide of the semiconductor material of the channel 22 and / or substrate 110, and may include SiO2, SiON, HfSiOx, LaSiOx, YSiOx, AlSiOx, or the like. The interfacial layer 210 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, or the like. When the material of the channel 22 is different from the material of the fin 32, the interfacial layer 210 on the channel 22 may be a different material than the interfacial layer 210 on the fin 32. In some embodiments, the interfacial layer 210 has a thickness in a range from about 5 Å to about 50 Å. Generally, the interfacial layer 210 is not present on (e.g., not grown on) the hard mask structure 28 or the gate spacer 41, as shown in Figures 10A and 10B.

[0075] After forming the interfacial layer 210, a gate dielectric layer 600 is formed on the exposed surfaces of the gate spacer 41, the hard mask structure 28, the inner spacer 74 (also depicted in dashed lines in FIG. 10 ), and the interfacial layer 210 (e.g., on the channel 22 and the fin 32), corresponding to operation 1400 of FIG. 18 . The gate dielectric layer 600 can be formed by one or more non-selective growth processes, such as chemical vapor deposition, atomic layer deposition, or the like, and can include one or more dielectric materials, such as HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , HfZrO x , HfLaO x , HfAlO x , HfYO x , HfSiO x , HfSiON, or the like. The thickness of the gate dielectric layer 600 is in the range of about 0.5 nm to about 5 nm. The gate dielectric layer 600 can completely or substantially completely cover the side surfaces of the gate spacer 41, as shown in FIG. 10B . The gate dielectric layer 600 may extend from a first level H1 above the nanostructure channel to a second level H2 below the nanostructure channel. The first level H1 may be the upper surface of the gate spacer 41, the interlayer dielectric 130, and / or the etch stop layer 131. The second level H2 may be the upper surface of the isolation structure 36 and / or the fin 32. The gate dielectric layer 600 includes a portion 600A' covering the side surfaces of the gate spacer 41, a portion 600B covering the inner spacer 74, and a portion 600C covering the channel 22 and the hard mask structure 28.

[0076] In Figures 11A and 11B, after forming the gate dielectric layer 600, a sacrificial interposer 500 is formed on the gate dielectric layer 600, for example, on the gate spacers 41, the hard mask structure 28, the inner spacers 74, the channel 22, and the fin 32. The sacrificial interposer 500 may be or include a material suitable for selective growth thereon. In some embodiments, the sacrificial interposer 500 comprises TiN, Si, Ge, W, Al2O3, or the like. The material of the sacrificial interposer 500 may be or include a material suitable for selective growth of the same or different materials thereon. For example, tungsten or TiN may be grown on the exposed surface of the TiN. In another example, TiN may be grown on the exposed surface of the TiN or Al2O3. In another example, Si, SiGe, or W may be grown on the exposed surface of the Si. The sacrificial interposer 500 can be formed by a suitable growth process, such as chemical vapor deposition, atomic layer deposition, or the like, and is merged between the channels 22 to protect the portion 600B of the gate dielectric layer 600 on the inner spacers 74 and the portion 600C of the gate dielectric layer 600 on the channels 22 and the hard mask structure 28. The sacrificial interposer 500 may or may not be merged over the hard mask structure 28. In FIG. 11A , the sacrificial interposer 500 is not merged over the hard mask structure 28, so that a thin layer of the sacrificial interposer 500 is present on the gate spacers 41 on either side of the gate opening 92. The thickness of the sacrificial interposer 500 can be in the range of about 1 nm to about 10 nm.

[0077] In FIG. 12A to FIG. 12D , after depositing the sacrificial interposer 500 , a sacrificial plug 500 ′ and a protection structure 510 are formed. The sacrificial plug 500 ′ and the protection structure 510 can be used as a mask 520 during the reduction of the area of ​​the gate dielectric layer 600 to form a reduced gate dielectric layer 600S.

[0078] In Figures 12A and 12B, after depositing the sacrificial interposer 500, the sacrificial material of the sacrificial interposer 500 is trimmed back, stopping at portion 600C of the gate dielectric layer 600, to remove the sacrificial material from the sides of the gate spacers 41 via a dry or wet etch. After the removal operation, the sacrificial plug 500' remains between the nanostructures (channels 22) and between the nanostructures 24 and the hard mask structure 28. The etch of the sacrificial material of the sacrificial interposer 500, which selectively stops at the gate dielectric layer 600, can be performed by an etch operation that may include SC1, SC2, HCl, NH4OH, H2O2, combinations thereof, or the like. After the etch operation, portions of the gate dielectric layer 600 at the ends of the nanostructures (channels 22) and at the ends of the hard mask structure 28 can be exposed. After the etch operation, the upper surface of the hard mask structure 28 can also be exposed.

[0079] Next, in Figures 12C and 12D , after trimming the sacrificial interposer 500 to form the sacrificial plug 500', a protective structure 510 is grown on the exposed surface of the sacrificial plug 500' to protect the exposed side surfaces of the portion 600C of the gate dielectric layer 600 overlying the via 22. The growth of the protective structure 510 on the sacrificial plug 500' can be selective, such that growth occurs on the exposed surface of the sacrificial plug 500' but not on the exposed surface of the gate dielectric layer 600, such as the portion 600C of the gate dielectric layer 600. The selective growth of the protective structure 510 can be or include atomic layer deposition or chemical vapor deposition. This selective growth can form a second material on the first material of the sacrificial plug 500'. For example, the first material can be TiN, and the second material can be W or TiN. In another example, the first material can be Al2O3, and the second material can be TiN. In another example, the first material may be Si, and the second material may be Si, SiGe, or W. As can be seen from the above examples, the second material may be the same as or different from the first material. The growth of the protection structure 510 may initially proceed laterally outward from the sacrificial plug 500', for example, in the Y-axis direction. Subsequently, the initially grown portion of the protection structure 510 may begin to grow perpendicularly in the Z-axis direction and eventually merge near the end of the channel 22, resulting in the side coverage of the portion 600C of the gate dielectric layer 600. In some embodiments, as shown in FIG. 12D , due to how the protection structure 510 merges near the channel 22, a notch 510N may exist in the protection structure 510 adjacent to the channel 22. Due to the notch 510N, the protection structure 510 may have a non-uniform width in the Y-axis direction along its height in the Z-axis direction. In some embodiments, the width W1 of the protection structure 510 may range from approximately 1 nm to approximately 20 nm. In some embodiments, the width W1 of the protective structure 510 can be measured as a percentage of the distance D1 between adjacent stacks of channels 22, as shown in FIG. 12D . In some embodiments, this percentage ranges from about 1% to about 40%. For example, the distance D1 can range from about 18 nm to about 100 nm. In this example, when the distance D1 is about 18 nm, the width W1 is about 1 nm, resulting in a percentage of about 5% to about 6%.

[0080] After forming the mask 520 including the sacrificial plug 500′ and the protection structure 510, a portion 600A″ of the gate dielectric layer 600 may be exposed in the gate opening 92. The portion 600A″ may be slightly smaller than the portion 600A′ described with reference to FIGS. 10A and 10B because the protection structure 510 partially covers the portion of the gate dielectric layer 600 between the stacked structures of the channel 22.

[0081] In Figures 13A and 13B, after forming a mask 520 including the sacrificial plug 500' and the protection structure 510, the exposed portion 600A" of the gate dielectric layer 600 on the gate spacer 41 is removed, corresponding to operation 1500 of Figure 18. The exposed portion 600A" of the gate dielectric layer 600 can be removed by a selective removal operation that removes material of the gate dielectric layer 600 from the sidewalls of the gate spacer 41 while retaining a portion 600C of the gate dielectric layer 600 on the channel 22 protected by the mask 520 including the sacrificial plug 500' and the protection structure 510. This removal operation can include high etch selectivity between the materials of the gate dielectric layer 600 and the protection structure 510, such as an HF-based or H2SO4-based wet etch for Si and HfO2, an HF-based or NF3-based dry etch for TiN and HfO2, and the like. This removal operation removes the exposed portion 600A″ of the gate dielectric layer 600 on the gate spacer 41 and removes the portion of the gate dielectric layer 600 on the upper surface of the hard mask structure 28. As shown in Figures 13A and 13B, the removal operation also removes material of the gate dielectric layer 600 above the isolation structure 36, exposing the upper surface of the isolation structure 36 in the gate opening 92.

[0082] In some embodiments, as shown in Figures 13C and 13D , after removing portion 600A″ of gate dielectric layer 600, a low-k spacer layer 42 may be formed on the exposed surfaces of gate spacer 41 and isolation structure 36. The low-k spacer layer 42 may be or include a low-k dielectric material, such as SiO, SiOC, SiN, organosilicate glass (OSG), or the like. The low-k spacer layer 42 may be formed by a suitable deposition process, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. After forming the low-k dielectric material (which may form a thin compliant layer on gate spacer 41, isolation structure 36, and hard mask structure 28), an anisotropic etch may be performed to remove the low-k spacer layer 42 material from the upper surface of hard mask structure 28. Forming the low-k spacers 42 before removing the mask 520 allows the mask 520 to protect the spaces between the channels 22 during the formation of the low-k spacers 42 and prevents the low-k spacers 42 from forming between the channels 22. This can help increase the gate fill margin for depositing one or more layers of the gate structure 200 after forming the reduced gate dielectric layer 600S. Forming the low-k spacers 42 can help reduce effective capacitance and increase gate-to-source / drain contact reliability by reducing leakage. In embodiments where the low-k spacers 42 are not formed, the increased spacing between the gate spacers 41 by removing the gate dielectric layer 600 from the gate spacers 41 can improve scaling. In some embodiments where the low-k spacers 42 are not formed, the increased volume between the gate spacers 41 by removing the gate dielectric layer 600 from the gate spacers 41 can reduce gate resistance (Rg).

[0083] In Figures 14A through 14F , after the gate dielectric layer 600 is reduced in size to form a reduced gate dielectric layer 600S, and after the selective formation of the low-k spacer 42 as discussed with reference to Figures 13C and 13D , the mask 520 can be removed. The protective structure 510 and the sacrificial plug 500' can be stripped by a wet or dry etch, stopping at the reduced gate dielectric layer 600S. The wet or dry etch can include SC1, SC2, HCl, NH4OH, H2O2, combinations thereof, or the like. As shown in Figures 14A and 14B , the reduced gate dielectric layer 600S remains on the nanostructure (channel 22) and the inner spacer 74.

[0084] As shown in Figures 14A and 14B, the reduced gate dielectric layer 600S may include a portion 600A (gate spacer portion) on the gate spacer 41 and a portion 600B (inner spacer portion) on the inner spacer 74 and the notch 600N. Portions 600A and 600B follow the contours of the mask 520. Due to the notch 600N, portion 600A may have a non-uniform width in the Y-axis direction along its height in the Z-axis. In some embodiments, the width W1 of portion 600A may be in a range from approximately 1 nm to approximately 20 nm. In some embodiments, the width W1 of portion 600A may be measured as a percentage of the distance D1 between adjacent stacks of channel 22, as shown in Figure 14B. In some embodiments, this percentage is in a range from approximately 1% to approximately 40%. For example, distance D1 may be in a range from approximately 18 nm to approximately 100 nm. In this example, when the distance D1 is approximately 18 nm, the width W1 is approximately 1 nm, resulting in a percentage ranging from approximately 5% to approximately 6%. In some embodiments, the reduced gate dielectric layer 600S may cover a portion of the surface area of ​​the side surface of the gate spacer 41. In some embodiments, this portion can be measured as a percentage of the surface area of ​​the gate spacer 41. For example, the portion of the gate spacer 41 covered by the reduced gate dielectric layer 600S may be in a range from approximately 0.5% to approximately 50%. In some embodiments, this portion may be in a range from approximately 5% to approximately 40%.

[0085] In FIG. 14C , after removing the mask 520, the hard mask structure 28 can be removed. The etching process used to remove the hard mask structure 28 can include wet chemical etching using hydrofluoric acid, hot phosphoric acid, plasma etching using CF₄ / CHF₃, reactive ion etching (RIE) using fluorine-based or chlorine-based chemistries, or similar methods. The etching process can remove the hard mask structure 28 while substantially not attacking the gate dielectric layer 600S, the isolation structure 36, and the gate spacers 41. In the embodiment shown in FIG. 14C , after removing the hard mask structure 28, a portion 600C of the upper surface of the hard mask structure 28 can be exposed.

[0086] In Figures 14D through 14F, low-k spacers 42 are formed after the mask 520 is removed. The formation of low-k spacers 42 is similar in most respects to that described with reference to Figures 13C and 13D. Because low-k spacers 42 are formed without hard mask 520 between channels 22, they can be deposited on portions 600C between channels 22, as shown in Figure 14D. Figure 14F shows that low-k spacers 42 can be present on portions of gate spacers 41 exposed after the hard mask structure 28 is removed.

[0087] In Figures 15A to 15I , after removing the hard mask 520 and optionally forming the low-k dielectric spacer 42, one or more additional layers of the gate structure 200, including a metal core layer 290 (sometimes also referred to as a conductive layer), are formed in the gate opening 92, corresponding to operation 1600 of Figure 18 . The metal core layer 290 is depicted in Figure 15A . As described with reference to Figure 16 , additional layers (e.g., the second interface layer 240, the second work function metal layer 700, and the work function metal layer 900, or a combination thereof) may be located between the metal core layer 290 and the reduced gate dielectric layer 600S, as well as between the metal core layer 290 and the gate spacer 41 in areas where the gate dielectric layer 600S is not reduced. Figure 15G is a plan view taken through the XY plane of the inner spacer 74 of Figures 15A and 15B . Figure 15H is a plan view taken through the XY plane of the channel 22C of Figures 15A and 15B . Due to the reduction in the area of ​​the gate dielectric layer 600, a reduced gate dielectric layer 600S including portions 600A and 600B is formed. The portions 600A and 600B that expose the gate spacers 41 and the side surfaces of the metal core layer 290 may be adjacent to or directly contact the gate spacers 41 between the portions 600A. As shown in FIG. 15G , due to the presence of the reduced gate dielectric layer 600S, the metal core layer 290 may directly contact the exposed portions of the gate spacers 41 (e.g., the portions of the gate spacers 41 not covered by the portions 600B and 600A of the reduced gate dielectric layer 600S). In some embodiments, as described with reference to FIG. 16 , additional layers may be located between the metal core layer 290 and the gate spacers 41. For example, the second interface layer 240, the second work function metal layer 700, the work function metal layer 900, the selective adhesion layer, or a combination thereof may be present between the metal core layer 290 and the gate spacer 41, with the unreduced gate dielectric layer 600S interposed therebetween. For example, the second interface layer 240 may directly contact the gate spacer 41. In another example, the second work function metal layer 700 may directly contact the gate spacer 41. In another example, the work function metal layer 900 may directly contact the gate spacer 41.

[0088] Figures 15C and 15D depict an embodiment in which a low-k dielectric constant spacer 42 is present on the portion of the gate spacer 41 exposed through the reduced gate dielectric layer 600S. Figure 15I is a plan view taken through the XY plane of the inner spacer 74 of Figures 15C and 15D. In embodiments in which the low-k dielectric constant spacer 42 is present, the metal core layer 290, the second interface layer 240, the second work function metal layer 700, or the work function metal layer 900 may be separated from the gate spacer 41 by the low-k dielectric constant spacer 42. For example, the second interface layer 240, the second work function metal layer 700, the work function metal layer 900, a selective adhesion layer, or a combination thereof may be present between the metal core layer 290 and the gate spacer 41, with the low-k dielectric constant spacer 42 therebetween. For example, the second interface layer 240 may directly contact the low-k dielectric constant spacer 42. In another example, the second work function metal layer 700 may directly contact the low-k dielectric constant spacer 42. In another example, the work function metal layer 900 may directly contact the low-k dielectric constant spacer 42. In some embodiments, a first portion of the metal core layer 290 may be separated from the gate spacer 41 by the reduced gate dielectric layer 600S, while a second portion of the metal core layer 290 may be separated from the gate spacer 41 by the low-k dielectric constant spacer 42. In some embodiments, the second portion has an area greater than the first portion.

[0089] 15E and 15F illustrate embodiments in which the hard mask structure 28 is not present because the hard mask structure 28 is removed in an operation prior to forming the metal core layer 290. In these embodiments, the metal core layer 290 and the optional second interface layer 240 and / or the second work function metal layer 700 and the work function metal layer 900 may fill the space previously occupied by the hard mask structure 28. In some embodiments, to physically and electrically isolate the gate structure 200 formed in the portion of the hard mask structure 28 adjacent to the source / drain features 82, the inner spacers 74HM described with reference to FIGS. 6A to 7B may be located between the gate structure 200 and the source / drain features 82, as depicted by the dashed lines in FIGS. 15E and 15F.

[0090] In FIG. 17 , after forming the gate structure 200, source / drain openings may be formed in the interlayer dielectric 130, and source / drain contacts 120 may be formed in the source / drain openings. The silicide layer 118 and the source / drain contacts 120 are formed on the source / drain features 82, which may be source / drain features 82P, source / drain features 82N, or a combination thereof.

[0091] In some embodiments, the silicide layer 118 is formed before forming the source / drain contacts 120. For example, an n-type or p-type metal layer can be formed as a thin, conformable layer on the exposed portions of the source / drain features 82. The metal layer can be or include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, or the like. In some embodiments, the metal layer is or includes one or more of Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or other suitable materials. After forming the metal layer, the silicide layer 118 can be formed by annealing the nanostructure device 10. After annealing, the silicide layer 118 may be or include one or more of NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, or the like. The silicide of the silicide layer 118 may diffuse into the area below the etch stop layer 131. The thickness of the silicide layer 118 may be in a range from about 1 nm to about 10 nm. If the thickness is less than 1 nm, the contact resistance may be too high. If the thickness is greater than 10 nm, the silicide layer 118 may short to the channel 22C.

[0092] After forming the silicide layer 118, source / drain contacts 120 are formed by filling openings above the source / drain features 82 with, for example, a liner layer and a filler layer. In some embodiments, the source / drain contacts 120 are formed by depositing a material that is or includes a conductive material, such as Co, W, Ru, combinations thereof, or the like. In some embodiments, the source / drain contacts 120 are or include a cobalt-based, tungsten-based, or ruthenium-based compound, or an alloy containing one or more elements, such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, or the like. The source / drain contacts 120 are located on the silicide layer 118 and contact the etch stop layer 131. The description and illustration of the nanostructure device 10 in many of the figures refer to a fully wrapped gate field effect transistor including a vertical stack of nanostructures (channels 22). In some embodiments, a silicide layer 118 and source / drain contacts 120 are formed in and on the source / drain features 82 of the FinFET device.

[0093] Additional processing may be performed to complete the fabrication of nanostructure devices 20A, 20B, and 20C. For example, gate contacts (or gate vias) may be formed to electrically couple to gate structure 200. Next, an interconnect structure may be formed over source / drain contacts 120 and the gate contacts. The interconnect structure may include multiple dielectric layers (including, for example, a second interlayer dielectric layer) surrounding metal features (including conductive traces and vias). This interconnect structure forms electrical connections between devices on substrate 110 (e.g., nanostructure devices 20A, 20B, and 20C), as well as electrical connections to integrated circuit devices outside of nanostructure device 10.

[0094] Embodiments of the present invention provide numerous advantages. By selectively removing portions of the gate dielectric layer 600 from the gate spacers 41 outside the channel 22 and inner spacers 74, parasitic capacitance can be reduced without sacrificing the on-state current Ion. This selective removal can be accomplished using a mask 520 comprising a sacrificial plug 500' and a protective structure 510 selectively formed longer than the sacrificial plug 500'.

[0095] According to at least one embodiment, a method is provided, comprising: forming a stack comprising a nanostructure channel, an interposer, and a hard mask structure by forming source / drain openings; forming a sacrificial gate structure on the stack; forming a spacer adjacent to the sacrificial gate structure; releasing the nanostructure channel by removing the interposer; forming a gate dielectric on sides of the nanostructure channel and the spacer; forming a reduced gate dielectric by removing a portion of the gate dielectric from sides of the spacer, the portion being laterally adjacent to the nanostructure channel; and forming a gate metal layer on the exposed portion of the reduced gate dielectric and the spacer.

[0096] In some other embodiments, the method further includes selectively growing a protection structure to cover an end portion of the gate dielectric over the nanostructure channel before removing the portion of the gate dielectric.

[0097] In some other embodiments, the step of selectively growing the protection structure includes: forming a sacrificial interposer between the nanostructure channels; and growing the protection structure on the exposed side surfaces of the sacrificial interposer.

[0098] In some other embodiments, the step of growing the protection structure includes growing the protection structure to have a first thickness adjacent to the sacrificial interposer that is greater than a second thickness adjacent to an end of the gate dielectric.

[0099] In some other embodiments, the step of removing the portion of the gate dielectric includes removing the portion of the gate dielectric exposed through the sacrificial interposer and the protection structure.

[0100] In some other embodiments, the method further includes removing the hard mask structure after removing the portion of the gate dielectric.

[0101] In some other embodiments, the method further includes forming a low-k dielectric layer on the exposed surface of the spacer layer above the hard mask structure after removing the portion of the gate dielectric.

[0102] According to at least one embodiment, a method is provided, comprising: forming a stack comprising alternating nanostructure channels and interposers by forming source / drain openings extending through alternating first and second semiconductor layers; releasing the nanostructure channels by removing the interposers; forming a gate dielectric over the nanostructure channels and on side surfaces of a spacer extending from a first level above the nanostructure channels to a second level below the nanostructure channels; forming a protection plug between the nanostructure channels; selectively growing a protection structure on exposed surfaces of the protection plugs; and removing a portion of the gate dielectric exposed through the protection plugs.

[0103] In some other embodiments, the step of forming the stack includes forming a hard mask structure above an uppermost interposer of the interposers during the formation of the source / drain openings.

[0104] In some other embodiments, the step of forming the protection plug includes forming one of the protection plugs between the uppermost interposer and the hard mask structure.

[0105] In some other embodiments, the step of selectively growing the protection structure includes growing tungsten on the protection plug comprising TiN or Si.

[0106] In some other embodiments, the step of selectively growing the protection structure includes growing TiN on a protection plug comprising TiN or Al 2 O 3 .

[0107] In some other embodiments, the step of selectively growing the protection structure includes growing silicon, silicon germanium, or tungsten on the protection plug comprising silicon.

[0108] In some other embodiments, the method further includes forming a metal gate layer on the nanostructure channel after removing the portion of the gate dielectric, wherein the metal gate layer has a first thickness vertically located in the space between the nanostructure channels and a second thickness outside the space, wherein the second thickness is greater than the first thickness.

[0109] According to at least one embodiment, a device is provided, comprising a first stack of nanostructures; a second stack of nanostructures adjacent to the first stack of nanostructures along a first direction; a source / drain adjacent to the first stack of nanostructures along a second direction transverse to the first direction; and a gate structure surrounding the first stack of nanostructures, the gate structure comprising: a gate dielectric comprising: a first portion extending between the first stack of nanostructures; and a second portion extending between the second stack of nanostructures, the first portion and the second portion being discontinuous in a region between the first stack of nanostructures and the second stack of nanostructures along the first direction; and a gate metal located on the gate dielectric, the gate metal extending between the first stack of nanostructures, between the second stack of nanostructures, and continuously between the first stack of nanostructures and the second stack of nanostructures in this region.

[0110] In some other embodiments, the device further includes a spacer layer adjacent to the gate dielectric and the gate metal along the second direction.

[0111] In some other embodiments, the gate metal directly contacts the spacer layer in this region and is separated from the spacer layer between the first stack of nanostructures and the second stack of nanostructures.

[0112] In some other embodiments, the device further includes a hard mask structure located above the topmost nanostructure in the first stack of nanostructures, wherein the gate dielectric surrounds the hard mask structure.

[0113] In some other embodiments, the first portion of the gate dielectric includes an outer portion extending beyond a side surface of the first stack of the nanostructure along a first direction.

[0114] In some other embodiments, the outer portion of the gate dielectric has a first thickness adjacent to the space between the first stack of nanostructures and a second thickness adjacent to the ends of the two nanostructures, and the first thickness is greater than the second thickness.

[0115] The foregoing description summarizes the features of many embodiments, enabling those skilled in the art to better understand the various aspects of the present invention. Those skilled in the art should understand and readily design or modify other processes and structures based on the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Various changes, substitutions, and modifications may be made to the present invention without departing from the spirit and scope of the present invention.

[0116] 10: Nanostructured devices 20A, 20B, 20C: Nanostructured devices 21, 21A, 21B, 21C: first semiconductor layer 22,22A,22B,22C: Channel 23: Second semiconductor layer 24: Nanostructure 25: Multilayer stack 28: Hard mask structure 28L: Hard mask layer 32: Fin 36: Isolation Structure 40: dummy gate structure 41: Gate spacer 41A: First spacer layer 41B: Second spacer layer 41F: Fin spacer 42: Low dielectric constant spacer layer 43: dummy gate dielectric layer 45: dummy gate layer 47: Mask layer 47A: First mask layer 47B: Second mask layer 59: Source / Drain Opening 64: Notch 74,74HM: Internal spacer 74L: Internal compartment 82,82N,82P: Source / drain components 92: Gate opening 110: Base 110A: first semiconductor layer 118: Silicide layer 120: Source / drain contact 130: Interlayer dielectric 131: Etching stop layer 200: Gate structure 210: Interface layer 240: Second interface layer 290:Metal core layer 500: Sacrificial intermediary layer 500': Sacrificial plug 510: Protective structure 510N: Notch 520:Mask 530: Gap 600,600S: Gate dielectric layer 600A, 600A', 600A'', 600B, 600C: Part 700: second work function metal layer 900: work function metal layer 1000:Method 1100, 1200, 1300, 1400, 1500, 1600: Operation CD1, D1: distance H1: First level H2: Second level W1: width

Claims

1. A method of forming an integrated circuit device, comprising: forming a trench to form a stack comprising a plurality of nanostructure channels, a plurality of interposers, and a hard mask structure; forming a sacrificial gate structure on the stack; forming a spacer layer adjacent to the sacrificial gate structure; releasing the plurality of nanostructure channels by removing the plurality of interposers; forming a gate dielectric layer on one side of the plurality of nanostructure channels and the spacer layer; forming a reduced gate dielectric layer laterally adjacent to the plurality of nanostructure channels by removing a portion of the gate dielectric layer from the side of the spacer layer; and forming a gate metal layer on an exposed portion of the reduced gate dielectric layer and the spacer layer.

2. The method of forming an integrated circuit device as claimed in claim 1 further includes: selectively growing a protective structure covering one end of the gate dielectric layer on the plurality of nanostructure channels before removing the portion of the gate dielectric layer.

3. The method for forming an integrated circuit device as claimed in claim 2, wherein the step of selectively growing the protective structure comprises: forming a plurality of sacrificial interposers between the plurality of nanostructure channels; and growing the protective structure on the exposed sides of the plurality of sacrificial interposers.

4. The method of forming an integrated circuit device as claimed in claim 3, wherein the step of growing the protective structure includes growing the protective structure to have a first thickness adjacent to the plurality of sacrificial interposers greater than a second thickness adjacent to the end of the gate dielectric layer.

5. The method of forming an integrated circuit device as claimed in claim 3, wherein the step of removing the portion of the gate dielectric layer comprises removing the portion of the gate dielectric layer exposed through the plurality of sacrificial interlayers and the protective structure.

6. The method of forming an integrated circuit device as claimed in any one of claims 1 to 5 further includes: removing the hard shield structure after removing the portion of the gate dielectric layer.

7. The method of forming an integrated circuit device as claimed in any one of claims 1 to 5 further includes: after removing the portion of the gate dielectric layer, forming a low dielectric constant dielectric layer on the exposed surface of the spacer layer above the hard shield structure.

8. A method of forming an integrated circuit device, comprising: forming a stack comprising alternating nanostructure channels and a plurality of interposers by forming a trench extending through alternating plurality of first semiconductor layers and a plurality of second semiconductor layers; releasing the plurality of nanostructure channels by removing the plurality of interposers; forming a gate dielectric layer on the plurality of nanostructure channels and on one side surface of a gate spacer extending from a first horizontal height above the plurality of nanostructure channels to a second horizontal height below the plurality of nanostructure channels; forming a plurality of sacrificial plugs between the plurality of nanostructure channels; selectively growing a protective structure on the exposed surfaces of the plurality of sacrificial plugs; and removing a portion of the gate dielectric layer exposed through the plurality of sacrificial plugs.

9. A method of forming an integrated circuit device as claimed in claim 8, wherein the step of forming the stack comprises: forming a hard mask structure over an uppermost intermediate layer of the plurality of intermediate layers during the formation of the trench.

10. The method of forming an integrated circuit device as claimed in claim 9, wherein the step of forming the sacrificial plug includes forming one of the plurality of sacrificial plugs between the uppermost intermediate layer and the hard shield structure.

11. The method of forming an integrated circuit device as claimed in any one of claims 8 to 10 further includes, after removing the portion of the gate dielectric layer, forming a metal gate layer on the plurality of nanostructure channels, the metal gate layer having a first thickness perpendicular to a space between the plurality of nanostructure channels and a second thickness outside the space, the second thickness being greater than the first thickness.

12. An integrated circuit device, comprising: a first stack of a plurality of nanostructures; a second stack of a plurality of nanostructures adjacent to the first stack of the plurality of nanostructures along a first direction; a source / drain adjacent to the first stack of the plurality of nanostructures along a second direction transverse to the first direction; and a gate structure surrounding the first stack of the plurality of nanostructures, the gate structure comprising: a gate dielectric layer comprising: A first portion extending between the plurality of nanostructures in a first stack; and a second portion extending between the plurality of nanostructures in a second stack, wherein the first portion and the second portion are discontinuous along the first direction in a region between the plurality of nanostructures in a first stack and the plurality of nanostructures in a second stack; and a gate metal located on the gate dielectric layer, the gate metal extending between the plurality of nanostructures in a first stack, between the plurality of nanostructures in a second stack, and continuously located between the plurality of nanostructures in a region between the plurality of nanostructures in a first stack and the plurality of nanostructures in a second stack.

13. The integrated circuit device of claim 12 further includes: a hard mask structure located on an uppermost nanostructure of the first stack of the plurality of nanostructures, wherein the gate dielectric layer surrounds the hard mask structure.

14. An integrated circuit arrangement as claimed in claim 12 or 13, wherein the first portion of the gate dielectric layer includes an exterior extending along the first direction beyond the side of the first stack of the plurality of nanostructures.

15. The integrated circuit device of claim 14, wherein the outer side of the gate dielectric layer has a first thickness adjacent to a space between the first stack of the plurality of nanostructures and a second thickness adjacent to the ends of the two nanostructures, the first thickness being greater than the second thickness.

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