Semiconductor device structure and method for forming the same

Abstract

This invention provides a semiconductor device structure and a method for forming the same. The structure includes a first conductive component disposed between two substrate portions; a second conductive component disposed above the first conductive component; a third conductive component disposed above the first conductive component; and a fourth conductive component disposed above the first conductive component. The fourth conductive component includes a top portion disposed above the second and third conductive components and a bottom portion disposed between the second and third conductive components. The first, second, third, and fourth conductive components are electrically connected.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor device structures and methods of forming the same. Prior Art

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each featuring smaller and more complex circuits than the previous one. Throughout the history of IC development, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component or circuit produced during the manufacturing process) has decreased. This process of device miniaturization has provided benefits such as increased production efficiency and reduced associated costs. However, this device miniaturization has also increased the complexity of processing and manufacturing ICs.

[0003] Therefore, there is a need to improve the processing and manufacturing of integrated circuits. Summary of the Invention

[0004] In some embodiments, a semiconductor device structure is provided, which includes a first conductive component disposed between two substrate portions; a second conductive component disposed above the first conductive component; a third conductive component disposed above the first conductive component; and a fourth conductive component disposed above the first conductive component, wherein the fourth conductive component includes a top portion disposed above the second conductive component and the third conductive component and a bottom portion disposed between the second conductive component and the third conductive component, and the first conductive component, the second conductive component, the third conductive component, and the fourth conductive component are electrically connected.

[0005] In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first dielectric material extending across a first gate electrode layer and a second gate electrode layer; a second dielectric material extending across the first gate electrode layer and the second gate electrode layer; a third dielectric material disposed in the first gate electrode layer between the first dielectric material and the second dielectric material; a fourth dielectric material disposed in the second gate electrode layer between the first dielectric material and the second dielectric material; and a feedthrough unit disposed between the first dielectric material and the second dielectric material and between the third dielectric material and the fourth dielectric material. The feedthrough unit includes: a first conductive member disposed between the third dielectric material and the fourth dielectric material, wherein the first conductive member has a first width and a first length; and a second conductive member disposed above the first conductive member and electrically connected to the first conductive member, wherein the second conductive member has a second width and a second length, wherein the second width is substantially greater than the first width and the second length is substantially less than the first length.

[0006] In some other embodiments, a method for forming a semiconductor device structure is provided, which includes depositing a first conductive component and a second conductive component in an interlayer dielectric layer, wherein the first conductive component is deposited above the first source / drain region and the second source / drain region, and the second conductive component is deposited above the third source / drain region and the fourth source / drain region; depositing a third conductive component above the first conductive component and the second conductive component and between the first conductive component and the second conductive component, wherein the third conductive component includes a top portion disposed above the first conductive component and the second conductive component and a bottom portion disposed between the first conductive component and the second conductive component; and depositing a fourth conductive component, wherein the fourth conductive component is electrically connected to the first conductive component, the second conductive component, and the third conductive component. Simple diagram description

[0007] The following detailed description, combined with the accompanying drawings, will provide a better understanding of the embodiments of the present invention. It should be noted that, in accordance with standard industry practice, the various features shown in the figures are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of illustration. Figures 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15 are perspective views of various stages in the manufacture of a semiconductor device structure according to some embodiments. 16A, 17A, 18A, and 19A are perspective views of various stages in the fabrication of a semiconductor device structure according to some embodiments. 16B, 17B, 18B, and 19B are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line AA of FIG. 16A , according to some embodiments. FIG. 18B-1 is a schematic cross-sectional view of one of the stages of manufacturing a semiconductor device structure according to another embodiment, taken along line AA of FIG. 16A . 16C, 17C, 18C, and 19C are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line BB of FIG. 16A, according to some embodiments. 20A, 20B, 20C, and 20D are perspective views of various stages in the fabrication of a semiconductor device structure according to some embodiments. 21A and 21B are schematic cross-sectional views of one of the stages of manufacturing a semiconductor device structure, taken along lines AA and BB of FIG. 16A , respectively, according to some embodiments. 22A and 22B are perspective views of a feed through via (FTV) unit according to some embodiments. FIG. 23 is a top view of a semiconductor device structure according to some embodiments. FIG. 24 is a perspective view of a semiconductor device structure according to some embodiments. 25A and 25B are schematic cross-sectional views of one of the stages of manufacturing a semiconductor device structure according to another embodiment, taken along lines AA and BB of FIG. 16A , respectively. FIG. 26 is a schematic cross-sectional view of one of the stages of manufacturing a semiconductor device structure, taken along line AA of FIG. 16A , according to another embodiment. Implementation Method

[0008] It should be understood that the following description provides many different embodiments or examples for implementing various components of the provided subject matter. Specific examples of various components and their arrangements are described below to simplify the description. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, component dimensions are not limited to the ranges or values ​​of one embodiment of the present disclosure but may depend on the processing conditions and / or desired properties of the component. Furthermore, the following description of forming a first component above or on a second component includes embodiments in which the first and second components are formed in direct contact, as well as embodiments in which additional components may be formed between the first and second components, eliminating the need for direct contact. Furthermore, the various examples in the present description may use repeated reference symbols and / or terms. This repeated reference symbol or terminology is for simplicity and clarity and is not intended to limit the relationship between the various embodiments and / or the described structures.

[0009] Furthermore, to facilitate description of the relationship of one element or component to another element or component in the drawings, spatially relative terms such as "below," "beneath," "lower," "above," "above," "upper," "top," and similar terms may be used. Spatially relative terms encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the description using spatially relative terms interpreted accordingly.

[0010] While embodiments of the present invention are discussed with reference to nanostructured channel field-effect transistors (e.g., gate-all-around (GAA) field-effect transistors, such as horizontal gate-all-around (HGAA) field-effect transistors or vertical gate-all-around (VGAA) field-effect transistors), some aspects of the present invention may be applied to other processes and / or other devices, such as planar field-effect transistors, fin field-effect transistors, and other suitable devices. Those skilled in the art will appreciate that other modifications are contemplated within the scope of the present invention. In the case of gate-all-around (GAA) transistor structures, the gate-all-around transistor structures may be patterned using any suitable method. For example, these structures may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Generally, double or multi-patterning processes combine photolithography and self-aligned processes to create patterns with smaller pitches, for example, than can be achieved using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern a wraparound gate structure.

[0011] FIG1 through FIG21B illustrate an exemplary process for fabricating a semiconductor device structure 100 according to an embodiment of the present invention. It should be understood that additional operations may be provided before, during, and after the process shown in FIG1 through FIG21B , and that some operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes is not limiting and is interchangeable.

[0012] Figures 1 through 15 are perspective views of various stages in the fabrication of a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, semiconductor device structure 100 includes a stack of semiconductor layers 104 formed over the front side of a substrate 101. Substrate 101 may be a semiconductor substrate. Substrate 101 may include a crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0013] The substrate 101 may include regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs).

[0014] The stack of semiconductor layers 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices (e.g., nanostructured channel field-effect transistors). In some embodiments, the stack of semiconductor layers 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the stack of semiconductor layers 104 includes alternating first and second semiconductor layers 106, 108. The first and second semiconductor layers 106, 108 are made of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of silicon, while the second semiconductor layer 108 may be made of silicon germanium. In some examples, the first semiconductor layer 106 may be made of silicon germanium, while the second semiconductor layer 108 may be made of silicon. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0015] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxial growth. For example, the epitaxial growth of each layer of the stack of semiconductor layers 104 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0016] The first semiconductor layer 106 or a portion of the first semiconductor layer 106 may form a nanostructured channel of the semiconductor device structure 100 during subsequent fabrication stages. The term "nanostructured" is used herein to designate any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term designates elongated material portions having circular and substantially circular cross-sections, as well as beam-shaped or rod-shaped material portions having, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructured transistor. A nanostructured transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define a channel or channels of the semiconductor device structure 100 is discussed further below.

[0017] Each first semiconductor layer 106 may have a thickness in a range from approximately 5 nm to approximately 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 may have a thickness in a range from approximately 2 nm to approximately 50 nm. FIG. 1 shows three first semiconductor layers 106 and three second semiconductor layers 108 arranged in an alternating pattern for illustrative purposes and is not intended to be limiting beyond the specific recitations in the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the stack of semiconductor layers 104, and the number of these layers depends on the desired number of channels in the semiconductor device structure 100. As shown in FIG. 1 , an oxide layer 110 is formed on the topmost first semiconductor layer 106, and a nitride layer 111 is formed on the oxide layer 110. The oxide layer 110 may be silicon oxide and may have a different etch selectivity than the nitride layer 111. The nitride layer 111 may include any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 111 may be a mask structure.

[0018] In FIG. 2 , fin structures 112 are formed from a stack of semiconductor layers 104. Each fin structure 112 has an upper portion comprising a first semiconductor layer 106 and a second semiconductor layer 108, and a base portion 116 formed from a substrate 101. Fin structures 112 can be formed by patterning a hard mask layer, such as an oxide layer 110 and a nitride layer 111 formed on the stack of semiconductor layers 104, using multiple patterning operations including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element comprising the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element can be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 in the unprotected areas through the hard mask layer, through the stack of semiconductor layers 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend in the X-direction. The trenches 114 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or a combination thereof.

[0019] In FIG. 3 , after forming the fin structures 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are buried in the insulating material 118. A planarization operation (e.g., chemical mechanical polishing (CMP) and / or etch-back) is then performed to expose the tops of the fin structures 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any other suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0020] In FIG. 4 , the insulating material 118 is recessed to form an isolation region 120. The recessing of the insulating material 118 exposes a portion of the fin structure 112, such as the stack of semiconductor layers 104. The recessing of the insulating material 118 also exposes the trenches 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 contacting the substrate portion 116 formed by the substrate 101. In some embodiments, the isolation region 120 is a shallow trench isolation region. In some embodiments, during the recessing of the insulating material 118, the oxide layer 110 and the nitride layer 111 are also removed.

[0021] In FIG. 5 , one or more sacrificial gate structures 130 are formed above the semiconductor device structure 100. The sacrificial gate structures 130 are formed above a first portion of the fin structure 112 and a first portion of the isolation region 120, while exposing a second portion of the fin structure 112 and a second portion of the isolation region 120. Each sacrificial gate structure 130 includes a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. In some embodiments, the mask layer 136 is a multi-layer structure. For example, the mask layer 136 includes an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. The sacrificial gate dielectric layer 132 may comprise one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may comprise silicon, such as polycrystalline silicon or amorphous silicon. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as the channel region of the semiconductor device structure 100.

[0022] In FIG. 6 , a spacer layer 138 is formed to cover the sacrificial gate structure 130, the second portion of the fin structure 112, and the second portion of the isolation region 120. The spacer layer 138 may comprise one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. In some embodiments, the spacer layer 138 is formed using a compliant process, such as an atomic layer deposition (ALD) process. In some embodiments, the spacer layer 138 has a thickness in a range from approximately 2 nm to approximately 10 nm.

[0023] In FIG. 7 , a mask 139 is formed between adjacent second portions of the fin structure 112. Mask 139 is formed on the portion of the spacer layer 138 formed on the second portion of the isolation region 120. Mask 139 can comprise any suitable material having a different etch selectivity than the material of the spacer layer 138. In some embodiments, mask 139 is a bottom antireflective coating (BARC) layer. In some embodiments, mask 139 is a dielectric layer having a different etch selectivity than the spacer layer 138. Mask 139 can be formed using a two-step process. First, a mask layer is formed on the sacrificial gate structure 130 and the second portion of the fin structure 112. The mask layer can comprise the same material as mask 139 and can be formed using any suitable process, such as spin coating. Next, an etch-back process is performed to remove a portion of the mask layer to form mask 139. As shown in FIG. 7 , mask 139 has a height along the Z direction that is less than the height of the fin structure 112. The mask 139 protects the portion of the spacer layer 138 formed on the second portion of the isolation region 120 during subsequent processes. In some embodiments, as shown in FIG. 7 , the top surface of the mask 139 is located between the top surface and the bottom surface of the second topmost first semiconductor layer 106.

[0024] In FIG. 8 , one or more etching processes are performed to recess the portion of the fin structure 112 not covered by the sacrificial gate structure 130 (and the portion of the spacer layer 138 formed on the sidewalls of the sacrificial gate structure 130) and remove a portion of the spacer layer 138. In some embodiments, the portion of the spacer layer 138 formed on top of the portion of the fin structure 112 not covered by the sacrificial gate structure 130 is removed to expose the portion of the fin structure 112 not covered by the sacrificial gate structure 130. Next, the exposed portion of the fin structure 112 not covered by the sacrificial gate structure 130 is recessed to expose the base portion 116, as shown in FIG. The portion of the spacer layer 138 formed on the sidewalls of the mask layer 136 may also be recessed. The one or more etching processes may include dry etching (e.g., reactive ion etching, neutron beam etching, or the like) and / or wet etching (e.g., using tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH)). The one or more etching processes form spacers 140, which include a first portion 140a formed on the sidewalls of the sacrificial gate electrode layer 134 and a second portion 140b formed on the second portion of the isolation region 120 not covered by the sacrificial gate structure 130. A mask 139 protects the second portion 140b of the spacers 140 during the one or more etching processes. In some embodiments, the second portion 140b of each spacer 140 has a U-shape, as shown in FIG. In some embodiments, after the one or more etching processes, the height of the mask 139 is substantially less than the height of the vertical portion of the second portion 140b of the spacer 140.

[0025] In FIG. 9 , edge portions of each second semiconductor layer 108 of the stack of semiconductor layers 104 are horizontally removed along the X-direction. The removal of the edge portions of the second semiconductor layer 108 forms a recess. In some embodiments, this portion of the second semiconductor layer 108 is removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of silicon germanium and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 is selectively etched using a wet etchant such as, but not limited to, ammonium hydroxide (NH₄OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0026] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the recess to form dielectric spacers 144. The dielectric spacers 144 can be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. In one embodiment, the dielectric spacers 144 include SiOCN. The dielectric spacers 144 can be formed by first forming a compliant dielectric layer using a compliant deposition process (such as atomic layer deposition), and then using an anisotropic etch to remove the compliant dielectric layer except for the dielectric spacers 144. The dielectric spacers 144 are protected by the first semiconductor layer 106 during the anisotropic etch process. The remaining second semiconductor layer 108 covers the dielectric spacers 144 along the X-direction.

[0027] In FIG. 10 , source / drain (S / D) regions 146 are formed from base portion 116 . In some embodiments, source / drain regions 146 may be grown vertically and horizontally to form facets that correspond to crystallographic planes of the material of base portion 116 . Herein, the terms "source region" and "drain region" are used interchangeably, and the structures of the source and drain regions are generally the same. Furthermore, depending on the context, the source / drain regions may be referred to as either sources or drains, either alone or together. In some embodiments, source / drain regions 146 are n-type epitaxial source / drain components and may be made from one or more layers of Si, SiP, SiC, or SiCP for n-type channel field-effect transistors. In some embodiments, source / drain regions 146 are p-type epitaxial source / drain components and may be made from one or more layers of Si, SiGe, or Ge for p-type channel field-effect transistors. For a p-channel field-effect transistor, a p-type dopant, such as boron (B), may also be included in the source / drain regions 146. The source / drain regions 146 may be formed by epitaxial growth methods using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. The source / drain regions 146 may include both doped and undoped epitaxial materials.

[0028] In FIG. 11 , a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the first portion 140a of the spacer 140 and is disposed on the mask 139 and the source / drain region 146. The CESL 162 may comprise an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof, and may be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any other suitable deposition technique. Next, an interlayer dielectric (ILD) layer 163 is formed on the CESL 162. The material of the ILD layer 163 may comprise a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for the interlayer dielectric layer 163. The interlayer dielectric layer 163 may be deposited using plasma-assisted chemical vapor deposition (PECVD) or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric layer 163, the semiconductor device structure 100 may be subjected to a thermal process to anneal the interlayer dielectric layer 163.

[0029] A planarization process is performed to expose the sacrificial gate electrode layer 134, as shown in FIG11 . The planarization process can be any suitable process, such as a chemical mechanical polishing process. The planarization process removes the portions of the interlayer dielectric layer 163 and the contact etch stop layer 162 disposed on the sacrificial gate structure 130. The planarization process also removes the mask 136.

[0030] In FIG. 12 , the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The interlayer dielectric layer 163 protects the source / drain region 146 during the removal process. The sacrificial gate structure 130 and the second semiconductor layer 108 can be removed by plasma dry etching and / or wet etching. In some embodiments, a wet etchant (e.g., tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate structure 130 and the second semiconductor layer 108 without removing the spacers 140, the isolation region 120, the interlayer dielectric layer 163, and the contact etch stop layer 162.

[0031] After forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170, as shown in FIG13 . The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) 168 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. The interfacial layer 168 may comprise an oxide, such as silicon oxide, and may be formed as a result of a cleaning process. In some embodiments, the gate dielectric layer 170 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by chemical vapor deposition, atomic layer deposition, or any other suitable deposition technique. The gate electrode layer 172 can include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 172 can be formed by chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition techniques. A gate dielectric layer 170 and a gate electrode layer 172 may also be deposited on the interlayer dielectric layer 163. Then, the gate dielectric layer 170 and the gate electrode layer 172 formed on the interlayer dielectric layer 163 are removed by, for example, chemical mechanical polishing until the top surface of the interlayer dielectric layer 163 is exposed.

[0032] In FIG. 14 , a hard mask 202 is formed on the interlayer dielectric layer 163. The hard mask 202 may comprise a dielectric material such as SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The hard mask 202 may be used to form one or more openings 204 in the gate structure 174, the interlayer dielectric layer 163, the contact etch stop layer 162, and the isolation region 120. The openings 204 may be formed between adjacent source / drain regions 146. In the channel region, openings 204 are formed in the gate electrode layer 172, the gate dielectric layer 170, and the isolation region 120. The openings 204 may be formed to separate the gate structure 174 into multiple portions (or to separate the gate electrode layer 172 into multiple gate electrode layers 172). The openings 204 may be formed through one or more etching processes. In some embodiments, a portion of the substrate 101 is exposed in the openings 204.

[0033] In FIG. 15 , a liner 205 and a dielectric material 206 are formed in each opening 204 . The liner 205 and dielectric material 206 may comprise any suitable dielectric material. In some embodiments, the liner 205 comprises the same material as the contact etch stop layer 162 , while the dielectric material 206 comprises the same material as the interlayer dielectric layer 163 . After the openings 204 are filled with the liner 205 and dielectric material 206 , a planarization process (e.g., a chemical mechanical polishing process) may be performed to expose the gate electrode layer 172 , as shown in FIG. The process performed in FIG. 14 and FIG. 15 may be referred to as a cut metal gate (CMG) process.

[0034] Figures 16A, 17A, 18A, and 19A are perspective views of various stages in the fabrication of the semiconductor device structure 100 according to some embodiments. Figures 16B, 17B, 18B, and 19B are schematic cross-sectional views of various stages in the fabrication of the semiconductor device structure 100, taken along line AA in Figure 16A, according to some embodiments. Figures 16C, 17C, 18C, and 19C are schematic cross-sectional views of various stages in the fabrication of the semiconductor device structure 100, taken along line BB in Figure 16A, according to some embodiments. As shown in Figures 16A through 16C, in some embodiments, the portion of the gate structure 174 located between the two dielectric materials 206 is removed and replaced with a dielectric material 208. In some embodiments, portions of three or more gate structures 174 are replaced with dielectric material 208. In some embodiments, a mask (not shown) is formed to expose the portion of the gate structure 174 to be removed. Next, one or more processes are performed to remove the portion of the gate structure 174. In some embodiments, the gate dielectric layer 170 and the gate electrode layer 172 are removed through this one or more processes. In some embodiments, the gate dielectric layer 170 is not removed and remains in the semiconductor device structure 100. The removal of the gate structure 174 forms an opening in the semiconductor device structure 100, and the opening may extend into or through the isolation region 120. In some embodiments, as shown in FIG. 16C , a portion of the base portion 116 may also be removed.

[0035] Next, dielectric material 208 is deposited in each opening. Dielectric material 208 may comprise any suitable dielectric material, such as a compound of Si, O, C, and N, or other high-k dielectric constant materials. In some embodiments, dielectric material 208 comprises SiN. In some embodiments, a liner (not shown) may be first deposited in the opening, and dielectric material 208 is deposited on the liner in the opening. In some embodiments, the liner may comprise the same material as liner 205, and dielectric material 208 may comprise the same material as dielectric material 206. After depositing dielectric material 208, a planarization process (e.g., a chemical mechanical polishing process) is performed to expose dielectric material 206 and gate structure 174. The process of replacing a portion of gate structure 174 with dielectric material 208 is referred to as a continuous polysilicon on diffusion (CPODE) process, which is used to form isolation regions that divide the active region into multiple segments. In some embodiments, this isolation region can be used to form a feedthrough via (FTV) cell, which electrically connects the front side of substrate 101 to the back side of substrate 101. Feedthrough cells are discussed in detail below. In some embodiments, the isolation region is defined by three dielectric materials 208, as shown in FIG16A , and the feedthrough cell has a dimension in the X direction that is twice the contact poly pitch (CPP), which defines the minimum center-to-center spacing between the gate electrode layers of adjacent transistors. In some embodiments, the isolation region is defined by multiple dielectric materials 208, and the feedthrough cell has a dimension in the X direction that is six times or greater than the CPP. The dimension of the feedthrough cell in the Y direction can be defined by adjacent dielectric materials 206, as shown in FIG16A . In some embodiments, the distance between the center points of adjacent dielectric materials 206 can be referred to as the cell height.

[0036] In Figures 17A-17C , conductive features 212a and 212b are formed in the interlayer dielectric layer 163. Conductive feature 212a is formed to provide an electrical path to the source / drain regions 146. Conductive feature 212b is formed to prevent chemical mechanical polishing dishing and / or to aid in photolithography loading effects. Furthermore, conductive feature 212b is formed to reduce the resistance of the feedthrough cell. In some embodiments, conductive features 212b may be slot conductive contacts. For example, conductive features 212b may extend above both source / drain regions 146, as shown in Figure 17A . In some embodiments, two conductive features 212b are formed in the interlayer dielectric layer 212b, with dielectric material 208 disposed between the two conductive features 212b, as shown in Figure 17A . In some embodiments, more than two conductive features 212b are formed, for example, three or more conductive features 212b are spaced apart along the X-direction, with dielectric material 208 located between adjacent conductive features 212b. In some embodiments, conductive features 212b are located within dielectric material 208 along the X-direction, and the outermost dielectric material 208 along the X-direction separates conductive features 212b and subsequently formed conductive features 220b (FIGS. 18A-18C) from the active region adjacent to the isolation region. In other words, dielectric material 208 is located at both ends of the feedthrough cell along the X-direction.

[0037] The conductive components 212a and 212b may comprise a conductive material, such as a metal. In some embodiments, the conductive components 212a and 212b comprise a material comprising one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The conductive components 212a and 212b may be formed by any suitable method, such as electrochemical plating (ECP) or physical vapor deposition. In some embodiments, the conductive components 212a and 212b comprise W or Co. A silicide layer 214 may be formed between each conductive component 212a and 212b and the corresponding source / drain region 146, as shown in FIG. 17A . The silicide layer 214 may comprise a material comprising one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi.

[0038] In some embodiments, a liner 210 is formed in the opening before forming the conductive features 212a and 212b. The liner 210 may comprise any suitable material. In some embodiments, the liner 210 is a metal nitride and is formed as a result of a process to form the silicide layer 214. A mask (not shown) may be used to form the conductive features 212a and 212b, and the mask may be removed after forming the conductive features 212a and 212b. After forming the conductive features 212a and 212b, a planarization process may be performed, and the resulting semiconductor device structure 100 is shown in FIG. 17A.

[0039] In Figures 18A-18C , an etch stop layer 216 is deposited on the top surface of the semiconductor device structure 100, a dielectric material 218 is deposited on the etch stop layer 216, and conductive features 220 a and 220 b are formed in the dielectric material 218. The etch stop layer 216 may comprise the same material as the contact etch stop layer 162, and the dielectric material 218 may comprise the same material as the interlayer dielectric layer 163. The conductive feature 220 a is formed to provide an electrical path to the source / drain regions 146 and the gate electrode layer 172. In some embodiments, the conductive feature 220 a is electrically connected to the conductive feature 212 a. The conductive feature 220 a is formed in the feedthrough cell to electrically connect the front side of the substrate 101 to the back side of the substrate 101. The conductive features 220 a and 220 b comprise a conductive material such as W, Ru, Mo, Cu, Ir, Al, or other suitable materials. In some embodiments, the conductive components 220a and 220b may comprise the same material as the conductive components 212a and 212b. In some embodiments, the conductive components 220a and 220b may comprise a different material than the conductive components 212a and 212b. For example, the conductive components 220a and 220b may comprise Cu, while the conductive components 212a and 212b may comprise W or Co. In some embodiments, an optional barrier layer 222 is formed to separate the conductive components 220a and 220b from the dielectric material 218 and the dielectric material 208. The optional barrier layer 222 may comprise Ti, Ta, TiN, or TaN. The optional barrier layer 222 may prevent material from diffusing from the conductive components 220a and 220b into the dielectric materials 208 and 218.

[0040] In some embodiments, the conductive features 220a and 220b are formed at different times. For example, a first mask (not shown) may be formed over the dielectric material 218 and patterned to form a first opening for the conductive feature 220a. In some embodiments, the depth of the first opening is equal to the combined thickness of the etch stop layer 216 and the dielectric material 218. After forming the conductive feature 220a in the first opening, a second mask (not shown) is formed over the semiconductor device structure 100 and patterned to form a second opening for the conductive feature 220b. The depth of the second opening is substantially greater than the depth of the first opening. In some embodiments, the depth of the second opening is equal to the thickness of the dielectric material 218 and the etch stop layer 216 plus the thickness of a portion of the dielectric material 208. Due to the difference in depth between the first and second openings, separate processes using two masks are performed to form the conductive features 220a and 220b. In some embodiments, the height of the conductive feature 220b along the Z direction is substantially greater than the height of the conductive feature 220a.

[0041] In some embodiments, the second opening exposes each of the two conductive members 212b and the dielectric material between the two conductive members 212b, such as the liner 210, the contact etch stop layer 162, the first portion 140a of the spacer 140, and the dielectric material 208. A selective etching process is then performed to recess the dielectric material without substantially affecting the conductive members 212b. A conductive member 220b is then deposited over the exposed portions of the conductive members 212b and in the second opening.

[0042] In some embodiments, the conductive component 220b includes a top portion 220bt and a bottom portion 220bb, as shown in FIG. The bottom portion 220bb may be disposed between adjacent conductive components 212b, while the top portion 220bt may be disposed above adjacent conductive components 212b. The top portion 220bt may have a thickness in the Z direction ranging from approximately 10 nm to approximately 30 nm. In some embodiments, the top portion 220bt has a first width in the X direction, and the bottom portion 220bb has a second width in the X direction, with the first width being substantially greater than the second width. For example, the first width may be approximately 20 nm greater than the second width. In some embodiments, the top portion 220bt and the bottom portion 220bb have the same width. In some embodiments, the first width is less than the second width. In some embodiments, the first width is less than a distance D1 defined by the distance between the centerlines of adjacent dielectric materials 208, as shown in FIG. 18B. If the first width is greater than the distance D1, the conductive component 220b may be too close to the active device adjacent to the feedthrough hole unit, which may cause an electrical short circuit between the conductive component 220b and the adjacent active device. In some embodiments, the distance D1 is equal to twice the contact polysilicon pitch.

[0043] In some embodiments, conductive features 220b are disposed adjacent to both sides of each conductive feature 212b, as shown in FIG. 18B-1. In this embodiment, a second opening exposes the conductive features 212b and the dielectric material surrounding the conductive features 212b, such as the liner 210, the contact etch stop layer 162, the first portion 140a of the spacer 140, and the dielectric material 208. A selective etching process is then performed to recess the dielectric material while substantially leaving the conductive features 212b unaffected. Second openings are formed between the conductive features 212b, with the inner surfaces (the sides of the conductive features 212b facing each other) exposed in the second openings. Furthermore, second openings are also formed outside the conductive features 212b, with the outer surfaces (the sides of the conductive features opposite the inner surfaces) of the conductive features 212b also exposed in the second openings. Conductive features 220b are then deposited on the conductive features 212b and within the second openings, as shown in FIG. 18B-1. As shown in FIG. 18B-1 , in some embodiments, the top portion 220bt of the conductive component 220b may be a continuous material with a uniform width, while the bottom portion 220bb may comprise multiple discrete segments with varying widths. As described above, the width of the conductive component 220b (e.g., the width of the top portion 220bt) may be less than the distance D1 to prevent electrical shorting between the conductive component 220b and adjacent active devices.

[0044] In some embodiments, the conductive member 220b has a first length along the Y direction, and the first length of the conductive member 220b can be substantially uniform, as shown in FIG18C . The dielectric material 208 has a second length along the Y direction. In some embodiments, the first length is substantially less than the second length. Similar to the first width of the conductive member 220b, if the first length of the conductive member 220b is greater than the second length, the conductive member 220b is too close to the active device adjacent to the feedthrough cell. In other words, if the first length is greater than the second length, the conductive member 220b is too close to the active gate electrode layer 172. As described above, the distance between the center points of adjacent dielectric materials 206 is the cell height, and the first length of the conductive member 220b is substantially less than the cell height. After forming the conductive members 220a and 220b, a planarization process can be performed, resulting in the semiconductor device structure 100 shown in FIG18A .

[0045] As shown in FIG18B , in some embodiments, the bottom surface of the conductive component 220 b may be located at approximately the same level as the bottom surface of the conductive component 212 b. In some embodiments, the bottom surface of the conductive component 220 b may be located at a different level than the bottom surface of the conductive component 212 b.

[0046] In Figures 19A-19C, an etch stop layer 224 is deposited on the top surface of the semiconductor device structure 100. A dielectric material 226 is deposited on the etch stop layer 224, and conductive features 228a and 228b are formed in the dielectric material 226. The etch stop layer 224 may comprise the same material as the contact etch stop layer 162. The dielectric material 226 may be an intermetallic dielectric (IMD) layer. The dielectric material 226 may be any suitable dielectric material, such as SiOx, SiOxCyHz, or SiOxCy, where x, y, and z are integers or non-integers. Conductive feature 228a is formed to provide an electrical path to the source / drain regions 146 and the gate electrode layer 172. In some embodiments, conductive feature 228a is electrically connected to conductive feature 220a. Conductive feature 228b is formed to electrically connect to conductive feature 220b. Conductive features 228a and 228b may comprise the same material as conductive features 220a and 220b. In some embodiments, an optional barrier layer 230 is formed to separate conductive features 228a and 228b from dielectric material 226. Optional barrier layer 230 may comprise the same material as optional barrier layer 222. In some embodiments, dielectric material 226, including conductive features 228a and 228b disposed therein, may be the lowest layer of an interconnect structure formed above the front side of substrate 101. Subsequent processing may include forming multiple layers of dielectric material having conductive features therein.

[0047] Figures 20A, 20B, 20C, and 20D are perspective views of various stages in the fabrication of a semiconductor device structure 100 according to some embodiments. Specifically, Figures 20A, 20B, 20C, and 20D illustrate backside fabrication processes. After forming the interconnect structure (for clarity, only the bottom layer of the interconnect structure is shown), the semiconductor device structure 100 is flipped upside down, with the substrate 101 positioned on top. Before flipping the semiconductor device structure 100, a carrier substrate (not shown) may be bonded to the interconnect structure.

[0048] In FIG. 20B , a portion or all of substrate 101 is removed. Substrate 101 can be removed or thinned using any suitable process. As shown in FIG. 20B , in some embodiments, conductive feature 220 b ( FIG. 19B ) is formed between two substrate portions 116 . To maximize space for conductive feature 220 b and subsequently formed conductive feature 306 ( FIG. 20D ), each of the two substrate portions 116 may have a smaller width along the Y direction in the areas where conductive features 220 b and 306 are formed. Removal or thinning of substrate 101 exposes substrate portion 116, isolation region 120, liner 205, and dielectric material 206. The exposed portions of the materials may be substantially coplanar, as shown in FIG. 20B .

[0049] In FIG. 20C , a mask 302 is formed on the exposed surface, and an opening 304 is formed in the mask 302. The mask 302 can comprise any suitable material. In some embodiments, the mask 302 comprises SiN. The opening 304 can also be formed in the isolation region 120, the dielectric material 208, the spacer 140, the mask 139, the contact etch stop layer 162, and the interlayer dielectric layer 163. In some embodiments, the conductive member 220 b and the conductive member 212 b are exposed in the opening 304.

[0050] In FIG. 20D , a conductive member 306 is formed in the opening 304 and electrically connected to the conductive member 220 b and the conductive member 212 b. The conductive member 306 comprises a conductive material, such as W, Ru, Mo, Cu, Ir, Al, or other suitable materials. In some embodiments, the conductive member 306 may comprise the same material as the conductive member 220 b. In some embodiments, an optional barrier layer 308 may be formed in the opening 304, and the conductive member 306 may be deposited on the barrier layer 308. The optional barrier layer 308 may comprise the same material as the optional barrier layer 222. After forming the conductive member 306, a planarization process may be performed. As a result, a portion of the mask 302 remains, and the mask 302 includes a surface that is substantially coplanar with the surface of the conductive member 306, as shown in FIG. 20D . Subsequent processing includes depositing an etch stop layer 310 ( FIGS. 21A and 21B ) over the mask 302 and the conductive member 306 , depositing a dielectric material 312 ( FIGS. 21A and 21B ) over the etch stop layer 310 , and depositing conductive members 314 a and 314 b ( FIGS. 21A and 21B ) within the dielectric material 312 . The etch stop layer 310 may comprise the same material as the contact etch stop layer 162 . The dielectric material 312 may be an intermetallic dielectric layer. Conductive member 314 a is formed from the backside of the semiconductor device structure 100 to provide an electrical path to the source / drain regions 146 and the gate electrode layer 172 . Conductive member 314 b is formed to electrically connect to the conductive member 306 . Conductive members 314 a and 314 b may comprise the same material as the conductive members 228 a and 228 b . In some embodiments, an optional barrier layer 316 is formed to separate the conductive features 314a, 314b from the dielectric material 312. The optional barrier layer 316 may comprise the same material as the optional barrier layer 222. In some embodiments, the dielectric material 312 including the conductive features 314a, 314b disposed therein may be the bottom layer of the backside interconnect structure (or the top layer when the front side of the semiconductor device structure 100 is on top). Subsequent processing may include forming multiple layers of dielectric material with the conductive features formed therein.

[0051] Figures 21A and 21B are schematic cross-sectional views of various stages of fabricating the semiconductor device structure 100, taken along lines AA and BB, respectively, of Figure 16A, according to some embodiments. After forming the backside interconnect structure, the semiconductor device structure 100 is flipped over so that the front side of the semiconductor device structure 100 is at the top. As shown in Figures 21A and 21B, in some embodiments, a feedthrough cell (FTV cell) includes a conductive feature 220b, a conductive feature 212b, and a conductive feature 306, and the feedthrough cell (FTV cell) is electrically connected to the frontside interconnect structure and the backside interconnect structure. The feedthrough cell (FTV cell) is formed in an isolation region between active regions, such as between logic cells. In some embodiments, as shown in Figure 21A, the width of the conductive feature 306 along the X-direction is greater than the first width of the top portion 220bt of the conductive feature 220b. In some embodiments, the width of the conductive feature 306 is greater than the combined width of the conductive features 212b and 220b, as shown in Figure 21A. The width of conductive feature 306 is less than distance D1 ( FIG. 18B ), which can be equal to twice the contact polysilicon pitch, to reduce the risk of electrical shorting between conductive feature 306 and adjacent active regions. Similarly, the length of conductive feature 306 along the Y direction is less than the second length of dielectric material 208 and less than the cell height of feedthrough via cell FTV cell, as shown in FIG. 21B . In some embodiments, the length of conductive feature 306 is less than the length of conductive feature 220 b, as shown in FIG. 21B , because conductive feature 306 is located between adjacent substrate portions 116 , while conductive feature 220 b is not constrained by substrate portions 116 .

[0052] Figures 22A and 22B are perspective views of a feedthrough via (FTV) unit according to some embodiments. For clarity, dielectric materials of the feedthrough unit, such as dielectric material 208, interlayer dielectric layer 163, contact etch stop layer 162, spacer 140, etch stop layer 216, dielectric material 218, liner 205, and dielectric material 206, are omitted. As shown in Figures 22A and 22B, the feedthrough unit includes conductive members 220b disposed on and between conductive members 212b. Top members 220bt are disposed on conductive members 212b, and bottom members 220bb are disposed between conductive members 212b. In some embodiments, each conductive member 212b includes a top member 212bt and a bottom member 212bb. In some embodiments, the top member 212bt has a width along the Y-axis that is substantially greater than the width of the bottom member 212bb, as shown in Figures 22A and 22B. The top portion 212bt of the conductive member 212b may be positioned above the two source / drain regions 146, while the bottom portion 212bb of the conductive member 212b may be positioned between the two source / drain regions 146, as shown in FIG. The two source / drain regions 146 are formed above the two base portions 116, and the conductive member 306 is positioned between the two base portions 116, as shown in FIG. In some embodiments, the conductive member 306 includes side portions 306a positioned adjacent to the sides of the conductive member 212b. This is the result of an etching process that forms openings exposing the conductive member 212b and the conductive member 220b. The etching process may be a selective etching process that removes dielectric material but does not remove the metal of the conductive members 212b and 220b. Portions of the liner 210 and the interlayer dielectric layer 163 adjacent to the sides of the conductive member 212b may be removed by the etching process.

[0053] FIG23 is a top view of the semiconductor device structure 100 according to some embodiments. For clarity, some components of the semiconductor device structure 100 are omitted in FIG23 . As shown in FIG23 , a dielectric material 206 is formed to cut through the gate electrode layer 172, and a dielectric material 208 is formed in some of the gate electrode layer 172 located between two dielectric materials 206. A feedthrough cell is formed between the two dielectric materials 206 and between the two outermost dielectric materials 208 along the X direction. The feedthrough cell includes a conductive member 220b disposed on and between conductive members 212b, and a conductive member 306 electrically connected to conductive members 220b and 212b. Conductive members 220b, 212b, and 306 can reduce the resistance of the feedthrough cell. As described above, in some embodiments, the feedthrough cell is within twice the contact polysilicon pitch, and the resistance of the feedthrough cell is approximately 40Ω, which is substantially lower than the resistance of conventional feedthrough cells.

[0054] FIG24 is a perspective view of a semiconductor device structure 100 according to some embodiments. As shown in FIG24 , two feedthrough via units (FTV) are used to transmit signals from a driver unit (Driver) to a receiver unit (Receiver). The signal is transmitted from the driver unit (Driver) to the backside interconnect structure 402 of the semiconductor device structure 100 through the first feedthrough via unit (FTV), and the signal is transmitted from the backside interconnect structure 402 to the receiver unit (Receiver) through the second feedthrough via unit (FTV), as shown in FIG24 . Because the conductive features in the backside interconnect structure 402 are less crowded, the conductive features in the backside interconnect structure 402 have lower resistance. As described above, the resistance in the feedthrough units is also reduced, thereby improving the cell speed.

[0055] Figures 25A and 25B are schematic cross-sectional views of various stages of fabricating the semiconductor device structure 100, taken along lines AA and BB, respectively, of Figure 16A , according to other embodiments. In some embodiments, conductive member 306 is not formed; instead, conductive member 220b extends into isolation region 120. In these embodiments, the substrate removal or thinning process shown in Figure 20B exposes conductive member 220b. Therefore, in some embodiments, the feedthrough unit includes conductive member 220b having a top portion 220bt and a bottom portion 220bb. The bottom portion 220bb may have a height in the Z direction that is substantially greater than the height of the conductive member 212b. In some embodiments, the bottom portion 220bb is disposed between substrate portions 116, as shown in Figure 25B .

[0056] FIG26 is a schematic cross-sectional view of one of the various stages of fabricating the semiconductor device structure 100, taken along line AA of FIG16A, according to other embodiments. For clarity, some components of the semiconductor device structure 100 are omitted in FIG26. As shown in FIG26, in some embodiments, a feedthrough cell is defined by two dielectric materials 208 spaced apart in the X direction by four times the contact polysilicon pitch (4 CPP). (The distance from the centerline of the dielectric material 208 to the centerline of the bottom portion 220bb is 1 CPP). Four conductive features 212b are formed in the interlayer dielectric layer 163, and each conductive feature 220b includes a continuous top portion 220bt and a discrete bottom portion 220bb. The bottom portion 220bb is disposed between adjacent conductive features 212b, as shown in FIG26. Conductive feature 306 is electrically connected to conductive features 212b and 220b. In some embodiments, the feedthrough cell is located between two dielectric materials 208 separated by six times the contact polysilicon pitch, and the resistance of the feedthrough cell is approximately 10Ω, which is substantially lower than the resistance of a conventional feedthrough cell.

[0057] Embodiments of the present invention provide a semiconductor device structure 100 including a feedthrough via unit having conductive features 220b, 212b, and 306. Conductive feature 220b may be disposed on and between conductive features 212b, and conductive feature 306 may be electrically connected to conductive features 220b and 212b. Some embodiments can achieve numerous advantages. For example, the conductive features 220b, 212b, and 306 arranged in various embodiments described herein can achieve reduced resistance. Furthermore, the size of conductive feature 306 can result in a reduced area penalty for the feedthrough via unit.

[0058] One embodiment is a semiconductor device structure, which includes a first conductive component disposed between two substrate portions; a second conductive component disposed above the first conductive component; a third conductive component disposed above the first conductive component; and a fourth conductive component disposed above the first conductive component, wherein the fourth conductive component includes a top portion disposed above the second conductive component and the third conductive component and a bottom portion disposed between the second conductive component and the third conductive component, and the first conductive component, the second conductive component, the third conductive component, and the fourth conductive component are electrically connected.

[0059] In some other embodiments, the top of the fourth conductive component has a first width, and the bottom of the fourth conductive component has a second width that is substantially smaller than the first width.

[0060] In some other embodiments, the fourth conductive component has a bottom surface located at the same level as the bottom surfaces of the second conductive component and the third conductive component.

[0061] In some other embodiments, the fourth conductive component has a bottom surface located at a different level than the bottom surfaces of the second conductive component and the third conductive component.

[0062] In some other embodiments, the second conductive component and the third conductive component each include a first metal, and the fourth conductive component includes a second metal different from the first metal.

[0063] In some other embodiments, the structure further includes a first barrier layer contacting the first conductive component, the second conductive component, and the third conductive component.

[0064] In some other embodiments, the structure further includes a second barrier layer contacting the second conductive component, the third conductive component, the fourth conductive component and the first barrier layer.

[0065] Another embodiment provides a semiconductor device structure comprising a first dielectric material extending across a first gate electrode layer and a second gate electrode layer; a second dielectric material extending across the first gate electrode layer and the second gate electrode layer; a third dielectric material disposed in the first gate electrode layer between the first dielectric material and the second dielectric material; a fourth dielectric material disposed in the second gate electrode layer between the first dielectric material and the second dielectric material; and a feedthrough via (FTV) unit disposed between the first dielectric material and the second dielectric material and between the third dielectric material and the fourth dielectric material, the feedthrough unit comprising: a first conductive member disposed between the third dielectric material and the fourth dielectric material, the first conductive member having a first width and a first length; and a second conductive member disposed above the first conductive member and electrically connected to the first conductive member, the second conductive member having a second width and a second length, the second width being substantially greater than the first width and the second length being substantially less than the first length.

[0066] In some other embodiments, the structure further includes a fifth dielectric material disposed between the first dielectric material and the second dielectric material and between the third dielectric material and the fourth dielectric material.

[0067] In some other embodiments, the first conductive component and the second conductive component are disposed in a fifth dielectric material.

[0068] In some other embodiments, the structure further includes a third conductive component and a fourth conductive component, wherein the third conductive component and the fourth conductive component are disposed above the first conductive component.

[0069] In some other embodiments, the second conductive component includes a top and a first bottom, and the first bottom is disposed between the third conductive component and the fourth conductive component.

[0070] In some other embodiments, the structure further includes a fifth conductive component and a sixth conductive component, wherein the fifth conductive component and the sixth conductive component are disposed above the first conductive component.

[0071] In some other embodiments, the second conductive component includes a second bottom and a third bottom, the second bottom is disposed between the third conductive component and the fifth conductive component, and the third bottom is disposed between the fourth conductive component and the sixth conductive component.

[0072] Another embodiment is a method comprising depositing a first conductive component and a second conductive component in an interlayer dielectric layer, the first conductive component being deposited above the first source / drain region and the second source / drain region, and the second conductive component being deposited above the third source / drain region and the fourth source / drain region. The method further comprises depositing a third conductive component above the first and second conductive components and between the first and second conductive components, the third conductive component comprising a top portion disposed above the first and second conductive components and a bottom portion disposed between the first and second conductive components. The method further comprises depositing a fourth conductive component, the fourth conductive component being electrically connected to the first, second, and third conductive components.

[0073] In some other embodiments, the method further includes depositing a first dielectric material over the interlayer dielectric layer, wherein the third conductive component is deposited in the first dielectric material.

[0074] In some other embodiments, the method further includes depositing a fifth conductive component in the first dielectric material, wherein the third conductive component and the fifth conductive component are deposited at different time points by using different masks.

[0075] In some other embodiments, the method further includes turning the semiconductor device structure upside down before depositing the fourth conductive component.

[0076] In some other embodiments, the third conductive component surrounds three surfaces of the first conductive component and three surfaces of the second conductive component.

[0077] In some other embodiments, the method further comprises depositing a barrier layer, wherein the third conductive component is deposited on the barrier layer.

[0078] The foregoing description summarizes the features of many embodiments, enabling those skilled in the art to better understand the various aspects of the present invention. Those skilled in the art should understand and readily design or modify other processes and structures based on the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Various changes, substitutions, and modifications may be made to the present invention without departing from the spirit and scope of the present invention.

[0079] 100:Semiconductor device structure 101: Base 104: semiconductor layer 106: first semiconductor layer 108: Second semiconductor layer 110,135:Oxide layer 111,137: Nitride layer 112: Fin structure 114: Groove 116: base part 118: Insulation material 120: Isolation Area 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer 134: Sacrificial gate electrode layer 136: Mask layer 138: Spacer layer 139,302: Mask 140: Spacer 140a: Part 1 140b: Part 2 144: Dielectric spacer 146: Source / Drain Region 162: Contact etch stop layer 163: Interlayer dielectric layer 168: Interface layer 170: Gate dielectric layer 172: Gate electrode layer 174: Gate structure 202: Hard Mask 204,304: Opening 205,210:Padding 206, 208, 218, 226, 312: Dielectric materials 212a, 212b, 220a, 220b, 228a, 228b, 306, 314a, 314b: conductive parts 212bb, 220bb: bottom 212bt,220bt:top 214: Silicide layer 216,224,310: Etch stop layer 222,230,308,316: Barrier layer 306a: side part 402: Backside interconnection structure D1: Distance Driver: Driver unit Receiver: Receiver unit logic cell: logic unit FTV, FTV cell: feedthrough hole unit 1CPP: ​​Contact Polysilicon Pitch 4CPP: Four times the contact polysilicon pitch

Claims

1. A semiconductor device structure, comprising: a first conductive component disposed between two substrate portions; a second conductive component disposed above the first conductive component and located above a first source / drain region and a second source / drain region; a third conductive component disposed above the first conductive component and located above a third source / drain region and a fourth source / drain region; and a fourth conductive component disposed above the first conductive component, wherein the fourth conductive component includes a top disposed above the second and third conductive components and a bottom disposed between the second and third conductive components, and the first conductive component, the second conductive component, the third conductive component, and the fourth conductive component are electrically connected.

2. The semiconductor device structure of claim 1, wherein the top of the fourth conductive member has a first width and the bottom of the fourth conductive member has a second width that is substantially smaller than the first width.

3. The semiconductor device structure of claim 1 or 2, wherein the fourth conductive component has a bottom surface at the same horizontal height as the bottom surfaces of the second conductive component and the third conductive component.

4. The semiconductor device structure of claim 1 or 2, wherein the fourth conductive component has a bottom surface located at a different horizontal height from the bottom surfaces of the second conductive component and the third conductive component.

5. A semiconductor device structure, comprising: a first dielectric material extending across a first gate electrode layer and a second gate electrode layer; a second dielectric material extending across the first gate electrode layer and the second gate electrode layer; a third dielectric material disposed in the first gate electrode layer between the first dielectric material and the second dielectric material; a fourth dielectric material disposed in the second gate electrode layer between the first dielectric material and the second dielectric material; and a feedthrough unit disposed between the first dielectric material and the second dielectric material and between the third dielectric material and the fourth dielectric material, wherein the feedthrough unit includes: A first conductive component is disposed between the third dielectric material and the fourth dielectric material, wherein the first conductive component has a first width and a first length; and a second conductive component is disposed above the first conductive component and electrically connected to the first conductive component, wherein the second conductive component has a second width and a second length, the second width being substantially greater than the first width and the second length being substantially less than the first length.

6. The semiconductor device structure of claim 5 further includes a fifth dielectric material disposed between the first dielectric material and the second dielectric material and between the third dielectric material and the fourth dielectric material.

7. The semiconductor device structure of claim 6, wherein the first conductive component and the second conductive component are disposed in the fifth dielectric material.

8. The semiconductor device structure of any one of claims 5 to 7 further includes a third conductive component and a fourth conductive component, wherein the third conductive component and the fourth conductive component are disposed above the first conductive component.

9. The semiconductor device structure of claim 8, wherein the second conductive member includes a top and a first bottom, and the first bottom is disposed between the third conductive member and the fourth conductive member.

10. The semiconductor device structure of claim 9 further includes a fifth conductive component and a sixth conductive component, wherein the fifth conductive component and the sixth conductive component are disposed above the first conductive component.

11. The semiconductor device structure of claim 10, wherein the second conductive member includes a second bottom and a third bottom, the second bottom being disposed between the third conductive member and the fifth conductive member, and the third bottom being disposed between the fourth conductive member and the sixth conductive member.

12. A method of forming a semiconductor device structure, comprising: depositing a first conductive component and a second conductive component in an interlayer dielectric layer, wherein the first conductive component is deposited above a first source / drain region and a second source / drain region, and the second conductive component is deposited above a third source / drain region and a fourth source / drain region; depositing a third conductive component above the first conductive component and the second conductive component and between the first conductive component and the second conductive component, wherein the third conductive component includes a top disposed above the first conductive component and the second conductive component and a bottom disposed between the first conductive component and the second conductive component; and depositing a fourth conductive component, wherein the fourth conductive component is electrically connected to the first conductive component, the second conductive component and the third conductive component.

13. The method of forming a semiconductor device structure as claimed in claim 12 further includes depositing a first dielectric material over the interlayer dielectric layer, wherein the third conductive component is deposited in the first dielectric material.

14. The method of forming a semiconductor device structure as claimed in claim 13 further includes depositing a fifth conductive component in the first dielectric material, wherein the third conductive component and the fifth conductive component are deposited at different time points using different masks.

15. A method of forming a semiconductor device structure as claimed in any one of claims 12 to 14, wherein the third conductive member surrounds the three surfaces of the first conductive member and the three surfaces of the second conductive member.

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