Driver circuit and its driving method, array substrate, display device

Abstract

A driver circuit and driving method thereof, an array substrate, and a display device are disclosed. The circuit includes: a logic control module; and a plurality of pins coupled to the logic control module. The plurality of pins includes: a clock pin, a data pin, and at least two output pins. The clock pin is configured to receive a clock signal. The data pin is configured to receive a data signal under the control of the logic control module during a valid level of the clock signal. The logic control module is configured to generate drive control signals corresponding to each output pin based on the data signals, so as to control electrical signals via the output pins.

Description

Technical Field

[0001] This application claims priority from PCT International Patent Application No. PCT / CN2021131003, filed on November 16, 2021, the disclosure of which is incorporated herein by reference in its entirety. This disclosure relates to the field of display technology, and more particularly to a driver circuit and driving method thereof, an array substrate, and a display device. Prior Art

[0002] Light emitting diodes (LEDs) are widely used in traditional displays, near-eye displays, 3D displays, and transparent displays due to their many advantages, including high efficiency, high brightness, high reliability, energy saving, and fast response speed. Summary of the Invention

[0003] In one aspect, a driver circuit is provided. The driver circuit includes a logic control module and a plurality of pins coupled to the logic control module. The plurality of pins include a clock pin, a data pin, and at least two output pins. The clock pin is configured to receive a clock signal. The data pin is configured to receive the data signal under the control of the logic control module during a phase in which the clock signal is at an active level. The logic control module is configured to generate a drive control signal corresponding to each output pin based on the data signal, thereby controlling the electrical signal flowing through the output pin.

[0004] In some embodiments, the effective level stage of the clock signal includes: a rising edge stage of the clock signal.

[0005] In some embodiments, the frequency of the clock signal is the same as the frequency of the data signal.

[0006] In some embodiments, the data signal includes address information and brightness information. The logic control module is further configured to compare the address information in the data signal with the address information of the driver circuit, and if the two match, obtain the brightness information in the data signal and generate the drive control signal based on the brightness information in the data signal.

[0007] In some embodiments, the data signal includes a first sub-data signal and a second sub-data signal. The address information includes: first address information in the first sub-data signal, and second address information in the second sub-data signal. The brightness information includes: amplitude information in the first sub-data signal, and duty cycle information in the second sub-data signal. The logic control module is further configured to compare the first address information with the address information of the driver circuit, and if the two match, generate an amplitude signal based on the amplitude information to control the amplitude of the electrical signal flowing through the output pin; and compare the second address information with the address information of the driver circuit, and if the two match, generate a duty cycle selection signal based on the duty cycle information to control the duration of the electrical signal flowing through the output pin.

[0008] In some embodiments, the plurality of pins further include: an address pin and a relay pin. The address pin is configured to receive an address signal. The logic control module is further configured to configure address information of the driver circuit based on the address signal and generate a relay signal based on the address signal. The relay pin is configured to output the relay signal.

[0009] In some embodiments, the plurality of pins further include: a chip power pin and a ground pin. The chip power pin is configured to receive a power supply voltage signal for driving the driver circuit. The ground pin is configured to receive a ground voltage signal.

[0010] In some embodiments, the number of the plurality of pins is an even number. Along the length direction of the driver circuit, the plurality of pins are arranged in two rows, and the number of pins in each row is the same.

[0011] In some embodiments, the number of the output pins is four. Each row of pins includes two output pins, and at least one pin is disposed between the two output pins.

[0012] In another aspect, a method for driving a driver circuit is provided. The method is applied to the driver circuit described in any of the above embodiments. The method includes: a clock pin in the driver circuit receives a clock signal; when the clock signal is at an active level, a logic control module in the driver circuit controls a data pin in the driver circuit to receive a data signal; and the logic control module generates a drive control signal corresponding to each output pin in the driver circuit based on the data signal to control the electrical signal flowing through the output pin.

[0013] In some embodiments, the data signal includes address information and brightness information. Generating a drive control signal corresponding to each output pin in the driver circuit based on the data signal includes: the logic control module comparing the address information in the data signal with the address information of the driver circuit; if the address information and the address information match, obtaining the brightness information in the data signal; and generating the drive control signal based on the brightness information in the data signal.

[0014] In some embodiments, the clock signal includes a first sub-clock signal and a second sub-clock signal; the data signal includes a first sub-data signal and a second sub-data signal; the address information includes: first address information in the first sub-data signal and second address information in the second sub-data signal; the brightness information includes: amplitude information in the first sub-data signal and duty cycle information in the second sub-data signal. The driving method includes: a driving configuration phase and a device control phase. In the driving configuration phase, when the first sub-clock signal is at a valid level, the logic control module controls the data pin to receive the first address information and compares the first address information with the address information of the driver circuit; if the two match, the logic control module controls the data pin to obtain the amplitude information and generates an amplitude signal based on the amplitude information. In the device control stage, at the valid level stage of the second sub-clock signal, the logic control module controls the data pin to receive the second address information and compares the second address information with the address information of the driver circuit; when the two match, the logic control module controls the data pin to obtain the duty cycle information and generates a duty cycle selection signal based on the duty cycle information.

[0015] In some embodiments, the clock signal further includes a third sub-clock signal preceding the first sub-clock signal; the data signal further includes a third sub-data signal; the address information further includes third address information within the third sub-data signal; and the brightness information further includes initialization information within the third sub-data signal. During the drive configuration phase, when the third sub-clock signal is at a valid level, the logic control module controls the data pin to receive the third address information and compares the third address information with the address information of the driver circuit. If the third address information matches, the logic control module controls the data pin to obtain the initialization information to initialize and configure the driver circuit.

[0016] In some embodiments, the frequency of the first sub-clock signal is the same as the frequency of the first sub-data signal; the frequency of the second sub-clock signal is the same as the frequency of the second sub-data signal; and the frequency of the third sub-clock signal is the same as the frequency of the third sub-data signal.

[0017] In yet another aspect, an array substrate is provided. The array substrate comprises: a plurality of driver circuits as described in any of the above embodiments; and a device group coupled to each output pin of the driver circuit. The device group comprises at least one functional element.

[0018] In some embodiments, the array substrate further includes: a plurality of signal lines. The plurality of driver circuits are arranged in a plurality of rows along a first direction. The plurality of signal lines include: a plurality of clock signal lines extending along the first direction; a plurality of data signal lines extending along the first direction; and a plurality of device power signal lines extending along the first direction. A clock signal line is coupled to a plurality of clock pins of a row of driver circuits; a data signal line is coupled to a plurality of data pins of a row of driver circuits; and the plurality of device groups coupled to a row of driver circuits are also coupled to at least one device power signal line.

[0019] In some embodiments, the plurality of device groups are arranged in multiple rows along the first direction. At least two of the device groups coupled to the driver circuit are located on either side of the driver circuit. The number of device power signal lines corresponding to the same row of driver circuits is two, and the two device power signal lines are located on opposite sides of the same row of driver circuits.

[0020] In some embodiments, the two rows of device groups located between any two adjacent rows of driver circuits are coupled to the same device power signal line.

[0021] In some embodiments, the driver circuit includes an address pin and a relay pin. In the same row of driver circuits, the relay pin of the Nth driver circuit is coupled to the address pin of the (N+1)th driver circuit, where N is a positive integer.

[0022] In some embodiments, the driver circuit includes an address pin and a relay pin. Among the plurality of driver circuits, the relay pin of the Mth driver circuit is coupled to the address pin of the M+1th driver circuit, where M is a positive integer.

[0023] In some embodiments, the plurality of signal lines further include: a plurality of address signal lines, wherein the relay pin of the Nth driver circuit is coupled to one end of the address signal line, and the address pin of the (N+1)th driver circuit is coupled to the other end of the address signal line.

[0024] In some embodiments, the plurality of signal lines further include: at least one feedback signal line. In the same row driver circuit, when the relay pin of the Nth driver circuit is coupled to the address pin of the (N+1)th driver circuit, the relay pin of the last driver circuit in any row driver circuit is coupled to one of the feedback signal lines; and in the plurality of driver circuits, when the relay pin of the Mth driver circuit is coupled to the address pin of the (M+1)th driver circuit, the relay pin of the last driver circuit is coupled to the feedback signal line.

[0025] In some embodiments, the driver circuit further includes a chip power pin and a ground pin. The plurality of signal lines further include: a plurality of chip power signal lines extending along the first direction; and a plurality of ground signal lines extending along the first direction. One chip power signal line is coupled to the plurality of chip power pins of a row of driver circuits; and one ground signal line is coupled to the plurality of ground pins of a row of driver circuits.

[0026] In some embodiments, the array substrate further includes a controller circuit coupled to the plurality of signal lines, wherein the controller circuit is configured to transmit corresponding signals to the plurality of signal lines respectively.

[0027] In some embodiments, the array substrate further includes: a substrate; a drive circuit layer disposed on one side of the substrate; and a device layer. The drive circuit layer includes a drive trace layer, an insulation layer, and a wiring layer stacked in sequence; the plurality of signal lines are located in the drive trace layer. The plurality of driver circuits and the device groups are located in the device layer. The wiring layer includes: a plurality of die pads bonded to the plurality of driver circuits; a plurality of device pads bonded to the plurality of device groups; and a plurality of connection lines respectively coupled to the plurality of die pads and the drive trace layer, and to the plurality of device pads and the drive trace layer.

[0028] In another aspect, a display device is provided, comprising: at least one array substrate according to any one of the above embodiments.

[0029] In some embodiments, the display device further includes: a driving substrate disposed on one side of the array substrate; a color filter substrate disposed on a side of the driving substrate away from the array substrate; and a liquid crystal layer disposed between the driving substrate and the color filter substrate. Simple diagram description

[0030] To more clearly illustrate the technical solutions of this disclosure, the following briefly describes the drawings required for use in some embodiments of this disclosure. Obviously, the drawings described below are merely illustrations of some embodiments of this disclosure, and those skilled in the art can derive other drawings based on these drawings. Furthermore, the drawings described below should be viewed as schematic diagrams and are not intended to limit the actual dimensions of the products, actual process flow of the methods, or actual timing of signals involved in the embodiments of this disclosure. Figure 1 is a structural diagram of a driver circuit according to some embodiments of the present disclosure; Figure 2 is a structural diagram of another driver circuit according to some embodiments of the present disclosure; Figure 3 is a structural diagram of another driver circuit according to some embodiments of the present disclosure; Figure 4 is a structural diagram of another driver circuit according to some embodiments of the present disclosure; Figure 5 is a structural diagram of another driver circuit according to some embodiments of the present disclosure; Figure 6 is a timing diagram corresponding to the driver circuit shown in Figure 1 according to the present disclosure; Figure 7 is a flowchart of a driving method of a driver circuit according to some embodiments of the present disclosure; Figure 8 is a structural diagram of an array substrate according to some embodiments of the present disclosure; Figure 9 is a structural diagram of another array substrate according to some embodiments of the present disclosure; Figure 10 is a structural diagram of another array substrate according to some embodiments of the present disclosure; Figure 11 is a structural diagram of another array substrate according to some embodiments of the present disclosure; Figure 12 is a partial structural diagram of an array substrate according to some embodiments of the present disclosure; Figure 13 is a partial structural diagram of another array substrate according to some embodiments of the present disclosure; Figure 14 is a film structure diagram of an array substrate according to some embodiments of the present disclosure; Figure 15 is a film structure diagram of another array substrate according to some embodiments of the present disclosure; Figure 16 is a block diagram of a controller circuit according to some embodiments of the present disclosure; FIG17 is a structural diagram of a display device according to some embodiments of the present disclosure. Implementation Method

[0031] The following, in conjunction with the accompanying drawings, clearly and completely describes the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only a portion of the embodiments of the present disclosure, and not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments provided herein are within the scope of protection of the present disclosure.

[0032] Throughout the specification and claims, unless the context requires otherwise, the term "comprise" and its alternative forms, such as the third-person singular form "comprises" and the present participle form "comprising," are to be interpreted as open and inclusive, meaning "including, but not limited to." Throughout the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any appropriate manner in any one or more embodiments or examples.

[0033] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of this disclosure, unless otherwise specified, "plurality" means two or more.

[0034] When describing some embodiments, the term "coupled" and its derivatives may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0035] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0036] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0037] As used herein, the term "if" is optionally interpreted to mean "when" or "at" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0038] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0039] In addition, the use of "based on" is meant to be open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0040] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0041] Example embodiments are described herein with reference to cross-sectional and / or plan views that are idealized example drawings. In the drawings, the dimensions of layers and regions are exaggerated for clarity. Thus, variations from the shapes of the drawings due to, for example, manufacturing techniques and / or tolerances, are contemplated. Thus, the example embodiments should not be construed as limited to the shapes of the regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing. For example, an etched region illustrated as a rectangle will typically have curved features. Thus, the regions illustrated in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the example embodiments.

[0042] Some embodiments of the present disclosure provide a driver circuit MIC and a driving method thereof, an array substrate 100, and a display device 1000. The driver circuit MIC and a driving method thereof, the array substrate 100, and the display device 1000 are schematically described below in conjunction with the accompanying drawings.

[0043] In some embodiments, as shown in Figures 8 to 11 , the array substrate 100 includes: a plurality of driver circuits MIC and at least two device groups EC coupled to each driver circuit MIC. Each device group EC includes at least one functional element FE (see Figure 14 ). The plurality of driver circuits MIC can, for example, be bonded to the array substrate 100.

[0044] In some examples, each device group EC may include one, two, three, four, or other functional elements FE. When a device group EC includes at least two functional elements FE, the at least two functional elements FE may be connected in series, for example. The number of functional elements FE included in each device group EC may be selected and set according to actual needs, and is not limited in this disclosure.

[0045] Optionally, in the present disclosure, the functional elements FE may be current-driven electronic components, such as heating elements, light-emitting elements, or sound-generating elements. They may also be electronic components that implement sensing functions, such as photosensors, thermosensors, and acoustic-electric transducer elements. The types of functional elements FE included in each device group EC may be the same or different. The number and type of functional elements FE included in any two device groups EC may be the same or different.

[0046] Exemplarily, the functional elements FE included in each device group EC are of the same type, for example, all light-emitting elements. Each device group EC includes the same number of functional elements FE, for example, four functional elements FE. The functional elements FE included in each device group EC are electrically connected in the same manner, for example, all connected in series. Configuring each device group EC in the same manner helps minimize differences between the device groups EC, minimize differences in signals received by the device groups EC, and minimize differences in luminance emitted by the device groups EC, thereby facilitating driving and debugging of the array substrate 100.

[0047] For example, the above-mentioned light-emitting element can be an LED, a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a quantum dot-organic light-emitting diode (QD-OLED) or an organic polymer light-emitting diode (PLED), etc.

[0048] Optionally, in the present disclosure, the driver circuit MIC may be an integrated circuit, or may be a packaged chip with pins.

[0049] In some examples, as shown in FIG1 , the driver circuit MIC includes a logic control module CTR and a plurality of pins P coupled to the logic control module CTR. The plurality of pins P include a clock pin CLKP, a data pin DataP, and at least two output pins OutP. For example, the number of output pins OutP can be two, three, or four.

[0050] Exemplarily, the clock pin CLKP is configured to receive a clock signal CLK. The clock signal CLK can be transmitted to the logic control module CTR and received by the logic control module CTR.

[0051] Exemplarily, the data pin DataP is configured to receive a data signal under the control of the logic control module CTR when the clock signal CLK is at a valid level.

[0052] For example, the logic control module CTR can detect and judge the clock signal CLK. When it is determined that the clock signal CLK is at a valid level, it can control the data pin DataP to receive the data signal Data (or sample the data signal Data). The data signal Data received by the data pin DataP can be transmitted to the logic control module CTR.

[0053] For example, the data signal Data can be transmitted in the form of data packets. During one operating cycle of the driver circuit MIC, the data pin DataP can receive multiple data packets under the control of the logic control module CTR. Within these multiple data packets, there is a time interval between any two adjacent data packets. Optionally, each data packet may comprise what can be called a sub-data signal. These multiple data packets may include: a first sub-data signal Data1, a second sub-data signal Data2, and a third sub-data signal Data3, etc.

[0054] For example, the clock signal CLK may be a square wave signal, and the data signal Data may be a digital signal. The clock signal CLK includes a plurality of active-level phases spaced sequentially apart. The logic control module CTR may control the data pin DataP to receive (or sample) the data signal Data once during each active-level phase, and receive the sampled data signal Data.

[0055] It will be appreciated that, as shown in FIG6 , the clock signal CLK may include multiple sub-clock signals, such as a first sub-clock signal CLK1, a second sub-clock signal CLK2, and a third sub-clock signal CLK3. The duration of each sub-clock signal may correspond to the transmission time of a data packet. For example, the duration of the first sub-clock signal CLK1 may correspond to the transmission time of the first sub-data signal Data1, the duration of the second sub-clock signal CLK2 may correspond to the transmission time of the second sub-data signal Data2, and the duration of the third sub-clock signal CLK3 may correspond to the transmission time of the third sub-data signal Data3. Each sub-clock signal has a fixed period (the period of different sub-clock signals can be the same), and within each period, the level of the sub-clock signal switches between a high level and a low level.

[0056] For example, between any two adjacent sub-clock signals, the clock pin CLKP may also receive a high-level signal, and correspondingly, the data pin DataP may also receive a high-level signal.

[0057] Optionally, the phase of the effective level of the clock signal CLK may include a rising edge phase of the clock signal CLK. That is, each time the logic control module CTR detects a rising edge phase of the clock signal CLK, it may receive the data signal Data.

[0058] It is understood that the duty cycle of the clock signal CLK is adjustable. That is, the duration of the high level and the duration of the low level within one cycle of the clock signal CLK are adjustable. By receiving the data signal Data during the rising edge of the clock signal CLK, the regularity and accuracy of the data signal Data received by the logic control module CTR can be improved.

[0059] Of course, the present disclosure may also include other examples of the effective level phase of the clock signal CLK, which can be selected and set according to actual needs, and the present disclosure is not limited thereto. For example, the effective level phase of the clock signal CLK may also include a high level phase or a falling edge phase of the clock signal CLK.

[0060] Optionally, the frequency of the clock signal CLK is the same as the frequency of the data signal Data. This helps ensure that the logic control module CTR can receive the data signal Data each time it detects a valid level of the clock signal CLK, thereby avoiding a situation where the data signal Data cannot be sampled based on the clock signal CLK.

[0061] For example, the frequency of the clock signal CLK may be 8 MHz.

[0062] For example, when the clock signal CLK includes a first sub-clock signal CLK1, a second sub-clock signal CLK2, and a third sub-clock signal CLK3, and the data signal includes a first sub-data signal Data1, a second sub-data signal Data2, and a third sub-data signal Data3, the frequency of the first sub-clock signal CLK1 is, for example, the same as the frequency of the first sub-data signal Data1; the frequency of the second sub-clock signal CLK2 is, for example, the same as the frequency of the second sub-data signal Data2; and the frequency of the third sub-clock signal CLK3 is, for example, the same as the frequency of the third sub-data signal Data3. This allows the logic control module CTR to receive all sub-data signals.

[0063] In other embodiments of the present disclosure, if the frequency of the clock signal CLK is different from the frequency of the data signal Data, then after receiving the clock signal CLK, the logic control module CTR may, for example, perform frequency division or frequency multiplication on the clock signal CLK to generate a frame rate signal. That is, the frequency of the frame rate signal may be higher or lower than the frequency of the clock signal CLK, so that the frequency of the generated frame rate signal may be the same as the frequency of the data signal Data. Then, the logic control module CTR may receive (or sample) the data signal Data according to the frame rate signal to ensure the regularity and accuracy of the reception of the data signal Data.

[0064] Exemplarily, the logic control module CTR is configured to generate a drive control signal corresponding to each output pin OutP based on the data signal Data, thereby controlling the electrical signal (e.g., current signal) flowing through each output pin OutP. Each output pin OutP can be coupled to a device cluster EC. That is, the number of device clusters EC coupled to each driver circuit MIC can be the same as the number of output pins OutP included in the driver circuit MIC. Thus, the electrical signal flowing through each output pin OutP can be transmitted to the corresponding device cluster EC.

[0065] For example, during the phase where the clock signal CLK is at an active level, the logic control module CTR can generate a drive control signal based on each data signal Data received (or sampled) by the data pin DataP. The logic control module CTR can, for example, generate at least two drive control signals, each of which can correspond one-to-one with an output pin OutP. In this way, the logic control module CTR can use each drive control signal to control the electrical signal passing through the corresponding output pin OutP, thereby controlling the operating state of the corresponding device assembly EC.

[0066] In one implementation, the clock signal is included in the data signal, and the driver circuit receives the data signal, including the clock signal, only through the data pin. This means that the clock signal occupies part of the data signal's time, which reduces the frequency and rate of the data signal, thereby reducing the operating frequency of the driver circuit and, consequently, the operating frequency of the array substrate (e.g., the data refresh rate).

[0067] Furthermore, in the aforementioned implementation, when the driver circuit generates a drive control signal to control the operating state of the device group, the crystal oscillator within the driver circuit corrects the clock signal to align the clock signals received by different driver circuits. However, due to inevitable manufacturing process variations, this can lead to differences in the crystal oscillators within different driver circuits, resulting in differences in the frequencies of the crystal oscillators themselves. This can easily lead to errors in the process of receiving data signals based on the clock signal.

[0068] The driver circuit MIC provided in some embodiments of the present disclosure provides a clock pin CLKP and separates the clock signal CLK from the data signal Data. This allows the clock pin CLKP and the data pin DataP to independently receive the clock signal CLK and the data signal Data, respectively. This allows the portion of the data signal Data containing the clock signal CLK to be released, allowing the data signal Data to be added during this portion of time. This results in a more uniform type of data signal Data received by the data pin DataP. This helps increase the frequency and rate of the data signal Data, thereby increasing the operating frequency of the driver circuit MIC and the array substrate 100. According to the inventors' calculations, the rate of the data signal Data can be increased by approximately 30%.

[0069] Moreover, in the array substrate 100 provided in some embodiments of the present disclosure, the controller circuit 1 provides a clock signal CLK to the clock pins CLKP of all driver circuits MIC, so that the frequencies of the clock signals CLK received by different driver circuits MIC are the same, which is beneficial to improving the accuracy of the received data signal Data.

[0070] In addition, it can be understood that since each device group EC can form a signal channel after being connected to the output pin OutP of the corresponding driver circuit MIC, and the driver circuit MIC includes multiple output pins OutP, the driver circuit MIC provided by the present disclosure can also be called a multi-channel driver circuit.

[0071] In one implementation of the present disclosure, the driver circuit includes only one output pin and is coupled to only one device group via this output pin. This driver circuit can be referred to as a single-channel driver circuit. In this case, the number of driver circuits included in the array substrate will be the same as the number of device groups, requiring a larger number of driver circuits.

[0072] In other implementations of the present disclosure, the driver circuit MIC is a multi-channel driver circuit including at least two output pins OutP. Each driver circuit MIC can be coupled to at least two device groups EC and can simultaneously drive the at least two device groups EC. This can significantly reduce the number of driver circuits MIC required for the array substrate 100, thereby lowering the cost of the array substrate. Furthermore, the reduction in the number of driver circuits MIC required for the array substrate 100 not only reduces the difficulty in manufacturing the array substrate 100, shortens the time required to mount and bond the driver circuit MIC to the array substrate, and improves the efficiency of manufacturing the array substrate 100, but also helps reduce the impact of the bonding yield of the driver circuit MIC on the yield of the array substrate 100, thereby improving the yield of the array substrate 100. It should be noted that the "simultaneous driving" or "simultaneous operation" referred to in this disclosure can have a temporal sequence of nanoseconds.

[0073] Furthermore, the present disclosure not only reduces the number of driver circuits MIC required for the array substrate 100, but also helps reduce the area occupied by the driver circuits MIC. For example, the driver circuit MIC in the present disclosure includes four output pins OutP (this driver circuit MIC can be referred to as a four-channel driver circuit), and the area of ​​this device driver circuit MIC can be 0.5936 mm². The area of ​​a single-channel driver circuit is 0.1681 mm², and the total area of ​​the four single-channel driver circuits controlling the four device groups is 0.6724 mm². Therefore, the area occupied by each driver circuit MIC in the present disclosure is less than the total area occupied by the four single-channel driver circuits, thereby helping to reduce the area of ​​the array substrate 100.

[0074] In the following, we take the example of a Mini LED as the light-emitting element FE included in each device group EC. For example, the electrical signal (current, for example) flowing through each output pin OutP has multiple states, including the amplitude of the current flowing through each output pin OutP and the duration of the current flowing through each output pin OutP.

[0075] It should be noted that when the functional element FE emits light, the brightness exhibited by the functional element FE is related to the amplitude and duration of the current it receives. For example, if the duration of the current received by the functional element FE is constant, the greater the amplitude of the current, the greater the brightness exhibited by the functional element FE, while the smaller the amplitude of the current, the smaller the brightness exhibited by the functional element FE. If the amplitude of the current received by the functional element FE is constant, the longer the duration of the current received, the greater the brightness exhibited, while the shorter the duration of the current received, the smaller the brightness exhibited. In this way, by controlling the current state of each output pin OutP, the brightness exhibited by each functional element FE can be controlled.

[0076] For example, the brightness presented by each functional element FE included in the same device group EC may be the same, and the brightness presented by each functional element FE included in different device groups EC may be the same or different.

[0077] In some embodiments, the data signal Data received by the data pin DataP may include address information and brightness information. The logic control module CTR is further configured to compare the address information in the data signal Data with the address information of the driver circuit MIC. If the two match, the logic control module CTR obtains the brightness information in the data signal Data and generates a drive control signal based on the brightness information in the data signal Data.

[0078] In some examples, each driver circuit MIC is configured with address information, which can represent the location of the driver circuit MIC in the array substrate 100. Different driver circuits MIC have different locations in the array substrate 100, and therefore, different driver circuits MIC have different address information.

[0079] In some examples, the data signal Data received by the data pins DataP of different driver circuits MIC is the same signal. The data signal Data includes multiple signal groups, each corresponding one-to-one to the multiple driver circuits MIC included in the array substrate 100. Each signal group includes address information and brightness information corresponding to the corresponding driver circuit MIC. Because each driver circuit MIC is coupled to at least two device groups EC, the brightness information corresponding to each driver circuit MIC can include brightness information corresponding to the at least two device groups EC.

[0080] For example, when the data pin DataP receives the data signal Data, the logic control module CTR of each driver circuit MIC can compare its own address information with the multiple address information in the data signal Data. If the address information matches (for example, the address information is the same), the logic control module CTR can obtain the signal group corresponding to the address information from the data signal Data, and then obtain the brightness information from the signal group, and then generate a driving control signal based on the brightness information.

[0081] In some examples, the logic control module CTR may include a decoder that can decode the data signal Data to obtain address information and brightness information in the data signal Data.

[0082] In some embodiments, the data signal Data may include a first sub-data signal Data1 and a second sub-data signal Data2. The address information includes first address information in the first sub-data signal Data1 and second address information in the second sub-data signal Data2. The brightness information includes amplitude information in the first sub-data signal and duty cycle information in the second sub-data signal Data2.

[0083] Here, the process of the logic control module CTR receiving the first sub-data signal and the second sub-data signal Data2 according to the clock signal CLK can be referred to the description in some of the above embodiments and will not be repeated here.

[0084] Exemplarily, the data pins DataP of different driver circuits MIC receive the same first sub-data signal Data1. The first sub-data signal Data1 may include multiple first signal groups, each corresponding one-to-one to a driver circuit MIC included in the array substrate 100. Each first signal group includes first address information and amplitude information corresponding to the corresponding driver circuit MIC. Because each driver circuit MIC is coupled to at least two device groups EC, the amplitude information corresponding to each driver circuit MIC may include amplitude information corresponding to the at least two device groups EC.

[0085] Exemplarily, the data pins DataP of different driver circuits MIC receive the same second sub-data signal Data2. The second sub-data signal Data2 may include multiple second signal groups, each corresponding one-to-one to a driver circuit MIC included in the array substrate 100. Each second signal group includes second address information and duty cycle information corresponding to the corresponding driver circuit MIC. Because each driver circuit MIC is coupled to at least two device groups EC, the duty cycle information corresponding to each driver circuit MIC may include duty cycle information corresponding to the at least two device groups EC.

[0086] For example, the first address information and the second address information can be of the same type. The amplitude information and the duty cycle information are different types of information. Therefore, the amplitude information and the duty cycle information can be transmitted to the data pin DataP twice.

[0087] For example, since the brightness displayed by the functional element FE is determined by both the amplitude and duration of the current it receives, the brightness information in the data signal Data may include current amplitude information and duty cycle information. The current amplitude information may represent the amplitude of the current received by the functional element FE, while the duty cycle information may represent the frequency of the current received by the functional element FE and the sub-duration of each current reception. It is understood that within a single operating cycle of the driver circuit MIC, the duration of the current received by the functional element FE is the sum of multiple sub-durations.

[0088] In some examples, the logic control module CTR is further configured to compare the first address information with the address information of the driver circuit MIC. If the first address information matches the address information of the driver circuit MIC, the module generates an amplitude signal based on the amplitude information to control the amplitude of the electrical signal flowing through the output pin OutP. Furthermore, the logic control module CTR is configured to compare the second address information with the address information of the driver circuit MIC. If the second address information matches the address information of the driver circuit MIC, the module generates a duty cycle selection signal based on the duty cycle information to control the duration of the electrical signal flowing through the output pin OutP. In other words, the drive control signal may include an amplitude signal and a duty cycle selection signal.

[0089] For example, when the data pin DataP receives the first sub-data signal Data1, the logic control module CTR of each driver circuit MIC can compare its own address information with the multiple first address information in the first sub-data signal Data1. If the address information of the two matches (for example, the address information of the two is the same), the logic control module CTR can obtain the first signal group to which the first address information belongs from the first sub-data signal Data1, and obtain amplitude information from the first signal group, and then generate an amplitude signal based on the amplitude information. This amplitude signal can determine the amplitude of the electrical signal passing through the output pin OutP, and thus the amplitude of the electrical signal (i.e., the current) transmitted to the functional element FE.

[0090] For example, when the data pin DataP receives the second sub-data signal Data2, the logic control module CTR of each driver circuit MIC can compare its own address information with the plurality of second address information in the second sub-data signal Data2. If the address information of the two sub-data signals matches (e.g., the address information of the two sub-data signals is the same), the logic control module CTR can obtain the second signal group to which the second address information belongs from the second sub-data signal Data2, and then obtain the duty cycle information from the second signal group. Furthermore, the logic control module CTR can generate a duty cycle selection signal based on the duty cycle information. The duty cycle selection signal can determine the frequency of the electrical signal (i.e., current) passing through the output pin OutP and the duration of each current passing through the output pin OutP, thereby determining the frequency of the current transmitted to the functional element FE and the duration of each current transmitted to the functional element FE.

[0091] In some embodiments, as shown in FIG1 to FIG4 , the plurality of pins P in the driver circuit MIC further includes a ground pin GNDP, wherein the ground pin GNDP is configured to receive a ground voltage signal.

[0092] In some examples, the ground pin GNDP can serve as a loop and reference for various signals in the driver circuit MIC.

[0093] In some examples, as shown in FIG1 , the logic control module CTR may include a control module CLM and at least two modulation modules PWMM. The output pins OUTP included in the driver circuit MIC may be configured to correspond one-to-one with the modulation modules PWMM. Each modulation module PWMM may be coupled to its corresponding output pin OUTP.

[0094] Exemplarily, the control module CLM is configured to generate a drive control signal (e.g., a duty cycle selection signal) corresponding to each modulation module PWMM based on a data signal Data (e.g., the second sub-data signal Data2). The drive control signal is used to control the conduction or cutoff of the corresponding modulation module PWMM, thereby controlling the conduction or cutoff between the corresponding output pin OutP and the ground pin GNDP, thereby achieving control over the device group EC.

[0095] For example, the drive control signal can control the corresponding modulation module PWMM so that the signal flowing through the modulation module PWMM (as well as the output pin OutP coupled to the modulation module PWMM and the device group EC coupled to the output pin OutP) is a pulse-width modulation signal; the drive control signal can control the duration of the current flowing through the output pin OutP and the device group EC by modulating the pulse-width modulation signal (for example, adjusting the duty cycle of the pulse-width modulation signal).

[0096] For example, as shown in Figures 1 to 4, the driver circuit MIC may include four output pins OutP: a first output pin Out1, a second output pin Out2, a third output pin Out3, and a fourth output pin Out4. The logic control module CTR may include four modulation modules PWMM: a first modulation module PWMM1 coupled to the first output pin Out1, a second modulation module PWMM2 coupled to the second output pin Out2, a third modulation module PWMM3 coupled to the third output pin Out3, and a fourth modulation module PWMM4 coupled to the fourth output pin Out4. The control module CLM included in the logic control module CTR may generate a first drive control signal, a second drive control signal, a third drive control signal, and a fourth drive control signal based on a data signal, and transmit the signals to the first modulation module PWMM1, the second modulation module PWMM2, the third modulation module PWMM3, and the fourth modulation module PWMM4, respectively.

[0097] For example, the first drive control signal can control the on / off switching of the first modulation module PWMM1, thereby controlling the on / off switching between the first output pin Out1 and the ground pin GNDP. When the first drive control signal turns the first modulation module PWMM1 on, the ground pin GNDP, the first output pin Out1, and the device group EC coupled to the first output pin Out1 can form a signal loop, which can drive the device group EC to operate (e.g., emit light). When the first drive control signal turns the first modulation module PWMM1 off, the signal loop is disconnected, and the device group EC stops operating (e.g., stops emitting light). Under the control of the first drive control signal, the first modulation module PWMM1 can modulate the current flowing through the device group EC, adjusting the frequency of the current flowing through the device group EC and the duration of each current flow through the device group EC, so that the current flowing through the device group EC presents a pulse width modulated signal. For example, the higher the frequency of the current flowing through the device group EC and the duration of each current flowing through the device group EC, the longer the duration of the current flowing through the functional element FE in the device group EC, and the greater the brightness presented by the functional element FE; conversely, the smaller the brightness presented by the functional element FE.

[0098] Accordingly, the second drive control signal can control the on / off switching of the second modulation module PWMM2, thereby controlling the on / off switching between the second output pin Out2 and the ground pin GNDP. Under the control of the second drive control signal, the second modulation module PWMM2 can modulate the current flowing through the device group EC coupled to the second output pin Out2, such that the current flowing through the device group EC presents a pulse-width modulated signal. The third drive control signal can control the on / off switching of the third modulation module PWMM3, thereby controlling the on / off switching between the third output pin Out3 and the ground pin GNDP. Under the control of the third drive control signal, the third modulation module PWMM3 can modulate the current flowing through the device group EC coupled to the third output pin Out3, thereby controlling the on / off switching between the fourth output pin Out4 and the ground pin GNDP. The fourth drive control signal can control the on / off switching of the fourth modulation module PWMM4, thereby controlling the on / off switching between the fourth output pin Out4 and the ground pin GNDP. The fourth modulation module PWMM4 can modulate the current flowing through the device group EC coupled to the fourth output pin Out4 under the control of the fourth driving control signal, so that the current flowing through the device group EC presents a pulse width modulation signal.

[0099] For example, the first modulation module PWMM1 through the fourth modulation module PWMM4 may include switching elements, such as metal oxide semiconductor field effect transistors (MOSFETs) and thin film transistors (TFTs). The first to fourth drive control signals may be pulse width modulation signals, and the switching elements may be turned on or off under the control of the pulse width modulation signals.

[0100] Optionally, in the present disclosure, as shown in FIG1 , each modulation module PWMM is coupled to a control module CLM. The coupling between the modulation module PWMM and the control module CLM can be implemented in a variety of ways, which are not limited in the present disclosure.

[0101] For example, the driver circuit MIC further includes a data bus DB. Each modulation module PWMM (e.g., the first modulation module PWMM1 through the fourth modulation module PWMM4) can be coupled to the data bus DB and coupled to the control module CLM via the data bus DB. Of course, each modulation module PWMM can also be directly coupled to the control module CLM via wiring, or coupled to the control module CLM via other means.

[0102] In some embodiments, as shown in Figures 1 to 4 , the multiple pins P in the driver circuit MIC further include an address pin Di_in and a relay pin Di_out. The address pin Di_in is configured to receive an address signal. The logic control module CTR is further configured to configure address information for the driver circuit MIC based on the address signal and to generate a relay signal based on the address signal. The relay pin Di_out is configured to output the relay signal.

[0103] In some examples, the address signal received by the address pin Di_in corresponds to the driver circuit MIC to which the address pin Di_in belongs. The address information configured by the logic control module CTR in the driver circuit MIC based on the address signal is the address information configured for the driver circuit MIC itself, as mentioned in some of the above examples. The address information configured based on the address signal can be used to identify the location of the driver circuit MIC within the array substrate 100.

[0104] For example, the address information can be a digital signal that can be modulated into an address signal. After the driver circuit MIC receives the address signal, the logic control module CTR can parse the address signal and obtain and store the address information contained in the address signal. Furthermore, the logic control module CTR can increment the address information (e.g., by 1 or another fixed amount) and modulate the incremented address information (new address information) into a new relay signal, which serves as the address signal for another driver circuit MIC. Of course, the driver circuit MIC can also use other different functions to generate new address information.

[0105] For example, the multiple driver circuits MIC included in the array substrate 100 can be cascaded. The cascading method of the multiple driver circuits MIC can be found in the following description and will not be elaborated here. It should be noted that, for the multiple cascaded driver circuits MIC, except for the last driver circuit MIC, the relay signal output by the relay pin Di_out of the remaining driver circuits MIC is another address signal. This relay signal carries address information and can serve as the address signal received by the address pin Di_in of the next driver circuit MIC. The relay pin Di_out of the last driver circuit MIC outputs a feedback signal, such as a high-level signal. This feedback signal does not carry address information and can be transmitted to the controller circuit 1.

[0106] In some examples, as shown in FIG1 , the logic control module CTR may further include a fifth modulation module PWMM5 . The fifth modulation module PWMM5 may be coupled to the relay pin Di_out.

[0107] For example, the address signal received by the address pin Di_in can be transmitted to the control module CLM in the logic control module CTR. The control module CLM can generate a relay control signal based on the address signal and transmit the relay control signal to the fifth modulation module PWMM5. The fifth modulation module PWMM5 can generate a relay signal in response to the relay control signal and load the relay signal onto the relay pin Di_out.

[0108] Exemplarily, the fifth modulation module PWMM5 may include a switching element, such as a transistor such as a MOSFET or a TFT. The relay control signal may be a pulse-width modulation signal, and the switching element may be turned on or off under the control of the pulse-width modulation signal. When the switching element is on, the fifth modulation module PWMM5 may output a current or voltage; when the switching element is off, the fifth modulation module PWMM5 may not output a current or voltage. In this manner, the fifth modulation module PWMM5 may modulate a pulse-width modulation signal as the relay signal.

[0109] Optionally, in the present disclosure, as shown in FIG1 , the fifth modulation module PWMM5 is coupled to the control module CLM. The coupling between the fifth modulation module PWMM5 and the control module CLM can be implemented in a variety of ways, which are not limited in the present disclosure.

[0110] For example, the fifth modulation module PWMM5 can be coupled to the data bus DB and coupled to the control module CLM through the data bus DB. Of course, the fifth modulation module PWMM5 can also be coupled to the control module CLM through dedicated traces, or can be coupled to the control module CLM through other methods.

[0111] Optionally, the first modulation module PWMM1 to the fifth modulation module PWMM5 are all coupled to the control module CLM via the data bus DB. In this way, the control module CLM can interact with the first modulation module PWMM1 to the fifth modulation module PWMM5 via the data bus DB.

[0112] In some embodiments, as shown in Figures 1 to 4 , the plurality of pins P in the driver circuit MIC further include a chip power pin VCCP. The chip power pin VCCP is configured to receive a power supply voltage signal for driving the driver circuit MIC. The driver circuit MIC may include multiple circuits that operate under the power supply voltage signal.

[0113] In some examples, as shown in FIG1 , the driver circuit MIC may include a power module PWRM. A power voltage signal received by the chip power pin VCCP may be transmitted to the power module PWRM. The power module PWRM may process the power voltage signal and distribute power to various circuits of the driver circuit MIC to ensure power supply to the driver circuit MIC.

[0114] In one of the aforementioned implementations, due to the limited number of pins in a single-channel driver circuit, the single-channel driver circuit reuses the same pin. Specifically, this implementation uses the PLC protocol to superimpose the data signal on the power voltage signal, and simultaneously receives the power voltage signal with the superimposed data signal through the same pin. In this case, a voltage regulation (Vin-Vth) regulation module is required within the driver circuit MIC. After receiving the power voltage signal with the superimposed data signal, the voltage regulation module can separate the data signal from the power voltage signal. However, the voltage regulation module occupies a certain area, thereby increasing the area of ​​the single-channel driver circuit. Furthermore, a level shift module is required within the driver circuit MIC. Because the data signal level must be higher than the minimum level of the power voltage signal, and considering the overall near- and far-end differences of the array substrate, higher requirements are placed on the driving current and voltage of the level shift module, which increases the driving cost of the array substrate.

[0115] The driver circuit MIC provided in the present disclosure provides separate data pins DataP and chip power pins VCCP, and separates the data signal Data and the power voltage signal. This allows the data pins DataP and VCCP to independently receive the data signal Data and the power voltage signal, respectively. This avoids the need for a voltage regulation module and a level conversion module within the driver circuit MIC, which helps reduce the area of ​​the driver circuit MIC and lowers the driving cost of the array substrate 100. Furthermore, it reduces the current flowing through the data pins DataP and chip power pins VCCP, optimizes the quality of the data signal Data and the power voltage signal, and reduces the risk of the power voltage signal malfunctioning due to near-end and far-end variations across the array substrate 100 and the level of the data signal Data. Furthermore, this configuration avoids the need for a modulation circuit that superimposes the data signal Data and the power voltage signal, lowering the quality requirements for the power voltage signal, thereby further reducing the driving cost of the array substrate 100.

[0116] It can be understood that in some embodiments of the present disclosure, the above-mentioned data pin DataP, clock pin CLKP, output pin OutP, address pin Di_in, relay pin Di_out, chip power pin VCCP, ground pin GNDP, etc. are examples of multiple pins P included in the driver circuit MIC, but the types of pins included in the multiple pins P are not limited to this, and can be specifically selected and set according to actual needs.

[0117] In some embodiments, as shown in FIG2 to FIG4 , the plurality of pins P included in the driver circuit MIC may be arranged in multiple rows along the length direction of the driver circuit MIC. The number of pins in each row may be the same.

[0118] In this way, during the process of bonding the driver circuit MIC to the array substrate 100, the force applied to the driver circuit MIC can be made more balanced, ensuring that the plane where the driver circuit MIC is located is substantially parallel to the plane where the array substrate 100 is located, thus avoiding the driver circuit MIC from being skewed, thereby ensuring the bonding yield of the driver circuit MIC.

[0119] In some examples, as shown in FIG2 to FIG4 , the number of pins P included in the driver circuit MIC may be an even number. The pins P are arranged in two rows along the length of the driver circuit MIC, with each row having the same number of pins.

[0120] By arranging the plurality of pins P in two rows, the two rows of pins can be positioned on opposite edges of the driver circuit MIC. This facilitates observation and inspection of the bonding process during the bonding of the driver circuit MIC to the array substrate 100, thereby reducing bonding difficulty and improving bonding yield. Furthermore, this arrangement ensures a more balanced force on the driver circuit MIC, preventing the driver circuit MIC from tilting during bonding.

[0121] In some examples, as shown in Figures 2-4 , in a single driver circuit MIC, the multiple pins P may include: a data pin DataP, a clock pin CLKP, an address pin Di_in, a relay pin Di_out, a chip power pin VCCP, a ground pin GNDP, and an output pin OutP. The number of data pins DataP may be one, the number of clock pins CLKP may be one, the number of address pins Di_in may be one, the number of relay pins Di_out may be one, the number of chip power pin VCCP may be one, and the number of ground pins GNDP may be one. Thus, the number of output pins OutP may be an even number.

[0122] For example, the number of output pins OutP can be two, four, six, etc.

[0123] Exemplarily, each row of pins includes output pins OutP. This allows the output pins OutP to be distributed on both sides of the driver circuit MIC, facilitating coupling of each output pin OutP with the corresponding device group EC. This also facilitates uniform distribution of the device group EC, reduces the spacing between each output pin OutP and the corresponding device group EC, and simplifies wiring. Furthermore, using the above arrangement to position the output pins OutP can also prevent electrical interference caused by the small spacing between the output pins OutP.

[0124] For example, as shown in FIG2 to FIG4 , the number of output pins OutP is four, wherein each row of pins includes two output pins OutP, and at least one pin P is disposed between the two output pins OutP.

[0125] For example, as shown in FIG4 , a pin P may be provided between two output pins OutP in the same row of pins. In this case, the two output pins OutP may both be located in the middle of the driver circuit MIC. Alternatively, one of the two output pins OutP may be located in the middle of the driver circuit MIC, while the other may be located at a corner of the driver circuit MIC.

[0126] 2 and 3 , in the same row of pins, three pins P may be provided between two output pins OutP. In this case, the two output pins OutP may both be located at the top corners of the driver circuit MIC.

[0127] By employing the above-described arrangement method to position the output pins OutP, the uniformity of the distribution of the component group EC is further improved, simplifying wiring. Furthermore, employing the above-described arrangement method to position the output pins OutP can also prevent electrical interference caused by the close spacing between the output pins OutP.

[0128] It should be noted that the present disclosure does not limit the arrangement order of the data pin DataP, the clock pin CLKP, the address pin Di_in, the relay pin Di_out, the chip power pin VCCP and the ground pin GNDP, and the specific arrangement can be selected according to actual needs.

[0129] For example, as shown in Figures 2 and 3 , the address pins Di_in and the relay pins Di_out can be located in the same row of pins. Of course, as shown in Figure 4 , the address pins Di_in and the relay pins Di_out can also be located in different rows of pins. The arrangement of the address pins Di_in and the relay pins Di_out can be determined based on the cascade relationship of the driver circuit MIC. The cascade relationship of the driver circuit MIC can be found in the following description and will not be further elaborated here.

[0130] For example, the chip power pin VCCP and the data pin DataP may be located in different rows of pins.

[0131] For example, as shown in FIG2 and FIG3, in the same driver circuit MIC, one row of pins may include an output pin OutP, a relay pin Di_out, a chip power pin VCCP, an address pin Di_in, and an output pin OutP arranged in sequence, and another row of pins may include an output pin OutP, a data pin DataP, a ground pin GNDP, a clock pin CLKP, and an output pin OutP arranged in sequence.

[0132] For another example, as shown in FIG4 , in the same driver circuit MIC, one row of pins may include a clock pin CLKP, an output pin OutP, an address pin Di_in, an output pin OutP, and a chip power pin VCCP arranged in sequence, while another row of pins may include a data pin DataP, an output pin OutP, a relay pin Di_out, an output pin OutP, and a ground pin GNDP arranged in sequence.

[0133] In some examples, the distance between the pin P of the driver circuit MIC and the edge of the driver circuit MIC can be in the range of 25 μm to 40 μm. This can not only make the driver circuit MIC have a smaller area, but also reduce the difficulty of manufacturing the driver circuit.

[0134] In the present disclosure, a length direction of the driver circuit MIC may be referred to as a first direction Y, and a width direction of the driver circuit MIC may be referred to as a second direction X.

[0135] For example, in the same row of pins, the spacing between two adjacent pins P can be 0.8 to 1.2 times the size of one pin P in the first direction Y. This not only increases the bonding process window for the pins P and reduces bonding defects caused by alignment deviation, but also reduces the spacing between the two adjacent pins P, avoiding an increase in the area of ​​the driver circuit MIC and reducing the cost of the array substrate 100.

[0136] For example, the size of the pins P of the driver circuit MIC in the first direction Y may range from 80 μm to 120 μm. In the same row of pins, the distance between two adjacent pins P in the first direction Y may range from 80 μm to 100 μm.

[0137] For example, the spacing between two rows of pins can be 0.8 to 1.2 times the size of a pin P in the second direction X. This not only increases the bonding process window of the pins P and reduces bonding defects caused by alignment deviation, but also reduces the spacing between two adjacent pins P, avoiding an increase in the area of ​​the driver circuit MIC and reducing the cost of the array substrate 100.

[0138] For example, the size of the pins P of the driver circuit MIC in the second direction X may range from 120 μm to 150 μm, and the spacing between two rows of pins may range from 130 μm to 170 μm.

[0139] Figure 5 is a schematic diagram of the structure of a driver circuit MIC. The driver circuit MIC includes four output pins OutP. The figure only shows the structures of a first modulation module PWMM1 coupled to the first output pin Out1, a second modulation module PWMM2 coupled to the second output pin Out2, and a fourth modulation module PWMM4 coupled to the fourth output pin Out4. Reference can be made to the first modulation module PWMM1.

[0140] The structure and function of the driver circuit MIC are schematically described below with reference to FIG5 .

[0141] In some examples, as shown in FIG5 , the driver circuit MIC may include: a voltage regulation circuit C310 , a low-dropout voltage regulator C330 , and an oscillator C340 .

[0142] For example, the power supply voltage signal received by the chip power supply pin VCCP can be transmitted to the voltage regulation circuit C310. The voltage regulation circuit C310 can regulate the power supply voltage signal to obtain a DC component in the power supply voltage signal, and can generate a supply voltage based on the DC component. The voltage regulation circuit C310 can provide the supply voltage to the low-dropout voltage regulator C330. The low-dropout voltage regulator C330 can convert the supply voltage into a relatively stable DC voltage (which can be gradually reduced in voltage) and transmit this DC voltage to the oscillator C340, the control module CLM, or other components (not shown), thereby providing power to the oscillator C340, the control module CLM, or other components (not shown).

[0143] For example, the voltage regulation circuit C310 may include a first-order RC filter followed by an active follower. The relatively stable DC voltage may be 1.8 volts. The oscillator C340 may provide a clock signal, the maximum frequency of which may be, for example, approximately 10 MHz. It should be noted that the clock signal provided by the oscillator C340 is different from the clock signal CLK received by the clock pin CLKP.

[0144] Exemplarily, the power module PWRM in the driver circuit MIC may include the aforementioned voltage regulation circuit C310 and the low voltage dropout regulator C330.

[0145] In some examples, as shown in FIG5 , the driver circuit MIC may further include: a control module CLM.

[0146] Exemplarily, the control module CLM may include a data link circuit and a control logic circuit. The data link circuit is configured to couple with circuits / modules or structures outside the control module CLM, such as the address pin Di_in, the data pin DataP, and the data bus DB. The control logic circuit is configured to receive external signals (e.g., an address signal received by the address pin Di_in, a data signal Data received by the data pin DataP, a clock signal CLK received by the clock pin CLKP, a DC voltage output by the low-dropout regulator C330, a clock signal output by the oscillator C340, etc.) through the data link circuit, and to generate drive control signals (e.g., first to fifth drive control signals) and output them through the data link circuit.

[0147] In some examples, as shown in FIG5 , the driver circuit MIC may further include: an address driver C360.

[0148] For example, the address signal received by the address pin Di_in can be transmitted to the control module CLM, which can obtain and store the address information in the address signal. The control module CLM can increment the address information, convert the incremented address information (new address information) into a new relay signal, and transmit the new relay signal C354 to the address driver C360. The control module CLM can also output an enable signal C352. During the address configuration phase, the control module CLM can activate the enable signal C352 to enable the address driver C360, which can then buffer the new relay signal C354 to the relay pin Di_out. During the device control and driver configuration phases, the control module CLM deactivates the enable signal C352, and the output of the address driver C360 is tri-stated, effectively decoupling it from the relay pin Di_out. For details about the address configuration phase, device control phase, and driver configuration phase, please refer to the description below and will not be repeated here.

[0149] Exemplarily, the fifth modulation module PWMM5 may include the above-mentioned address driver C360.

[0150] In some examples, as shown in FIG5 , the driver circuit MIC may further include: a dimming circuit C370, a transistor C375, and a brightness control circuit C380. Of course, the driver circuit MIC may include additional, fewer, or different components.

[0151] For example, the control module CLM can output a PWM clock select signal C356 and a maximum current signal C358. During the address configuration phase, the control module CLM can control the dimming circuit C370 to turn off transistor C375, effectively blocking the current path from the device group EC. During the device control phase, the PWM clock select signal C356 is used by the dimming circuit C370 to control the duty cycle of PWM dimming. Based on the selected duty cycle, the dimming circuit C370 controls the on and off frequency and on duration of transistor C375. During the on-time of transistor C375, a current path is established from the first output pin Out1 (coupled to the device group EC) to the ground pin GNDP through transistor C375, and the brightness control circuit C380 sinks the drive current through the first output pin Out1. During the off-time of transistor C375, the current path is interrupted, preventing current from flowing through the device group EC. When transistor C375 is on, brightness control circuit C380 receives a maximum current signal C358 from control module CLM and controls the current level flowing through first output pin Out1. During the device control phase, control module CLM controls the duty cycle of dimming circuit C370 and maximum current C358 of brightness control circuit C380 to set the functional elements FE in device group EC to the desired brightness.

[0152] For example, the first modulation module PWMM1 may include the dimming circuit C370, the transistor C375, and the brightness control circuit C380. The current amplitude signal may refer to the maximum current signal C358, and the duty cycle selection signal may refer to the PWM clock selection signal C356.

[0153] In some examples, the driver circuit MIC may further include a voltage-controlled constant current circuit (not shown). The input reference voltage and input reference current of the voltage-controlled constant current circuit may be generated by a power supply voltage signal received at the chip power supply pin VCCP. The voltage-controlled constant current circuit may be coupled to the brightness control circuit C380.

[0154] In some examples, as shown in FIG5 , the first modulation module PWMM1 further includes a short-circuit detector and an open-circuit detector. The open-circuit detector comprises an operational amplifier connected in a virtual open mode and is used to detect whether a circuit break occurs between the device group EC and the driver circuit MIC. The Vopen terminal can be a floating signal terminal. The short-circuit detector comprises an operational amplifier connected in a virtual short mode and is used to detect whether a short circuit occurs between the device group EC and the driver circuit MIC. The potential of Vshort can be the same as the potential of the signal received at the other terminal of the device group EC.

[0155] For example, information about short circuits and / or open circuits between each device assembly EC and the driver circuit MIC is collected in the driver circuit MIC's control module CLM. Information is then transmitted through the driver circuit MIC's relay pin Di_out (for example, by appending the information sequentially to the end of a new relay signal C354 according to encoding rules) and transmitted step by step until it is output by the relay pin Di_out of the last driver circuit MIC in the cascaded series of multiple driver circuits MIC and fed back to the controller circuit 1. The controller circuit 1 can respond to this feedback information and promptly detect any anomalies in the driver circuit MIC or device assembly EC.

[0156] For example, during the power-up and / or address configuration phases, CRC (loop redundancy check) check information can also be outputted from the relay pin Di_out of the last driver circuit MIC in a series of multiple cascaded driver circuits MIC, and fed back to the controller circuit 1. The controller circuit 1 can respond to the feedback information and promptly detect any anomalies in the driver circuit MIC or device assembly EC.

[0157] In some examples, as shown in FIG5 , the driver circuit MIC may further include a data selector MUX and an analog-to-digital converter ADC. When the driver circuit MIC forms a signal loop with the corresponding connected device group EC via multiple output pins OutP, it can transmit the electrical signals of the multiple signal loops to the data selector MUX. These signals are then processed by the analog-to-digital converter ADC in a time-sharing manner and then transmitted to the control module CLM. These signals are then transmitted through the relay pin Di_out of the driver circuit MIC (for example, by appending the electrical signals of the multiple signal loops to a new relay signal C354 according to a sequence and coding rule) and are subsequently transmitted step by step until they are output by the relay pin Di_out of the last driver circuit MIC in the cascaded series of driver circuits MIC and fed back to the controller circuit 1. The controller circuit 1 can respond to this feedback information by adjusting the signal level it outputs (for example, the level of the device power supply voltage VLED), thereby reducing the power consumption of the array substrate 100.

[0158] In some examples, as shown in FIG5 , the driver circuit MIC may further include a thermal shutdown delay sensor TSD and a thermal shutdown delay controller TS. The thermal shutdown delay sensor TSD is used to detect the internal temperature of the driver circuit MIC. If the internal temperature of the driver circuit MIC reaches a preset protection temperature (typically set between 150°C and 170°C), the thermal shutdown delay controller TS activates and shuts down the output of the driver circuit MIC, reducing power consumption and, consequently, the internal temperature of the driver circuit MIC. If the internal temperature of the driver circuit MIC drops to a preset restart temperature (restart temperature = protection temperature - delay temperature), the driver circuit MIC resumes output. The delay temperature is typically set between 15°C and 30°C. The thermal shutdown delay controller TS can be coupled to a data selector MUX, and can then feed abnormal information back to the control module CLM via the data selector MUX to control the operating status of the driver circuit MIC.

[0159] In the following, in conjunction with the timing diagram shown in FIG6 , a driving method of the driver circuit MIC is schematically described by taking the structure of the driver circuit MIC shown in FIG1 as an example.

[0160] In some embodiments, the driving method of the driver circuit MIC includes: S100 to S300.

[0161] S100, the clock pin CLKP in the driver circuit MIC receives the clock signal CLK.

[0162] S200, at the stage of the valid level of the clock signal CLK, the logic control module CTR in the driver circuit MIC controls the data pin DataP in the driver circuit MIC to receive the data signal Data.

[0163] S300, the logic control module CTR generates a driving control signal corresponding to each output pin OutP in the driver circuit MIC according to the data signal Data, so as to control the electrical signal flowing through the output pin OutP.

[0164] In some examples, the data signal includes: address information and brightness information.

[0165] Illustratively, in the above S300, based on the data signal, a drive control signal corresponding to each output pin OutP in the driver circuit MIC is generated, including: the logic control module CTR compares the address information in the data signal Data with the address information of the driver circuit MIC, and when the two match, obtains the brightness information in the data signal Data, and generates the drive control signal based on the brightness information in the data signal Data.

[0166] Here, for the description of the clock signal CLK, the data signal Data, and the driving control signal, etc., please refer to the description in some of the above embodiments and will not be repeated here.

[0167] The beneficial effects that can be achieved by the driving method of the driver circuit MIC provided in some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the driver circuit MIC provided in some of the above embodiments, and will not be repeated here.

[0168] It should be noted that the driving method of the driver circuit MIC may include multiple stages, as shown in Figure 7, for example, it may include: a power-on stage, an address configuration stage T1, a drive configuration stage T2, a device control stage T3 and a power-off stage.

[0169] During a power-on phase, a chip power pin VCCP in the driver circuit MIC may receive a power voltage signal.

[0170] For example, the controller circuit 1 can provide a power supply voltage signal and load the power supply voltage signal to the chip power supply pin VCCP, and then provide the power supply voltage signal to the driver circuit MIC through the chip power supply pin VCCP to power the driver circuit MIC. At this time, the driver circuit MIC is in a power-on state.

[0171] Optionally, the controller circuit 1 can simultaneously load the power supply voltage signal to multiple driver circuits MIC included in the array substrate 100, thereby enabling each driver circuit MIC of the array substrate 100 to be powered on at the same time.

[0172] Optionally, the array substrate 100 can serve as a light board for providing a light source in the display device 1000. When the array substrate cooperates with the passive display panel in the display device 1000 to achieve display, after the display device 1000 is powered on and the external circuit (e.g., the circuit board driving the array substrate 1000) is powered on, the external circuit can apply a power supply voltage signal to the driver circuit MIC, thereby synchronizing the power-on of the driver circuit MIC with the power-on of the display device 1000. In some cases, after the display device 1000 is powered on, the controller circuit 1 applies a power supply voltage signal to the driver circuit MIC, so that after the driver circuit MIC is powered on, the passive display panel can display an image after a period of time. This is not a limitation here.

[0173] During the address configuration phase T1, the address pin Di_in of the driver circuit MIC receives an address signal. The logic control module CTR in the driver circuit MIC configures the address information of the driver circuit MIC based on the address signal and generates and outputs a relay signal. The relay signal can serve as the address signal for the next driver circuit MIC (i.e., the subsequent driver circuit MIC).

[0174] For example, for multiple cascaded driver circuits MIC, the address signal received by the first driver circuit can be provided by the controller circuit 1. The address signals received by the remaining driver circuits MIC can be relay signals output by the relay pin Di_out of the previous driver circuit MIC.

[0175] For example, as shown in FIG6 , in a plurality of cascaded driver circuits MIC, Di_in(n) represents the address signal received by the address pin Di_in of the nth driver circuit MIC; Di_out(n) represents the relay signal output by the relay pin Di_out of the nth driver circuit MIC. In the address configuration phase T1, the relay signal output by the nth driver circuit MIC serves as the address signal for the n+1th driver circuit MIC. Here, n is a positive integer.

[0176] In this stage, among the multiple cascaded driver circuits MIC, each driver circuit MIC is sequentially configured with address information according to the cascade order until the last driver circuit MIC is configured with address information, thereby achieving configuration of address information for each driver circuit MIC.

[0177] It should be noted that, as shown in FIG6 , FB represents the feedback signal output by the last driver circuit MIC. This feedback signal can be transmitted to the controller circuit 1, indicating that the configuration of the address information of each driver circuit MIC is complete. For example, the feedback signal output by the last driver circuit MIC does not contain any address information.

[0178] The drive configuration phase T2 includes an initialization configuration phase T21 and an amplitude configuration phase T22, which are performed sequentially. As shown in Figure 6, DataP represents the signal received by the data pin DataP, and CLKP represents the signal received by the clock pin CLKP. The clock signal CLK includes a third sub-clock signal CLK3 and a first sub-clock signal CLK1, which are performed sequentially. The data signal Data includes a third sub-clock signal Data3; the address information also includes third address information within the third sub-clock signal Data3; and the brightness information also includes initialization information within the third sub-clock signal Data3. The data signal Data also includes a first sub-clock signal Data1; the address information also includes first address information within the first sub-clock signal; and the brightness information also includes current amplitude information within the first sub-clock signal. The third sub-clock signal CLK3 and the third sub-clock signal Data3 correspond to the initialization configuration phase T21, while the first sub-clock signal CLK1 and the first sub-clock signal Data1 correspond to the amplitude configuration phase T22.

[0179] During the initialization and configuration phase T21, the clock pin CLKP of the driver circuit MIC receives the third sub-clock signal CLK3. After the logic control module CTR detects and determines the third sub-clock signal CLK3, while the third clock signal CLK3 is at a valid level, the logic control module CTR controls the data pin DataP to receive the third sub-data signal Data3. The logic control module CTR obtains third address information from the third sub-data signal Data3 and compares the third address information with the address information of the driver circuit MIC to which it belongs. If the third address information matches, the logic control module CTR controls the data pin DataP to obtain the corresponding initialization information to initialize the driver circuit MIC.

[0180] For example, at least a portion of the driver circuit MIC can simultaneously receive the third sub-clock signal CLK3 and the third sub-data signal Data3, and thus can be initialized and configured simultaneously. This helps to reduce the time required to initialize and configure the driver circuit MIC.

[0181] During the amplitude configuration phase T22, the clock pin CLKP of the driver circuit MIC receives the first sub-clock signal CLK1. After the logic control module CTR detects and determines the first sub-clock signal CLK1, during the valid level phase of the first sub-clock signal CLK1, the logic control module CTR controls the data pin DataP to receive the first sub-data signal Data1. The logic control module CTR obtains the first address information from the first sub-data signal Data1 and compares it with the address information of the driver circuit MIC to which it belongs. If the first address information matches, the logic control module CTR controls the data pin DataP to obtain current amplitude information and generates an amplitude signal based on the amplitude information.

[0182] For example, at least a portion of the driver circuit MIC can simultaneously receive the first sub-clock signal CLK1 and the first sub-data signal Data1, and thus can simultaneously generate the amplitude signal, which is beneficial for reducing the time required to generate the amplitude signal.

[0183] For example, the amplitude information obtained by the logic control modules CTR of different driver circuits MIC may be the same or different, depending on the working state of the device group EC.

[0184] For example, the amplitude information acquired by the logic control modules CTR of different driver circuits MIC is the same. Accordingly, the amplitude signals generated by the logic control modules CTR of different driver circuits MIC are the same. The amplitude signal can be selected to correspond to the maximum current amplitude signal, for example.

[0185] During the device control phase T3, the clock signal CLK further includes the second sub-clock signal CLK2. The data signal Data further includes the second sub-data signal Data2. The address information further includes the second address information in the second sub-data signal Data2. The brightness information further includes the duty cycle information in the second sub-data signal Data2.

[0186] The clock pin CLKP of the driver circuit MIC receives the second sub-clock signal CLK2. After the logic control module CTR detects and determines the second sub-clock signal CLK2, during the valid level phase of the second sub-clock signal CLK2, the logic control module CTR can control the data pin DataP to receive the second sub-data signal Data2. The logic control module CTR can obtain second address information from the second sub-data signal Data2 and compare the second address information with the address information of the driver circuit MIC to which it belongs. If the two match, the logic control module CTR can control the data pin DataP to obtain duty cycle information and generate a duty cycle selection signal based on the duty cycle information.

[0187] For example, the duty cycle information obtained by the logic control modules CTR of different driver circuits MIC may be the same or different, depending on the working state of the device group EC.

[0188] For example, when the amplitude signals generated by different driver circuits MIC are identical, the operating state of the device group EC can be determined by the duty cycle selection signal. By encoding the second sub-data signal Data2 and including different duty cycle information in the second sub-data signal Data2, different driver circuits MIC can generate different duty cycle selection signals based on the corresponding duty cycle information. This allows the device groups EC coupled to different driver circuits MIC to have different operating states (e.g., display different brightness levels).

[0189] During the power-off phase, the driver circuit MIC is in a power-off state and does not operate.

[0190] Alternatively, the transmission of the power supply voltage signal may be stopped, thereby placing the driver circuit MIC in a power-off state. Furthermore, optionally, the driver circuit MIC may be powered off when external circuits in the display device 1000 are powered off. In other words, when the display device 1000 is shut down, the driver circuit MIC may be powered off and in a power-off phase.

[0191] It is understood that, before the device control stage T3, the driving method of the driver circuit MIC may further include a device power supply voltage application stage. During this stage, a device power supply voltage signal (as indicated by VLED in FIG6 ) may be applied to the device group EC. This allows the device group EC to operate under the control of the driver circuit MIC. For example, the functional element FE may emit light under the control of the driver circuit MIC.

[0192] Next, the structure of the array substrate 100 will be schematically described with reference to the accompanying drawings.

[0193] In the array substrate 100 provided in some embodiments of the present disclosure, the arrangement of the multiple driver circuits MIC included therein includes various arrangements, which can be selected and set according to actual needs, and the present disclosure does not limit this.

[0194] In some examples, as shown in FIG8 to FIG11 , the plurality of driver circuits MIC may be arranged in a plurality of rows along the first direction Y. The number of driver circuits MIC included in each row of driver circuits may be the same or different.

[0195] In some examples, as shown in FIG8 to FIG11 , the plurality of driver circuits MIC may be arranged in a plurality of columns along the second direction X. The number of driver circuits MIC included in each column of driver circuits may be the same or different.

[0196] In the present disclosure, the arrangement of the plurality of device groups EC included in the array substrate 100 includes various arrangements, which can be selected and set according to actual needs, and the present disclosure does not limit this.

[0197] In some examples, as shown in FIG8 to FIG11 , the plurality of device groups EC may be arranged in a plurality of rows along the first direction Y. The number of device groups EC included in each row may be the same or different.

[0198] In some examples, as shown in FIG8 to FIG11 , the plurality of device groups EC may be arranged into a plurality of columns along the second direction X. The number of device groups EC included in each column may be the same or different.

[0199] In some examples, as shown in Figures 8 to 11, at least two device groups EC coupled to the driver circuit MIC are located on either side of the driver circuit MIC. Two rows of device groups are provided between any two adjacent rows of driver circuits.

[0200] The above-mentioned configuration method is used to set the driver circuit MIC and the device group EC, which is not only conducive to reducing the distance between each device group EC and the corresponding driver circuit MIC and simplifying the wiring difficulty, but also conducive to improving the distribution uniformity of the driver circuit MIC and the device group EC and reducing the wiring difficulty.

[0201] Exemplarily, in the same column driver circuit and / or the same row driver circuit, multiple driver circuits MIC may be arranged at equal intervals.

[0202] Exemplarily, in the same column device group and / or the same row device group, multiple device groups EC may be arranged at equal intervals.

[0203] Furthermore, the functional elements FE (see FIG. 14 ) included in the plurality of device groups EC may be arranged in an array. For example, the plurality of functional elements FE may be arranged at equal intervals.

[0204] This is conducive to further improving the distribution uniformity of the driver circuit MIC and the device group EC, reducing the difficulty of debugging the array substrate, and further reducing the difficulty of wiring.

[0205] It should be noted that, in some examples, as shown in FIG13 , the array substrate 100 may have a first region C1 and a second region C2. The driver circuit MIC shown in FIG12 is also located in the first region C1, for example. The plurality of driver circuits MIC located in the second region C2 are arranged in a row, for example, along the second direction X.

[0206] For example, in the same row of driver circuits, the driver circuits MIC located in the first region C1 may be arranged at equal intervals. In the same row of driver circuits, the spacing between a driver circuit MIC located in the second region C2 and an adjacent driver circuit MIC located in the first region C1 may be smaller than the spacing between any two adjacent driver circuits MIC located in the first region C1.

[0207] Furthermore, the relative position of the driver circuit MIC in the first region C1 relative to the device group EC it drives may be different from the relative position of the driver circuit MIC in the second region C2 relative to the device group EC it drives. Furthermore, the array substrate 100 has a bonding area, in which circuit board bonding pads are provided for connecting to an external circuit (e.g., a circuit board, a flexible circuit board, a chip-on-film, etc.). The second region C2 may be located at an end of the array substrate 100 close to the bonding area, and the first region C1 may be located on a side of the second region C2 away from the bonding area.

[0208] For example, as shown in FIG13 , the driver circuit MIC has two output pins OutP (e.g., Out1 and Out2) to drive two device groups EC. The array substrate 100 is provided with a fan-out region and a bonding region. The fan-out region includes fan-out traces coupled to circuit board bonding pads in the bonding region. The fan-out traces are also coupled to the driver traces of the driver circuit MIC and the device groups EC. The second region C2 may overlap with the fan-out region, and in particular, each device group EC in the second region C2 may overlap with the fan-out region. In the second region C2, the driver circuit MIC may be located on the side of the two device groups EC to which it is coupled, away from the bonding region.

[0209] It is understood that the array substrate 100 of the present disclosure integrates the driver circuit MIC of the driver device group EC. This simplifies the external circuitry driving the array substrate 100 and its control method, facilitating the miniaturization of the external circuitry. In particular, this not only reduces the volume of the integrated circuits in the external circuitry, thereby lowering the cost of the integrated circuits, but also reduces the area of ​​the circuit boards in the external circuitry.

[0210] In some embodiments, as shown in FIG8 to FIG12 , the array substrate 100 further includes a plurality of signal lines L and a controller circuit 1 coupled to the plurality of signal lines L. The controller circuit 1 is configured to transmit corresponding signals to the plurality of signal lines respectively.

[0211] In some examples, the plurality of signal lines L may be of various types. The controller circuit 1 may generate various types of signals and transmit each signal to a corresponding type of signal line L. For example, the controller circuit 1 may generate clock signals, data signals, address signals, and other signals and provide them to the driver circuit MIC via the signal lines L.

[0212] In some examples, as shown in FIG8 to FIG11 , the plurality of signal lines L may include: a plurality of clock signal lines CLKL extending along a first direction Y and arranged along a second direction X. One clock signal line CLKL may be coupled to a plurality of clock pins CLKP of a row of driver circuits MIC.

[0213] For example, the number of clock signal lines CLKL and the number of columns of driver circuits MIC may be the same.

[0214] For example, the clock signal line CLKL can be arranged in a corresponding row of driver circuits MIC, close to a side of the clock pin CLKP. This can reduce the distance between the clock signal line CLKL and the clock pin CLKP in the corresponding row of driver circuits MIC, thereby reducing wiring difficulty.

[0215] For example, the clock signal line CLKL may be arranged between a corresponding row of driver circuits MIC and the device group EC. In another example, the clock signal line CLKL may be arranged on a side of the device group EC away from the corresponding row of driver circuits MIC.

[0216] For example, the controller circuit 1 can be coupled to the plurality of clock signal lines CLKL and provide a clock signal CLK to the plurality of clock signal lines CLKL. Each clock signal line CLKL can transmit the received clock signal CLK to a corresponding row of driver circuits MIC and to a clock pin CLKP of each driver circuit MIC.

[0217] It should be noted that the clock signal CLK provided by the controller circuit 1 is, for example, generated by the same crystal oscillator. The clock signals CLK provided by the controller circuit 1 to different clock signal lines CLKL can be, for example, identical. This allows the multiple driver circuits MIC included in the array substrate 100 to receive the same clock signal CLK, ensuring that the frequencies of the clock signals CLK received by the different driver circuits MIC are uniform, thereby improving the accuracy of the received data signal Data.

[0218] In some examples, as shown in FIG8 to FIG11 , the plurality of signal lines L may include: a plurality of data signal lines DataL extending along a first direction Y. One data signal line DataL may be coupled to a plurality of data pins DataP of a row of driver circuits MIC.

[0219] Exemplarily, the number of data signal lines DataL and the number of columns of driver circuits MIC may be the same.

[0220] For example, the data signal line DataL can be arranged in a corresponding row of driver circuits MIC, close to a side of the data pin DataP. This can reduce the distance between the data signal line DataL and the data pin DataP in the corresponding row of driver circuits MIC, thus reducing wiring difficulty.

[0221] For example, the data signal line DataL may be arranged between a corresponding row of driver circuits MIC and the device group EC. In another example, the data signal line DataL may be arranged on a side of the device group EC away from the corresponding row of driver circuits MIC.

[0222] For example, the controller circuit 1 can be coupled to the aforementioned multiple data signal lines DataL and provide data signals Data to the multiple data signal lines DataL. The data signals Data received by different data signal lines DataL can be the same signal. When the logic control module CTR in each driver circuit MIC receives a clock signal and detects that the clock signal CLK is at a valid level, it can control its data pin DataP to receive the data signal Data from the data signal line DataL.

[0223] The present disclosure utilizes data signal lines DataL to transmit data signals Data, thereby avoiding the problem of excessive number of pads and traces caused by using SPI (Serial Peripheral Interface) for data signal Data transmission. This simplifies the structures of the array substrate 100, the controller circuit 1, and the driver circuit MIC, thereby reducing the costs of the array substrate 100 and the driver circuit MIC.

[0224] For example, the controller circuit 1 may be provided with an encoder. The encoder may encode data according to the 4b / 5b encoding protocol, the 8b / 10b encoding protocol, or other encoding protocols to generate a data signal Data, which is transmitted to the data signal line DataL. The decoder of the logic control module CTR may decode the data signal Data to obtain address information and brightness information contained in the data signal Data.

[0225] Here, regarding the data signal Data provided by the controller circuit 1, please refer to the description in some of the above examples, and will not be repeated here.

[0226] In some examples, as shown in FIG8 to FIG11 , the plurality of signal lines L may include: a plurality of device power signal lines VLEDL extending along a first direction Y. The plurality of device groups EC coupled to a row of driver circuits MIC are further coupled to at least one device power signal line VLEDL.

[0227] Exemplarily, the plurality of device groups EC may be arranged in a row along the second direction X. In this case, the plurality of device groups EC may be coupled to, for example, one device power signal line VLEDL.

[0228] For example, the plurality of device groups EC may be arranged in multiple columns along the second direction X. If at least two device groups EC coupled to a driver circuit MIC are located on either side of the driver circuit MIC, the number of device power signal lines VLEDL corresponding to the same row of driver circuits MIC may be two, with the two device power signal lines VLEDL located on opposite sides of the same row of driver circuits MIC. In this case, one device power signal line VLEDL may be coupled to a device group EC located on one side of the driver circuit MIC, and the other device power signal line VLEDL may be coupled to a device group EC located on the other side of the driver circuit MIC.

[0229] For example, the device power signal line VLEDL may be provided on a side of the device group EC coupled thereto that is away from the corresponding driver circuit MIC.

[0230] For example, the controller circuit 1 can be coupled to the plurality of device power signal lines VLEDL and provide device power voltage signals to the plurality of device power signal lines VLEDL. The device power voltage signals received by different device power signal lines VLEDL can be the same signal.

[0231] It is understood that, since each device power signal line VLEDL can be disposed on a side of the device group EC coupled thereto that is away from the corresponding driver circuit MIC, two device power signal lines VLEDL located between two adjacent rows of driver circuits MIC can be disposed adjacent to each other, and no other signal line L can be disposed between the two device power signal lines VLEDL. Since the device power voltage signals received by different device power signal lines VLEDL can be the same signal, the two device power signal lines VLEDL can be combined into one device power signal line VLEDL.

[0232] In some examples, as shown in FIG8 to FIG11 , two rows of device groups located between any two adjacent rows of driver circuits MIC are coupled to the same device power signal line VLEDL, which is a merged device power signal line VLEDL.

[0233] This helps reduce the number of device power signal lines VLEDL, and further reduces the number of signal lines L, which helps simplify the structure of the array substrate 100 and reduce the cost and difficulty of preparing the array substrate 100.

[0234] Exemplarily, the size of the merged device power signal line VLEDL in the second direction X may be greater than or equal to the size of the device power signal line VLEDL before the merger in the second direction X. Optionally, the merged device power line VLEDL may include a hollow portion.

[0235] In some examples, as shown in FIG8 to FIG11 , the plurality of signal lines L may include: a plurality of chip power signal lines VCCL extending along a first direction Y. A chip power signal line VCCL may be coupled to a plurality of chip power pins VCCP of a row of driver circuits MIC.

[0236] Exemplarily, the number of chip power signal lines VCCL and the number of rows of driver circuits MIC may be the same.

[0237] For example, the chip power signal line VCCL can be arranged in a corresponding row of driver circuits MIC, close to a side of the chip power pin VCCP. This can reduce the distance between the chip power signal line VCCL and the chip power pin VCCP in the corresponding row of driver circuits MIC, thus reducing wiring difficulty.

[0238] For example, the chip power signal line VCCL can be set between the corresponding row of driver circuits MIC and the device group EC. For another example, the chip power signal line VCCL can be set on the side of the device group EC away from the corresponding row of driver circuits MIC.

[0239] Exemplarily, the controller circuit 1 can be coupled to the plurality of chip power signal lines VCCL and provide power voltage signals to the plurality of chip power signal lines VCCL. Each chip power signal line VCCL can transmit the received power voltage signal to a corresponding row of driver circuits MIC and to the chip power pin VCCP of each driver circuit MIC.

[0240] In some examples, as shown in FIG8 to FIG11 , the plurality of signal lines L may include: a plurality of ground signal lines GNDL extending along a first direction Y. One ground signal line GNDL may be coupled to a plurality of ground pins GNDP of a row of driver circuits MIC.

[0241] Exemplarily, the number of ground signal lines GNDL and the number of rows of driver circuits MIC may be the same.

[0242] For example, the ground signal line GNDL can be disposed in a corresponding row of driver circuits MIC, close to a side of the ground pin GNDP. This can reduce the distance between the ground signal line GNDL and the ground pin GNDP in the corresponding row of driver circuits MIC, thereby reducing wiring difficulty.

[0243] For example, the ground signal line GNDL may be disposed between a corresponding row of driver circuits MIC and the device group EC. In another example, the ground signal line GNDL may be disposed on a side of the device group EC away from the corresponding row of driver circuits MIC.

[0244] Exemplarily, the controller circuit 1 can be coupled to the plurality of ground signal lines GNDL and provide ground signals to the plurality of ground signal lines GNDL. Each ground signal line GNDL can transmit the received ground signal to a corresponding row of driver circuits MIC and to the ground pin GNDP of each driver circuit MIC.

[0245] For example, as shown in FIG12 and FIG13 , the ground signal line GNDL has a larger dimension in the second direction X. The driver circuit MIC can be arranged to overlap with the ground signal line GNDL. This facilitates utilizing the ground signal carried on the ground signal line GNDL to provide electromagnetic shielding for the driver circuit MIC.

[0246] In some examples, as shown in FIG8 to FIG11 , the plurality of signal lines L may further include a plurality of address signal lines ADDRL. A relay pin Di_out of a driver circuit MIC may be coupled to one end of an address signal line ADDRL, and an address pin Di_in of another driver circuit MIC may be coupled to the other end of the address signal line ADDRL.

[0247] The configuration of the multiple address signal lines ADDRL is related to the configuration of the driver circuit MIC. For example, as shown in Figures 8 to 11, the driver circuits MIC in the array substrate 100 are cascaded. There are various cascade configurations for the driver circuit MIC, and the specific configuration can be selected based on actual needs, which is not limited in this disclosure.

[0248] In one possible example, as shown in Figures 8-10 , the driver circuit MIC includes an address pin Di_in and a relay pin Di_out. Within the same row driver circuit, the relay pin Di_out of the Nth driver circuit MIC is coupled to the address pin Di_in of the N+1th driver circuit MIC, where N is a positive integer. In other words, among the multiple driver circuits MIC included in the array substrate 100, multiple driver circuits MIC within the same row driver circuit are cascaded, while driver circuits in different rows are not cascaded.

[0249] At this time, in the same row driver circuit, the relay pin Di_out of the Nth driver circuit MIC can be coupled to one end of an address signal line ADDRL, and the address pin Di_in of the N+1th driver circuit MIC can be coupled to the other end of the address signal line ADDRL. However, in different row driver circuits, no coupling is performed through the address signal line ADDRL.

[0250] It should be noted that, in each row driver circuit, the address pin Di_in of the first driver circuit MIC can be coupled to one end of an address signal line ADDRL, and the other end of the address signal line ADDRL can be coupled to the controller circuit 1 to receive the address signal.

[0251] It is understood that within the same row of driver circuits, the N+1th driver circuit MIC can serve as a subsequent driver circuit to the Nth driver circuit MIC. After the Nth driver circuit MIC obtains and stores its own address information, the Nth driver circuit MIC can configure address information for the N+1th driver circuit MIC based on its own address information, thereby dynamically allocating addresses to the cascaded driver circuits MIC. In other words, the relay signal output by the relay pin Di_out of the Nth driver circuit MIC can serve as the address signal of the N+1th driver circuit MIC and be received by the address pin Di_in of the N+1th driver circuit MIC.

[0252] In this example, as shown in FIG8 to FIG10, the address pin Di_in and the relay pin Di_out included in the driver circuit MIC can be located on the same side. Accordingly, each address signal line ADDRL can extend along the first direction Y.

[0253] Furthermore, within the same row driver circuit, the address pins Di_in and relay pins Di_out of different driver circuits MIC can, for example, be located on the same side. This allows multiple address signal lines ADDRL corresponding to the same row driver circuit to be located on the same side of the row driver circuit MIC, and the extensions of the multiple address signal lines ADDRL corresponding to the same row driver circuit can overlap. This helps reduce the routing space for the address signal lines ADDRL in the second direction X, increasing the routing space for other signal lines L. This in turn helps increase the width of traces such as the device power signal line VLEDL and the ground signal line GNDL, thereby reducing the resistance of these signal lines L.

[0254] For example, the address signal line ADDRL may be arranged between a corresponding row driver circuit MIC and the device group EC. In another example, the address signal line ADDRL may be arranged on a side of the device group EC away from the corresponding row driver circuit MIC.

[0255] In another possible example, as shown in FIG11 , the driver circuit MIC includes an address pin Di_in and a relay pin Di_out. Among the multiple driver circuits MIC included in the array substrate 100, the relay pin Di_out of the Mth driver circuit MIC is coupled to the address pin Di_in of the M+1th driver circuit MIC, where M is a positive integer. In other words, the multiple driver circuits MIC included in the array substrate 100 are cascaded sequentially. For example, the multiple driver circuits MIC can be cascaded in an S-shaped manner.

[0256] At this time, among the multiple driver circuits MIC included in the array substrate 100, the relay pin Di_out of the Mth driver circuit MIC can be coupled to one end of an address signal line ADDRL, and the address pin Di_in of the M+1th driver circuit MIC can be coupled to the other end of the address signal line ADDRL.

[0257] It should be noted that, among the multiple driver circuits MIC, the address pin Di_in of the first driver circuit MIC can be coupled to one end of an address signal line ADDRL, and the other end of the address signal line ADDRL can be coupled to the controller circuit 1 to receive the address signal.

[0258] It is understood that among the multiple driver circuits MIC described above, the M+1th driver circuit MIC can serve as a subsequent driver circuit to the Mth driver circuit MIC. After the Mth driver circuit MIC obtains and stores its own address information, the Mth driver circuit MIC can configure address information for the M+1th driver circuit MIC based on its own address information, thereby allocating dynamic addresses to the cascaded driver circuits MIC. In other words, the relay signal output by the relay pin Di_out of the Mth driver circuit MIC can serve as the address signal of the M+1th driver circuit MIC and be received by the address pin Di_in of the M+1th driver circuit MIC.

[0259] In this example, as shown in FIG11 , the address pin Di_in and relay pin Di_out included in the driver circuit MIC can be located on different sides. Accordingly, each address signal line ADDRL coupled to different driver circuits MIC in the same row driver circuit can have a zigzag shape, such as an S-shape or a Z-shape. One end of the address signal line ADDRL can be located on one side of the same row driver circuit MIC and coupled to the address pin Di_in of one of the driver circuits MIC, while the other end of the address signal line ADDRL can be located on the other side of the same row driver circuit MIC and coupled to the relay pin Di_out of another of the driver circuits MIC. Each address signal line ADDRL coupled to different driver circuits MIC in different row driver circuits can be linear and extend along the second direction X. One end of the address signal line ADDRL can be coupled to the address pin Di_in of a driver circuit MIC in one row of driver circuits MIC, and the other end of the address signal line ADDRL can be coupled to the relay pin Di_out of a driver circuit MIC in another row of driver circuits MIC.

[0260] In some examples, as shown in FIG8 to FIG11 , the plurality of signal lines L may further include at least one feedback signal line FBL. The at least one feedback signal line FBL may extend along the first direction Y, for example.

[0261] In one possible example, as shown in FIG8 to FIG10 , in the same row driver circuit, when the relay pin Di_out of the Nth driver circuit MIC is coupled to the address pin Di_in of the (N+1)th driver circuit MIC, the plurality of signal lines L may include: a plurality of feedback signal lines FBL. The relay pin Di_out of the last driver circuit MIC in any row driver circuit is coupled to one feedback signal line FBL.

[0262] For example, in the aforementioned cascade relationship, each row of the multi-channel driver circuits included in the array substrate 100 has a final driver circuit MIC, and its relay pin Di_out is coupled to a feedback signal line FBL. That is, the number of feedback signal lines FBL and the number of rows of driver circuits MIC can be the same.

[0263] For example, as shown in Figures 8-10 , the feedback signal line FBL can be arranged in a corresponding row of driver circuits MIC, near the relay pin Di_out. This can reduce the distance between the clock signal line CLKL and the relay pin Di_out in the corresponding row of driver circuits MIC, thus reducing wiring complexity.

[0264] For example, the feedback signal line FBL may be arranged between a corresponding row of driver circuits MIC and the device group EC. In another example, the feedback signal line FBL may be arranged on a side of the device group EC away from the corresponding row of driver circuits MIC.

[0265] In another possible example, as shown in FIG11 , among the multiple driver circuits MIC included in the array substrate 100, when the relay pin Di_out of the Mth driver circuit MIC is coupled to the address pin Di_in of the M+1th driver circuit MIC, the multiple signal lines L may include a feedback signal line FBL. The relay pin Di_out of the last driver circuit MIC is coupled to the feedback signal line FBL.

[0266] For example, as shown in FIG11 , the feedback signal line FBL can be disposed in the last driver circuit MIC, near the relay pin Di_out. This reduces the distance between the clock signal line CLKL and the relay pin Di_out in the driver circuit MIC, thus reducing wiring complexity.

[0267] It is understood that one end of each of the feedback signal lines FBL is coupled to the relay pin Di_out in the driver circuit MIC, and the other end is coupled to the controller circuit 1. After the last driver circuit MIC of each row driver circuit is configured, or after the last driver circuit MIC of the plurality of driver circuits MIC is configured, a signal can be fed back to the controller circuit 1 via the feedback signal line FBL to indicate that the configuration is complete.

[0268] In addition, in some of the above examples, when the driver circuit MIC includes a short circuit detector and a disconnection detector, information such as a short circuit and / or a short circuit between each device group EC and the driver circuit MIC can also be fed back to the controller circuit 1 through the feedback signal line FBL.

[0269] It should be understood that Figures 8 to 11 are merely used to illustrate the coupling relationship between the driver circuit MIC, the device group EC, and the signal lines L. In Figures 8 to 11 , to more clearly illustrate the electrical connection relationship, the dimensions of the driver circuit MIC, the device group EC, and the signal lines L are not drawn to scale, and the relative positions between the driver circuit MIC, the device group EC, and the signal lines L are not shown according to their actual positions.

[0270] In some embodiments, from the perspective of film layer structure, as shown in FIG14 , the array substrate 100 further includes: a substrate 2 , a driving circuit layer 3 disposed on one side of the substrate 2 , and a device layer 4 .

[0271] In some examples, the substrate 2 may be a substrate formed of an inorganic material, or a substrate formed of an organic material, or a substrate formed by stacking organic and inorganic materials.

[0272] For example, the material of the substrate 2 can be a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, etc.

[0273] Exemplarily, the material of the substrate 2 may also be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

[0274] In some examples, as shown in FIG. 14 , the plurality of driver circuits MIC and device groups EC included in the array substrate 100 may be located in the device layer 4 .

[0275] In some examples, as shown in FIG14 , the driving circuit layer 3 includes: a driving wiring layer 31 , an insulating layer 32 , and a wiring layer 33 , which are stacked in sequence.

[0276] For example, as shown in FIG14 , the array substrate 100 includes a plurality of signal lines L that can be located in the aforementioned drive wiring layer 31. Specifically, the drive wiring layer 31 can include data signal lines DataL for carrying data signals, clock signal lines CLKL for carrying clock signals, and device power supply lines VLEDL for carrying device power signals.

[0277] For example, as shown in FIG14 , the wiring layer 33 may include: a plurality of chip pads (not shown), a plurality of device pads 332, and a plurality of connection lines 333. The plurality of driver circuits MIC may be bonded to the plurality of chip pads, and the functional elements FE in the plurality of device groups EC may be bonded to the plurality of device pads 332. Of course, the wiring layer 33 may also include, for example, controller pads for bonding to the controller circuit 1.

[0278] In the present disclosure, the die pads bonded to the pins P of the same driver circuit MIC may constitute a die pad group. The driver circuit layer 3 of the array substrate 100 may include multiple die pad groups, each die pad group being bonded to a respective driver circuit MIC in a one-to-one correspondence.

[0279] For example, in the present disclosure, the driver circuit MIC may include a clock pin CLKP, at least two output pins OutP, an address pin Di_in, a relay pin Di_out, a chip power pin VCCP, a data pin DataP, a ground pin GNDP, etc. Accordingly, a chip pad group may include a clock pad for coupling with the clock pin CLKP, output pads for coupling with each output pin OutP, an address pad for coupling with the address pin Di_in, a relay pad for coupling with the relay pin Di_out, a chip power pad for coupling with the chip power pin VCCP, a data pad for coupling with the data pin DataP, a ground pad for coupling with the ground pin GNDP, etc.

[0280] In the array substrate 100, the arrangement of each chip pad in the chip pad group can be arranged according to the arrangement of the pins P of the driver circuit MIC, so as to meet the bonding requirements of the driver circuit MIC and the chip pad group. This disclosure does not impose any restrictions on this.

[0281] For example, as shown in FIG14 , connecting wires 333 can be coupled to the chip pad and the drive trace layer 31, respectively. Connecting wires 333 can also be coupled to the device pad 332 and the drive trace layer 31, respectively. That is, the chip pad 331 can be coupled to the corresponding signal line L in the drive trace layer 31 via connecting wires 333, and the device pad 332 can be coupled to the corresponding signal line L in the drive trace layer 31 via connecting wires 333. Of course, the driver circuit MIC can also be coupled to the device assembly EC via connecting wires 333.

[0282] Optionally, the output pin OutP and the device pad connected to the device group EC, the address pad and the address signal line ADDRL, the chip power pad and the chip power signal line VCCL, the data pad and the data signal line DataL, the device pad connected to the device group EC and the device power signal line VLEDL, some of the address pads and the address signal line ADDRL, and the ground pad and the ground signal line GNDL can all be coupled via connection wires 333. Of course, in the present disclosure, the ground pad and the ground signal line GNDL can also be directly coupled via vias.

[0283] Optionally, the connection line 333 can pass through the via hole in the insulating layer 32 to achieve coupling with the driving wiring layer 31.

[0284] In one example of the present disclosure, the thickness of the driving wiring layer 31 may be greater than the thickness of the wiring layer 33. This is beneficial for reducing the resistance of the driving wiring layer 31 and reducing the voltage drop of the signal on each signal line L.

[0285] Optionally, the thickness of the drive wiring layer 31 can range from 1.5 μm to 7 μm. The material of the drive wiring layer 31 can include copper. For example, the drive wiring layer 31 can be formed by sputtering, wherein the drive wiring layer 31 can be composed of a stack of multiple film layers such as MoNb / Cu / MoNb. The side of the multilayer film layer close to the substrate 2 is a MoNb thin film with a thickness of approximately 300 Å, which is mainly used to improve the adhesion between the drive wiring layer 31 and the substrate 2. The Cu thin film in the multilayer film layer can provide a better transmission channel for electrical signals. The film layer on the side away from the substrate 2 is a MoNb thin film with a thickness of approximately 200 Å, which can be used to protect the Cu thin film and prevent the low-resistivity Cu thin film from being exposed and oxidized. Since the thickness of a single sputtering process generally does not exceed 1 μm, multiple sputtering processes are required to form a drive wiring layer 31 with a thickness exceeding 1 μm. Furthermore, the drive trace layer 31 can also be formed by electroplating. Specifically, a seed layer can be formed using MoNiTi to increase the nucleation density of metal grains in the subsequent electroplating process. Low-resistivity copper can then be electroplated, followed by an anti-oxidation layer. This anti-oxidation layer can be made of MoNiTi. Optionally, the surface of the drive trace layer 31 facing away from the substrate 2 can be covered with an insulating layer 32 to ensure the reliability and stability of the electrical path.

[0286] Optionally, the thickness of the wiring layer 33 is approximately 6000 Å. During the manufacturing process from the array substrate to the bonding of electronic components, each pad exposed to air may oxidize. In this case, an anti-oxidation material layer can be applied only to the exposed surface area of ​​each pad, i.e., the surface of the pad area will have an additional layer than the area where the wiring traces are located. Alternatively, the wiring layer 33 can be configured as a stacked structure of at least two layers, with the film layer away from the substrate 2 being made of an oxidation-resistant metal or alloy material. Specifically, it can be composed of a stacked structure of MoNb / Cu / CuNi. The bottom layer of the stack, MoNb, is primarily used to improve adhesion. The middle layer of Cu, due to its low resistivity, is primarily used to transmit electrical signals. The top layer of the stack, CuNi, prevents oxidation of the middle layer and ensures a secure connection with the electronic components. The surface of the wiring trace away from the substrate 2 is covered by another insulating layer 51 to ensure the reliability and stability of the electrical path.

[0287] Optionally, as shown in FIG14 , the array substrate 100 may further include: a buffer layer 52 disposed between the substrate 2 and the drive trace layer 3; a first flat layer 53 disposed between the insulating layer 32 and the wiring layer 33; a second flat layer 54 and a reflective layer 55 disposed on the side of the insulating layer 51 away from the wiring layer 33; a transparent electrode 56 disposed on the bonding pads in the peripheral region; and an anisotropic conductive adhesive 57 disposed between the transparent electrode 56 and an external circuit (e.g., a flexible circuit board). The buffer layer 52 prevents impurities in the substrate 2 from adversely affecting the conductive properties of the drive trace layer 3; the first flat layer 53 provides a flat surface for fabricating the wiring layer 33; the second flat layer 54 provides a flat surface for subsequent bonding of the functional element FE and the driver circuit MIC; the reflective layer 55 may be made of white ink to increase the reflectivity of the array substrate 100 and reduce light loss; and the transparent electrode 56 and anisotropic conductive adhesive 57 are used to electrically connect the bonding pads in the peripheral region (e.g., circuit board bonding pads) to an external circuit (e.g., a flexible circuit board).

[0288] Optionally, as shown in FIG14 , the array substrate 100 may further include an encapsulation layer 58 disposed on a side of the device layer 4 away from the substrate 2. The encapsulation layer 58 comprises a layered structure for encapsulating the functional elements FE on the substrate 2. For example, encapsulation glue may be applied to the surface of the functional elements FE in the array substrate 100 and dried to form the encapsulation layer 58. The material of the encapsulation layer 58 may include a transparent light-curable or heat-curable resin, that is, the material of the encapsulation layer 58 may be a transparent protective glue. In some embodiments, the encapsulation layer 58 may include a plurality of transparent protective structures 581.

[0289] Optionally, as shown in FIG14 , the pins of the functional element FE are coupled to the device pads 332 through solder paste T, and each device pad 332 is coupled according to the position of the functional element FE in the electrical circuit.

[0290] Figure 15 shows another structural diagram of the array substrate 100 disclosed herein. Figure 15 does not show the individual functional elements FE and driver circuit MIC. If the second planar layer 54 is made of an organic insulating material, multiple vent holes 511 can be provided in the insulating layer 51. Each of these vent holes 511 exposes a portion of the underlying first planar layer 53. During the manufacturing process of the array substrate 100, gas accumulated in the first planar layer 53 can be released through the vent holes 511, thereby preventing warping and delamination of the film layer of the array substrate 100 and improving product yield.

[0291] For example, in the structure shown in FIG15 , a plurality of vent holes 511 are provided, but this is merely illustrative and not a limitation of the embodiments of the present disclosure. In other embodiments, a greater or lesser number of vent holes 511 may be provided.

[0292] Some embodiments of the present disclosure provide a display device 1000 , as shown in FIG17 . The display device 1000 includes the array substrate 100 as described in any of the above embodiments.

[0293] Based on this, in the device group EC included in the array substrate 100, each functional element FE may be a light-emitting element.

[0294] In some examples, the display device 1000 may be an LED display device or a liquid crystal display device.

[0295] For example, when the display device 1000 is an LED display device, the functional element FE (such as Micro LED, Mini LED, LED, etc.) can emit light to directly display an image.

[0296] Alternatively, each functional element FE can emit light of the same color, such as blue, red, green, or yellow. In this way, the display device 1000 can be a monochrome display device, such as an instrument dial, a signal indicator screen, or the like. Alternatively, each functional element FE can emit light of multiple different colors, such as at least two of red, green, blue, and yellow, and the functional elements FE emitting different colors can be independently controlled. In this way, the display device 1000 can achieve color display through light mixing.

[0297] For example, when the display device 1000 is a liquid crystal display device, the array substrate 100 can serve as a backlight source. In this case, the display device 1000 further includes: a drive substrate 200 disposed on one side of the array substrate 100; a color filter substrate 300 disposed on a side of the drive substrate 200 away from the array substrate 100; and a liquid crystal layer 400 disposed between the drive substrate 200 and the color filter substrate 300.

[0298] Optionally, each functional element FE can emit light of the same color, such as white or blue. Each device group EC can operate independently under the drive of the driver circuit MIC, allowing each device group EC to emit light independently. In this way, the display device 1000 can achieve local dimming, realize HDR (High-Dynamic Range) effects, and improve the display quality of the display device 1000. In any device group EC, the number and coupling method of the functional elements FE are the same. This ensures the uniform distribution of the functional elements FE on the array substrate 100, which helps improve the uniformity of the array substrate 100's light emission and reduces the difficulty of debugging the backlight source (i.e., the array substrate 100).

[0299] In some examples, the controller circuit 1 in the array substrate 100 may include an FPGA (Field Programmable Gate Array) and / or a PHY block. For example, the controller circuit 1 is powered by an input voltage (VP) and is connected to ground (GND). The controller circuit 1 may use an active matrix drive method or a passive matrix drive method to control the array substrate 100, which helps reduce power consumption and avoid undesirable phenomena such as flicker.

[0300] Exemplarily, as shown in FIG16 , the controller circuit 1 includes a timing controller D10 and a bridge D20. The timing controller D10 can generate an image control signal D15 indicating the values ​​used to drive pixels of the array substrate 100 and the timing for driving the pixels. For example, the timing controller D10 controls the timing of an image frame or video frame and controls the timing for driving each device group EC within the device group EC (e.g., LEDs within an LED light zone) within the image frame or video frame. Furthermore, the timing controller D10 controls the brightness of each LED light zone within the LED light zone during a given image frame or video frame. The image control signal D15 is provided by the timing controller D10 to the bridge D20.

[0301] The bridge D20 converts the image control signal D15 into an address signal and a data signal. For example, the bridge D20 can generate an address signal for the first driver circuit MIC in the driver circuit MIC group during the addressing mode according to the above control scheme.

[0302] The beneficial effects that can be achieved by the display device 1000 provided in some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the driver circuit MIC and the array substrate 100 provided in some of the above embodiments, and will not be repeated here.

[0303] In some examples, the display device 1000 can be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or graphic. More specifically, it is contemplated that the embodiments described herein can be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic signage or indicators, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of jewelry), and the like.

[0304] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions conceived by a person skilled in the art within the technical scope disclosed herein should be covered by the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the patent application.

[0305] CLKP: Clock pin CLM: Control Module CTR: Logic Control Module DataP: Data pin DB: Data bus Di_in: address pin Di_out: relay pin GNDP: Ground pin MIC: Driver circuit Out1: The first output pin Out2: Second output pin Out3: The third output pin Out4: The fourth output pin OutP: output pin P: Pin PWMM: Modulation Module PWMM1: first modulation module PWMM3: The third modulation module PWMM4: The fourth modulation module PWMM5: The fifth modulation module PWRM: Power Module VCCP: Chip power pin C310: voltage regulation circuit C330: Low Dropout Voltage Regulator C340: Oscillator C352: Enable signal C354: Relay signal C356: PWM pulse selection signal C358: Maximum current signal C360: Address Driver MUX: Data Selector ADC: Analog-to-digital converter TSD: Thermal Shutdown Delay Sensor TS: Thermal Shutdown Delay Controller C370: Dimming circuit C375: Transistor C380: Brightness control circuit FB: Feedback signal VLED: power supply voltage signal T1: Address configuration phase T2: Driver configuration phase T3: Device control stage T21: Initialization configuration phase T22: Amplitude configuration stage CLK1: first sub-clock signal CLK2: second sub-clock signal CLK3: The third sub-clock signal Data1: first sub-data signal Data2: Second sub-data signal Data3: The third sub-data signal VLEDL: device power signal line FBL: Feedback signal line Y: first direction X: Second direction ADDRL: address signal line VCCL: chip power signal line DataL: Data signal line EC: Device Group GNDL: Ground signal line CLKL: clock signal line 100: array substrate 1: Controller circuit 332: device pad 333: Connecting line 33: Wiring layer FE: Functional Element 2: Substrate 3: Drive routing layer 52: buffer layer 32: Insulation layer 53: First flat layer 54: Second flat layer 55:Reflection layer 56: Transparent electrode 57: Anisotropic conductive adhesive 31: Drive wiring layer 51: Insulation layer 4: Device layer 58: Encapsulation layer 581: Transparent protective structure T:Solder paste 511: vent hole 1000: Display device D10: Timing Controller D20: Bridge D15: Image control signal 100: array substrate 200:Drive substrate 300: Color film substrate 400: Liquid crystal layer

Claims

1. An array substrate, comprising: Multiple driver circuits, each driver circuit including multiple pins; The plurality of pins includes: a clock pin configured to receive a clock signal; a data pin configured to receive a data signal; at least two output pins; and a device group coupled to each output pin in the driver circuit, the device group including at least one functional element; the array substrate further includes: a plurality of signal lines; wherein the plurality of driver circuits are arranged as a multi-row driver circuit, the driver circuits in each row of driver circuits being arranged along a first direction; the plurality of signal lines include: a plurality of clock signal lines extending along the first direction; one clock signal line coupled to a plurality of clock pins of a row of driver circuits; a plurality of data signal lines extending along the first direction; one data signal line coupled to a plurality of data pins of the row of driver circuits; and a plurality of device power signal lines extending along the first direction; the plurality of device groups coupled to the row of driver circuits are also coupled to at least one device power signal line.

2. The array substrate as claimed in claim 1, wherein, Multiple device groups are arranged in multiple rows of device groups, with the device groups in each row arranged along the first direction; at least two device groups coupled to the driver circuit are located on opposite sides of the driver circuit; wherein, there are two device power signal lines corresponding to the same row of driver circuits, and the two device power signal lines are located on opposite sides of the same row of driver circuits.

3. The array substrate as claimed in claim 2, wherein, Two groups of devices located between any two adjacent driver circuits are coupled to the same device power signal line.

4. The array substrate as described in any one of claims 1 to 3, wherein, The driver circuit includes address pins and relay pins; in the same row of driver circuits, the relay pin of the Nth driver circuit and the address pin of the (N+1)th driver circuit are coupled; N is a positive integer; or, wherein the driver circuit includes the address pins and the relay pins; in the plurality of driver circuits, the relay pin of the Mth driver circuit and the address pin of the (M+1)th driver circuit are coupled; M is a positive integer.

5. The array substrate as claimed in claim 4, wherein, The multiple signal lines also include: multiple address signal lines; the relay pin of the Nth driver circuit is coupled to one end of the address signal line, and the address pin of the (N+1)th driver circuit is coupled to the other end of the address signal line.

6. The array substrate as described in claim 4, wherein the plurality of signal lines further comprises: At least one feedback signal line; In the same row of driver circuits, when the relay pin of the Nth driver circuit and the address pin of the (N+1)th driver circuit are coupled, the relay pin of the last driver circuit in any row is coupled to a feedback signal line; in the plurality of driver circuits, when the relay pin of the Mth driver circuit and the address pin of the (M+1)th driver circuit are coupled, the relay pin of the last driver circuit is coupled to the feedback signal line.

7. The array substrate as claimed in any one of claims 1 to 3, wherein, The driver circuit further includes a chip power pin and a ground pin; the multiple signal lines further include: multiple chip power signal lines extending along the first direction; one chip power signal line coupled to multiple chip power pins of the row driver circuit; and multiple ground signal lines extending along the first direction; one ground signal line coupled to multiple ground pins of the row driver circuit.

8. The array substrate as described in any one of claims 1 to 3, further comprising: A controller circuit coupled to the multiple signal lines; The controller circuit is configured to transmit corresponding signals to the plurality of signal lines respectively.

9. The array substrate as described in any one of claims 1 to 3, further comprising: Substrate; A driving circuit layer is disposed on one side of the substrate; the driving circuit layer includes a driving trace layer, an insulating layer and a wiring layer stacked sequentially; the plurality of signal lines are located in the driving trace layer; And, device layer; The plurality of driver circuits and the device group are located in the device layer; wherein the wiring layer includes: a plurality of wafer pads bonded to the plurality of driver circuits; a plurality of device pads bonded to the plurality of device groups; and a plurality of connection lines respectively coupled to the plurality of wafer pads and the driver wiring layer, and coupled to the plurality of device pads and the driver wiring layer.

10. The array substrate as described in any one of claims 1 to 3, wherein the driver circuit includes a logic control module, and the plurality of pins are coupled to the logic control module; wherein, The data pin is configured to receive the data signal under the control of the logic control module during the effective level of the clock signal; the logic control module is configured to generate a drive control signal corresponding to each output pin based on the data signal, so as to control the electrical signal flowing through the output pin.

11. The array substrate as claimed in claim 10, wherein, The effective level phase of the clock signal includes: the rising edge phase of the clock signal.

12. The array substrate as claimed in claim 10, wherein, The frequency of the clock signal is the same as the frequency of the data signal.

13. The array substrate as claimed in claim 10, wherein, The data signal includes address information and brightness information; the logic control module is further configured to compare the address information in the data signal with the address information of the driver circuit, and if they match, obtain the brightness information in the data signal and generate the drive control signal based on the brightness information in the data signal.

14. The array substrate as claimed in claim 13, wherein, The data signal includes a first sub-data signal and a second sub-data signal; the address information includes: a first address information located in the first sub-data signal and a second address information located in the second sub-data signal; the brightness information includes: amplitude information located in the first sub-data signal and duty cycle information located in the second sub-data signal; the logic control module is further configured to compare the first address information with the address information of the driver circuit, and if they match, generate an amplitude signal based on the amplitude information to control the amplitude of the electrical signal flowing through the output pin; and compare the second address information with the address information of the driver circuit, and if they match, generate a duty cycle selection signal based on the duty cycle information to control the duration of the electrical signal flowing through the output pin.

15. The array substrate as claimed in any one of claims 1 to 3, wherein, The number of the plurality of pins is even; along the length of the driver circuit, the plurality of pins are arranged in two rows, with each row having the same number of pins.

16. The array substrate as claimed in any one of claims 1 to 3, wherein, The number of output pins is four; each row of pins includes two output pins, and at least one pin is provided between the two output pins.

17. A display device, comprising: The array substrate as described in any one of claims 1 to 16.

18. The display device as claimed in claim 17, further comprising: A driving substrate disposed on one side of the array substrate; A color filter substrate disposed on the side of the driving substrate away from the array substrate; And a liquid crystal layer disposed between the driving substrate and the color filter substrate.

Images