Semiconductor device and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor device includes forming a gate oxide layer on an epitaxial layer, the epitaxial layer including a drift region and a source region, forming a first boron-containing layer on the gate oxide layer, performing a thermal process to move boron in the first boron-containing layer toward the epitaxial layer to form a second boron-containing layer between the epitaxial layer and the gate oxide layer, and forming a gate on the gate oxide layer.

Description

[Technical Field]

[0001] This disclosure and some embodiments relate to a semiconductor device and a method of manufacturing the same. [Previous Technology]

[0002] Silicon carbide semiconductor devices are prone to problems such as low channel mobility, threshold voltage drift, insufficient reliability of the gate oxide layer at high temperatures, and drift of the body diode in the forward conduction state due to the presence of silicon carbide / silicon oxide interface defects. The presence of silicon carbide / silicon oxide interface defects severely limits the channel mobility of silicon carbide semiconductor devices, and the reliability of the gate oxide layer and the stability of the threshold voltage are also significantly affected. Therefore, a method to reduce silicon carbide / silicon oxide interface defects is needed to improve the performance of silicon carbide semiconductor devices. [Summary of the Invention]

[0003] Some embodiments of this disclosure provide a method for forming a semiconductor device, comprising forming a gate oxide layer on an epitaxial layer, the epitaxial layer including a drift region and a source region, forming a first boron-containing layer on the gate oxide layer, performing a thermal process to move boron in the first boron-containing layer toward the epitaxial layer to form a second boron-containing layer between the epitaxial layer and the gate oxide layer, and forming a gate on the gate oxide layer.

[0004] In some embodiments, the method further includes performing an annealing process in an oxygen-containing environment after forming the second boron-containing layer.

[0005] In some embodiments, the process temperature for performing the thermal process is higher than the process temperature for forming the first boron-containing layer.

[0006] In some embodiments, the thickness of the first boron-containing layer is lower than the thickness of the gate oxide layer before the thermal process is performed.

[0007] In some embodiments, the thickness of the first boron-containing layer is 3% to 10% of the thickness of the gate oxide layer before the thermal process is performed.

[0008] In some embodiments, after the second boron-containing layer is formed, the boron content on the upper surface of the gate oxide layer is lower than the boron content at the interface between the gate oxide layer and the second boron-containing layer.

[0009] Some embodiments of this disclosure provide a semiconductor device comprising a substrate, an epitaxial layer, a boron-containing layer, a gate dielectric layer, and a gate. The epitaxial layer is on the substrate and includes a drift region and a source region. The boron-containing layer is on the epitaxial layer. The gate dielectric layer is on the boron-containing layer. The gate is on the gate dielectric layer.

[0010] In some embodiments, the thickness of the boron-containing layer is less than the thickness of the gate dielectric layer.

[0011] In some embodiments, the boron-containing layer is a boron oxide layer, and the gate dielectric layer is a silicon oxide layer.

[0012] In some embodiments, the boron content on the upper surface of the gate dielectric layer is lower than the boron content at the interface between the gate dielectric layer and the boron-containing layer.

Implementation Method

[0014] Some embodiments of the semiconductor device disclosed herein are used to improve interface defects between a substrate and a gate dielectric layer. Specifically, a boron-containing layer may be formed between the gate dielectric layer and the substrate, and the boron in the boron-containing layer may be used to promote stress relaxation of silicon oxide. Therefore, interface defects between the substrate and the gate dielectric layer are reduced, and the electron mobility of the semiconductor device is improved.

[0015] Figures 1 to 5 illustrate cross-sectional views of a method for manufacturing a semiconductor device 100 according to some embodiments of the present disclosure. Figures 1 to 5 illustrate that the semiconductor device 100 is a planar semiconductor device. Referring to Figure 1, an epitaxial layer 120 is formed on a substrate 110, wherein the epitaxial layer 120 may include a drift region 122, a well region 124, a source region 126, and a body contact region 128. Specifically, the well region 124 is on the drift region 122, the source region 126 and the body contact region 128 are in the well region 124, and the body contact region 128 is adjacent to the source region 126. The substrate 110, the drift region 122 and the source region 126 may have a first conductor type, and the well region 124 and the body contact region 128 may have a second conductor type different from the first conductor type. In some embodiments, the first conductor type may be N-type and the second conductor type may be P-type. In some embodiments, the doping concentration of the substrate 110 and the source region 126 may be higher than the doping concentration of the drift region 122. The doping concentration of the body contact region 128 may be higher than the doping concentration of the well region 124. In some embodiments, the substrate 110 and the epitaxial layer 120 may be made of semiconductor, such as silicon carbide.

[0016] Referring to Figure 2, a gate oxide layer 130 is formed on the epitaxial layer 120. Specifically, the gate oxide layer 130 can be formed by any suitable oxidation process, such as performing a dry oxidation process to oxidize the surface of the epitaxial layer 120, thereby forming the gate oxide layer 130 on the epitaxial layer 120. The thickness of the formed gate oxide layer 130 (thickness T2 in Figure 3) is approximately 400 Å to approximately 500 Å. In some embodiments, the gate oxide layer 130 is made of silicon oxide. During the thermal oxidation process, silicon atoms on the surface of the epitaxial layer 120 bond with oxygen atoms, releasing stress and causing bulk expansion, which in turn leads to interface defects between the epitaxial layer 120 and the gate oxide layer 130. These interface defects may cause a decrease in the electron mobility of the semiconductor device 100. In some embodiments, the surface of the epitaxial layer 120 may be cleaned before forming the gate oxide layer 130.

[0017] Referring to Figure 3, a first boron-containing layer 140 is formed on the gate oxide layer 130. Specifically, the first boron-containing layer 140 can be formed on the gate oxide layer 130 by any suitable method, such as ion implantation, atomic layer deposition, chemical vapor deposition, etc. In some embodiments, the first boron-containing layer 140 is a boron oxide layer (B₂O₃). In some embodiments, the process temperature for forming the first boron-containing layer 140 is between approximately 900 degrees Celsius and approximately 1000 degrees Celsius. In some embodiments, the thickness T1 of the first boron-containing layer 140 is less than the thickness T2 of the gate oxide layer 130, for example, the thickness T1 of the first boron-containing layer 140 is 3% to 10% of the thickness T2 of the gate oxide layer 130.

[0018] Referring to Figure 4, a thermal process is performed to move boron in the first boron-containing layer 140 toward the epitaxial layer 120, thereby forming a second boron-containing layer 150 between the epitaxial layer 120 and the gate oxide layer 130. In some embodiments, the second boron-containing layer 150 is a boron oxide layer (B₂O₃). Specifically, the process temperature for performing the thermal process is higher than the process temperature for forming the first boron-containing layer 140, and the atomic radius of boron atoms is small. Therefore, the thermal energy of the thermal process provides sufficient driving force to move boron in the first boron-containing layer 140 downwards between the epitaxial layer 120 and the gate oxide layer 130. The downwardly moving boron occupies the positions of silicon atoms on the surface of the epitaxial layer 120, thereby reducing the silicon oxide bond strength of the gate oxide layer 130 on the surface of the epitaxial layer 120. In this way, stress relaxation of the oxide can be promoted, thereby reducing interface defects between the epitaxial layer 120 and the gate oxide layer 130. The electron mobility of the semiconductor device 100 also increases accordingly. In some embodiments, the process temperature for performing the thermal process is between approximately 1200°C and approximately 1500°C. The thermal process in Figure 4 allows most of the boron in the first boron-containing layer 140 to move downwards between the epitaxial layer 120 and the gate oxide layer 130, forming the second boron-containing layer 150. Therefore, after performing the thermal process, the first boron-containing layer 140 is no longer present above the gate oxide layer 130, and the boron content on the upper surface of the gate oxide layer 130 (the interface between the gate oxide layer 130 and the gate 160 in the subsequent Figure 5) is lower than the boron content at the interface between the gate oxide layer 130 and the second boron-containing layer 150. The boron content of the gate oxide layer 130 is also lower than the boron content of the second boron-containing layer 150. After the formation of the second boron-containing layer 150, the thickness T4 of the gate oxide layer 130 is between approximately 400 Å and approximately 500 Å. The thickness T3 of the second boron-containing layer 150 is lower than the thickness T4 of the gate oxide layer 130. For example, the thickness T3 of the second boron-containing layer 150 is 3% to 10% of the thickness T4 of the gate oxide layer 130. When the thickness T3 of the second boron-containing layer 150 is less than the above thickness, the boron content between the epitaxial layer 120 and the gate oxide layer 130 may be insufficient, and therefore the interface defects between the epitaxial layer 120 and the gate oxide layer 130 cannot be effectively reduced.

[0019] After forming the second boron-containing layer 150, a first annealing process is performed in an oxygen-containing environment to make the boron oxide structure in the second boron-containing layer 150 more dense. In some embodiments, during the first annealing process, an inert gas (e.g., argon) can be used as a carrier to carry oxygen, and the ratio of oxygen to inert gas flow rate is not less than 1 / 9. In some embodiments, the ratio of oxygen to inert gas flow rate is between 1 / 9 and 2 / 9 during the first annealing process. In some embodiments, the process temperature of the first annealing process is lower than the process temperature of the thermal process used to form the second boron-containing layer 150. In some embodiments, the process temperature of the first annealing process is between approximately 900 degrees Celsius and approximately 1000 degrees Celsius. When the process temperature of the first annealing process is higher than the above temperatures, the gate oxide layer 130 may be prone to leakage current. When the process temperature of the first annealing process is lower than the above-mentioned temperature, the boron oxide structure of the second boron-containing layer 150 may not be dense, and therefore cannot effectively reduce the interface defects between the epitaxial layer 120 and the gate oxide layer 130.

[0020] After performing the first annealing process, a second annealing process is performed in an environment containing nitrogen gas to further reduce interface defects between the epitaxial layer 120 and the gate oxide layer 130. In some embodiments, the nitrogen gas may be nitric oxide, nitrous oxide, nitrogen, ammonia, or a combination thereof.

[0021] Referring to Figure 5, a gate 160 is formed on the gate oxide layer 130. Specifically, after forming the gate 160, the gate 160, the gate oxide layer 130, and the second boron-containing layer 150 may be patterned, thus exposing the upper surface of the epitaxial layer 120. In some embodiments, the gate 160, the gate oxide layer 130, and the second boron-containing layer 150 may have the same pattern. In some embodiments, the second boron-containing layer 150, the gate oxide layer 130, and the gate 160 may be combined and referred to as a gate structure. Next, a dielectric layer 170 is formed on the epitaxial layer 120, the gate 160, the gate oxide layer 130, and the second boron-containing layer 150, a source electrode 180 that contacts the source region 126 and the body contact region 128 is formed on the dielectric layer 170 and the epitaxial layer 120, and a drain electrode 190 is formed under the substrate 110.

[0022] The formed semiconductor device 100 includes a substrate 110, an epitaxial layer 120, a second boron-containing layer 150, a gate oxide layer 130, a gate 160, a dielectric layer 170, a source electrode 180, and a drain electrode 190. The epitaxial layer 120 is on the substrate 110 and includes a drift region 122, a well region 124, a source region 126, and a body contact region 128. The second boron-containing layer 150 is on the epitaxial layer 120. The gate oxide layer 130 is on the second boron-containing layer 150, wherein the thickness T3 of the second boron-containing layer 150 is less than the thickness T2 of the gate oxide layer 130. The gate 160 is on the gate oxide layer 130. The dielectric layer 170 covers the sidewalls of the second boron-containing layer 150, the gate oxide layer 130, and the gate 160, and the upper surface of the gate 160. The source electrode 180 covers the dielectric layer 170 and the epitaxial layer 120, and the source electrode 180 is electrically connected to the source region 126 and the bulk contact region 128 of the epitaxial layer 120. The dielectric layer 170 electrically isolates the source electrode 180 from the gate electrode 160. The drain electrode 190 is located below the substrate 110. The second boron-containing layer 150 between the gate oxide layer 130 and the epitaxial layer 120 disclosed herein can be used to reduce interface defects between the gate oxide layer 130 and the epitaxial layer 120, thereby improving the electron mobility of the semiconductor device 100.

[0023] Figure 6 illustrates a cross-sectional view of a semiconductor device 100 according to other embodiments disclosed herein. The difference between the semiconductor device 100 in Figure 6 and the semiconductor device 100 in Figure 5 is that the semiconductor device 100 in Figure 5 is a planar semiconductor device, while the semiconductor device 100 in Figure 6 is a trench semiconductor device. The second boron-containing layer 150, the gate oxide layer 130, and the gate 160 of the semiconductor device 100 in Figure 6 form a trench structure and are formed in the trench of the epitaxial layer 120. The second boron-containing layer 150, the gate oxide layer 130, and the gate 160 are formed between well regions 124. The gate oxide layer 130 runs along the bottom and sidewalls of the gate 160, the second boron-containing layer 150 runs along the bottom and sidewalls of the gate oxide layer 130, and the second boron-containing layer 150 contacts the epitaxial layer 120. Other details of the structure of the semiconductor device 100 in Figure 6 are as described in Figures 1 through 5, and therefore will not be repeated here.

[0024] The semiconductor device 100 in Figure 6 is manufactured in a similar manner to the semiconductor devices 100 in Figures 1 to 5. The difference lies in that, when forming the semiconductor device 100 in Figure 6, the epitaxial layer 120 has trenches between well regions 124, and the gate oxide layer 130 and the first boron-containing layer 140 are conformally formed on the epitaxial layer 120. Next, a thermal process is performed to move the boron in the first boron-containing layer 140 toward the epitaxial layer 120, thereby forming a second boron-containing layer 150 between the epitaxial layer 120 and the gate oxide layer 130. Next, a gate 160 is formed in the trench of the epitaxial layer 120, and a photolithography process is performed to remove excess gate 160, gate oxide layer 130, and second boron-containing layer 150, such that the top surfaces of the epitaxial layer 120, gate 160, gate oxide layer 130, and second boron-containing layer 150 are coplanar. After photolithography, the upper surface of the epitaxial layer 120 is exposed. Next, a dielectric layer 170 is formed covering the gate 160, the gate oxide layer 130, and the second boron-containing layer 150. A source electrode 180 covering the dielectric layer 170 is formed on the epitaxial layer 120, and a drain electrode 190 is formed under the substrate 110. It should be understood that the details of forming the gate oxide layer 130, the first boron-containing layer 140, and the second boron-containing layer 150 in Figure 6 have been discussed in Figures 3 and 4, and therefore will not be repeated here. Other details regarding the fabrication of the remaining components of the semiconductor device 100 in Figure 6 are as described in Figures 1 to 5, and therefore will not be repeated here. The second boron-containing layer 150 between the gate oxide layer 130 and the epitaxial layer 120 in Figure 6 can also be used to reduce interface defects between the gate oxide layer 130 and the epitaxial layer 120, thereby improving the electron mobility of the semiconductor device 100.

[0025] It should be noted that although this disclosure only illustrates planar semiconductor devices and trench semiconductor devices containing boron-containing layers, this disclosure is not limited thereto. As long as the boron-containing layer is formed between the gate dielectric layer and the epitaxial layer to reduce interface defects between the epitaxial layer and the gate oxide layer, the structure and manufacturing method of the semiconductor device can fall within the protection scope of this disclosure. For example, the boron-containing layer disclosed herein can also be applied to other types of semiconductor devices, such as shielded gate trench semiconductor devices and super junction semiconductor devices.

[0026] The above description is only a part of the embodiments disclosed herein, and not all of the embodiments. Any equivalent changes made by those skilled in the art to the technical solutions disclosed herein by reading the specification thereof shall be covered by the claims of this disclosure. [Simplified Explanation of the Diagram]

[0013] Figures 1 to 5 illustrate cross-sectional views of methods for manufacturing conductor devices according to some embodiments of the present disclosure. Figure 6 illustrates cross-sectional views of semiconductor devices according to other embodiments of the present disclosure. [Biomaterial Storage]

[0028] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a gate oxide layer on an epitaxial layer, the epitaxial layer including a drift region and a source region; forming a first boron-containing layer on the gate oxide layer; performing a thermal process to move boron in the first boron-containing layer toward the epitaxial layer to form a second boron-containing layer between the epitaxial layer and the gate oxide layer; and forming a gate on the gate oxide layer.

2. The method as described in claim 1 further comprises: performing an annealing process in an oxygen-containing environment after forming the second boron-containing layer.

3. The method as described in claim 1, wherein a process temperature at which the thermal process is performed is higher than a process temperature at which the first boron-containing layer is formed.

4. The method as described in claim 1, wherein, prior to performing the thermal process, the thickness of the first boron-containing layer is less than the thickness of the gate oxide layer.

5. The method as described in claim 1, wherein, prior to performing the thermal process, the thickness of the first boron-containing layer is 3% to 10% of the thickness of the gate oxide layer.

6. The method as claimed in claim 1, wherein after the second boron-containing layer is formed, the boron content on an upper surface of the gate oxide layer is lower than the boron content at an interface between the gate oxide layer and the second boron-containing layer.

7. A semiconductor device comprising: a substrate; an epitaxial layer on the substrate, the epitaxial layer including a drift region and a source region; a boron-containing layer on the epitaxial layer; a gate dielectric layer on the boron-containing layer, wherein the boron content of the gate dielectric layer is lower than the boron content of the boron-containing layer; and a gate on the gate dielectric layer.

8. The semiconductor device as claimed in claim 7, wherein the thickness of the boron-containing layer is less than the thickness of the gate dielectric layer.

9. The semiconductor device as claimed in claim 7, wherein the boron-containing layer is a boron oxide layer and the gate dielectric layer is a silicon oxide layer.

10. The semiconductor device of claim 7, wherein the boron content of an upper surface of the gate dielectric layer is lower than the boron content of an interface between the gate dielectric layer and the boron-containing layer.

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