Micro light-emitting package
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- ENNOSTAR CORP
- Filing Date
- 2023-02-04
- Publication Date
- 2026-08-01
Smart Images
Figure TWG2TB001903594_001 
Figure TWG2TB001903594_002 
Figure TWG2TB001903594_003
Abstract
Description
Miniature Light-Emitting Diode Packaging Structure The present disclosure relates to a packaging structure, and more particularly to a miniature light-emitting diode packaging structure having a multi-layer resin wiring substrate. Currently, micro light-emitting diode display technology mainly uses red, green, and blue light-emitting diodes (LEDs) as the three primary color light sources, and requires a very high black ratio to achieve better contrast in the displayed image. However, the metal wiring on the surface of the substrate of a general display unit package affects the black ratio of the entire display unit package, resulting in a decrease in contrast. Some embodiments of the present disclosure provide a miniature light-emitting diode packaging structure. The miniature light-emitting diode packaging structure includes a multi-layer resin wiring substrate, a plurality of miniature light-emitting diode chips, and a protective layer. The multi-layer resin wiring substrate includes a black resin layer and a conductive structure, and the conductive structure is located in the black resin layer. The plurality of miniature light-emitting diode chips are disposed on the multi-layer resin wiring substrate and are electrically connected to the conductive structure, and the protective layer covers the miniature light-emitting diode chips. The miniature light-emitting diode chips include a first miniature light-emitting diode chip, a second miniature light-emitting diode chip, and a third miniature light-emitting diode chip. The first miniature light-emitting diode chip emits red light, the second miniature light-emitting diode chip emits green light, and the third miniature light-emitting diode chip emits blue light. The above does not represent every embodiment or aspect of the present disclosure, but only provides examples of some novel aspects and features described herein. When combined with the accompanying drawings and the appended claims, the above features and advantages of the present disclosure, as well as other features and advantages, will become apparent from the following detailed description of representative embodiments and methods for implementing the present disclosure. The following disclosure provides different embodiments for implementing different components in the provided packaging structure. Specific examples of each component and its configuration are described below to simplify the embodiments of the present disclosure, and are of course not intended to limit the present disclosure. For example, when it is mentioned in the description that a first component is formed on a second component, it may include an embodiment in which the first component and the second component are in direct contact, or it may include an embodiment in which additional components are formed between the first component and the second component such that the first component and the second component are not in direct contact. In addition, the present disclosure may repeat element symbols and / or characters in different embodiments or examples. Such repetition is for the purpose of brevity and clarity, and is not intended to represent a relationship between the different embodiments and / or examples discussed. Referring to FIG. 1, the micro light-emitting diode packaging structure 1000 includes a multi-layer resin wiring substrate 100, a plurality of micro light-emitting diode chips 200, and a protective layer 300. The multi-layer resin wiring substrate 100 includes a black resin layer 40 and a conductive structure 20, and the conductive structure 20 is located in the black resin layer 40. The plurality of micro light-emitting diode chips 200 are disposed on the multi-layer resin wiring substrate 100 and are electrically connected to the conductive structure 20. Moreover, the protective layer 300 covers the micro light-emitting diode chips 200. In some embodiments, the micro light-emitting diode chip 200 can be a micro light-emitting diode chip (micro LED chip) or a quantum dot light-emitting diode (quantum dot LED), but the present disclosure is not limited thereto. In some embodiments, the micro light-emitting diode chip 200 can emit red light, green light, or blue light, but the present invention is not limited thereto, and the micro light-emitting diode chip 200 can also emit light of other wavelengths, such as ultraviolet light (UV). Referring to FIG. 1, in some embodiments, the multi-layer resin wiring substrate 100 includes a conductive structure 20 and a black resin layer 40. The conductive structure 20 includes a first conductive layer 22, a second conductive layer 24, a first via conductor 32, and a second via conductor 34. The black resin layer 40 includes a first black resin layer 42 and a second black resin layer 44. The first black resin layer 42 covers the side surface and the top surface of the first conductive layer 22, and the first via conductor 32 passes through the first black resin layer 42 and is electrically connected to the first conductive layer 22. The second conductive layer 24 is disposed on the first black resin layer 42, and the second conductive layer 24 is electrically connected to the first via conductor 32 and the first conductive layer 22. The second black resin layer 44 covers the second conductive layer 24, and the second via conductor 34 passes through the second black resin layer 44 and is electrically connected to the second conductive layer 24. In some embodiments, the black resin layer 40 includes a thermoplastic resin, such as polyphthalamide (PPA), poly(1,4-cyclohexylene dimethylene terephthalate) (PCT); a thermosetting resin, such as a thermosetting silicone resin (Silicone Molding Compound, SMC), a thermosetting epoxy resin (Epoxy Molding Compound, EMC); nylon 9T (Polyamide9T, PA9T); other suitable materials or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the black resin layer 40 includes a first black resin layer 42 and a second black resin layer 44, wherein the first black resin layer 42 and the second black resin layer 44 include carbon black. The carbon black concentrations of the first black resin layer 42 and the second black resin layer 44 are respectively between 2% and 5% by weight, and can be, for example, 2%, 3%, 4%, 5%, but the present disclosure is not limited thereto. In some embodiments, the protective layer 300 includes carbon black, and its concentration is between about 0.1% and 2% by weight, and can be, for example, 0.1%, 0.3%, 0.5%, 0.7%, 0.9%, 1.1%, 1.5%, 1.7%, 2%, but the present disclosure is not limited thereto. FIG. 2 is a top view of the multi-layer resin wiring substrate 100 according to some embodiments of the present disclosure. In some embodiments, the width a of the top surface 34s of the second via conductor is 20 micrometers to 50 micrometers (μm), and the length b of the top surface 34s of the second via conductor is 20 micrometers to 50 micrometers. In some embodiments, along the first direction D1, the pitch d between the top surfaces 34s of each second via conductor is 20 micrometers to 50 micrometers. Along the third direction D3, the pitch c between the top surfaces 34s of each second via conductor is 20 micrometers to 50 micrometers. The width e of the multi-layer resin wiring substrate 100 is 200 micrometers to 500 micrometers, and the length f of the multi-layer resin wiring substrate 100 is 200 micrometers to 500 micrometers. In some embodiments, the micro light-emitting diode packaging structure 1000 includes six top surfaces 34s of the second conductive vias, and the second conductive vias 34 are respectively surrounded by the second black resin layer 44, and the six top surfaces 34s of the second conductive vias are respectively exposed on the upper surface 44t of the second black resin layer. In some embodiments, the area of the upper surface 44t of the second black resin layer is the area of the upper surface of the multi-layer resin wiring substrate 100 minus the total area of the six top surfaces 34s of the second via conductors. The ratio of the area of the upper surface 44t of the second black resin layer to the area of the upper surface of the multi-layer resin wiring substrate 100 is between 93% and 97%, that is, the black occupation ratio is 93% to 97%, and the black occupation ratio can be, for example, 93%, 94%, 95%, 96%, 97%, but the present disclosure is not limited thereto. Since the first via conductor 32, the second conductive layer 24, and the second via conductor 34 are all coated in the black resin layer 40, only the top surface 34s of the second via conductor will be exposed. Therefore, when looking down from above the multi-layer resin wiring substrate 100, the metal traces of the first via conductor 32 and the second conductive layer 24 cannot be seen, which greatly increases the black occupation ratio and improves the contrast of the display. In some embodiments, the length f of the multilayer resin wiring substrate 100 may be 450 micrometers, the width e of the multilayer resin wiring substrate 100 may be 450 micrometers, and the area of the upper surface of the multilayer resin wiring substrate 100 is 202,500 square micrometers. The width a of the top surface 34s of the second via conductor is 45 micrometers, the length b is 45 micrometers, and the total area of the six top surfaces 34s of the second via conductors is 12,150 square micrometers. The area of the upper surface 44t of the second black resin layer is the area of the upper surface of the multilayer resin wiring substrate 100 minus the total area of the six top surfaces 34s of the second via conductors. Therefore, the area of the upper surface 44t of the second black resin layer is 190,350 square micrometers. The ratio of the area of the upper surface 44t of the second black resin layer to the area of the upper surface of the multilayer resin wiring substrate 100 is 94%, that is, the black area ratio is 94%. Please refer to FIGS. 3-11. According to some embodiments of the present disclosure, a cross-sectional schematic diagram of the micro light-emitting diode packaging structure 1000 at each stage in the manufacturing method is shown. Please refer to FIG. 3. In some embodiments, a temporary substrate 10 is provided. In some embodiments, the temporary substrate 10 may include a polyethylene terephthalate (PET) carrier, a polyimide (PI) carrier, a polypropylene (PP) carrier, a polycarbonate (PC) carrier, other suitable carriers, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the temporary substrate 10 may include sapphire, quartz, glass, other suitable carriers, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the temporary substrate 10 may include a wafer, a chip, other suitable carriers, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the temporary substrate 10 may include ceramics, other suitable carriers, or a combination thereof, but the present disclosure is not limited thereto. Please refer to FIG. 4, where a first conductive layer 22 is provided on the temporary substrate 10. In some embodiments, the first conductive layer 22 can be formed on the temporary substrate 10 by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a high density plasma CVD (HDP-CVD) process, a spin coating process, an electroplating process, a sputtering process, a low-pressure chemical vapor deposition (LPCVD) process, a low-temperature chemical vapor deposition (LTCVD) process, other suitable methods, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first conductive layer 22 can be copper, aluminum, iron, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. Referring to FIG. 5, in some embodiments, a first via conductor 32 is formed on the first conductive layer 22. The first via conductor 32 is in contact with the first conductive layer 22 and extends in the second direction D2. In some embodiments, the first via conductor 32 is electrically connected to the first conductive layer 22. In some embodiments, the first via conductor 32 can be formed on the first conductive layer 22 by an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a high density plasma CVD process, a spin coating process, an electroplating process, a sputtering process, a low-pressure chemical vapor deposition process, a low-temperature chemical vapor deposition process, other suitable methods, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first via conductor 32 can be copper, aluminum, iron, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. Referring to FIG. 6, according to some embodiments of the present disclosure, a first black resin layer 42 is formed on the upper surface 10t of the temporary substrate, on the side surface 22s and the top surface 22t of the first conductive layer, and on the side surface 32s of the first via conductor, and the top surface 32t of the first via conductor is exposed. In some embodiments, the upper surface 42t of the first black resin layer is substantially flush with the top surface 32t of the first via conductor. In other embodiments, the first black resin layer 42 is formed on the temporary substrate 10, the first conductive layer 22 and the first via conductor 32, and the top surface 32t of the first via conductor is exposed. In some embodiments, the first black resin layer 42 can be formed by molding, lamination, coating process or other suitable forming processes. In some embodiments, the first black resin layer 42 can be a thermoplastic resin, such as polyphthalamide, poly(1,4-cyclohexanedimethylene terephthalate), other suitable materials or combinations thereof, however, the present disclosure is not limited thereto. In some embodiments, the first black resin layer 42 can be a thermosetting resin, such as a thermosetting silicone resin, a thermosetting epoxy resin, other suitable materials or combinations thereof, however, the present disclosure is not limited thereto. In some embodiments, the first black resin layer 42 can be nylon 9T, other suitable materials or combinations thereof, however, the present disclosure is not limited thereto. FIG. 7 shows that in some embodiments, a second conductive layer 24 is provided on the upper surface 42t of the first black resin layer and the top surface 32t of the first via conductor, such that the top surface 32t of the first via conductor is in contact with the second conductive layer 24. Specifically, the first via conductor 32 is in electrical contact with the second conductive layer 24. In some embodiments, the second conductive layer 24 can be formed by atomic layer deposition process, chemical vapor deposition process, physical vapor deposition process, high density plasma chemical vapor deposition process, spin coating process, electroplating process, sputtering process, low pressure chemical vapor deposition process, low temperature chemical vapor deposition process, other suitable methods or combinations thereof on the first black resin layer 42 and the top surface 32t of the first via conductor, but the present disclosure is not limited thereto. In some embodiments, the second conductive layer 24 can be copper, aluminum, iron, other suitable materials or combinations thereof, however, the present disclosure is not limited thereto. FIG. 8 shows that in some embodiments, a second vias conductor 34 is formed on the second conductive layer 24, the second vias conductor 34 contacts the second conductive layer 24, and the second vias conductor 34 extends in the second direction D2. In some embodiments, the second vias conductor 34 is electrically connected to the second conductive layer 24. In some embodiments, the second vias conductor 34 can be formed on the second conductive layer 24 by an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a high density plasma chemical vapor deposition process, a spin coating process, an electroplating process, a sputtering process, a low pressure chemical vapor deposition process, a low temperature chemical vapor deposition process, other suitable methods, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the second vias conductor 34 can be copper, aluminum, iron, other suitable materials, or a combination thereof, however, the present disclosure is not limited thereto. Referring to FIG. 9, it shows that in some embodiments, a second black resin 44 is formed on the upper surface 42t of the first black resin layer, on the side surface and the top surface of the second conductive layer 24, and on the side surface of the second vias conductor 34, and the top surface 34s of the second vias conductor is exposed. Referring to FIG. 9, in some embodiments, the second black resin layer 44 has an upper surface 44t, the second vias conductor 34 has a top surface 34s exposed to the upper surface 44t of the second black resin layer, and the top surface 34s of the second vias conductor is substantially coplanar with the upper surface 44t of the second black resin layer. The upper surface 44t of the second black resin layer is substantially flush with the top surface 34s of the second vias conductor, serving as a die bonding area for electrically connecting the micro light emitting diode chip. In some other embodiments, the second black resin layer 44 is formed on the first black resin layer 42, the second conductive layer 24, and the second vias conductor 34, and the top surface 34s of the second vias conductor is exposed. In some embodiments, the second black resin layer 44 can be formed by a molding, lamination, coating process, or other suitable forming process. In some embodiments, the second black resin layer 44 can be a thermoplastic resin, such as polyphthalamide, polyethylene terephthalate 1,4-cyclohexanedimethanol ester, other suitable materials, or a combination thereof, however, the present disclosure is not limited thereto. In some embodiments, the second black resin layer 44 can be a thermosetting resin, such as a thermosetting silicone resin, a thermosetting epoxy resin, other suitable materials, or a combination thereof, however, the present disclosure is not limited thereto. In some embodiments, the second black resin layer 44 can be nylon 9T, other suitable materials, or a combination thereof, however, the present disclosure is not limited thereto. Next, as shown in FIG. 10, a removal process is performed to remove the temporary substrate 10 from the first black resin layer 42, exposing the lower surface 22b of the first conductive layer from the lower surface 42b of the first black resin layer, serving as the solder pads of the package. In some embodiments, the lower surface 42b of the first black resin layer is substantially flush with the lower surface 22b of the first conductive layer. In some embodiments, the removal process includes laser debonding, plasma etching, chemical etching, or other suitable removal processes. Finally, the multilayer resin wiring substrate 100 of the present disclosure is formed. In some embodiments, a plurality of micro light-emitting diode chips 200 are disposed on the upper surface of the multilayer resin wiring substrate 100 and electrically connected to the conductive structure 20. FIG. 11 is an illustration showing a micro light-emitting diode chip 200 electrically connected to the top surface 34s of the second conductive via, but more than one micro light-emitting diode chip 200 can be electrically connected to the corresponding top surfaces 34s of the second conductive vias respectively. In some embodiments, the plurality of micro light-emitting diode chips 200 are arranged side by side. Also, the electrode pads 200p (electrode pad) of the micro light-emitting diode chips 200 are electrically connected to the top surfaces 34s of the second conductive vias. In some embodiments, the micro light-emitting diode chips 200 can be transferred onto the multilayer resin wiring substrate 100 by mass transfer methods such as laser transfer, stamp transfer, etc. In some embodiments, a protective layer 300 is formed on the upper surface and side surfaces of the micro light-emitting diode chips 200, and finally the micro light-emitting diode package structure 1000 as shown in FIG. 1 is formed. In some embodiments, the protective layer 300 surrounds the micro light-emitting diode chips 200. In some embodiments, the protective layer 300 may include polysiloxane or silicone, epoxy molding compound (EMC), liquid molding compound (LMC), but the present disclosure is not limited thereto, and other suitable encapsulation materials are also applicable to the present disclosure. In some embodiments, the light transmittance of the protective layer 300 can be greater than 90%. In some embodiments, the thickness of the protective layer 300 is 20 microns to 90 microns, such as 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, or 90 microns. Referring to FIGS. 10 and 11, in some embodiments, the second via conductor 34 is closer to the center line C of the multilayer resin wiring substrate 100 than the first via conductor 32. Referring to FIG. 2, the center line C is the middle position of the length f of the multilayer resin wiring substrate 100 along the first direction D1. Therefore, the pitch between the two electrode pads 200p of the micro light-emitting diode chip 200 corresponds to the pitch d (20 microns to 50 microns) between the top surfaces 34s of the two second via conductors, so as to improve the transfer yield of the micro light-emitting diode chip 200. Referring to FIG. 1, in some embodiments, the first black resin layer 42 has a lower surface 42b, and the first conductive layer 22 has a lower surface 22b. The lower surface 42b of the first black resin layer and the lower surface 22b of the first conductive layer are substantially coplanar. In some embodiments, the lower surface 22b of the first conductive layer is slightly recessed from the lower surface 42b of the first black resin layer. As the solder pad of the package, the micro light-emitting diode packaging structure 1000 can be electrically bonded to the panel substrate 400 by using a solder paste process. Referring to FIG. 12, in another embodiment, the thickness h of the multilayer resin wiring substrate 100 is 80 to 120 microns. The height g of the top surface 34s of the second via conductor protruding from the upper surface 44t of the second black resin layer is 0 to 5 microns, that is, the distance between the top surface 34s of the second via conductor and the upper surface 44t of the second black resin layer is between 0 and 5 microns. Referring to FIG. 12, in some embodiments, the lower surface 22b of the first conductive layer protrudes from the lower surface 42b of the first black resin layer. Referring to FIG. 12, in some embodiments, the lower surface 22b of the first conductive layer can be thickened by electroplating, so that the lower surface 22b of the first conductive layer protrudes from the lower surface 42b of the first black resin layer as the solder pad of the package. In some embodiments, the first black resin layer 42 has a first black resin layer side surface 42s, and the second black resin layer 44 has a second black resin layer side surface 44s. The first black resin layer side surface 42s and the second black resin layer side surface 44s are substantially coplanar. Therefore, in the second direction D2, a vertical plane perpendicular to the lower surface 42b of the first black resin layer is formed. In some embodiments, the first black resin layer 42 and the second black resin layer 44 can be of the same material. In some embodiments, the first black resin layer 42 and the second black resin layer 44 can be of different materials. In some embodiments, the carbon black concentration of the first black resin layer 42 is the same as that of the second black resin layer 44. In some embodiments, the carbon black concentration of the first black resin layer 42 is different from that of the second black resin layer 44. In some embodiments, the carbon black concentration of the second black resin layer 44 is higher than that of the first black resin layer 42. In some embodiments, the carbon black concentration of the second black resin layer 44 is lower than that of the first black resin layer 42. FIG. 13 is a top view of a substrate of Comparative Example 1 of the present disclosure. Comparative Example 1 is a substrate 110 of a general package, and a large area of metal wiring 38 is provided on its surface, which will reduce the black ratio of the entire package. The black ratio of the general substrate 110 is about 70% to 75%. FIG. 14 is a top view of a substrate of Comparative Example 2 of the present disclosure. The substrate 120 of the general package of Comparative Example 2 of the present disclosure uses a black material layer 60 (black matrix) to cover the metal wiring (not shown) on the outer periphery of the substrate 120, and exposes some metal wiring 38 in the middle of the substrate 120. The black ratio of Comparative Example 2 is about 85% to 90%, but the reliability of the black material layer 60 is poor and it is easy to peel off. Therefore, the yield of the substrate 120 with the black material layer 60 covered is poor. According to Comparative Example 1 and Comparative Example 2, the present disclosure disposes the metal wiring inside the multilayer resin wiring substrate 100. Therefore, the exposed area of the metal wiring is reduced, and only the top surface 34s of the second via conductor in the die bonding area is exposed. Therefore, the black ratio can be increased to 93% to 97%. FIG. 15 is a schematic plan view of a display device including an embodiment of the present disclosure. In some embodiments, the panel substrate 400 includes a plurality of micro light-emitting diode packaging structures 1000. The plurality of micro light-emitting diode packaging structures 1000 can be arranged on the panel substrate 400. In some embodiments, the micro light-emitting diode packaging structures 1000 are arranged on the panel substrate 400 in a 2×3 manner, but the present disclosure is not limited thereto. In some embodiments, the micro light-emitting diode packaging structures 1000 are arranged on the panel substrate 400 in various rows and columns (n×m, n = 1, 2, 3, 4, 5..., m = 1, 2, 3, 4, 5...), such as 2×2, 3×2, 2×3, 3×3, 3×4, 5×5, 2×5. Referring to FIG. 15, in some embodiments, each micro light-emitting diode packaging structure 1000 includes a plurality of micro light-emitting diode chips 200 (200a, 200b, 200c). In some embodiments, the micro light-emitting diode packaging structure 1000 further includes a first micro light-emitting diode chip 200a, a second micro light-emitting diode chip 200b, and a third micro light-emitting diode chip 200c. In some embodiments, as shown in FIG. 15, the first micro light-emitting diode chip 200a, the second micro light-emitting diode chip 200b, and the third micro light-emitting diode chip 200c within each micro light-emitting diode packaging structure 1000 can be arranged in a column or a row. In some embodiments, the first micro light-emitting diode chip 200a, the second micro light-emitting diode chip 200b, and the third micro light-emitting diode chip 200c can emit lights of different colors from each other. In some embodiments, the first micro light-emitting diode chip 200a can emit red light, the second micro light-emitting diode chip 200b can emit green light, and the third micro light-emitting diode chip 200c can emit blue light. Referring to FIG. 16, in some embodiments, a cross-sectional view of mounting the micro light-emitting diode packaging structure 1000 on the panel substrate 400. Referring to FIG. 16, in some embodiments, the micro light-emitting diode packaging structure 1000 is mounted on the panel substrate 400 by a bonding material (not shown). Referring to FIG. 16, in some embodiments, the lower surface 22b of the first conductive layer, i.e., the solder pad of the package, can be bonded to the electrical bonding pad 410 on the panel substrate 400 by a bonding material. However, the present disclosure is not limited thereto, and epoxy resin bonding, eutectic bonding, metal bonding, etc. can be used. The electrical bonding pad 410 can be bonded corresponding to the lower surface 22b of the first conductive layer (i.e., the solder pad of the package) of the micro light-emitting diode packaging structure 1000 to be mounted on the electrical bonding pad 410 of the panel substrate. Referring to FIG. 16, in some embodiments, the material of the panel substrate 400 can be glass, FR-4 glass epoxy, polyimide (PI), but the present disclosure is not limited thereto. In some embodiments, the panel substrate 400 can be a circuit board, but the present disclosure is not limited thereto. In some embodiments, the panel substrate 400 can include an active matrix driving circuit or a passive matrix driving circuit, but the present disclosure is not limited thereto. In some embodiments, a large-sized display can be assembled by splicing several panel substrates 400 on which the micro light-emitting diode packaging structures 1000 are mounted. Referring to FIG. 17, it is a top perspective view of the micro light-emitting diode packaging structure 1000 of the present disclosure. Referring to FIG. 17, in some embodiments, the protective layer 300 includes a horizontal protective layer upper surface 300t and a vertical protective layer side surface 300s, forming a rectangular packaging body or a cubic packaging body. In some embodiments, the protective layer side surface 300s is substantially coplanar with the first black resin layer side surface 42s and the second black resin layer side surface 44s. FIG. 18 is a schematic cross-sectional view of the micro light-emitting diode packaging structure 2000 according to another embodiment of the present disclosure. FIG. 18 and FIG. 1 use the same or similar element symbols to represent the same or similar elements. As shown in FIG. 18, the difference between the micro light-emitting diode packaging structure 2000 and the micro light-emitting diode packaging structure 1000 is that the micro light-emitting diode packaging structure 2000 includes a control element 50. That is, the difference between the multi-layer resin wiring substrate 102 and the multi-layer resin wiring substrate 100 is that the multi-layer resin wiring substrate 102 further includes a control element 50. The control element 50 is disposed on the second conductive layer 24 and is electrically connected to the second conductive layer 24. The second via conductor 34 is disposed on the control element 50 and is electrically connected to the control element 50. Moreover, a plurality of micro light-emitting diode chips 200 are disposed on the multi-layer resin wiring substrate 102 and are electrically connected to the second via conductor 34, and a protective layer 300 covers the micro light-emitting diode chips 200. In some embodiments, the control element 50 includes a micro drive integrated circuit device, a micro control integrated circuit device, or a combination of the above. Referring to FIG. 19, FIG. 19 is a photograph of the upper surface (light-emitting surface) of the micro light-emitting diode chip 200 having periodically arranged concavo-convex patterns. In some embodiments, the micro light-emitting diode chip 200 is not equipped with a sapphire substrate, but is equipped with periodically arranged concavo-convex patterns after laser lift-off of the sapphire substrate to enhance light extraction and adjust the pointing angle of the micro light-emitting diode chip 200. Referring to FIG. 20, FIG. 20 is a top view of the micro light-emitting diode chip 200 disposed on the multi-layer resin wiring substrate 100. Referring to FIG. 2, the ratio of the total area of the top surface 34s of the second via conductor to the area of the upper surface of the multi-layer resin wiring substrate 100 is between 3% and 6%, that is, the die bonding area accounts for 3 to 6%, for example, 3%, 4%, 5%, or 6%. In some embodiments, the length f of the multi-layer resin wiring substrate 100 can be 450 microns, the width e of the multi-layer resin wiring substrate 100 can be 450 microns, and the area of the upper surface of the multi-layer resin wiring substrate 100 is 202500 square microns. The width a of the top surface 34s of the second via conductor is 45 microns, the length b of the top surface 34s of the second via conductor is 45 microns, and the total area of the six top surfaces 34s of the second via conductor is 12150 square microns. That is, the die bonding area accounts for 6%. Referring to FIG. 20, in some embodiments, the ratio of the total upper surface area of the micro light-emitting diode chip 200 to the area of the upper surface of the multi-layer resin wiring substrate 100 is from 1% to 6%, that is, the chip area ratio can be from 1% to 6%. That is, the chip area ratio can be 1%, 2%, 3%, 4%, 5%, or 6%. In some embodiments, the length g of the micro light-emitting diode chip 200 ranges from 10 micrometers (μm) to 90 micrometers, and the width h of the micro light-emitting diode chip 200 ranges from 10 micrometers to 50 micrometers. In some embodiments, the length g of the micro light-emitting diode chip 200 can be 80 micrometers, and the width h of the micro light-emitting diode chip 200 can be 40 micrometers. The micro light-emitting diode chip 200 has an upper surface (light-emitting surface). Therefore, the total upper surface area of the micro light-emitting diode chip 200 is 9600 square micrometers. Also, the length f of the multi-layer resin wiring substrate 100 can be 450 micrometers, the width e of the multi-layer resin wiring substrate 100 can be 450 micrometers, and the area of the upper surface of the multi-layer resin wiring substrate 100 is 202500 square micrometers. So, the ratio of the total upper surface area of the micro light-emitting diode chip 200 to the area of the upper surface of the multi-layer resin wiring substrate 100 is 4.7%. That is, the chip area ratio is 4.7%. Since the micro light-emitting diode chip 200 (200a, 200b, 200c) is electrically bonded to the top surface 34s (die bonding area) of the second via conductor, the micro light-emitting diode chip 200 will cover a part of the area of the top surface 34s of the second via conductor (such as covering half of the area of the top surface 34s of the second via conductor). Therefore, the partial area of the top surface 34s of the second via conductor that can be observed from the outside is limited to a smaller area. In some embodiments, the ratio of the chip area ratio to the die bonding area ratio ranges from 0.3 to 2. In some embodiments, the ratio of the chip area ratio to the die bonding area ratio can be 0.4, 0.5, 0.6, 0.7, 0.78, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.56, 1.6, 1.7, 1.8, 1.9. Components between the embodiments of the present disclosure can be arbitrarily combined and used as long as they do not violate the inventive spirit or conflict with each other. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps in the specific embodiments described in the specification. Any person of ordinary skill in the art can understand from the disclosure of the present disclosure the processes, machines, manufactures, compositions of matter, devices, methods, and steps developed currently or in the future. As long as they can perform substantially the same functions or achieve substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods, and steps. Any embodiment or claim of the present disclosure does not have to achieve all the purposes, advantages, and / or features disclosed in the present disclosure. 10: Temporary substrate 10t: Upper surface of the temporary substrate 20: Conductive structure 22: First conductive layer 22t: Top surface of the first conductive layer 22s: Side surface of the first conductive layer 22b: Bottom surface of the first conductive layer 24: Second conductive layer 32: First via conductor 32t: Top surface of the first via conductor 32s: Side surface of the first via conductor 34: Second via conductor 34s: Top surface of the second via conductor 38: Metal trace 40: Black resin layer 42: First black resin layer 42t: Upper surface of the first black resin layer 42b: Bottom surface of the first black resin layer 42s: Side surface of the first black resin layer 44: Second black resin layer 44t: Upper surface of the second black resin layer 44s: Side surface of the second black resin layer 50: Control element 60: Black material layer 100: Multilayer resin wiring substrate 102: Multilayer resin wiring substrate 110: Substrate 120: Substrate 200: Micro light-emitting diode chip 200a: First micro light-emitting diode chip 200b: Second micro light-emitting diode chip 200c: Third micro light-emitting diode chip 200p: Electrode pad 300: Protective layer 300t: Upper surface of the protective layer 300s: Side surface of the protective layer 1000: Micro light-emitting diode packaging structure 2000: Micro light-emitting diode packaging structure 400: Panel substrate 410: Electrical bonding pad C: Center line The viewpoints of the embodiments of the present disclosure can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industrial standard conventions, some components may not be drawn to scale. In fact, for the sake of clear description, the sizes of different components may be increased or decreased. FIG. 1 is a cross-sectional schematic diagram of a micro light-emitting diode packaging structure according to some embodiments of the present disclosure. FIG. 2 is a top view of a multilayer resin wiring substrate according to some embodiments of the present disclosure. FIGS. 3-11 are cross-sectional schematic diagrams of various stages in the manufacturing method of the micro light-emitting diode packaging structure according to some embodiments of the present disclosure as shown in FIG. 1. FIG. 12 is a cross-sectional schematic diagram of a multilayer resin wiring substrate according to another embodiment of the present disclosure. FIG. 13 is a top view of the substrate of Comparative Example 1 of the present disclosure. FIG. 14 is a top view of the substrate of Comparative Example 2 of the present disclosure. FIG. 15 is a schematic plan view of a display device according to an embodiment of the present disclosure. FIG. 16 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure. FIG. 17 is a top view three-dimensional diagram of the micro light-emitting diode packaging structure of the present disclosure. FIG. 18 is a cross-sectional schematic diagram of a micro light-emitting diode packaging structure according to another embodiment of the present disclosure. FIG. 19 is a photograph of the upper surface of the micro light-emitting diode chip of the present disclosure having periodically arranged uneven patterns. FIG. 20 is a top view of the micro light-emitting diode chip disposed on the multilayer resin wiring substrate of the present disclosure. 20: Conductive structure 22: First conductive layer 22b: Lower surface of the first conductive layer 24: Second conductive layer 32: First via conductor 34: Second via conductor 40: Black resin layer 42: First black resin layer 42b: Lower surface of the first black resin layer 42s: Side surface of the first black resin layer 44: Second black resin layer 44s: Side surface of the second black resin layer 100: Multilayer resin wiring substrate 200: Micro light-emitting diode chip 300: Protective layer 1000: Micro light-emitting diode packaging structure
Claims
1. A miniature light-emitting diode packaging structure, comprising: A multilayer resin wiring substrate includes a black resin layer and a conductive structure located in the black resin layer, wherein the black resin layer includes a first black resin layer and a second black resin layer, and the first black resin layer and the second black resin layer include carbon black; a plurality of micro light-emitting diode (LED) chips are disposed on the multilayer resin wiring substrate and electrically connected to the conductive structure; and a protective layer covers the micro LED chips, the micro LED chips including a first micro LED chip, a second micro LED chip and a third micro LED chip, wherein the first micro LED chip emits red light, the second micro LED chip emits green light and the third micro LED chip emits blue light.
2. The micro LED packaging structure of claim 1, wherein the conductive structure includes a first conductive layer, a first via conductor, a second conductive layer, and a second via conductor; wherein the first black resin layer covers the first conductive layer; the first via conductor passes through the first black resin layer and is electrically connected to the first conductive layer; the second conductive layer is disposed on the first black resin layer and is electrically connected to the first via conductor and the first conductive layer; the second black resin layer covers the second conductive layer; and the second via conductor passes through the second black resin layer and is electrically connected to the second conductive layer.
3. The miniature light-emitting diode packaging structure as described in claim 2, wherein, The second black resin layer has an upper surface, and the second through-hole conductor has a top surface exposed on the upper surface of the second black resin layer. The top surface of the second through-hole conductor and the upper surface of the second black resin layer are coplanar.
4. The miniature light-emitting diode packaging structure as described in claim 2, wherein, The second black resin layer has an upper surface, and the second through-hole conductor has a top surface exposed above the upper surface of the second black resin layer. The distance between the top surface of the second through-hole conductor and the upper surface of the second black resin layer is between 0 and 5 micrometers.
5. The miniature light-emitting diode packaging structure as described in claim 2, wherein, The second black resin layer has an upper surface, and the area ratio of the upper surface of the second black resin layer to the upper surface of the multilayer resin wiring substrate is 93% to 97%.
6. The miniature light-emitting diode packaging structure as described in claim 5, wherein, The second via conductor has a top surface exposed on the upper surface of the second black resin layer, and the ratio of the total area of the top surface of the second via conductor to the area of the upper surface of the multilayer resin wiring substrate is between 3% and 6%.
7. The miniature light-emitting diode packaging structure as described in claim 6, wherein, These micro-light-emitting diode chips have an upper surface, and the ratio of the total area of the upper surface of these micro-light-emitting diode chips to the area of the upper surface of the multilayer resin wiring substrate is 1% to 6%.
8. The micro light-emitting diode packaging structure of claim 7, wherein the first black resin layer has a first black resin layer side surface, the second black resin layer has a second black resin layer side surface, and the first black resin layer side surface and the second black resin layer side surface are coplanar.
9. The micro light-emitting diode encapsulation structure as claimed in claim 1, wherein the black resin layer comprises thermoplastic resin and thermosetting resin.