Method for predicting parasitics in designed analogue circuits

Abstract

This invention discloses an analog circuit design apparatus comprising a primary design unit and a plurality of secondary design units. The primary design unit is constructed as follows: receiving information representing the technical requirements of an analog circuit; identifying, based on the received information, a plurality of circuit portions forming the analog circuit; determining, for each of the plurality of circuit portions, the respective technical specifications of that circuit portion; generating a set of designs, including the respective designs of each circuit portion; for at least one circuit portion of the plurality of circuit portions, if the analog circuit will include the designed circuit portion, obtaining information related to parasitic effects that will be experienced in the analog circuit; rewriting the design of at least one circuit portion based on the obtained information about parasitic effects; and outputting a completed circuit design including at least one circuit portion, which was rewritten based on the obtained information about parasitic effects.

Description

Technical Field

[0001] The present disclosure relates to methods and systems for analog circuit design, and more particularly to methods and systems for the automated design process of analog circuits. Prior Art

[0002] Analog components cause most of the failures in wafer production testing and account for up to 95% of the demagnetization. Although the circuit design of digital circuits has become automated to some extent recently, the automation of analog circuit design has proven to be problematic, not only due to parasitic effects, for example. Traditional analog circuit design methods may involve "best guess" estimates or specification guard bands manually performed by an engineering team depending on prior knowledge and experience, often resulting in over-designed and inefficient circuits, or circuits prone to failure. Therefore, there is a need to establish a more effective and reliable process for designing analog circuits. Summary of the Invention

[0003] Aspects of the present invention are as set forth in the independent claims, and the optional features are as set forth in the dependent claims. Aspects of the present invention can be combined with each other, and the features of one aspect can be applied to other aspects.

[0004] In a first aspect, there is provided an analog circuit design device. The device includes at least one design unit configured to: Receive information representing the technical requirements of an analog circuit; Based on the received information, identify a plurality of circuit portions forming the analog circuit; For each of the plurality of circuit portions, determine the respective technical criteria of the circuit portion; Generate a set of designs, including the respective designs of each circuit portion; For at least one of the plurality of circuit portions, if the analog circuit is to include the designed circuit portion, obtain information related to the parasitic effects that will be experienced in the analog circuit; Rewrite the design of at least one circuit portion based on the obtained information regarding parasitic effects; and Output a completed circuit design including at least one circuit portion, the circuit design being rewritten based on the obtained information regarding parasitic effects.

[0005] It will be understood that obtaining information regarding parasitic effects may include extracting information regarding parasitic effects.

[0006] Advantageously, this design device allows the parasitic effects to be estimated and considered as part of the initial design process, which was previously very difficult to achieve for analog circuits. Furthermore, the analog circuit design device can automatically design an analog circuit to meet the customer requirements for machine learning implementation. Therefore, the designer does not need to manually (re)design the analog circuit.

[0007] In some examples, information related to the context of components or parts of a circuit can be obtained and used as part of the design process - in other words, what will be experienced when the components or parts of the circuit are placed in situ in the completed circuit (in some examples, the context can be provided as part of the technical criteria, although in other examples, it can be provided as some part outside the technical criteria). This context can include the parameters and variables that the parts or components of the circuit will experience during use. The context for any given circuit part or component can be generated based on simulating the performance of the circuit parts or components that interact with the given circuit part or component, or even by simulating the completed circuit that includes the given circuit part or component. For example, at least one design unit can be configured to produce at least one respective design of a corresponding circuit part based on the context of at least one other circuit part.

[0008] It will be understood that the analog circuit design device can include a primary design unit and a plurality of secondary design units. The primary design unit can be configured to: Based on the received information, identify a plurality of circuit parts that form an analog circuit; For each circuit part of the plurality of circuit parts, determine the respective technical criteria for that circuit part; and Provide the respective technical criteria for each circuit part to at least one of the plurality of secondary design units.

[0009] Each of the plurality of secondary design units of the analog circuit design device can be configured to: a) Design the respective circuit parts of the plurality of circuit parts based on the technical criteria provided by the primary design unit; and b) Output the resulting design of the respective circuit parts.

[0010] The primary design unit can further be configured to: c) Obtain a set of designs that includes the respective designs of each circuit part from each of the plurality of secondary design units; d) Generate at least one initial design of the analog circuit based on this set of designs; e) If the analog circuit is to include the circuit part, obtain information related to the parasitic effects that will be experienced in the analog circuit.

[0011] At least one of the secondary design units can be configured to rewrite the design of its respective circuit part based on information related to parasitic effects; and The primary design unit can be configured to output a completed circuit design including at least one rewritten circuit part.

[0012] In some examples, the analog circuit design unit is configured to populate the database of parasitic effects and circuit design by repeating steps a) to e) a plurality of times, where each time steps a) to e) are repeated, new technical criteria are provided by the primary design unit. The analog circuit design unit can be configured to repeat steps a) to e) for predefined circuit parts or components that match the identified or selected circuit structure, and / or for known or selected structural or functional blocks (such as DACs, level shifters, comparators, etc.). The predefined circuit parts can be sensitive to variations. For example, the bridge capacitors on a DAC depend on the total capacitance to the input stage of the comparator, which includes the input device and any parasitic capacitance of the wiring.

[0013] The analog circuit design device can be configured to obtain information related to the parasitic effects that would be experienced in the analog circuit if the analog circuit were to include the designed circuit part by mathematically simulating (i) the designed circuit and (ii) the performance of at least one of the completed analog circuits including the designed circuit part in a virtual test bench.

[0014] Additionally or alternatively, the design device can be configured to obtain information related to the parasitic effects that would be experienced in the analog circuit if the analog circuit were to include the designed circuit part by performing a lookup in the database of circuit design and parasitic effects. For example, the parasitic effects can be looked up from the database of individual circuit elements (parts of the circuit) using various terms including but not limited to configuration, process, topology, and any other dimensional factors.

[0015] Additionally or alternatively, the analog circuit design device can be configured to obtain information related to the parasitic effects experienced by the generated design by performing a lookup in the database of circuit design and parasitic effects for similar generated designs. It will be understood that the similar generated designs can include designs having a selected critical level greater than the similarity, for example, a selected critical level greater than the common features.

[0016] Additionally or alternatively, the design device is configured to perform a lookup in a database of circuit designs and parasitic effects for at least one of the respective circuit portions for similar respective circuit portions, and wherein the design device is configured to obtain information regarding the parasitic effects experienced by the generated design based on the values of the parasitic effects obtained via the lookup of at least one of the respective circuit portions.

[0017] In some examples, the design device is configured to obtain information regarding the parasitic effects experienced by the generated design by using a machine learning model to predict the parasitic effects. Additionally or alternatively, the design device may be configured to use a machine learning model to predict the parasitic effects and obtain information regarding the parasitic effects experienced by each respective circuit portion. In some examples, the machine learning model may have been trained using the design device.

[0018] It will be understood that the parasitic effects include at least one of parasitic capacitance, parasitic resistance, and parasitic inductance.

[0019] In some examples, the analog circuit design device is configured to rewrite the design of its respective circuit portions in the case where information regarding the parasitic effects experienced by the generated design indicates that such parasitic effects are greater than a selected critical level of the parasitic effects. In some examples, the technical criteria may specify an acceptable critical level of the parasitic effects. In such examples, the information regarding the parasitic effects experienced by the generated design may indicate that the circuit (and / or portions of the circuit) no longer meets the technical criteria. In such examples, rewriting the design of the respective portions based on the information regarding the parasitic effects may include rewriting the technical criteria, such as rewriting the technical criteria of at least one respective circuit portion.

[0020] In another aspect, there is provided a method for training a machine learning model useful for predicting parasitic effects in a designed analog circuit. The method includes: At each of a plurality of secondary design units of an analog circuit design device: a) Designing respective circuit portions of a plurality of circuit portions based on technical criteria provided by a primary design unit; and b) Outputting the resulting design of the respective circuit portions; and At the primary design unit of the analog circuit design device: c) Obtaining a set of designs including the respective designs of each circuit portion from at least one of the plurality of secondary design units; d) Generating at least one initial design of the analog circuit based on the set of designs; e) Obtaining information related to parasitic effects experienced by at least one of the circuit portion and the generated design by mathematically simulating the performance of the generated design using a virtual test bench; and Repeating steps a) to e) a plurality of times, wherein each time steps a) to e) are repeated, new technical criteria are provided by a primary design unit.

[0021] It will be understood that in some examples, step d) is optional and information related to the parasitic effects of the circuit portion can be obtained before generating the initial design of the analog circuit. It will also be understood that obtaining information related to the parasitic effects may include extracting information related to the parasitic effects.

[0022] In some examples, this method may further include step f) populating a database with parasitic effects and corresponding circuit designs. This step can be repeated when steps a) to e) are repeated. Then, the database can be used to train a machine learning model (such as a neural network, a convolutional neural network, or a deep learning module) to estimate the parasitic effects of a circuit design (such as a circuit design not included in the database). This neural network may include at least one of a deep residual network (ResNet), a highway network, a dense connection network (DenseNet), and a capsule network.

[0023] In another aspect, there is provided a method for designing an analog circuit. This method includes: Receiving information representing the technical requirements of the analog circuit; Based on the received information, identifying a plurality of circuit portions forming the analog circuit; For each circuit portion of the plurality of circuit portions, determining the respective technical criteria of the circuit portion; Generating a set of designs each including the respective design of each circuit portion; For at least one circuit portion of the plurality of circuit portions, obtaining information related to the parasitic effects that the circuit portion and / or the analog circuit will experience if the analog circuit is to include the designed circuit portion; Rewriting the design of at least one circuit portion based on the obtained information related to the parasitic effects; and Outputting a completed circuit design including at least one circuit portion rewritten based on obtaining information related to the parasitic effects.

[0024] This method may further include, at a primary design unit of an analog circuit design device: Based on the received information, identifying a plurality of circuit portions for forming the analog circuit; For each of a plurality of circuit portions, determine respective technical criteria for the circuit portion, and Provide the respective technical criteria for each circuit portion to at least one of a plurality of secondary design units.

[0025] This method may further include, at each of a plurality of secondary design units of an analog circuit design device: a) Design respective circuit portions of the plurality of circuit portions based on the technical criteria provided by a primary design unit; and b) Output the resulting design of the respective circuit portions; and This method may further include, at the primary design unit: c) Obtain a set of designs including the respective designs for each circuit portion from each of the plurality of secondary design units; d) Generate at least one initial design for the analog circuit based on this set of designs; e) If the analog circuit is to include the circuit portion, obtain information related to parasitic effects that will be experienced in the analog circuit.

[0026] It will be understood that obtaining information related to parasitic effects may include extracting information related to parasitic effects.

[0027] This method may further include: At at least one of the secondary design units, rewrite the design of its respective circuit portion based on the information related to parasitic effects; and At the primary design unit, output a completed circuit design including at least one rewritten circuit portion.

[0028] This method may include populating a database of parasitic effects and circuit designs by repeating steps a) to e) a plurality of times, where each time steps a) to e) are repeated, new technical criteria are provided by the primary design unit. This method may include repeating steps a) to e) for pre-defined circuit portions or components that match the identified or selected circuit structure, and / or for known or selected structural or functional blocks (e.g., DACs, level shifters, comparators, etc.). The pre-defined circuit portions may be sensitive to variations. For example, the bridge capping on a DAC depends on the total capacitance to the comparator input stage, which includes the input device and any wiring parasitic capacitance.

[0029] In some examples, this method includes obtaining information related to parasitic effects that will be experienced in the analog circuit by mathematically simulating the performance of the generated design in a virtual test bench if the analog circuit is to include the designed circuit portion.

[0030] Additionally or alternatively, the method may include obtaining information related to the parasitic effects to be experienced in the analog circuit by performing a lookup in a database of circuit designs and parasitic effects if the analog circuit is to include the designed circuit portion.

[0031] Additionally or alternatively, the method may include obtaining information related to the parasitic effects to be experienced in the analog circuit by performing a lookup in a database of circuit designs and parasitic effects for designs used in similarity generation if the analog circuit is to include the designed circuit portion. It will be understood that the designs used in similarity generation may include designs having a selected threshold level of similarity greater than, for example, a selected threshold level of common features.

[0032] Additionally or alternatively, the method may include, if the analog circuit is to include the designed circuit portion, performing a lookup in a database of circuit designs and parasitic effects for at least one of the respective circuit portions that are similar, based on the values of the parasitic effects obtained via a lookup of at least one of the respective circuit portions, and obtaining information related to the parasitic effects to be experienced in the analog circuit.

[0033] Additionally or alternatively, the method may include obtaining information related to the parasitic effects to be experienced in the analog circuit by using a machine learning model to predict the parasitic effects if the analog circuit is to include the designed circuit portion. Additionally or alternatively, the method may include using a machine learning model to predict the parasitic effects and obtaining information related to the parasitic effects experienced by each respective circuit portion. In some examples, the machine learning model may have been trained using this design device.

[0034] It will be understood that the parasitic effects include at least one of parasitic capacitance, parasitic resistance, and parasitic inductance.

[0035] In some examples, in the case where the information related to the parasitic effects indicates that these parasitic effects are greater than a selected threshold level of parasitic effects, the design of its respective circuit portion is rewritten. In some examples, the technical criteria may specify an acceptable threshold level of parasitic effects. In such examples, the information related to the parasitic effects experienced by the generated design may indicate that the circuit (and / or many parts of the circuit) no longer meets the technical criteria. In such examples, rewriting the design of the respective portion based on the information related to the parasitic effects may include rewriting the technical criteria, such as rewriting the technical criteria of at least one respective circuit portion.

[0036] In some examples, rewriting the design of respective parts based on information related to parasitic effects includes rewriting the corresponding technical criteria of respective circuit parts.

[0037] It will be understood that this method may further include manufacturing an analog circuit for the output design.

[0038] In another aspect, there is provided a computer-readable non-transitory storage medium including a program for a computer, the computer being configured to cause a processor to execute any of the above methods. Brief Description of the Drawings

[0039] Embodiments of the present disclosure will now be described by way of example only with reference to the accompanying drawings, wherein:

[0040] FIG. 1A shows a functional schematic diagram of an example analog circuit;

[0041] FIG. 1B shows the functional schematic diagram of FIG. 1A divided into conceptual blocks;

[0042] FIG. 2 shows a functional schematic diagram of a computer-implemented hierarchical model for designing an analog circuit;

[0043] FIG. 3 shows a functional schematic diagram of another example implementation of a computer-implemented model for designing an analog circuit;

[0044] FIG. 4 shows a functional schematic flowchart of a method for designing an analog circuit using, for example, the example computer-implemented model of FIG. 2 or FIG. 3;

[0045] FIG. 5 shows a functional schematic flowchart of another example method for designing an analog circuit using, for example, the example computer-implemented model of FIG. 2 or FIG. 3;

[0046] FIG. 6A shows various parts of an analog circuit designed by a computer-implemented hierarchical model, such as the model described with reference to any one of FIGS. 1A to 5;

[0047] FIG. 6B shows an example of an analog circuit including the design of the circuit part of FIG. 6A; and

[0048] FIG. 7 shows a schematic diagram of an exemplary method for training a machine learning model to estimate or predict parasitic effects. Embodiments

[0049] Figure 1A shows a simplified functional schematic diagram of an exemplary analog electronic circuit, which in this example is an analog-to-digital converter (ADC) 1000. The analog circuit may include a number of parts or components, such as comparator 1001, DAC 1002, level shifter 1003, and OP-AMP 1004. Although each part or component may be considered initially separately, when this part or component is applied in situ to the circuit, the before-and-after relationship or environment in which it operates may affect how the component / block operates, and thus affect the parasitic effects experienced by the circuit part and the entire circuit. Due to the complex feedback loops and mathematical relationships involved between the different parts / components of the analog circuit, it has been previously proven difficult to automate the design of analog circuits.

[0050] Embodiments of the claims relate to methods and systems for automating the design of analog circuits, which methods and systems can predict or anticipate parasitic effects in the designed circuit or in many parts of the designed circuit, so that a more efficient circuit can be designed. In this case, the inventors have achieved this by developing a computer-implemented model that will be responsible for designing parts or components of the analog circuit for respective units or "blocks". An example of this model is shown in Figure 2. This hierarchical model involves using primary design units (referred to as "parent blocks" 900) that serve as control entities, and a number of secondary design units (referred to as "child blocks" 950a-d), where the secondary design units receive instructions from the primary design unit or parent block regarding what they need to design. Each secondary design unit or child block 950a-d is configured to design respective components or parts of the analog circuit based on the instructions received from the parent block 900. These instructions include the technical requirements ("criteria") of the components or parts that need to be satisfied (such as functional requirements).

[0051] The instructions may also include information related to the context of components or parts of the circuit, i.e., what the part or component of the circuit would experience when placed in situ in the completed circuit (in some examples, this context may be provided as part of the technical criteria, although in other examples, it may be provided as supplementary to the technical criteria). This context may include the parameters and variables that the part or component of the circuit would experience in use. The context of any given circuit part or component can be generated based on simulating the performance of the circuit part or component that interacts with the given circuit part or component, or even by simulating the completed circuit that includes the given circuit part or component. For example, the parent block 900 may be configured to assemble the completed circuit from the parts or components designed by each of the sub-blocks 950a-d and simulate the operation of the assembled circuit. Additionally or alternatively, the context of any given circuit part or component can be generated based on mathematical calculations or extraction.

[0052] By designing the analog circuit in this way, the parasitic effects that the respective circuit parts, or the circuit that includes a plurality of the respective circuit parts, will experience can be estimated (e.g., by the parent block 900), and if necessary, a rewritten circuit can be generated that can mitigate the parasitic effects.

[0053] The computer-implemented hierarchical model is iterative. Once the parent block 900 has instructed each of the sub-blocks 950a-d to design their respective parts, it is likely that a certain degree of redesign of the circuit and its respective parts will be required to account for the parasitic effects and / or optionally the context originating from the respective circuit parts designed by the other sub-blocks 950a-d.

[0054] In particular, once the circuit part has been designed or the initial design of the completed analog circuit has been made, due to the estimated parasitic effects that can be experienced by either the specific circuit part or the completed analog circuit, a redesign of either the circuit part and / or the completed analog circuit may be required. Therefore, the process of designing these circuit parts can be repeated to rewrite the design of more than one circuit part in an attempt to mitigate and reduce the estimated parasitic effects considered in them. The process of rewriting the design of the circuit parts can be iteratively repeated by the sub-blocks 950a-d, for example, until any changes in the estimated parasitic effects due to any adjustments to any other part or component of the analog circuit have been accounted for. For example, this process can be iteratively repeated until any change in the estimated parasitic effects is less than a selected critical level of change in the parasitic effects.

[0055] Parasitic effects of any given circuit part can be generated based on simulating the performance of a circuit part that interacts with the given circuit part, or even by simulating a completed circuit that includes the given circuit part. For example, the parent block 900 can be constructed to assemble a completed circuit from parts designed by each of the sub-blocks 950a-d and simulate the operation of the assembled circuit. Parasitic effects of any given circuit part can be additionally or alternatively generated based on mathematical calculations or selections. Additionally or alternatively, parasitic effects of any given circuit part can be obtained by performing a lookup in a database of circuit designs and parasitic effects and / or predicted using a machine learning model.

[0056] The inventors have found it advantageous that such an iterative hierarchical model allows for the automation of the design of analog circuits. As a result, advantageously, this means that over-designed analog circuits and / or circuits with unacceptable parasitic effects can be avoided, and instead more efficient circuits can be designed and created.

[0057] As stated above, FIG. 1A shows an exemplary analog circuit 1000 that is an analog-to-digital converter (ADC) in this example. Conceptually, for example, based on their respective functionality, circuits can be divided into functional blocks corresponding to different parts or components of the circuit. For example, the ADC can include a comparator 1001, a digital-to-analog converter (DAC) 1002, a multi-bit level shifter 1003, and more than one OP-AMP 1004. In the example shown in FIG. 1A, the circuit can be conceptually divided into blocks corresponding to these different parts or components. For example, as shown in FIG. 1B, the comparator can be conceptually divided into a first "sub-block" 950a, the DAC into a second sub-block 950b, the level shifter into a third sub-block 950c, and the OP-AMP into a fourth sub-block 950d. The ADC as a whole can be conceptually classified as its own block (labeled "parent block" 900 in FIG. 1B). It will be understood that the ADC itself can form a conceptual block within a larger analog circuit.

[0058] As stated above, in in-situ use, there are interactions between each different block of the analog circuit. The in-situ interactions between these blocks (which can include the parasitic effects experienced by their respective parts when placed in the completed circuit), and thus the parameters and variables experienced by each block when placed in the circuit, affect the performance of the circuit. For example, the specifications of the OP-AMP used in the circuit can depend on many parameters and variables caused by the selection and design of the comparator, DAC, and / or level shifter, and the connections between them.

[0059] The inventors have recognized that the design and selection of each circuit part should thus be carried out in a way that takes into account the parasitic effects experienced by the completed circuit and / or the respective circuit parts (optionally and the interactions caused by the context of each respective circuit part), thereby designing a completed analog circuit with minimal parasitic effects.

[0060] A non - exhaustive list of examples of parameters and variables that can affect the selection and design of these different blocks includes: silicon process, temperature range, output load, output impedance, input capacitance, input common - mode range, input differential swing, supply voltage, type of available transistors, output common - mode range, output swing, settling time, noise tolerance; power supply rejection ratio (PSRR); common - mode range - input (Intput CMR); common - mode range - output (Output CMR); linearity; maximum offset; bandwidth; minimum slew rate; intrinsic delay; minimum phase margin; dynamic power consumption; static power consumption; IP3 point; filter center frequency; filter band - pass range; load step response; line step response; output accuracy; noise figure; calibration range; noise floor; SNR; ENOB; SINAD; output frequency range; jitter - ptp; jitter - RMS; output ripple ptp; total harmonic distortion; startup time; channel isolation; reference voltage; gain error; offset error; gain drift. These parameters and variables can be referred to as the "context" or environment in which the block is located. To create the best analog circuit, understanding this context can improve the design of the circuit.

[0061] However, it will of course be understood that the design of an analog circuit is an iterative process, whereby the selection and adjustment of one block can affect the context of another block and so on. Thus, once the components of one block have been selected / adjusted to form a circuit part, it may be necessary to adjust or re - select the components of another block to take into account the parasitic effects experienced by the completed circuit / circuit part and / or optionally the new context in which the block is located. This iterative process is impractical, error - prone, and can only be detected through communication for manual execution.

[0062] As stated above, a exemplary computer - implemented model used in a method for automating the design of an analog circuit is shown in FIG. 2. FIG. 2 schematically shows the blocks shown in FIG. 1B and the interactions between the blocks, which were discussed above.

[0063] In the example shown in FIG. 2, each block of the model is responsible for designing the component / functionality indicated by that block. In FIG. 2, sub-block 1 950a is responsible for designing comparator 1001, sub-block 2 950b is responsible for designing DAC 1002, sub-block 3 950c is responsible for designing level shifter 1003, and sub-block 4 950d is responsible for designing OP-AMP 1004. Parent block 900 is responsible for overall design of ADC 1000 and delegates portions / components / functionality of the design of the ADC to sub-blocks 950a-d. In some examples, parent block 900 may select how many sub-blocks 950a-d are needed and attribute responsibilities to each block. Although sub-blocks 950a-d are shown in sequence, it should be understood that this sequence does not necessarily represent the order in which the various parts of the circuit are designed. For example, parent block 900 may instruct sub-block 950d, which is responsible for the OP-AMP, to design that portion of the circuit. In some examples, sub-blocks 950a-d may be constructed to first design the output and work backward from there.

[0064] Although each respective circuit part may initially be designed individually by its corresponding respective block, when each respective circuit part is applied in situ as a whole to the circuit, operating each respective circuit part can affect how both the respective circuit part and the entire circuit operate. This operation will also include parasitic effects that the entire circuit will experience when in use. Thus, although the parent block may instruct each sub-block to design their respective portions, once the initial version of the designed circuit is assembled from the portions or components designed by each sub-block 950a-d by parent block 900, it is likely that a certain degree of rewriting or even redesign of circuit 1000 and its portions or components will be needed to account for the final parasitic effects and optional relationships created by the portions designed by the other sub-blocks 950a-d. As stated above, this will be an iterative process.

[0065] Thus, parent block 900 is constructed to serve as a controller that processes and manipulates the design processes performed by each sub-block. To perform this function, as shown in FIG. 2, parent block 900 may include a number of different modules, each constructed to perform a different function as part of the design process. The parent block in FIG. 2 includes an indication module 901, an assembly module 902, and a verification and simulator module 903.

[0066] The indication module 901 is configured to receive customer requirements for the circuit to be designed, along with other requirements such as those indicated by the foundry, such as PDK / conditions / control parameters, and is configured to convert these into a series or set of technical criteria that each sub-block 950a-d needs to meet when designing their respective components of the circuit. It is also configured to prepare and send instructions on what they need to design and what criteria they need to meet in doing so to each sub-block 950a-d. The instructions may also include the context of other design parts of the circuit designed by other sub-blocks, and the broader context of the circuit in which the components or parts of this circuit are intended to operate. For example, the technical criteria may be adjusted taking into account the context.

[0067] The assembly module 902 is configured to receive and process all the respective design parts or components of the analog circuit provided by each sub-block 950a-d, and is configured to assemble the completed analog circuit based on the respective design parts or components. Then, the completed analog circuit can be tested by the verification and simulator module 903.

[0068] The verification and simulator module 903 is configured to receive the designed components from each sub-block and compare these with the technical set of requirements to determine whether the designed part or component is satisfactory. This may include, for example, comparing their performance with the customer requirements by verifying whether the respective designed circuit parts or components meet their corresponding technical criteria and / or whether the designed analog circuit meets the customer requirements. It can additionally or alternatively include a sanity check to determine whether the designed circuit is valid in the sense that it can operate within certain technical limitations.

[0069] The verification and emulator module 903 is also configured to act as a "test bench" and simulate the operation of the assembled components of this circuit. This simulation can generate parasitic information, as well as optional context information. For example, the verification and emulator module 903 can be configured to, if the analog circuit is to include the designed circuit portion, obtain information related to the parasitic effects that will be experienced in the analog circuit by mathematically simulating (i) the designed circuit portion and (ii) the performance of at least one of the completed analog circuits including the designed circuit portion in a virtual test bench. Additionally or alternatively, the verification and emulator module 903 can be configured to, if the analog circuit will include the designed circuit portion, obtain information related to the parasitic effects that will be experienced in the analog circuit by performing a lookup in a database of circuit designs and parasitic effects, such as by performing a lookup in a database of circuit designs and parasitic effects for similar generated designs. Additionally or alternatively, the verification and emulator module 903 can be configured to perform a lookup in a database of circuit designs and parasitic effects for at least one of the respective circuit portions for similar respective circuit portions, and obtain information related to the parasitic effects experienced by the generated design based on the values of the parasitic effects obtained via the lookup of at least one of the respective circuit portions. In other examples, the verification and emulator module 903 is configured to obtain information related to the parasitic effects experienced by the generated design by using a machine learning model to predict the parasitic effects.

[0070] The verification and emulator module 903 can be configured to populate a database of parasitic effects and circuit designs, for example, if the indication module 901 instructs the sub-blocks 950a-d to repeatedly design the process of the circuit portion a plurality of times based on (new or rewritten) corresponding technical criteria.

[0071] The verification and emulator module 903 can additionally compare the simulation function of the circuit with customer requirements, and optionally verify whether the designed circuit portion meets its corresponding technical criteria and / or whether the designed analog circuit meets customer requirements. In some examples, it will be understood that the emulator module can replace the verification module 903.

[0072] Each sub-block 950a-d also includes a number of different modules, each module configured to perform a different function as part of the design process. In the example shown in FIG. 2, each sub-block 950a-d includes converter modules 951a-d, assembly modules 952a-d, and simulator modules 953a-d. It will be understood that in some examples, each sub-block 950a-d may further include additional modules for indicating a third-level design unit or "grandchild" block, similar to the way the parent block 900 in FIG. 2 includes modules such as an indication module and a verification module for indicating and verifying the design process by the sub-blocks 950a-d, as will be described in more detail below with reference to FIGS. 3 to 6.

[0073] The converter modules 951a-d of each sub-block 950a-d are configured to receive the technical criteria received by the parent block 900, and optionally receive the context of the circuit as a whole, as well as the context of other components of the circuit, and convert these into a set of requirements for designing a part or component of an analog circuit to meet these criteria. It will be understood that in some examples, this context information may be provided and received as part of the technical criteria, but in other examples, the context information may be provided by additional technical criteria (e.g., separate).

[0074] The assembly modules 952a-d are configured to select and / or design electronic components to meet the desired requirements, which requirements meet the criteria indicated by the context of the parent block and the circuit as a whole and / or the context of other components of the circuit.

[0075] The simulator modules 953a-d may also be configured to simulate how those components will operate in situ to check / verify whether the designed part or component designed by the assembly module is technically feasible. In some examples, the simulator modules 953a-d may also obtain information related to the parasitic effects of the respective circuit portions designed for their blocks, and in a manner similar to the verification and simulator modules 903 of the parent block 900 described above (it will be understood that in such examples, the verification and simulator modules 903 of the parent block 900 may not need to obtain information related to parasitic effects, as this may already have been performed by the simulator modules 953a-d of each sub-block 950a-d).

[0076] In use, the parent block 900 receives a set of requirements for an analog circuit 1000 to be designed. In the example shown in FIG. 2, the parent block 900 receives a set of requirements for an ADC to be designed, the ADC having certain characteristics, including, for example, characteristics specified by the foundry that will manufacture the ADC. The parent block 900 receives these requirements and instructs the module 901 to convert these into a set of technical criteria. These technical criteria are then sent to each of the sub-blocks 950a-d.

[0077] The instruction module 901 can send these technical criteria to each of the sub-blocks 950a-d in parallel (i.e., all at the same time) or serially (e.g., sending the criteria to sub-block 1, then sub-block 2, then sub-block 3, etc.). In some examples, the instruction module 901 can wait until the designed circuit is received from the first sub before sending a set of technical criteria to the next sub, and in some examples, the instruction module can be configured to adjust the technical criteria sent to the next sub based on the designed circuit received by the previous sub - namely, based on the context of the designed circuit received by the previous sub.

[0078] In an example where the technical criteria are sent serially to the sub-blocks 950a-d, the technical criteria can include means for distinguishing which parts of the technical criteria are relevant to which sub-blocks 950a-d - for example, the technical criteria can include headers or flags that identify whether a particular part of the technical criteria is relevant to the sub-blocks 950a-d. These headers or flags can be determined by the parent block 900 and thus the technical criteria are adjusted to incorporate them.

[0079] Each of the sub-blocks 950a-d receives these technical criteria from the parent block 900, and each respective converter module 951a-d converts these into a set of requirements for designing a part or component of the analog circuit to meet those technical criteria. The assembly modules 952a-d receive these requirements and design the components / parts of the circuit that meet these requirements. It will be understood that this design process can include looking up in a database of known circuit designs (or many parts thereof) and finding the circuit design that best matches these technical criteria.

[0080] Then, the simulator modules 953a-d simulate how these components / parts of the circuit will work in situ to check whether the designed components / parts of the circuit designed by assembling the modules are technically feasible and / or verify whether the respective circuit parts of the corresponding design meet their corresponding technical criteria. If the designed circuit part meets its corresponding technical criteria, the sub-blocks 950a-d then construct to send or output the designed part or component of the circuit to the parent block 900. If the designed circuit part does not meet its corresponding technical criteria, then the sub-blocks 950a-d are constructed to rewrite the design of its circuit part and repeat this process.

[0081] Once the parent block 900 receives back all the designed parts or components of this circuit from all the sub-blocks 950a-d, the assembly module 902 of the parent block 900 then assembles the completed circuit (in this case, the ADC) from the parts or components designed by each sub-block, and verifies whether the designed circuit meets the technical requirements via the verification and simulator module 903. This can be done by simulating how the assembled circuit performs and comparing this simulated performance with the customer requirements and / or technical requirements. It will be understood that in some examples, this simulated performance of the completed analog circuit design can be used to obtain parasitic effects and / or optional context information (e.g., for another design unit), and the parent block 900 can adjust the technical criteria based on the parasitic effects and / or optional context information obtained via the simulation of the completed analog circuit design.

[0082] If the simulated performance of the designed circuit does not meet the customer requirements or technical requirements (e.g., the parameters of the simulated circuit are greater than a critical level different from the parameters specified by the technical requirements, e.g., the parasitic effect is higher than the critical level of the parasitic effect), then the verification module 903 passes it to the indication module 901. The indication module 901 can then adjust the technical criteria based on the difference between the simulated performance of the circuit and the technical requirements, and send these revised technical criteria back to the sub-blocks 950a-d.

[0083] In some examples, the parent block 900 (e.g., the verification module 903 / indication module 901) can be configured to determine which part or component of the circuit is responsible for the circuit not meeting the technical requirements (e.g., which part is responsible for a large part of the parasitic effects), and in the case where the sub-blocks 950a-d can be identified, the parent block 900 can be configured to send the revised technical criteria only to the sub-block responsible for the damaged part or component of this circuit. However, in other examples, the revised criteria can be sent back to all sub-blocks 950a-d. It will also be understood that in some examples, the parent block 900 can determine that additional and / or alternative sub-blocks 950a-d and / or grandchild blocks may be required to design the relevant part or component of the circuit, e.g., to meet the revised technical criteria.

[0084] Then, this process continues in an iterative manner, where the converter modules 951a-d of each sub-block 950a-d receive these revised or rewritten technical criteria from the parent block 900 and convert them into a new set of requirements for designing parts or components of the analog circuit to meet one of those rewritten technical criteria. The assembly modules 952a-d receive these new requirements and design the components / parts of the circuit that meet these requirements. Then, the simulator modules 953a-d simulate how the redesigned components / parts of the circuit will work in situ to check whether the designed components / parts of the circuit designed by the assembly module are technically feasible. Then, the sub-blocks 950a-d are configured to send the (re)designed components / parts of the circuit back to the parent block 900.

[0085] Once the parent block 900 receives back all the (re)designed components / parts of the circuit from all the sub-blocks 950a-d, the parent block 900 then assembles the completed circuit (in this case, the ADC) from the components / parts designed by each sub-block and verifies via the verification and simulator module 903 whether the designed circuit meets the technical requirements. This module 903 can simulate how the assembled circuit will perform and compare this simulated performance with the technical requirements. If the simulated performance does not meet the technical requirements, this process is repeated, whereby a revised set of criteria is sent back to the sub-blocks 950a-d. In some examples, the parent 900 (e.g., the verification and simulator module 903) can populate a database with the designed circuit / circuit part and its simulated parasitic effects, e.g., for use in training a machine learning model or for use in future estimation of parasitic effects.

[0086] It will be understood that sub-blocks 950a-d and / or parent block 900 may also include a loop mitigation module to stop the occurrence of an endless redesign loop. For example, the loop mitigation module can be configured to have a record of a previously designed circuit, and if the circuit or a component / portion of the redesigned completed circuit is exactly the same as the component / portion of the previously designed circuit or completed circuit, then output a loop indication, or only the difference from the component / portion of the previously designed circuit or completed circuit is less than a selected difference threshold level. For example, parent block 900 can include a loop mitigation module and can be configured to end this design process and receive the last designed circuit as the completed circuit in the case where the loop mitigation module provides this loop indication. Additionally or alternatively, for example, if this design process is repeated for a selected number of iterations, then parent block 900 can be configured to reduce the difference threshold level of the selected difference. This can have the effect of finding an "optimal compromise" working circuit that meets the technical requirements.

[0087] FIG. 3 illustrates a functional schematic diagram of another exemplary implementation of a computer-implemented model for designing an analog circuit. The implementation of this model is similar to the model shown in FIG. 2 in many aspects, and the functionality described above with respect to parent block 900 and sub-block 950d in FIG. 2 can be attributed to the parent block and sub-blocks in FIG. 3. Additionally, some of the functionality described with respect to the primary design unit or parent block 900 in FIG. 2 can be attributed to the secondary design unit or sub-blocks 950a-d in FIG. 3, where this sub-block has a tertiary design unit or a "grandchild" block etc. below it.

[0088] More specifically, as shown in FIG. 3, the model hierarchical structure includes a core design layer that includes a primary design unit or parent block. Although only one parent block 900 is shown in the core design layer in FIG. 3, it will be understood that in some examples, there may be more than one parent block 900, for example, where each parent block 900 operates in parallel. For example, each parent block 900 can be configured to design different aspects of an analog circuit (e.g., different from each other in functionality and / or structure).

[0089] Below the core design layer is the first design layer. The first design layer includes secondary design units or sub-blocks 950 that are coupled to the parent block 900 of the upper layer (in this case, the core design layer). In the illustrated example, there are six sub-blocks, and all sub-blocks are coupled to the parent block of the core design layer. Sub-blocks 950 are divided into two different groups: the first group includes sub-blocks 1, 2, and 3; and the second group includes sub-blocks 3, 4, and 5. Each sub-block 950 is coupled to parent block 900. These two groups can represent different functional regions or areas of the analog circuit that the parent block 900 indicates for parallel design.

[0090] In the illustrated example, the sub-blocks 950 of the first group are coupled in parallel to the parent block 900 of the core design layer, and the sub-blocks 950 of the second group are coupled in parallel to the parent block 900 of the core design layer. The sub-blocks 950 can be grouped in this way to design different regions or aspects of the analog circuit (e.g., different from each other functionally and / or structurally). However, it will be understood that in some examples, not all of the sub-blocks 950 of the first design layer need to be coupled in parallel to the parent block of the core design layer. For example, sub-blocks 1 and 3 of the first design layer can be coupled to the parent block 900 of the core design layer, and sub-block 2 of the first design layer can be coupled in series to sub-blocks 1 and 3 of the first design layer, respectively.

[0091] The grouping of the sub-blocks 950 can be determined by the parent block 900 of the core design layer. For example, the parent block 900 can be configured to group the sub-blocks of the first design layer in order to design different aspects of the analog circuit (e.g., different from each other functionally and / or structurally). The parent block 900 of the core design layer can be configured to do this based on a decision of requirements from the customer specifications.

[0092] Below the first design layer is the second design layer. The second design layer includes three-level design units or grandchild blocks 1, 2, 3, 4, 5, 6, 7, and 8 960. The grandchild blocks 960 are coupled to the sub-blocks of the upper layer (the first design layer). Not every sub-block of the first design layer is coupled to the grandchild blocks of the second design layer. In the illustrated example, the grandchild blocks 1, 2, and 3 of the second design layer are coupled in parallel to the sub-block 2 of the first design layer. However, as described above for the sub-blocks 950 of the first design layer, it will be understood that in some examples, not all of the grandchild blocks of the second design layer need to be coupled in parallel to the sub-blocks of the first design layer. For example, the grandchild blocks 1 and 3 of the second design layer can be coupled to the sub-block 2 of the first design layer, and the grandchild block 2 of the second design layer can be coupled in series to the grandchild blocks 1 and 3 of the second design layer, respectively.

[0093] Below the second design layer is another (nth) design layer. The nth design layer includes great-grandchild blocks 1, 2, 3, and 4 970. The great-grandchild blocks 970 are coupled to the grandchild blocks 960 of the upper layer (the second design layer) in almost the same way as the grandchild blocks 960 of the second design layer are coupled to the sub-blocks 950 of the first design layer. Thus, it will be understood that there can be a plurality of additional design layers below the second design layer, and each additional design layer includes its own blocks that are coupled to the blocks of its upper layer.

[0094] The block hierarchical structure shown in FIG. 3 enables blocks of different layers of the model to be constructed to design aspects or parts of the analog circuit with different levels of complexity. For example, the parent block 900 can be constructed to design a completed analog circuit, the child block 950 is constructed to design functional components of the analog circuit (such as op-amps, AC / DC converters, level shifters, comparators, voltage regulators, power switches, etc.), and the grandchild block 960 is constructed to design the various components of the functional component (such as the configuration of resistors, transistors, capacitors, diodes, inductors, etc. for the component). However, it will be understood that the grandchild block 960 can be constructed to design more hierarchical blocks, such as operational amplifiers or voltage references or comparators, etc.

[0095] (The parent block 900 of the core design layer) can be constructed to determine the level of complexity of the block construction of the selected layer for design, and / or the blocks of one layer can be constructed to determine the level of complexity of the block construction of the underlying layer for design.

[0096] Additionally or alternatively, the block hierarchical structure shown in FIG. 3 enables blocks of different layers of the model to be constructed to design aspects or parts of the analog circuit based on different functional or structural requirements. For example, one layer can include blocks constructed to design aspects or parts of the analog circuit based on a functional requirement (such as size), and another layer can include blocks constructed to design another functional requirement (such as current or voltage).

[0097] FIG. 4 shows a functional schematic flowchart of a method for designing an analog circuit using, for example, the hierarchical model implemented by the exemplary computer of FIG. 2 or FIG. 3.

[0098] More specifically, in step 300, the parent block 900 receives customer requirements. For example, the customer requirements can define the functionality of the circuit and certain limitations required by it - such as peak current, voltage, etc. The customer requirements can also specify other features, such as the PDK / foundry by which the circuit will be manufactured. The parent block 900 is constructed to convert 302 the customer requirements into a set of technical guidelines. The parent block 900 can additionally or alternatively be constructed to determine whether to send these technical guidelines in parallel or in series to the child block 950, and / or whether to send different sets of guidelines to the child block 950 of the next layer.

[0099] At this stage, the parent block 900 can also be constructed to determine the number of layers of the model, or alternatively, the blocks of each layer can be constructed to determine whether blocks of the underlying layer are needed when designing various parts of the circuit, and the tasks of various parts of the circuit are designed by the blocks in the upper layer.

[0100] Once the parent block 900 has converted 302 the customer requirements into criteria, it then sends 304 these to the child blocks of the first layer. In the example shown, the parent block 900 sends 304 the technical criteria in parallel to Child 1, Child 2, and Child 3.

[0101] Upon receiving this technical criteria, in this example, Child 1 determines 306 that it needs to interface with the blocks of the next layer (child block 960), and instructs Child 1 to design the first part of the circuit based on this criteria. Meanwhile, Child 2 designs 307 the initial third part of the circuit based on the technical criteria, and Child 3 designs 308 the initial third part of the circuit based on the technical criteria.

[0102] Grandchild 1 designs 308 the first part of the circuit based on the technical criteria, and sends 312 this first part of the design back to Child 1, which can then forward this to the parent (optionally, after having first performed some simulations / verifications). Then, Child 1 instructs 314 Grandchild 2 to design the second part of the circuit based on this criteria. Grandchild 2 designs 316 the second part of the circuit based on this criteria, and sends 318 this back to Child 1, which can then optionally forward it to the parent.

[0103] Once Child 1 (via Grandchild 1 and Grandchild 2) has designed the first and second parts of the circuit, Child 1 sends 320 the context information to Child 2. Child 2 can rewrite or adjust the technical criteria received from the parent based on the context information obtained from Child 1. Then, Child 2 rewrites the initially designed third part of the circuit based on the context information received from Child 1.

[0104] In the example shown in FIG. 4, once the third part of the circuit has been designed by Child 2, the rewritten third part of this design can be sent to the parent, and the context information can be sent 324 to Child 3. The context information can include the context created by the first, second, and third parts of the circuit. Then, Child 3 rewrites 326 the initial design of the fourth part of the circuit based on the received context information, and sends 328 the designed fourth part to the parent block 900.

[0105] Once the parent block 900 has received all the design parts of the circuit, the parent block 900 generates an initial design for the analog circuit based on a set of designs obtained by the child blocks, and checks or verifies 330 whether the initial design of the design for the analog circuit meets the customer requirements. As stated above, the parent block 900 can do this by simulating the performance of the completed circuit by employing verification and simulation modules. If the analog circuit will include all the circuit parts of the design, the parent block 900 also obtains information related to the parasitic effects that will be experienced in the analog circuit.

[0106] In the case where the designed completed circuit does not meet the customer requirements, the parent block can directly re - send 332 the adjusted criteria to the block responsible for the circuit part that fails to meet the requirements of the designed circuit, and provide additional information about what needs to be adjusted (and optionally by which block) - for example, the criteria can be adjusted to take into account additional information for redesigning the block to meet the customer requirements. In some examples, the parent block 900 can send 332 only a part of the designed circuit back to the block responsible for designing that part - for example, the parent block 900 can send the first part of the analog circuit back to grandchild 1, for example with information about what needs to be adjusted and / or with information about the adjusted criteria.

[0107] It will be understood that in the above examples, the first, second, third, and fourth parts of the analog circuit can be independent parts of the circuit and / or functionally dependent on each other. In other examples, the first, second, third, and fourth parts of the analog circuit can be a selected subset of the analog circuit. For example, the second part can contain many parts of the first part, the third part contains many parts of the first and second parts, and the fourth part can contain many parts of the first, second, and third parts.

[0108] Although the example shown in FIG. 4 shows that only the parent block obtains information related to parasitic effects once all child blocks have designed their respective circuit parts, in some examples, the parent block 900 can obtain information related to parasitic effects after each child block has designed its respective part and before the next child block designs its respective circuit part.

[0109] FIG. 5 shows a functional schematic flowchart of another exemplary method for designing an analog circuit using a hierarchical model implemented on a demonstration computer such as that of FIG. 2 or FIG. 3. The method of FIG. 5 shares many features common to the method of FIG. 4.

[0110] In step 500, the parent block 900 receives customer requirements. For the method described above with respect to FIG. 4, the customer requirements may, for example, define the functionality of the circuit and certain limitations that will be required by it - such as peak current, voltage, and the like. The customer requirements may also specify other characteristics, such as the PDK / foundry by which the circuit will be manufactured. The parent block 900 is configured to transform 502 the customer requirements into a set of technical guidelines. The parent block 900 can additionally or alternatively be configured to determine whether to send these guidelines to the child blocks 950 in parallel or in series, and / or whether to send different sets of guidelines to the child blocks 950 of the next layer.

[0111] At this stage, the parent block 900 can also be configured to determine the number of layers of the model, or alternatively, each layer of blocks can be configured to determine whether blocks of the lower layer are needed when designing the various parts of the circuit, and the tasks of the various parts of the circuit are designed by the blocks in the upper layer.

[0112] Once the parent block 900 has transformed 502 the customer requirements into guidelines, it then sends 504 these to child 1 of the first design layer. These guidelines can specify how many child blocks 950 of this layer are to be used, and which child block 950 is to be specified to design each part of the analog circuit.

[0113] Upon receiving these guidelines, child 1 designs 506 the first part of the analog circuit based on the received guidelines. It will be understood that child 1 can be configured to design the first part of the analog circuit based on a subset / first part of the guidelines applicable to it, as determined by the parent block.

[0114] Once child 1 has designed the first part of the analog circuit, the guidelines received by the parent block 900 may instruct child 1 to send 508 the designed first part of the circuit and the guidelines to the second child (child 2) of the same layer. Child 2 can design 510 the second part of the analog circuit based on the received guidelines, and in some examples, can design the second part of the analog circuit based only on a subset of the guidelines (e.g., only those parts applicable to it) or based on all the guidelines.

[0115] Sub - block 2 also rewrites the design of the second part of the analog circuit based on the context created by the first part designed by the analog circuit designed by Sub - block 1. In some examples, this context can be expressed in the form of an adjusted set of criteria - for example, Sub - block 1 and / or the parent block can be configured to adjust the criteria based on the context and / or parasitic effects provided by the first part designed by the circuit designed by Sub - block 1, although it will be understood that in other examples, the context and / or parasitic effects can be provided outside / separately from the criteria. For example, in an example where the parent block includes verification and emulator modules, the verification and simulation modules can simulate the performance of the design part or component of the circuit to obtain context and / or parasitic effect information. Additionally or alternatively, in an example where each sub - block includes verification and emulator modules, these verification and simulation modules can simulate the performance of the design part or component of the circuit to obtain context and / or parasitic effect information.

[0116] In some examples, Sub - block 2 can determine the parts of the circuit design assignment for which it needs to employ lower - level blocks, and / or determine whether to employ these lower - level blocks in series and / or in parallel. Additionally or alternatively, the criteria received by Sub - block 2 can indicate (e.g., as determined by the parent block) that Sub - block 2 will employ lower - level blocks to design the circuit part that Sub - block 2 is assigned to design (and whether to employ these blocks in series or in parallel). For example, as shown in FIG. 6, Sub - block 2 can optionally instruct Grand - child 1 and Grand - child 2 to design a subset of the second part of the analog circuit. In such examples, Sub - block 2 can optionally verify 513 whether the circuit parts designed by the lower - level blocks (in the example shown, Grand - child 1 and Grand - child 2) meet the criteria they are required to meet.

[0117] Then, Sub - block 2 sends 514 the first part designed, the second part designed, and the criteria to Sub - block 3. In some examples, the criteria can be modified by the previous sub - block. For example, the criteria can be modified by Sub - block 1 and / or Sub - block 2 before being sent to the next sub - block. For example, Sub - block 2 can be configured to modify the criteria it sends to Sub - block 3 based on the first part designed of the circuit and / or the second part designed of the circuit.

[0118] Then, Sub - block 3 designs 516 the third part of the analog circuit based on the received criteria and additionally or alternatively based on the first part designed of the circuit and / or the second part designed of the circuit.

[0119] Then, Child 3 sends 518 the completed circuit to the parent block, and the parent block generates an initial design for the analog circuit based on the respective circuit part designs, and checks or verifies 520 whether the designed completed circuit meets the customer requirements. As stated above, the parent block can do this by simulating the performance of the completed circuit by employing verification and simulation modules. If the analog circuit is to include all the designed circuit parts, the parent block 900 also obtains information regarding the parasitic effects that will be experienced in the analog circuit.

[0120] If the designed completed circuit does not meet the customer requirements, the parent block can resend 522 the designed completed circuit to Child 1, with additional information on what needs to be adjusted (and optionally by which block). Additionally or alternatively, in the case where the designed completed circuit does not meet the customer requirements, the parent block can send back 524 only a part of the designed circuit to the block responsible for designing that part - for example, the parent block can send the second part of the analog circuit back to Child 2, for example with information on what needs to be adjusted and / or with information on the adjusted criteria. Then, Child 2 can design that part of the circuit, or send it directly back to the parent block for checking whether the customer requirements are met, or send it to Child 3, which can then redesign the third part of the circuit based on the redesigned second part of the circuit (and / or optionally based on the adjusted criteria).

[0121] It will be understood that in the above example, the first, second, third, and fourth parts of the analog circuit can be independent parts of the circuit and / or functionally dependent on each other. In other examples, the first, second, third, and fourth parts of the analog circuit can be a selected subset of the analog circuit. For example, the second part can contain many parts of the first part, the third part contains many parts of the first and second parts, and the fourth part can contain many parts of the first, second, and third parts.

[0122] Although the example shown in FIG. 5 shows that only the parent block obtains information regarding parasitic effects once all child blocks have designed their respective circuit parts, in some examples, the parent block 900 can obtain information regarding parasitic effects after each child block has designed its respective part and before the next child block designs its respective circuit part.

[0123] FIG. 6A shows an input buffer, a level shifter, a DAC, and a comparator. Each of these can form part of a completed analog circuit, such as the completed ADC shown in FIG. 6B.

[0124] As described above, the examples shown in FIGS. 6A and 6B have been designed using a computer-implemented hierarchical model. The parent block (or primary design unit) is responsible for designing the entire ADC, while the child blocks (or secondary design units) are responsible for each of the input buffer, level shifter, DAC, and comparator, respectively. The parent block receives the technical requirements from the user and converts these into technical specifications, which are used by each child block to design its respective circuit portion. In designing its respective portion of the circuit, the child block considers and uses the context of the other portions of the circuit. This model is also iterative, where once the parent block 900 has instructed each child block 950a-d to design their respective portions or components, a degree of redesign is performed on the circuit and its portions such that the context provided by the other portions of the circuit is used in designing the respective circuit portions and the entire circuit. As described above, each child block and / or parent block may also perform verification / validation to determine whether the designed portion / completed circuit meets the required technical requirements.

[0125] In the designed circuit shown in FIG. 6B, the reason for having two DACs is that this circuit provides differential ADC operation. The reason for having a plurality (three in the example shown) of input buffers is that two input buffers are used to buffer two inputs, and the reference is also buffered as an input.

[0126] As stated above, the analog circuit design device can utilize a machine learning model to estimate the parasitic effects of any circuit or circuit portion it has designed.

[0127] The machine learning model can include a neural network. This neural network can include at least one of a deep residual network, highway network, densely connected network, and capsule network.

[0128] For any such type of network, the network can include a plurality of different neurons, which are organized into different layers. Each neuron is configured to receive input data, process this input data, and provide output data. Each neuron can be configured to perform a specific operation on its input, for example, this can involve mathematically processing the input data. The input data of each neuron can include the outputs from a plurality of other previous neurons. As part of the operation of the neuron on the input data, each input data stream (for example, each input data stream for providing its output to a neuron from one of the previous neurons) is assigned a weight. Thus, the processing of the input data by the neuron includes applying weights to different input data streams, so that different input data items will contribute more or less to the overall output of the neuron. Adjusting the input values of the neuron, such as the result of a change in the input weights, can cause a change in the output value of the neuron. The output data from each neuron can be sent to a plurality of subsequent neurons.

[0129] Neurons are organized in a hierarchical manner. Each layer contains a plurality of neurons, which operate on the data provided to them by the outputs of the neurons in the previous layer. A large number of different neurons can exist within each layer, and each neuron applies different weights to its input data and performs different operations on its input data. The input data for all the neurons in a layer can be the same, and the output from the neurons will be passed to the neurons in the subsequent layer.

[0130] The precise routing between neurons in different layers forms the main difference between capsule networks and deep residual networks (including variants such as highway networks and densely connected networks).

[0131] For a residual network, the layers can be organized into blocks, such that the network includes a plurality of blocks, and each block includes at least one layer. For a residual network, the output data from a layer of neurons can follow more than one different path. For a traditional neural network (such as a convolutional neural network), the output data from a layer is passed into the next layer, and this continues until the end of the network, so that each layer receives input from the layer immediately preceding it and provides output to the layer immediately following it. However, for a residual network, different routing can occur between the layers. For example, the output from a layer can be passed to a number of different subsequent layers, and the input for a layer can be received from a number of different previous layers.

[0132] In a residual network, neuron layers can be organized into different blocks, where each block contains at least one layer of neurons. The blocks can be configured with layers stacked together such that the output of the previous layer (or layers) is fed into the input of the layers of the next block. The structure of the residual network can be such that the output from a block (or layer) is passed into the block (or layer) immediately following it and at least one other subsequent block (or layer) further downstream. Shortcuts can be introduced into the neural network, which pass data from one layer (or block) to another while bypassing other layers (or blocks) in between. This may enable more efficient training of the network, for example, when dealing with very deep networks, as it may be able to address problems associated with degradation when training such a network (which will be discussed in more detail below). The configuration of the residual neural network can allow for branching such that the same input provided to a block of one layer, or layers, is provided to at least another block of one layer, or layers (e.g., such that another layer can operate on both the input data and the output data from a block of one layer, or layers). When using the backpropagation algorithm to train the network, this configuration can achieve deeper penetration of the network. For example, this is because during learning, layers or blocks of layers can be capable of serving as inputs, the input of the previous layer / block, and the output of the previous layer / block, and shortcuts can be used to provide deeper penetration when updating the weights for the network.

[0133] For capsule networks, layers can be nested inside other layers to provide 'capsules'. Different capsules can be rewritten such that they perform different tasks more proficiently compared to other capsules. Capsule networks can provide dynamic routing between capsules such that for a given task, the task is assigned to the most competent capsule for handling that task. For example, a capsule network can avoid routing the output from each neuron in one layer to each neuron in the next layer. Lower-level capsules are constructed to send their inputs to higher-level (subsequent) capsules that are determined to be the capsules most likely to process that input. Capsules can predict the activity of higher-level capsules. For example, a capsule can output a vector whose orientation represents the attributes of the object under discussion. In response, each subsequent capsule can provide as output the probability of the object for which the capsule is trained to recognize being present in the input data. This information (e.g., probability) can be fed back to the capsule, which can then dynamically determine routing weights and forward the input data to the subsequent capsule most likely to be relevant for processing that data.

[0134] For any type of neural network, it may include a plurality of different layers with different functions. The neural network may include at least one convolutional layer, which is configured to convolve the input data across its height and width. The neural network may also have a plurality of filter layers, each filter layer including a plurality of neurons, which are configured to focus on the filter and apply the filter to different parts of the input data. Other layers for processing the input data may be included, such as pooling layers (to introduce non-linearity), such as max pooling and global average pooling, rectified linear unit layers (ReLU), and loss layers, for example, some of which may include regularization functions. The final block of the many layers may receive the input from the last output layer (if there are branches, it may receive more layers). The final block may include at least one fully connected layer.

[0135] The final output layer may include a classifier, such as a softmax, sigmoid, or tanh classifier. Different classifiers may be suitable for different types of outputs; for example, where the output is a binary classifier, a sigmoid classifier may be appropriate. The neural network of the present disclosure may be configured to predict the binding affinity between a target and a test object. In this case, the output may be a prediction for the dissociation constant value for equilibrium. The output of the neural network may provide an indication of the probability of the combination of the target and the test object. It may provide a more detailed analysis as an output indicating whether the binding between the target and the test object is proven, for example, in binary form, where the first output indicates 'yes' and the second output indicates 'no'. In this case, the network can be used as a filter for pulling out a smaller group of compounds that need more detailed examination.

[0136] Figure 7 shows a schematic diagram of an exemplary method for training a machine learning model to estimate parasitic effects. The neural network 700 is constructed to take as input 710 a designed circuit portion and / or an analog circuit. The designed circuit portion and / or analog circuit can be stored in a database and may have been designed using the computer-implemented models described above with reference to FIGS. 1A to 6B, and using a hierarchical model of primary and secondary design cells. The circuit portion and / or analog circuit can be vectorized and / or encoded, for example by using one-hot encoding to provide a binary format. This input is then fed into a set of 3D layers in the neural network. The network has several characteristics that can vary as the training of the network continues. For each neuron, there can be a plurality of weights, each weight being applied to a respective input stream of output data from neurons in the previous layer. These weights are variables that can be modified to provide a change to the output of the neural network. These weights can be modified in response to training so that they provide more accurate data. In response to having trained these weights, the modified weights are referred to as 'learned'. Additionally, the size and connectivity of the layers may depend on the typical input data of the network; although, these can also be variables that can be modified and learned during training, including strengthening of connections.

[0137] To train the network, for example to learn the values of the weights, these weights are assigned an initial value. These initial values can be random in nature; however, to improve the training of the network, appropriate initialization of these values can be applied, such as Xavier / Glorot initialization. Such initializations can prevent the situation where the initial random weights are too large or too small and can never correctly train the neural network to overcome these initial biases. This type of initialization can involve using a distribution with a mean of zero but a fixed variance to assign the weights.

[0138] Once weights have been assigned, training object data can be fed or input into neural network 700. This can include operating the neural network on known design circuit pairs (and / or circuit portions) and corresponding estimates / simulations and / or known parasitic effects to predict parasitic effects for the input circuit portion / analog circuit output 720. Based on this information, a backpropagation optimization method such as using gradient descent (e.g., stochastic gradient descent) and a loss function is performed on the network to compare 730 the predicted parasitic effects with the expected or known parasitic effects of the circuit portion / analog circuit. For example, a virtual test bench can be used to obtain the expected or known parasitic effects. Algorithms such as mini-batch gradient descent, RMSprop, Adam, Adadelta, and Nesterov can be used during this process. This can enable identification of the extent to which each different point (neuron) or path (between neurons in subsequent layers) in the network contributes to an incorrect decision score, such that it can be determined 740 whether any weight adjustments are needed. The weights can then be adjusted 750 based on the calculated error. For example, the contribution of the neuron(s) that contribute or most contribute to an incorrect decision is minimized or removed.

[0139] After iterations of training the network with different pairs of the designed circuit (and / or circuit portions) and corresponding parasitic effects, the weights can be updated 750, and this process can be repeated many times. To suppress the possibility of overtraining the network, training variables such as the learning rate and momentum can be varied and / or controlled to selected values. Additionally, regularization techniques such as L2 or dropout can be used, which reduce the likelihood that different layers become overtrained and too specific to the training data and thus not as applicable to other similar data as usual. Similarly, batch normalization can be used to assist training and improve accuracy. Generally, the weights are adjusted such that if the network is operated again on the same training images, the network will produce the expected results. Although, the extent to which this is true will depend on the training variables, such as the learning rate.

[0140] It will be understood that when training, increasing the depth of the neural network can cause problems, such as due to the vanishing gradient problem, and it can also provide a slower network. However, the present disclosure can provide a network with increased depth and accuracy without sacrificing the ability to properly train the network.

[0141] The depth of the network used can be selected to balance between accuracy and the time taken to provide an output. An increase in network depth provides increased accuracy, although it can also increase the time taken to provide an output. The use of a branched structure (as opposed to that in a convolutional neural network) enables the full training of the network to occur as the network depth increases, which in turn provides a network with improved accuracy.

[0142] It will be understood that, in the context of the present disclosure, a non-exhaustive list of exemplary analog parameters that can form the basis of criteria includes: noise tolerance; power supply rejection ratio (PSRR); common mode range - input (Input CMR); common mode range - output (Output CMR); linearity; maximum offset; bandwidth; minimum slew rate; intrinsic delay; minimum phase margin; dynamic power consumption; static power consumption; IP3 point; filter center frequency; filter bandpass range; load step response; line step response; output accuracy; noise figure; calibration range; noise floor; SNR; ENOB; SINAD; output frequency range; jitter - ptp; jitter - RMS; output ripple ptp; total harmonic distortion; startup time; channel isolation; reference voltage; gain error; offset error; gain drift.

[0143] It will also be understood that design units (such as primary, secondary, and tertiary design units) can be implemented in software or hardware (e.g., as an application - specific circuitry). For example, a design unit can be implemented as part of a computer system. This computer system can include a bus or other communication mechanism for passing information, data, signals, and information among the various components of the computer system. The components can include input / output (I / O) components that process user (i.e., sender, receiver, service provider) actions, such as selecting buttons from a keypad / keyboard, selecting one or more buttons or links, etc., and sending corresponding signals to the bus. The I / O components can also include output components, such as a display and a cursor control (e.g., a keyboard, keypad, mouse, etc.). A transceiver or network interface can send and receive signals between the computer system and other devices (such as another user device, a merchant server, or a service provider server) via a network. In one embodiment, the transmission is wireless, although other transmission media and methods can also be suitable. A processor, which can be a microcontroller, a digital signal processor (DSP), or other processing component, processes these various signals, such as displaying on the computer system or transmitting via a communication link to other devices. The processor can also control the transmission of information (such as cookies or IP addresses) to other devices.

[0144] Components of a computer system may also include a system memory component (e.g., RAM), a static storage component (e.g., ROM), and / or a disk drive (e.g., solid state drive, hard disk drive). The computer system performs specific operations using a processor and other components by executing one or more instruction sequences contained in the system memory component.

[0145] Logic can be encoded in a computer-readable medium, which can mean any medium that participates in providing instructions to a processor for execution. Such a medium can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. In many embodiments, non-volatile media includes optical discs or magnetic disks, volatile media includes dynamic memory such as a system memory component, and transmission media includes coaxial cables, copper wires, and optical fibers. In one embodiment, the logic is encoded in a non-transitory computer-readable medium. In one example, the transmission media can take the form of acoustic or light waves, such as those generated during radio wave, optical, and infrared data communication.

[0146] Some common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tapes, any other magnetic media, CD-ROMs, any other optical media, punched cards, paper tapes, any other physical media with a pattern of holes, RAM, PROM, EPROM, FLASH-EPROM, any other memory chip or memory cartridge, or any other media that can be rewritten by a computer to be readable.

[0147] In many embodiments of the present disclosure, the execution of an instruction sequence for practicing the present disclosure can be performed by a computer system. In many other embodiments of the present disclosure, a plurality of computer systems 600 coupled to a network (e.g., LAN, WLAN, PTSN, and / or many other wired or wireless networks, including those such as telecommunications, mobile, and cellular telephone networks) via a communication link can execute an instruction sequence to practice the present disclosure in cooperation with each other.

[0148] It will also be understood that many aspects of the present disclosure can be implemented using hardware, software, or a combination of hardware and software. Moreover, where applicable, without departing from the spirit of the present disclosure, the hardware components and / or software components described herein can be combined into composite components that include software, hardware, and / or both. Where applicable, without departing from the scope of the present disclosure, the hardware components and / or software components described herein can be divided into sub-components that include software, hardware, or both. Additionally, where applicable, it is contemplated that software components can be implemented as hardware components and vice versa.

[0149] Software according to the present disclosure, such as code and / or data, can be stored on one or more computer-readable media. It is also contemplated that the software identified herein can be implemented using one or more general-purpose or special-purpose computers and / or computer systems that are networked and / or otherwise. Where applicable, the order of the various steps described herein can be changed, combined into composite steps, and / or divided into sub-steps to provide the features described herein.

[0150] The various features and steps described herein can be implemented as systems that include one or more memories storing the various information described herein and one or more processors coupled to the one or more memories and a network, wherein the one or more processors are operable to execute the steps as described herein, because the non-transitory machine-readable medium includes a plurality of machine-readable instructions that, when executed by the one or more processors, cause the one or more processors to execute a method that includes the steps described herein and a method executed by one or more devices (e.g., a hardware processor, a user device, a server, and other devices described herein).

[0151] In the context of the present disclosure, other examples and variations of the devices and methods described herein will be apparent to those skilled in the art.

[0152] 700: Neural network 900: Parent block 901: Indication module 902: Assembly module 903: Verification and analogizer module 950: Sub-block 950a: Sub-block 950b: Sub-block 950c: Sub-block 950d: Sub-block 951a: Converter module 951b: Converter module 951c: Converter module 951d: Converter module 952a: Assembly module 952b: Assembly module 952c: Assembly module 952d: Assembly module 953a: Simulator module 953b: Simulator Module 953c: Simulator Module 953d: Simulator Module 960: Grandchild Block 970: Great-grandchild Block 1000: Analog-to-Digital Converter 1001: Comparator 1002: DAC 1003: Level Shifter 1004: OP-AMP

Claims

1. A method for predicting parasitic effects in a designed analog circuit, the method comprising: at each of a plurality of secondary design units of an analog circuit design device: a) designing respective circuit portions of the plurality of circuit portions based on technical criteria provided by the primary design unit; and b) outputting the resulting designs of the respective circuit portions; and at the primary design unit of the analog circuit design device: c) obtaining a set of designs comprising the respective designs for each circuit portion from at least one of the plurality of secondary design units; d) generating at least one initial design for the analog circuit based on the set of designs; e) obtaining information relating to parasitic effects experienced by at least one of the circuit portions and the generated design by mathematically simulating the performance of the generated design using a virtual test bench; and repeating steps a) to e) a plurality of times, wherein each time steps a) to e) are repeated, new technical criteria are provided by the primary design unit.

2. The method of claim 1, comprising, if the analog circuit is to include a circuit portion of the design, obtaining information relating to the parasitic effects to be experienced in the analog circuit by performing a search in a database of circuit designs and parasitic effects.

3. The method of claim 1 or 2, comprising, if the analog circuit is to include a circuit portion of the design, obtaining information relating to the parasitic effects to be experienced in the analog circuit by performing a search in a database of circuit designs and parasitic effects used for similar generation designs.

4. The method of claim 1 or 2, comprising, if the analog circuit is to include a circuit portion of the design, performing a search in a database of circuit designs and parasitic effects for at least one of the similar circuit portions based on the value of the parasitic effect obtained by searching for at least one of the respective circuit portions, and obtaining information relating to the parasitic effect to be experienced in the analog circuit.

5. The method of claim 1 or 2, comprising, if the analog circuit is to include a circuit portion of the design, using a machine learning model to predict parasitic effects and obtain information relating to the parasitic effects to be experienced in the analog circuit.

6. The method of claim 1 or 2, wherein the parasitic effect includes at least one of parasitic capacitance, parasitic resistance, and parasitic inductance.

7. The method of claim 1 or 2, wherein, when information relating to parasitic effects indicates that such parasitic effects are greater than the critical level of the selected parasitic effect, the design of rewriting the respective circuit portions is performed.

8. The method of claim 1 or 2, wherein rewriting the design of the respective part based on information related to parasitic effects includes corresponding technical guidelines for rewriting the respective circuit part.

9. The method of claim 1 or 2 further includes designing and manufacturing an analog circuit for the output.

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