Memory system

Abstract

This invention provides a memory chip and memory system for accurately measuring and appropriately controlling the temperature of a semiconductor memory device. To achieve the above objectives, the memory chip in the embodiment includes: a memory cell array; a temperature sensor capable of outputting first temperature data; a stress sensor capable of outputting first stress data; a correction circuit that generates second temperature data based on the first stress data and the first temperature data; and an interface capable of sending the second temperature data to a memory controller connected to an external device.

Description

Memory chips and memory systems The embodiments of the present invention relate to a memory chip and a memory system. A memory system is known, comprising NAND (Not AND) memory as a semiconductor memory device and a memory controller for controlling the semiconductor memory device. In recent years, NAND memory has achieved high-density mounting, leading to increased heat generation from semiconductor memory devices. Since the temperature of semiconductor memory devices is regulated to be below a certain level in safety standards, it is necessary to suppress temperature rise. For example, a function (e.g., thermal throttling) is implemented: by incorporating a temperature sensor in the semiconductor memory device to monitor the temperature, once a predetermined temperature threshold is reached, the temperature rise is suppressed, thereby controlling access to the memory to prevent temperature increases. One of the problems that this invention aims to solve is to provide a memory chip and memory system that can accurately measure and appropriately control the temperature of a semiconductor memory device. To achieve the above objectives, the memory chip in the embodiment includes: a memory cell array; a temperature sensor capable of outputting first temperature data; a stress sensor capable of outputting first stress data; a correction circuit that generates second temperature data based on the first stress data and the first temperature data; and an interface capable of sending the second temperature data to a memory controller connected to an external device. (First Embodiment) Figure 1 is a block diagram showing an example of the configuration of the memory system according to the first embodiment. The memory system 3 is, for example, a storage device configured to read data from non-volatile memory. The memory system can be implemented, for example, in the form of an SSD (Solid State Disk). Alternatively, the memory system can also be implemented in the form of a hard disk drive (HDD) or a memory card. The memory system 3 includes a memory controller 4 and non-volatile memory 5. Non-volatile memory 5 is a semiconductor memory device that stores data non-volatilely. Non-volatile memory 5 is, for example, NAND flash memory. NAND flash memory contains a plurality of blocks. Each block contains a plurality of memory cells. A block is a unit for erasing data. A block contains a plurality of pages. A page is a unit for reading and writing data. Hereinafter, non-volatile memory 5 will be referred to as NAND memory 5. The memory controller 4 can also be implemented using circuitry such as a system-on-a-chip (SoC). The memory controller 4 is electrically connected to the NAND memory 5 via a NAND interface (I / F) 10. NAND memory 5 includes one or more memory chips 100. Each memory chip 100 can operate independently. Therefore, the memory chips 100 function as units capable of parallel operation. Here, as an example, NAND memory 5 has 100-0 and 100-1 as one or more memory chips 100. The number of memory chips 100 included in memory system 3 is not limited to two. The memory CPU (Central Processing Unit) 11 is configured as a processor that controls the RAM (Random Access Memory) 12 and NAND flash memory 10. The memory CPU 11 can perform instruction processing and other tasks to process various instructions from the host 2. RAM12 is a volatile memory used as a buffer for data transfer between NAND memory 5 and host 2, or as the working area of ​​memory CPU 11. RAM 12 can temporarily store stress correction table 20. Stress correction table 20 is described below. Stress correction table 20 is stored in memory chip 100 and, as needed, in RAM 12. Stress correction table 20 can also be stored in RAM 12 after the memory system 3 is powered on. NAND I / F10 uses, for example, Toggle NAND flash interface and Open NAND flash interface (ONFI) as standards. NAND I / F10 is connected to multiple memory chips 100 in NAND memory 5 via multiple channels (Ch). Recently, technology for densely mounting more memory chips 100 within a single NAND memory module 5 has been continuously developing, and the miniaturization and integration of each memory chip 100 are also progressing. Each memory chip 100 contains a boost circuit; therefore, the higher the density of memory chips 100 mounted within the NAND memory module 5, the higher the heat generation and power consumption of the NAND memory module 5. When a large number of memory chips 100 are stacked and packaged, there is a risk that the heat generation in certain areas within the NAND memory module 5 may significantly increase. Therefore, in memory system 3, if the temperature of NAND memory 5 rises, in order to prevent NAND memory 5 from malfunctioning, the processing speed of NAND memory 5 is generally reduced to suppress the temperature rise. For example, memory system 3 has the following function (hereinafter referred to as "thermal throttling"): using a temperature sensor installed in memory chip 100 to monitor the temperature, once a specified temperature threshold is reached, the processing speed is reduced to suppress the temperature rise. As long as the temperature of NAND memory 5 does not reach the specified temperature, NAND memory 5 will be controlled to operate at the specified processing speed. Once the temperature of NAND memory 5 reaches the specified temperature threshold, it switches to a mode that uses thermal throttling to periodically reduce the processing speed of NAND memory 5, thereby lowering the temperature of NAND memory 5. For example, the upper limit of the temperature at which NAND memory 5 can operate stably is about 85°C. Figure 2 is a block diagram showing one example of the configuration of the memory system 3. Figure 2 mainly explains the configuration of the memory chip 100. The memory controller 4 outputs instructions required for the operation of the memory chip 100 to the memory chip 100. By outputting these instructions to the memory chip 100, the memory controller 4 performs tasks such as reading data from the memory chip 100, writing data to the memory chip 100, or erasing data from the memory chip 100. The memory controller 4 and the memory chip 100 are connected via an input / output interface (I / F) 101 and a control signal input interface (I / F) 102. The input / output I / O 101 generates data strobe signals DQS and BDQS (complementary signals to DQS) based on signals supplied by the input / output control circuit 103. When the input / output I / O 101 outputs data from the data input / output lines (DQ0 to DQ7), it outputs the data strobe signals DQS and BDQS. Subsequently, the memory controller 4 receives data from the data input / output lines (DQ0 to DQ7) according to the timing of the data strobe signals DQS and BDQS. Furthermore, the input / output I / O 101 may also include, for example, instruction input terminals and address input terminals. The control signal input I / F102 receives the chip enable signal BCE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal BWE, read enable signal RE, BRE (complementary signal of RE), and write protection signal BWP from the memory controller 4. The input / output control circuit 103 outputs the data read from the memory cell array 110 to the memory controller 4 via the input / output I / F 101. The input / output control circuit 103 receives various instructions, addresses, and write data, such as write, read, erase, and status read, via the control signal input I / F 102 and the control circuit 105. The control circuit 105 supplies the control signal input via the control signal input I / F 102 to the input / output control circuit 103. The control circuit 105 controls the temporary register 104, temperature sensor 106, stress sensor 107, voltage generation circuit 109, memory cell array 110, etc. In this embodiment, the input / output control circuit 103 and the control circuit 105 are described according to their functional categories. However, the input / output control circuit 103 and the control circuit 105 can also be implemented using the same hardware resources. The register 104 outputs the instruction input from the input / output control circuit 103 to the control circuit 105. The register 104, for example, latches an address supplied by the memory controller 4. Then, the register 104 converts the latched address to an internal physical address. The register 104 is used to inform the outside world of the various states of the memory chip 100. The register 104 has a standby / busy register (not shown) and a write status register (not shown). The standby / busy register stores data indicating whether the memory chip 100 is in a standby or busy state, and the write status register stores data indicating whether the write was successful or failed. Temperature sensor 106 measures the temperature of memory chip 100. Temperature sensor 106 includes, for example, a bandgap reference circuit (BGR circuit) 106a and an analog-to-digital converter circuit (ADC circuit) 106b. The BGR circuit 106a is, for example, a circuit equipped with a diode. When the control circuit 105 receives the enable signal EN for the "H" (High) level, the BGR circuit 106a uses the bandgap voltage to detect the temperature and outputs a voltage Vtemp that is proportional to the temperature of the memory chip 100. The BGR circuit 106a generates Vtemp and also generates a reference voltage VREF that does not change with temperature. The ADC circuit 106b outputs a temperature code based on Vtemp and VREF. The temperature code is digital data representing the temperature of the temperature sensor 106 or its surroundings. The temperature code is represented by multi-bit data. The temperature sensor 106 can output the generated temperature code to the control circuit 105. The voltage generation circuit 109 is supplied with ground voltage and power supply voltage from the outside. Based on these voltage and temperature codes, the voltage generation circuit 109 generates various voltages used during data erasure, data writing, and data reading. The voltage generation circuit 109 can change the various voltages to be applied to the memory cell array 110 according to the temperature of the memory cell array 110. For example, the threshold voltage of the memory cell MC varies with temperature. Therefore, during data readout, the voltage generation circuit 109 generates the voltage to be applied to the word line in accordance with the temperature characteristics of the threshold voltage of the memory cell MC. The stress sensor 107 is a sensor that detects the stress generated in the memory chip 100. The stress includes strain or pressure generated in the memory chip 100. The stress sensor 107 is, for example, constructed using a piezoresistive sensor. When a piezoresistive element is deformed by stress, its resistance changes. This effect is called the piezoresistive effect. For example, when an external force is applied to a semiconductor material, strain occurs in the crystal lattice, and the energy states of the valence band or conduction band change. As a result, the number or mobility of carriers in the energy bands changes, and the conductivity or resistivity changes. This characteristic can be used as the detection principle for physical sensors such as strain sensors, pressure sensors, and stress sensors. Figure 3 shows an example of a stress sensor 107. The stress sensor 107 includes, for example, a resistive element 107a, a measuring unit 107b, and a control unit 107c. The resistive element 107a includes a piezoresistive element. When the stress sensor 107 receives the "H (High)" level activation signal EN from the self-control circuit 105, a fixed current I flows in the resistor 107a. The measuring unit 107b measures the voltage applied to the resistor 107a and sends the voltage applied to the resistor 107a to the control unit 107c. The control unit 107c pre-memorizes a reference voltage. The reference voltage refers to the voltage applied when current I flows in the unstressed resistor 107a. The control unit 107c generates a stress value from the difference between the voltage applied to the resistor 107a and the reference voltage, and sends the generated stress value to the control circuit 105. In the first embodiment, the RAM12 in FIG1 stores the stress correction table 20. Figure 8 is a diagram illustrating an example of the stress correction table 20 of the embodiment. One item in the stress correction table 20 is the stress value shown by the stress sensor 107 (moreover, the stress value here is in arbitrary units (also sometimes abbreviated as au)). Another item in stress correction table 20 is the temperature correction value (°C). The temperature correction value is obtained by subtracting the true temperature of the memory chip 100 from the temperature displayed by the temperature sensor 106. Here, the true temperature of the memory chip 100 refers to the temperature when the stress applied to the memory chip 100 is zero. The temperature correction value may be positive or negative. The stress correction table 20 illustrates the relationship between stress values ​​and temperature correction values. In the stress correction table 20, appropriate temperature correction values ​​are pre-entered based on the operating environment of the memory chip 100. For example, while maintaining a constant temperature for the memory chip 100, the stress applied to the memory chip 100 is varied. The temperature change of the memory chip 100 as indicated by the temperature sensor 106 at that time is recorded, and the stress correction table 20 is created. Regarding the input time point for stress correction table 20, for example, an appropriate temperature correction value can be input during the manufacturing of memory chip 100. Alternatively, an appropriate temperature correction value can be input after the memory package 200 is completed. The stress correction table 20 shows that the higher the stress value, the greater the negative temperature correction value. That is, it indicates that the greater the actual stress generated in the memory chip 100 compared to the value shown by the temperature sensor 106, the higher the temperature correction value. The stress correction table 20 is stored, for example, in the memory cell array 110 within the memory chip 100. The stress correction table 20 may also be stored in the RAM 12 as needed. The stress correction table 20 may also be stored in the RAM 12 when the memory system 3 is powered on. Here, the steps by which the memory CPU 11 obtains the true value of the temperature of the memory chip 100 in the first embodiment will be explained. The memory CPU 11 sends a command to the control circuit 105 requesting a temperature code. The control circuit 105 receives the command from the memory CPU 11 and sends it to the temperature sensor 106. The temperature sensor 106 receives the command from the control circuit 105 and sends a temperature code to the control circuit 105, which then sends the temperature code to the memory controller 4. This temperature code contains the temperature of the memory chip 100 measured by the temperature sensor 106. The memory CPU 11 sends a command to the control circuit 105 requesting a stress value. The control circuit 105 receives the command from the memory CPU 11 and sends it to the stress sensor 107. The stress sensor 107 receives the command from the control circuit 105 and sends a signal containing the stress value to the control circuit 105. The control circuit 105 then sends the signal containing the stress value to the memory controller 4. The memory CPU 11 sends a command to the control circuit 105 requesting the stress correction table 20. The control circuit 105 reads the stress correction table 20 stored in the memory cell array 110 and sends it to the memory controller 4. The memory CPU 11 stores the stress correction table 20 in the RAM 12. The memory CPU11 can execute any one of the following instructions: requesting a temperature code, requesting a stress value, or requesting a stress correction table 20; or they can execute them simultaneously. The memory CPU 11 calculates the temperature correction value by referring to the stress value and stress correction table 20. The memory CPU 11 obtains the true temperature value of the memory chip 100 by referring to the temperature measured by the temperature sensor 106 and the temperature correction value. The memory controller 4 uses the true temperature of the memory chip 100, for example, to perform thermal throttling. In memory systems without stress sensors, when high stress is applied to the memory chip, the temperature sensor outputs a temperature lower than the true temperature of the memory chip. For example, even if the true temperature of the memory chip is 85°C, if the stress is high, the memory chip will be perceived as being below 85°C, thermal throttling will not function, and the memory chip will be controlled in a way that does not reduce processing speed. The memory chip operating at a processing speed that is mismatched with its temperature can sometimes lead to a shorter lifespan. According to this embodiment, the memory controller 4 can control the memory system 3 using the temperature corrected by the stress correction table 20. Specifically, when the stress applied to the memory chip 100 is high, the temperature sensor 106 outputs a temperature lower than the true temperature of the memory chip 100. However, because the memory system 3 has the stress sensor 107 and the stress correction table 20, the true temperature of the memory chip 100 can be obtained. That is, the memory system 3 can perform thermal throttling using the temperature at which the stress applied to the memory chip 100 is zero. Therefore, the memory chip 100 can be appropriately controlled based on a more accurate temperature. (Second Embodiment) In the second embodiment, the same symbols are used for the same components as in the first embodiment and the description is omitted. Only the different components are described. Although in the first embodiment the stress correction table 20 is stored in RAM 12, in the second embodiment the stress correction table 20 is stored in temporary register 104. Figure 4 is a block diagram showing an example of the internal structure of the memory system 3 in the second embodiment. The RAM 12 in the second embodiment does not store the stress correction table 20. Figure 5 is a block diagram showing an example of the internal structure of the memory chip 100 according to the second embodiment. The control circuit 105 acquires the temperature code from the temperature sensor 106 and stores the temperature code in the temporary register 104. The control circuit 105 acquires the stress value from the stress sensor 107 and stores the stress value in the temporary register 104. The temporary register 104 stores the stress correction table 20 after the power is turned on. Before the power is turned on, the stress correction table 20 is stored in the memory cell array 110 and stored in the temporary register 104 as needed. Here, the steps by which the memory controller 4 acquires the true value of the temperature of the memory chip 100 in the second embodiment will be explained. The memory CPU 11 requests the temperature of the memory chip 100 from the control circuit 105. The control circuit 105 receives a command from the memory CPU 11 requesting the temperature of the memory chip 100, and sends the command requesting the temperature code to the temperature sensor 106. The temperature sensor 106 receives the command from the control circuit 105 and sends a temperature code to the control circuit 105. The temperature code contains the temperature of the memory chip 100 measured by the temperature sensor 106. The control circuit 105 receives a command from the memory CPU 11 requesting the temperature of the memory chip 100, and sends a command to the stress sensor 107 requesting a stress value. The stress sensor 107 receives the command from the control circuit 105 and sends a signal containing the stress value to the control circuit 105. The control circuit 105 receives a command from the memory CPU 11 requesting the temperature of the memory chip 100, reads the stress correction table 20 stored in the memory cell array 110, and stores it in the temporary register 104. The control circuit 105 can execute any one of the following commands: requesting temperature code, requesting stress value, and reading stress correction table 20; or they can execute them simultaneously. The control circuit 105 calculates the temperature correction value by referring to the stress value and the stress correction table 20. The control circuit 105 obtains the true temperature value of the memory chip 100 by referring to the temperature of the memory chip 100 measured by the temperature sensor 106 and the temperature correction value. The control circuit 105 sends the true temperature value of the memory chip 100 to the memory controller 4. The memory CPU 11 refers to the true temperature value of the memory chip 100 and performs thermal throttling, for example. Furthermore, after obtaining the true temperature value of the memory chip 100, the control circuit 105 generates a temperature code containing the true temperature value of the memory chip 100 and supplies it to the voltage generation circuit 109. The voltage generation circuit 109 generates various voltages based on the temperature code containing the true temperature value of the memory chip 100. The memory controller 4 in the second embodiment can receive the true temperature value of the memory chip 100 by requesting the temperature of the memory chip 100 from the control circuit 105. That is, the memory controller 4 can obtain the true temperature value of the memory chip 100 without performing temperature correction. Furthermore, in the second embodiment, the voltage generation circuit 109 can generate various voltages based on the true value of the temperature of the memory chip 100. Therefore, the voltage generation circuit 109 can use the true value of the temperature of the memory chip 100 to set the voltage to be applied to the memory chip 100. Specifically, the true value of the temperature of the memory chip 100 can be used to adjust various voltages used during data erasure, data writing, and data reading, and then applied to the memory chip 100. As a result, the memory chip 100 can be controlled by a voltage that matches the temperature of the memory chip 100. (Third Embodiment) In the third embodiment, the same symbols are used for the same components as in the first and second embodiments and the descriptions are omitted. Only the different components are described. Figure 6 is a block diagram showing an example of the internal structure of the memory chip 100 according to the third embodiment. After the power is turned on, the temporary register 104 stores the current adjustment table 30. Before the power is turned on, the current adjustment table 30 is stored in the memory cell array 110 and stored in the temporary register 104 as needed. In the third embodiment, the circuitry in the memory chip 100 further includes a current adjustment circuit 31. Examples of the circuitry in the memory chip 100 include, for example, a control circuit 105 or an input / output control circuit 103, but it is not limited to these. The circuitry in the memory chip 100 may include the current adjustment circuit 31 in all its circuitry, or it may include only one circuit. The current adjustment circuit 31 is connected to one end of the circuitry in the memory chip 100. Current flows through the current adjustment circuit 31 in the circuitry of the memory chip 100. Figure 7 illustrates an example of a current adjustment circuit 31. The current adjustment circuit 31 is composed of a parallel circuit of multiple MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Figure 7 illustrates a parallel arrangement of four MOSFETs, but the number of MOSFETs in the current adjustment circuit 31 is not limited to four. The MOSFETs in the current adjustment circuit 31 can be individually switched on and off. The number of MOSFETs to be switched on in the current adjustment circuit 31 is controlled by the control circuit 105. Figure 9 shows an example of the current adjustment table 30 in Embodiment 3. One item of the current adjustment table 30 is the stress value shown by the stress sensor 107. Another item of the current adjustment table 30 indicates the number of MOSFETs to be turned on in the current adjustment circuit 31. Current adjustment table 30 shows the relationship between the stress value and the number of MOSFETs to be turned on. Current adjustment table 30 indicates that the higher the stress value, the greater the number of MOSFETs to be turned on. That is, the higher the stress value, the smaller the resistance value of the current adjustment circuit 31. In the current adjustment meter 30, the number of MOSFETs to be turned on is pre-input according to the usage environment of the memory chip 100. For example, the number of MOSFETs to be turned on can be input during the manufacturing of the memory chip 100. Alternatively, the number of MOSFETs to be turned on can be input after the memory package 200 is completed. Furthermore, in the current adjustment meter 30, the number of MOSFETs to be turned on can also be individually input according to the circuits connected to the current adjustment circuit 31 in the memory chip 100. Here, the third embodiment describes the steps of the control circuit 105 acquiring the stress value of the memory chip 100 and controlling the current adjustment circuit 31. The control circuit 105 sends a command requesting a stress value to the stress sensor 107. The stress sensor 107 receives the command from the control circuit 105 and sends a signal containing the stress value to the control circuit 105. The control circuit 105 reads the current adjustment table 30 stored in the memory cell array 110 and stores it in the temporary register 104. The control circuit 105 can execute either the instruction to request the stress value or the reading from the current adjustment table 30, or both simultaneously. The control circuit 105 determines the number of MOSFETs to be turned on by referring to the current adjustment table 30 and the stress value. The control circuit 105 turns on an appropriate number of MOSFETs contained in the current adjustment circuit 31. The following describes a memory system without current regulation circuitry. The resistance of the circuitry within the memory chip changes with temperature; therefore, the voltage applied to the circuitry within the memory chip is controlled in a temperature-dependent manner. However, under high stress conditions applied to the memory chip, a lower voltage is applied to the circuitry within the memory chip, resulting in a lower current flow. In the third embodiment, the current flowing in the memory chip 100 can be controlled according to the stress applied to the memory chip 100. Specifically, the greater the stress value, the lower the voltage applied to the circuitry in the memory chip 100 compared to the reference voltage, but at the same time, the resistance value of the current adjustment circuit 31 is also lower. Therefore, an appropriate current value can flow in the circuitry in the memory chip 100. (Structure of Memory Package) Figure 10 is a cross-sectional view showing an example of the internal structure of the memory package 200 according to this embodiment. The memory package 200 includes a packaging substrate 40 and eight memory chips 100 (100_0 to 100_7). For example, the plurality of memory chips 100 are sealed on the packaging substrate 40 with molding resin (not shown). Furthermore, the memory controller 4 of Figure 1 is omitted from the illustration in Figure 10. Also, although there are eight memory chips 100 stacked, it is not limited to eight and can be appropriately varied. Each memory chip 100 has a plurality of terminals 50 for transmitting and receiving signals with external devices (such as the memory controller 4). Memory chips 100_0 to 100_7 are sequentially deposited on the upper surface of the packaging substrate 40 from the bottom side, with exposed terminals 50, for example, in a stepped manner with the center staggered. Furthermore, the terminals 50 of each memory chip 100 are electrically connected to the packaging substrate 40, for example, by gold wires. The memory chip 100 in Figure 1 can be any one of memory chips 100_0 to 100_7, or it can be considered as a whole corresponding to memory chips 100_0 to 100_7. Each memory chip 100 includes a stress sensor 107. The stress sensor 107 can be manufactured together with the memory cell array 110 or control circuitry 105 and integrated on the packaging substrate 40. Alternatively, the stress sensor 107 can be mounted on the memory chip 100 in a form that is embedded in the packaging substrate 40. Furthermore, it is undeniable that this invention is not limited to the embodiments described above, but can be modified in various ways without departing from the spirit of the invention. Although several embodiments of the invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and similarly, are also included within the scope of the invention described in the claims and its equivalents. [Related Applications] This application enjoys priority based on Japanese Patent Application No. 2024-028039 (filed on February 28, 2024). This application incorporates the entire contents of that basic application by reference. 3: Memory System; 4: Memory Controller; 5: NAND Memory; 10: NAND I / F; 11: Memory CPU; 12: RAM; 20: Stress Correction Table; 30: Current Adjustment Table; 31: Current Adjustment Circuit; 40: Packaging Substrate; 50: Terminals; 100 (100_0, 100_1, 100_2, 100_3, 100_4, 100_5, 100_6, 100_7): Memory Chip; 101: Input / Output I / F; 102: Control Signal Input I / F 103: Input / output control circuit 104: Temporary register 105: Control circuit 106: Temperature sensor 106a: BGR circuit 106b: ADC circuit 107: Stress sensor 107a: Resistor 107b: Measurement unit 107c: Control unit 109: Voltage generation circuit 110: Memory cell array 200: Memory package ALE: Address latch enable signal BCE: Chip enable signal BDQS: Complementary signal to data strobe signal BRE: Complementary signal to read enable signal BWE: Write enable signal BWP: Write protection signal CLE: Instruction latch enable signal DQ0~DQ7: Data input / output lines DQS: Data strobe signal RE: Read enable signal Figure 1 is a block diagram showing an example of the configuration of the memory system according to the first embodiment. Figure 2 is a block diagram showing an example of the configuration of the memory chip included in the memory system according to the first embodiment. Figure 3 is a block diagram showing an example of the configuration of the stress sensor included in the memory system according to the first embodiment. Figure 4 is a block diagram showing an example of the configuration of the memory system according to the second embodiment. Figure 5 is a block diagram showing an example of the configuration of the memory chip included in the memory system according to the second embodiment. Figure 6 is a block diagram showing an example of the configuration of the memory chip included in the memory system according to the third embodiment. Figure 7 is a diagram showing an example of the current adjustment circuit included in the memory system according to the third embodiment. Figure 8 is a diagram showing an example of the stress correction table included in the memory system according to the embodiment. Figure 9 is a diagram showing an example of the current adjustment table included in the memory system according to the third embodiment. Figure 10 is a cross-sectional view showing an example of the internal configuration of the memory package according to the embodiment. 3: Memory System 4: Memory controller 100: Memory Chip 101: Input / Output (I / F) 102: Control signal input I / F 103: Input / output control circuit 104: Temporary Register 105: Control Circuit 106: Temperature sensor 106a:BGR circuit 106b: ADC circuit 107: Stress Sensor 109: Voltage Generation Circuit 110: Memory Cell Array ALE: Address latch enable signal BCE: Chip Enable Signal BDQS: Complementary signal of data gating signal BRE: Read out the complementary signal of the enable signal BWE: Write enable signal BWP: Write Protection Signal CLE: Instruction Latch Enable Signal DQ0~DQ7: Data input / output lines DQS: Data Gating Signal RE: Read out the enable signal

Claims

1. A memory system comprising: a memory chip and a memory controller; the memory chip comprising: a memory cell array; a temperature sensor capable of outputting first temperature data; a stress sensor capable of outputting first stress data; a correction circuit capable of generating second temperature data from the first temperature data based on the first stress data; and an interface capable of outputting the second temperature data to an external source; the memory controller comprising: a processor that, based on the second temperature data received from the memory chip, controls: writing data to the memory cell array, reading data from the memory cell array, or erasing data already written to the memory cell array.

2. The memory system of claim 1, wherein the memory chip further comprises a stress correction table referenced when correcting the first temperature data, and the correction circuit generates the second temperature data that corrects the first temperature data using the first stress data and the stress correction table.

3. The memory system of claim 2, wherein the memory chip further comprises a register, and the register stores the stress correction table, the first temperature data and the first stress data.

4. The memory system of claim 1, wherein the stress sensor has a piezoresistive element, and the stress sensor uses the piezoresistive element to output the first stress data.

5. The memory system of claim 1 further includes a voltage generating circuit, wherein the voltage generating circuit generates a voltage based on the second temperature data and applies the generated voltage to the memory cell array.

6. The memory system of claim 1 further comprises: a current adjustment circuit connected in parallel and capable of changing current, and a current adjustment table referenced when changing the resistance value of the current adjustment circuit, wherein the correction circuit uses the first stress data and the current adjustment table to control the resistance value of the current adjustment circuit.

7. The memory system of claim 1, wherein the memory controller controls the memory system in a first mode or a second mode based on the second temperature data.

8. A memory system comprising: a memory chip including a memory cell array, a temperature sensor capable of outputting first temperature data, and a stress sensor capable of outputting first stress data; and a memory controller including a processor that receives the first temperature data and the first stress data from the memory chip, generates second temperature data based on the first temperature data and the first stress data, and controls, based on the second temperature data: writing data to the memory cell array, reading data from the memory cell array, or erasing data already written to the memory cell array.

9. The memory system of claim 8, wherein the stress sensor has a piezoresistive element, and the stress sensor uses the piezoresistive element to output the first stress data.

10. The memory system of claim 8, wherein the memory controller controls the memory system in a first mode or a second mode based on the second temperature data.

11. The memory system of claim 10, wherein in the first mode, the memory controller controls the memory system at a first processing speed, and in the second mode, the memory controller controls the memory system at a second processing speed, wherein the second processing speed is less than the first processing speed.

12. The memory system of claim 8 further comprises volatile memory, wherein the volatile memory stores the stress correction table referenced when correcting the first temperature data, the first temperature data, and the first stress data.

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