Mask image optimization based on multi-layer wafer image analysis

Abstract

Some embodiments provide a method for optimizing a mask layout for manufacturing a mask used to fabricate an integrated circuit (IC) comprising multiple layers of components. The method receives a mask layout including mask images of a set of first-layer components corresponding to the IC, the first-layer components being adjacent to second-layer components. The method generates a first wafer image including representative images predicted to be manufactured for use in the first layer of the IC, this prediction being based on the received mask images corresponding to the first layer. Based on the positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image of the second layer, the method modifies at least one mask image in the set of mask images of the first layer.

Description

Prior Art

[0001] In lithography, optical proximity and process variations / effects need to be corrected, and the variation across production conditions needs to be minimized to achieve optimal wafer printing. In the past, efforts to correct for these effects started with simple variations, adding a hammer head at the line-end to prevent circuit end shortening. This first generation of correction is called rule-based optical proximity correction (OPC). Later, as wafer feature sizes continued to shrink, OPC became more complex and evolved into a model-based approach. Additional patterns were added to the mask to improve the wafer process window, a measurement method that is adaptive to production variability. At about the same time, the concept of inverse lithography technology (ILT) was introduced. ILT is a mask layout optimization, a mathematically rigorous inverse approach to determine the mask shape that will produce the desired on-wafer result. ILT has been explored and developed over the past three decades as the next generation of OPC, providing several solutions to the challenges of advanced node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of the lithography toolkit known as resolution enhancement technology.

[0002] Given a known forward transformation from mask layout to image (representing a wafer) for a particular lithography process, mask layout optimization (e.g., ILT) computes an optimized mask image of a desired wafer target with the best pattern fidelity and / or the largest process window. The optimal solution for mask layout optimization may not be limited to simple heuristic modifications of the target mask layout. More specifically, mask layout optimization explores the optimal solution that is very different from the original mask layout. To perform mask layout optimization, some approaches define the following mathematical functions and operators: Mask image function: ψ Target mask image pattern: Φ Forward operator: f Wafer image pattern:ω

[0003] The forward operator contains a set of wafer simulation operations to convert the mask pixel image to the wafer image (e.g. electromagnetics of the three-dimensional (3D) mask image, optics of the illumination and projection lenses, behavior of the photoresist, dose and focus conditions, aberrations, etc.). ω = f(ψ), and (1) ψ *= f -1(Φ) (2) where ψ * is the optimized mask image function. However, because the forward operator f is of many-to-one form (i.e., multiple different mask images will produce the same wafer image), Equation 1 does not have a well-defined inverse function. Moreover, for typical target mask image patterns Φ (e.g., drawn layouts, layouts with Manhattan geometry and sharp corners), there is no mask image function ψ that satisfies Φ = f(ψ). These problems can be solved by recasting the inverse problem as an optimization problem to find the best solution to the problem from a set of possible options given the desired results and constraints.

[0004] Optimization attempts to find a solution that is as close to the optimal solution as possible within reasonable computational time constraints. A merit function (also called a loss function, cost function, energy function, or Hamiltonian (analogous to quantum mechanics, where the Hamiltonian is an operator corresponding to the total energy of the system)) is defined and labeled H(ψ). This function indicates the quality of the solution (i.e., how well the mask image produces a simulated wafer image that is as close as possible to the target wafer image). A traditional example of such a loss function is: (3)

[0005] The loss function is the integral of the absolute value of the difference between the wafer image and the target wafer image over the area of the region of the wafer image. The realities of mask production may impose various constraints. For example, two disjoint chrome regions are separated by a minimum distance and a chrome line has a minimum width. These constraints can be addressed by defining a subspace of the full solution space of the mask image function and restricting the solution to this subspace. However, despite these constraints, pattern-dependent heuristics and the ability to extensively explore broad regions of the solution space are currently not included in mask layout optimization. This means that conventional mask layout optimization frequently results in mask layouts that cannot be predicted by a knowledgeable lithologist. An example is the problem of placement of sub-resolution assist features (SRAFs). Prior to mask layout optimization, SRAFs are placed empirically and carefully and are fixed during the computation of the rest of the mask image for the mask layout. In contrast, mask layout optimization determines the best SRAFs and the rest of the mask layout simultaneously.

[0006] Current mask pattern optimization schemes are based on local search heuristics that seek solutions that are close to the local minimum, although not necessarily globally optimal. Furthermore, since there are several nearly optimal solutions, a solution can be selected from a set of solutions to be output to the optimization. Typically, once all constraints are considered, such that features are larger than a certain size to satisfy mask manufacturing requirements, maximum depth of focus (DoF) is desired, and SRAFs do not cause stray patterns to be printed on the wafer, a solution that satisfies the constraints is unique in mask layout optimization.

[0007] Typically, conventional mask image optimization schemes optimize a cost function similar to the loss function H (Equation 3) described above. In some cases, mask image optimization simplifies its calculations by using certain approximations or reducing the number of variables. For example, FIG. 1 illustrates an example of a mask image, a simulated wafer profile and its target, a cost function, and a cost gradient at the beginning of an optimization. Clearly, the wafer profile has not reached the wafer target, the cost function is non-zero, and the cost gradient is non-flat. FIG. 2 illustrates an example of a mask image, a simulated wafer profile and its target, a cost function, and a cost gradient at the end of an optimization. At this point, the simulated wafer profile has reached the wafer target, the cost function is close to zero, and the cost gradient is flat. Summary of the invention

[0008] Some embodiments provide a method for optimizing a mask layout for producing masks used to manufacture an integrated circuit (IC) by defining multiple layers of IC components on a wafer. To optimize a mask layout having multiple sets of mask images corresponding to multiple different layers of the IC, the method iteratively (i) uses a mask image of one of the layers to generate a simulated wafer image of the layer and (ii) modifies the set of mask images of the layer to improve the position and shape of the manufactured IC components of the layer based on the simulated wafer image of the layer while considering components of at least another layer of the IC (e.g., by comparing the shape of the optimized layer with the shapes of one or more other layers). That is, the mask optimization process for a given layer considers not only the predicted manufacturing shape of the layer, but also how the predicted manufacturing shapes relate to the shapes of other layers (e.g., the predicted manufacturing shapes of interconnect segments in a metal layer and the predicted manufacturing shapes of through holes used to connect the interconnect segments to IC components in other metal layers).

[0009] To perform mask optimization (e.g., as part of a mask production operation in an overall electronic design automation (EDA) process), some embodiments perform an iterative optimization process for each layer. The mask production tool initially generates a mask layout with multiple mask images for each layer of a completed design layout (which specifies the intended design of the IC to be manufactured). The mask layout defines a set of masks that will be manufactured and used to manufacture the IC by shining light through transparent areas of the masks onto a substrate coated with photoresist. The chemical structure of the photoresist makes the material easier or more difficult to remove (depending on whether a positive or negative photoresist is used) so that when additional steps (e.g., photoresist development, etching) are applied, the desired pattern remains on the substrate.

[0010] The iterative optimization process simulates the shape that will be manufactured using the mask to generate one or more simulated wafer images. Some embodiments generate a single simulated wafer image, while other embodiments generate multiple wafer images to account for various process errors. Such process errors include misalignment (where one layer is slightly shifted relative to other layers due to misalignment of the mask relative to the wafer during manufacturing) and process variation errors that can result in different sizes (and slightly different shapes) of the manufactured parts. Such process variations can result from, for example, the depth of focus and / or exposure intensity when passing light through the mask during the wafer production process, or from the dose used during the mask making process.

[0011] These simulations can be performed using lithography simulations (i.e., simulations of the various manufacturing steps), or using machine trained networks (e.g., neural networks) that reproduce the effects of such simulations. Once a simulated wafer image is generated, the simulated wafer image can be compared to a target (ideal prediction) wafer image based on the design layout. In some embodiments, the target wafer image can reproduce the design layout but also introduce rounded corners and similar curved features (true straight lines and sharp corners may not be practically manufacturable at high resolution) using, for example, Gaussian convolution, low pass filtering, etc.

[0012] In addition to comparing the simulated wafer image to the target wafer image and attempting to modify the mask image so that the simulated wafer image matches the target wafer image, some embodiments incorporate into the optimization process considerations the multi-layer interfaces (i.e., interfaces that include IC components on both the layer and another layer and that necessitate overlap of components on these separate layers) across the layer being optimized. That is, the mask image is not only modified to reduce the difference between the simulated and target wafer images, but is also modified to ensure that the overlap between these IC components on different layers is resilient to various process variations.

[0013] Some embodiments perform this optimization as a gradient descent problem. Some such embodiments use a loss function with a first single layer term and a multi-layer aware term, where the first single layer term applies a cost to the difference between the simulated and target wafer images, and the multi-layer aware term applies a cost based on the adaptability of multi-layer overlap. Other embodiments use a loss function with a single layer term, where the single layer term has individual components that are weighted based on the importance of different regions to one or more MLIs (multi-layer interfaces). At each iteration of the optimization process, the gradient of the loss function with respect to mask image shapes (or mask image pixels) determines how to modify these mask image shapes.

[0014] Various different techniques may be used in different embodiments to consider different layers of the IC when optimizing the mask image. For example, some embodiments compare only the simulated wafer image of the primary layer (the layer being optimized) and the target image of the primary layer while considering the MLI of other layers. Other embodiments compare not only the simulated wafer image of the primary layer and the target wafer image, but also the target wafer image of the primary layer and the images of other layers. The images of other layers may be simulated images of the other layers based on the mask layout of the other layers (i.e., one or more simulated images of each other layer) or idealized images (e.g., based on the design layout of the other layers).

[0015] Different embodiments also perform different types of comparisons. For example, when comparing simulated and target wafer images of a primary layer, some embodiments determine the similarity and / or difference between the two images. Specifically, some embodiments attempt to match the outline of the simulated wafer image with the outline of the target wafer image. When comparing a shape in the simulated wafer image of the primary layer with a shape in the image of an adjacent layer, some embodiments determine the intersection between the primary layer shape and the adjacent layer shape (e.g., the area of the intersection). Some embodiments determine the correlation between the two shapes (e.g., the goal of optimization is to increase this correlation). Some embodiments determine the similarity and / or difference between two shapes when performing a comparison between shapes on different layers.

[0016] When performing optimization of a primary layer while also considering other layers through the presence of MLI, some embodiments treat overlapping regions and non-overlapping regions differently. That is, regions of the primary layer shape that are associated with MLI are treated differently during optimization than regions of the same primary layer that are not affected by MLI. For example, some embodiments optimize masks to produce primary layer features that have the greatest overlap area with their corresponding features in other layers. Other embodiments identify overlapping regions and are more rigorous in ensuring that these regions more closely match the target wafer image than non-overlapping regions.

[0017] Additionally, some embodiments distinguish the importance of different portions of a shape within an overlap region. Some embodiments recognize that certain points along a shape within an overlap region are more critical than other points within the overlap region. For example, in the case of a through hole located at the corner of a curved line segment, the edge of the through hole along the edge of the line segment may be considered more critical than the edge along the interior of the line segment.

[0018] As previously mentioned, some embodiments use a loss function term that compares the simulated image of the primary layer to the target image of that layer while taking into account overlap with other layers. Specifically, some embodiments do not treat all differences between the simulated image and the target image equally, but rather weight different portions of the simulated wafer shape more heavily based on their relevance to the MLI. In some embodiments, regions along each contour (e.g., each pixel or subset of those pixels) are assigned a weight value that weights the cost incurred based on that region being different from the target image. Overlapping regions are assigned higher weight values than non-overlapping regions, and in an overlap, more critical regions are assigned higher weight values than less critical regions. The loss function thus weights differences in more critical regions with the highest weight, and thus the optimization process is biased to focus primarily on aligning the most critical regions to the solution of the target image (i.e., the mask image).

[0019] Other embodiments use both a loss term that compares the simulated image of the primary layer to the target image and an additional loss term that takes the MLI into account. Different embodiments may apply different weights to the two loss terms. In some such embodiments, all portions of the simulated wafer shape are treated equally in the first (single layer) loss term. Different embodiments use different techniques to compute an additional (multi-layer aware) loss term that involves comparing the shape of features on the primary layer to the shapes of features on other layers.

[0020] For example, for a given MLI including a shape in a primary layer and a shape in another layer, some embodiments calculate the intersection of these shapes and define a cost for the MLI based on the area of the intersection (e.g., inversely proportional to the intersection). Some embodiments generate a number of simulated wafer images of the primary layer (and in some cases simulated wafer images of other layers) based on different possible misalignment and / or process variation errors. For at least a subset of these wafer image pairs (i.e., a simulated wafer image of the primary layer and a simulated or optimized wafer image of the other layer), an optimizer calculates the intersection of the two shapes. Different embodiments use the minimum of these intersections as the overlap area (representing the worst case), calculate the logical intersection of all intersection areas as the overlap area (representing a very unlikely but potentially worse case), or calculate the average area (representing an expected area), and then determine the cost based on the calculated area.

[0021] Other embodiments use a set of evaluation points for each shape in the primary layer that is part of the MLI. In this case, some embodiments weight the evaluation points based on whether they are part of an overlap region of the shapes and thereby influence the MLI. For evaluation points within the overlap region, some embodiments designate multiple points as being more or less critical to the overlap (as described above for assigning weights to multiple points when comparing the target image). Weights are assigned to the evaluation points based on these different classifications, and the evaluation points for each shape are compared to simulated wafer images of the appropriate adjacent layer. In some embodiments, an optimization procedure evaluates whether each evaluation point is on the correct side of the boundary of a shape in another layer (e.g., inside or outside the shape). Some embodiments assign a cost to each evaluation point, and these costs are then weighted (i.e., using the assigned weights).

[0022] Still other embodiments may use other different techniques to calculate the loss function terms that take into account the MLI. For example, some embodiments calculate tolerance regions for each main layer component shape in the simulation area, and the tolerance regions are used to restrict the boundaries of the main layer shape (by assessing the cost of the main layer shape that exceeds the tolerance region). Some embodiments define the tolerance region for a given main layer shape based on the position of the shapes in the other layers (the other layers that form the MLI with the main layer shape) and the shapes (and the shapes of the main layer components). Under this framework, the main layer shape can be anywhere within the boundaries of the tolerance region (although the position of the main layer shape is still restricted based on the single layer cost). Some such embodiments do not assess the cost of the main layer shape that is restricted to the tolerance region, and then assess additional costs based on the extent to which the main layer shape exceeds the tolerance region.

[0023] The above description is about modifying a primary layer at once while taking into account the shape of the primary layer and the relationship of the other layers. In some embodiments, these other layers may be optimized prior to the multi-layer aware optimization process (e.g., using an initial single-layer process that does not take into account the other layers). In other embodiments, multiple layers are optimized at once. In this case, the optimization process does not modify a single layer of the mask layout at each iteration, but rather modifies the mask images of multiple layers at once.

[0024] The above invention content is used as a brief introduction to some embodiments of the present invention. It is not intended to be an introduction or overview of all the inventions disclosed herein. The following embodiments and the drawings referenced in the embodiments will further describe the embodiments described in the invention content and other embodiments. Therefore, in order to understand all the embodiments described herein, it is necessary to read the invention content, embodiments, drawings and claims in full. In addition, the claimed subject matter is not limited by the illustrative details in the invention content, embodiments and drawings. Simple diagram description

[0025] The novel features of the present invention are described in the appended claims. However, for illustrative purposes, several embodiments of the present invention are described in the following drawings.

[0026] [FIG. 1] shows an example of a mask image at the beginning of an optimization, its simulated wafer profile and its target, cost function, and cost gradient. [FIG. 2] illustrates a mask image at the end of an optimization, its simulated wafer profile and its target, cost function, and cost gradient. [Fig. 3] A conceptual diagram showing the different types of shapes described in this application. [FIG. 4] A conceptual diagram shows an example portion of an IC including three adjacent layers. [Figure 5] shows an example of a design with a through via overhang DRC violation. [Figure 6] illustrates an example of a through hole overhang design, showing the nominal, inner, and outer profiles. [Figure 7] shows an example of a through hole overhang design, showing only the inner contour. [FIG. 8] illustrates an example of the intersection or overlap between the through hole contour and the inner metal contour. [FIG. 9] illustrates an example of a through hole profile and an inner metal profile for an example double misalignment situation. FIG. 10 shows an example of an inner through hole profile and an inner metal profile of another example misalignment situation. [FIG. 11] A conceptual illustration of an example of a high-level mask image optimization process having an input corresponding to a single layer to produce an optimized mask image for the single layer. [FIG. 12] A conceptual illustration of an example of an iterative mask image optimization process. [FIG. 13] illustrates an example design layout of a metal layer of an IC. [FIG. 14A] to [FIG. 14B] respectively illustrate a mask image of a metal layer before and after at least one iteration of mask image optimization. [FIG. 15A] to [FIG. 15B] respectively illustrate an example mask image of a perforated layer before and after at least one iteration of optimization. [FIG. 16] A conceptual illustration of an example of a high-level mask image optimization process that uses inputs corresponding to multiple layers to produce an optimized mask image for a single layer.

[0014] Figure 17 conceptually illustrates a process of performing wafer simulation to optimize a mask layout of a single layer of an IC design layout in some embodiments. [FIG. 18] illustrates an example of a curved edge converted into a pixel dose map through rasterization. [FIG. 19] Conceptual illustration of an optimizer modifying the profile of a circular metal plate shape. [FIG. 20] A conceptual illustration of a process for comparing a layer of simulated images with a layer of target images while taking overlap into account in some embodiments. [FIG. 21] Conceptual illustration of a multilayer interface between adjacent layer shapes having a set of evaluation points identified along the contours of the primary layer shapes in a simulated wafer image. [FIG. 22] A conceptual diagram illustrating another example of selection of evaluation points for a through hole shape forming a multi-layer interface with a line segment shape.

[00106] Figure 23 conceptually illustrates a process for assigning costs to MLIs in simulated wafer images based on the intersection of components of the MLIs in some embodiments. [Figure 24] illustrates an example of the adaptability and susceptibility of multiple different intersections between components on multiple layers to misalignment. [FIG. 25] Conceptually illustrates a process of using multiple evaluation points for each of multiple shapes to compare a simulated image of a primary layer with other images in accordance with some embodiments. [FIG. 26] A conceptual illustration of a through hole shape and a line segment shape, wherein the through hole is slightly closer to the end of the line segment and the through hole shape has an evaluation point. [FIG. 27] A conceptual illustration of a simulated through-hole shape partially located outside a line segment shape of another layer.

[0028] Figure 28 conceptually illustrates a process of using a tolerance range of shapes in a layer of a simulated wafer to calculate the cost of MLIs that include the shapes in that layer in some embodiments. [Fig. 29] A conceptual diagram illustrating an example of an elliptical tolerance zone overlapping a through hole shape. [FIG. 30] A conceptual diagram illustrating an example of the tolerance range of a through hole shape connecting two conductive lines in different metal layers. [FIG. 31] A conceptual illustration of an example of a multilayer interface including an intersection of a metal layer and a through-hole in an adjacent through-hole layer. [Figure 32] Conceptually illustrates an example of a high-level mask image co-optimization process that uses input corresponding to multiple layers to produce optimized mask images for the multiple layers. [FIG. 33] A conceptual diagram of a process for performing wafer simulation in some embodiments. [Figure 34] Conceptually illustrates an example of a high-level mask image optimization process of some embodiments, which uses input corresponding to multiple layers and simultaneously utilizes deep learning to produce a single-layer optimized mask image. [FIG. 35] Conceptual illustration of using a neural network to produce an output of a wafer image from a set of mask pixel images. [FIG. 36] Conceptual illustration of multiple networks, each trained to generate a different wafer image in response to a different mask pixel image received as input. [Figure 37] illustrates a novel scheme for mask image optimization using a wafer-based simulated neural network.

[0038] Figure 38 conceptually illustrates a process of generating training data for training one or more MT networks to generate wafer images based on a mask pixel image of a mask layout of an IC design or a portion of an IC design in some embodiments. [Figure 39] Conceptually illustrates a process of training configurable parameters of an MT network having a plurality of processing nodes of some embodiments, wherein the MT network having a plurality of processing nodes is used during optimization of a mask layout produced for a design layout of an IC. [Figure 40] A process of the overall EDA flow of some embodiments is conceptually illustrated. [Figure 41] A computer system is conceptually illustrated, and some embodiments of the present invention are implemented using this computer system. Implementation

[0027] In the following embodiments of the present invention, many details, examples and embodiments of the present invention are described. However, it is clear and obvious to those skilled in the art that the present invention is not limited to the described embodiments and that the present invention can be practiced without some of the specific details and examples discussed.

[0028] Some embodiments provide a method for optimizing mask layouts used to produce masks used to manufacture integrated circuits (ICs) by defining multiple layers of IC components on a substrate. To optimize a mask layout having multiple sets of mask images corresponding to multiple different layers of the IC, the method iteratively (i) uses a mask image of one of the layers to generate a simulated wafer image of the layer and (ii) modifies the set of mask images of the layer to improve the location and shape of the manufactured IC components of the layer based on the simulated wafer image of the layer and the simulated wafer image of at least one other layer of the IC. That is, the mask optimization process for a given layer considers not only the predicted manufacturing shape of the layer, but also how those predicted manufacturing shapes relate to the predicted manufacturing shapes of other layers (e.g., the relationship between the predicted manufacturing shape of interconnect segments in a metal layer and the predicted manufacturing shape of through holes used to connect the interconnect segments to IC components in other metal layers).

[0029] Before further describing the mask optimization operations of some embodiments, certain aspects of IC design and manufacturing will be described. An IC includes a set of multiple layers that are typically fabricated on a substrate. These layers typically include the substrate layer itself (the base semiconductor layer of the IC), one or more device layers (where the transistors are located), one or more metal layers (also called interconnect layers or routing layers, through which metal interconnects pass in a plane), and one or more interposer layers. Interposer (or dielectric) layers are spaced between the device and metal layers and allow for z-axis connections (for example, the plane of the metal layer is parallel to the xy plane). These interposer layers include a via layer between a pair of metal layers and a contact layer between the device layer and the metal layer, and vias and contacts are two examples of z-axis connections that pass between at least two layers of an IC.

[0030] The design of these layers is defined by a design layout of the IC in some embodiments. In some embodiments, the design layout includes the layout of each layer (e.g., each device layer, each routing layer, and / or each via layer). For a given layer, the design layout defines the shape of the components (e.g., interconnect segments, vias, etc.) defined on the layer.

[0031] In order to manufacture the layers and their components based on the design layout, one or more masks (referred to herein as "masks") are manufactured and used. A mask is an opaque plate with transparent areas that allow light to enter through a defined pattern. A mask layout corresponding to the transparent areas of the mask is determined. In some embodiments, the mask layout has an overall mask image for each device or wiring layer. The overall mask image for each layer can be decomposed into one or more individual mask images, such as by using a coloring technique that assigns one or more different colors to each shape in the overall mask image to assign shapes to individual mask images having the color. Each mask image for each layer can be used to produce a mask, which is then used to manufacture the components of that layer.

[0032] That is, just as the design layout includes multiple design layers corresponding to the final manufactured IC layers (also referred to herein as wafers), the mask layout includes multiple mask layers corresponding to the final manufactured masks (which are themselves used to manufacture IC layers). In some embodiments, each layer of the design layout corresponds to a layer of the mask layout, and the mask layout may include one or more mask images.

[0033] The mask image defines the mask layout in the geometric domain and displays a pattern of transparent areas, including primary transparent areas where the designed components will be manufactured and secondary transparent areas (e.g., SRAFs) that will assist in the manufacturing of the designed components (i.e., by allowing more light to pass through the mask). In some embodiments, the mask image is rasterized into a mask pixel image that defines the mask layout in the pixel domain. It should be understood that due to the nature of the masking process, the mask shape (1) does not necessarily correspond to the manufactured IC components (i.e., to the design layout shape) in a 1:1 ratio and (2) cannot always be simply related to individual IC components (i.e., to the design layout shape) by human observation.

[0034] FIG. 3 conceptually illustrates different types of shapes described in the present application. These different types of shapes include design layout shapes 305, target wafer image shapes 310 (a predicted shape), mask layout shapes 315, and simulated wafer image shapes 320 (another predicted shape). Design layout shapes 305 are shapes that are a portion of an actual design layout (e.g., an actual design layout output by a physical design process). In many cases, these shapes are rectilinear shapes (i.e., having straight lines, and in some such cases, only straight lines at specific angles relative to each other). In other examples, design layout shapes 305 may have curved features (i.e., at least some contours of the shape may be curved).

[0035] From each design layout shape 305, a target wafer image shape 310 can be generated. In some embodiments, the target wafer image shape 310 predicts a shape that is closest to the design layout shape 305 and can be physically manufactured. In some embodiments, at high resolution, angled corners (e.g., right angle corners of the design layout shape 305) cannot be physically manufactured. To generate the target wafer image shape 310, some embodiments may use various corner rounding algorithms (e.g., low pass filter and / or Gaussian convolution). These target wafer image shapes are used as the ideal output of the wafer simulation process during mask optimization.

[0036] The mask layout shape 315 is also generated from the design layout shape (or from the target wafer image shape) in a mask production process. In many cases, the mask layout shape 315 does not closely resemble the specific design layout shape 305. In addition, as shown in this case, sometimes multiple separate shapes are used to manufacture a single IC component corresponding to a single design layout shape 305. In certain cases, various small features, other than smooth-edged shapes, may be added to the mask layout shape 315 to better manufacture the IC component. In some cases, very small shapes called sub-resolution assist features (SRAFs) may be included in the mask layout. In addition, due to the nature of IC manufacturing and the very small distances involved, a mask layout shape 315 designed primarily for the manufacture of one IC component may affect the shapes of other nearby IC components.

[0037] During the iterative mask optimization process, the mask layout shape 315 is iteratively modified to determine the shape of the manufactured component that will best result in matching the design layout shape 305 (or at least matching the target wafer image shape 310). Part of this mask optimization process includes wafer simulation, in which various techniques are used to generate a simulated wafer shape 320 based on the current wafer layout shape. As described in more detail herein, the wafer simulation process may use lithography simulation in some embodiments, which simulates various lithography operations (e.g., exposure, photoresist development, and etching) used to use masks to manufacture IC layers. Other embodiments use a machine trained network (e.g., a neural network) to generate the simulated wafer shape 320 from the mask layout. The goal of the iterative mask optimization is to arrive at the mask layout shape 315. When the mask layout shape 315 is provided to the wafer simulation process, the mask layout shape 315 will result in a simulated wafer shape 320 that matches the target wafer image shape 310.

[0038] Masks generated by mask optimization are used to fabricate one or more layers of an IC. In some embodiments, an IC layer corresponds to a set of one or more masks of a mask layout, such that the IC layer is fabricated using the set of masks. In some such embodiments, a mask is used to fabricate at least a portion of two or more layers. Mask simulation is the generation of a mask image (or mask pixel image) to simulate the characteristics of the corresponding mask when it is fabricated. Mask optimization is the modification of one or more mask images of a mask layout to arrive at a resulting mask layout that produces an optimized mask. In some embodiments, mask optimization is performed using wafer simulation, which will be described below.

[0039] A substrate is a base plate used to package bare IC dies. A wafer is an example of a substrate and is a thin slice of semiconductor (e.g., silicon) material used to make ICs. Light is shone through a mask (i.e., through a transparent area of the mask) onto the wafer to make a layer of ICs on the wafer. In some embodiments, light is shone through multiple masks (one mask at a time) to make a layer of ICs. This process involves the application of a photoresist to the substrate so that after light is shone through one or more masks of a layer, the areas that received the light have different chemical properties than the areas that did not receive the light. Wafer simulation is the generation of one or more mask pixel images of one or more wafer images (e.g., wafer pixel images, wafer outline images) based on a mask image rasterization from a mask layout to simulate the shapes that would be produced on the wafer when manufactured based on the mask layout.

[0040] A via is a small hole that passes through one or more via layers to intersect a conductor on each adjacent metal layer (e.g., directly with an interconnect segment or with a via pad connected to an interconnect segment). A via is an example of a z-axis component, specifically a z-axis connection that passes between at least two layers. Another example of a z-axis component is a z-axis capacitor, where metal components in two layers do not physically touch but form a capacitor.

[0041] In some embodiments, the through-holes are plated with metal (e.g., copper) to form electrical connections through insulating layers. Contact layers are similar to through-holes, but rather than connecting metal layers to other metal layers, contact layers connect metal (conductor / interconnect) layers to device layers. That is, through-holes refer to z-axis components that connect interconnects on different metal layers (e.g., lines representing conductors) and that connect higher-level interconnects to circuit elements, while contacts refer to z-axis components that connect portions of circuit elements on an IC substrate and one or more lower metal layers (e.g., metal layer 1) to form circuit elements (e.g., to form transistors). Because through-holes and contacts connect portions of multiple layers together, it is important that the metal layer components properly cover the entirety of the through-holes and contacts (i.e., it is important to have proper overlap for a particular z-axis component).

[0042] When an IC is fabricated, in some embodiments, different layers of the IC may be misaligned. For example, in some embodiments, a first layer of metal is fabricated, and a second layer of vias is fabricated over the fabricated first layer of metal but not aligned to the first layer of metal. Misalignment issues between layers may arise when, for example, different machines are used to fabricate different layers of the IC. When the layers are misaligned, in some embodiments, insufficient overhang of the multilayer interface may occur.

[0043] To ensure proper overhang of multi-layer interfaces, some embodiments consider mask images of multiple layers when optimizing one or more mask images used to fabricate such layers. For example, when optimizing a first metal layer, some embodiments consider one or more mask images of the first metal layer and one or more mask images of an adjacent via layer. This may allow the possibility of insufficient overhang to be minimized or eliminated. Alternatively or concurrently, some embodiments consider one or more mask images of a second metal layer adjacent to the via layer. In such embodiments, the first metal layer is located on one side of the via layer and the second metal layer is located on the other side of the via layer. Such embodiments may optimize the mask of the via layer and / or the second metal layer concurrently or alternatively, i.e., optimization may be performed for one of the three layers at a time or for more than one of the three layers simultaneously.

[0044] Some embodiments of the present invention extend mask image optimization (e.g., Inverse Lithography Technology (ILT) optimization) from a traditional one-layer optimization to a multi-layer optimization process. Traditional mask image optimization operates on one layer at a time and only within the context of that single layer. Any interactions with layers above and below the layer whose mask image or images are being optimized are not considered.

[0045] As described above, ILT is a type of mask layout optimization, which is a mathematically rigorous inverse scheme to determine the mask shape that will produce the desired on-wafer result. Given a known forward transformation from mask layout to image (representing the wafer) for a particular lithography process, ILT calculates an optimized mask image that produces the desired wafer target with the best pattern fidelity and / or the largest process window. The optimal solution for mask layout optimization is not limited to a simple heuristic modification of the target mask layout. More specifically, mask layout optimization explores the optimal solution that optimizes a very different mask layout from the original. To perform mask layout optimization, some embodiments define operators ψ (mask image function), Φ (target mask image pattern), f (a forward operator comprising a set of wafer simulation operations to transform the mask pixel image to the wafer image), and ω (wafer image pattern). Thereby, ω = f(ψ), and ψ * = f -1(Φ), where ψ * is the optimized mask image function. Optimization attempts to find a solution that is as close to the optimal solution as possible within reasonable computational time constraints. In some embodiments, a merit function (also known as a loss function, cost function, energy function, or Hamiltonian) is defined and labeled H(ψ). This function indicates the quality of the solution (i.e., how well the mask image produces a simulated wafer image that is as close as possible to the target wafer image). A conventional example of such a loss function is , i.e., Equation 3 above. This loss function is the integration of the absolute value of the difference between the wafer image and the target wafer image over the area of the region of the wafer image. In some embodiments, one or more additional terms (e.g., wafer images at various operating conditions across the process window (i.e., over- or under-exposure and out-of-focus), normalized wafer image logarithmic slope of the wafer image, robustness to mask image error enhancement factors, or other factors deemed appropriate) are included in the loss function.

[0046] The multi-layer mask image optimization process considers the layers above and / or below (hereinafter referred to as adjacent layers). In particular, when optimizing the mask image for a particular layer, the shapes and process variations produced on multiple silicon wafer interconnect layers are taken into account. This results in an improved mask that is optimized for silicon manufacturability involving multiple layers. In addition, some embodiments provide a method for simultaneously co-optimizing multiple mask images for multiple adjacent layers, which again considers the interaction between adjacent silicon wafer interconnect layers. Additional cost function terms are introduced during iterative mask image optimization (which considers the silicon wafer interaction between the layer being optimized and the adjacent layers). In some embodiments, deep learning (e.g., machine training networks) is used to calculate silicon wafer details for adjacent layers, thereby making the calculation of new loss function terms sufficient to ensure the tractability of the overall optimization loop.

[0047] Discussion throughout this specification is about consideration of Back End of Line (BEOL) interfaces (e.g., vias connecting metal line segments) when optimizing one or more mask images of a mask layout based on wafer simulation. However, one of ordinary skill in the art will appreciate that Front End of Line (FEOL) layer interfaces and / or Middle End of Line (MEOL) interfaces may be considered concurrently or alternatively.

[0048] Some embodiments optimize one or more mask images of a first layer of an IC based on the first layer and one or more additional layers adjacent to the first layer. FIG. 4 conceptually illustrates an example portion of an IC 400 including three adjacent layers 410-430. In this example, three layers 410-430 of IC 400 are illustrated, but IC 400 may include one or more additional layers (e.g., one or more additional via layers and / or metal layers, one or more device layers, etc.). As illustrated, two metal layers 410, 430 are located on either side of a via layer 420. In some embodiments, the via layer 420 passes through an inter-layer dielectric (ILD) (not illustrated) to connect line segments on the two metal layers 410, 430.

[0049] Some embodiments use vias to connect a line segment on the first metal layer 410 to a metal line segment on the second metal layer 430. For example, a via hole 422 is defined on the via layer 420, and via pads 424A-B are respectively defined on both sides of the via hole 422 to connect the first metal line segment 412 on the first metal layer 410 to the second metal line segment 432 on the second metal layer 430. In some embodiments, the via hole 422 passes through the ILD between the two metal layers 410 and 430, and the via pads 424A and 424B are respectively located on the metal layers 410 and 430 to connect the metal line segments 412 and 432, respectively.

[0050] This figure also shows the via hole 422, the via pad 424, and the line segments 412, 432 from a top-down perspective. As shown, the via pad 424 is larger than the via hole 422 so as to completely cover the via hole 422, and the line segments 412, 432 completely cover the via pad 424. In some embodiments, mask optimization is performed to ensure that the via pads of the IC's vias are larger than their corresponding via holes when the via pads are fabricated on the wafer. Alternatively or in addition, in some embodiments, mask optimization is performed to ensure that the interconnect line ends defined on the metal layer (the line ends of the line segments 412, 432 in the metal layers 410, 430) are larger than the via pads to which they are connected (and therefore also larger than the via holes that need to be smaller than the via pads) when the interconnect line ends are fabricated on the wafer. Similar optimization can be performed to ensure that the pads of the contacts are smaller than the line ends to which they are connected and the holes of the contacts are smaller than their pads.

[0051] Some embodiments perform z-axis analysis so that mask layout can be optimized based on the z-axis analysis. The z-axis analysis includes (1) analysis of planar connections of z-axis connections (e.g., vias, contacts) (i.e., analysis of metal line ends and their connected via pads) and (2) analysis of z-axis connections (analysis of via pads and their corresponding via holes). Joint analysis includes jointly analyzing planar and z-axis connections (e.g., analysis of two metal line ends, two via pads, and a via hole at the interface of a single metal via). A simplified joint analysis is performed in some embodiments, which ignores the via pads and performs analysis based only on metal line ends and via holes.

[0052] To optimize one or more mask images of the first metal layer 410, some embodiments consider the mask image of the first metal layer 410 and the mask image of the through-hole layer 420. Some embodiments also consider the mask image of the second metal layer 430 and / or an additional through-hole layer on the other side of the first metal layer 410. To optimize one or more mask images of the second metal layer 430, some embodiments consider the mask image of the second metal layer 420 and the mask image of the first metal layer 410 and / or the mask image of the second metal layer 430. One or both of the mask images of these metal layers may be considered. To optimize one or more mask images of the second metal layer 430, some embodiments consider the mask image of the second metal layer 420 and the mask image of the through-hole layer 420. Some embodiments also consider the mask image of the first metal layer 410 and / or an additional through-hole layer on the other side of the second metal layer 430. Any of these optimizations may include performing a z-axis analysis (analyzing the overhang of wire ends on via pads and analyzing the overhang of via pads on via holes individually), a joint analysis (analyzing the overhang of wire ends on via pads and the overhang of wire ends on via pads on via holes together), or a simplified joint analysis (analyzing the overhang of wire ends on via holes).

[0053] In some embodiments, mask image optimization is performed for each layer 410-430 individually, while still considering the other layers in the mask image optimization of a given layer. That is, to perform mask image optimization for a particular individual layer, a wafer simulation is performed for both the particular layer and one or more other (adjacent) layers (e.g., based on the mask images of the other layers), but only the particular layer is optimized during the process. In other embodiments, two or more of the layers 410-430 are optimized simultaneously, such that the wafer simulation involves mask images of multiple layers, and the mask image modification modifies the mask images of multiple layers simultaneously.

[0054] Mask optimization for IC layers (e.g., layers 410-430) is performed in some embodiments to improve the manufacturability of the IC and to improve one or more masks used in manufacturing the IC so that the masks produce an IC that is as close as possible to the design of the IC (as shown in the design layout of the IC). In some embodiments, Designs For Manufacturability (DFM) rules are also followed, which exist in the form of recommended rules that seek to enhance the quality of the IC design layout from a manufacturability perspective. DFM rules are considered complementary to standard Design Rule Checking (DRC) rules and are generally written into a geometric design space. DFM rules are more conservative based on the design than DRC rules. In addition, in some embodiments, DFM rules are more often not fully followed, and some DFM rules are considered optional based on various factors. If a design layout is not considered to have any DFM rule violations, it is considered to be fully manufacturable or at least satisfactorily manufacturable in some embodiments.

[0055] Various DFM rule scoring methodologies are used in the industry to validate the quality of such layout designs from a manufacturability perspective. In some embodiments, DFM rules are documented for a single layout design layer (e.g., minimum width or minimum spacing of a structure such as a conductor). In some embodiments, DFM rules are documented for multiple patterns within a particular neighborhood or context. DFM rules are also documented for multiple design layers in some embodiments (e.g., rules for minimum multi-layer interface overlap or minimum multi-layer interface overhang for routing in a preferred direction). Here, multiple design layers may include metal layers for interconnect routing as well as via layers. DFM rules are extremely complex in some embodiments. Additionally, DFM rules are subject to various implementation limitations in some embodiments. For example, in some embodiments of a particular design layout, a via closure rule is marked as "violated" at multiple different locations within the design layout, and all locations of such violations are scored equally using traditional geometry-based methods.

[0056] FIG5 shows an example of a design with a via overhang DRC violation. Although this figure shows each via connected to a metal line end on an adjacent metal layer for simplicity, each via is also connected to another metal line end on another adjacent metal layer (i.e., another metal layer on the other side of the via layer). This figure also shows the via hole of each via and does not show the via pad of each via for simplicity.

[0057] In this figure, four via overlap areas are depicted, all marked as insufficient overhang DFM rule violations (indicated by arrows). These violations adequately represent the concerns of manufacturing violations for manufacturing vias, and the variation in manufacturing metal lines and the misalignment between the two layers will combine to make the overlap between the via holes and the metal lines too small. Since these figures represent electrical conductors at the nanoscale, a reasonable overlap between the manufactured via holes and the manufactured wire ends needs to be maintained to obtain a sufficiently good electrical connection. In some embodiments, FIG. 5 is a CAD drawing. The manufactured shapes are generally curved shapes with rounded corners and significantly tapered wire ends. Since the minimum width wire ends are significantly tapered, the manufactured wire ends have sufficient "overhang" to "cover" the manufactured via holes.

[0058] However, these various violations may actually be different from a lithographic point of view, due to the design context or the neighborhood in which they are located. The four via holes shown will generally become more distorted circular when manufactured, and the line ends will be more tapered. Although the CAD drawings are identical to each other, each example of the manufactured via holes and line ends will have significant variation when compared to each other. In this case, the task of mask image optimization is to try to make the results as similar as possible to each other, although some random variation will generally still occur. Although mask image optimization attempts to make these differences disappear, systematic variations (caused by different neighborhoods) caused by the inability of mask image optimization to consistently optimize each case cannot be completely avoided. In some embodiments, given an optimized mask image or set of mask images (e.g., mask layout) prepared for this design, detailed lithography simulations indicate that one of the "failed" closed locations was actually successfully printed during lithography, i.e., achieved adequate via coverage, and should not have been considered a failure at all. Examples are illustrated with reference to Figures 6 to 10.

[0059] In some embodiments, different shapes (e.g., contours) are calculated for each IC component (e.g., line segment, via, contact) to correspond to different sets of process conditions that may occur during actual manufacturing of the IC component. In these embodiments, the different sets of process conditions represent different values of a set of process parameters, and each set of process conditions includes different values of each process parameter.

[0060] The set of process parameters in some embodiments includes one or more process parameters regarding at least one of the depth of focus and the exposure intensity used during the wafer fabrication process. In such embodiments, a different profile is generated for each shape in the simulated wafer image to represent different process parameters that may occur due to variations in the wafer fabrication process (i.e., a mask production process that uses a physical design layout and one or more masks to produce a physical wafer). Alternatively or concurrently, the set of process parameters includes one or more process parameters regarding the dose used during the mask process. In such embodiments, a different profile is generated for each shape in the simulated mask image to represent different process parameters that may occur due to variations in the mask production process (i.e., a mask production process that produces a physical mask from a mask layout).

[0061] Given an arbitrary input design mask reflecting a portion of a design, some embodiments produce multiple images reflecting the entire process at nominal process values and at extreme values or data values reflecting absolute limits (e.g., 1, 2, or 3 standard deviations). Each of these outputs is referred to as a "set" of process conditions or as a process corner, such as a nominal, minimum, or maximum set of process conditions or a process corner.

[0062] Some embodiments generate a plurality of profile sets including a maximum profile (also referred to as an outer profile), a minimum profile (also referred to as an inner profile), and a nominal profile for each shape (e.g., each through hole, each contact, each line segment) of the IC design (these profiles correspond to a set of maximum process conditions, a set of minimum process conditions, and a set of nominal process conditions, respectively). These different sets of process conditions include different values of a specific set of process parameters. For example, in some embodiments, the process parameters may be related to the depth of focus and the exposure intensity used during the wafer production process of the line segment.

[0063] For example, the first set of process conditions in some embodiments represents nominal process conditions of process parameters, including average depth of focus and average exposure intensity. For another example, the second set of process conditions in some embodiments represents maximum process conditions of process parameters, including maximum depth of focus and maximum exposure intensity.

[0064] In other embodiments, the second set of process conditions representing the maximum process conditions includes a minimum depth of focus and a maximum exposure intensity. However, in other embodiments, the second set of process conditions representing the maximum process conditions includes a maximum depth of focus and a minimum exposure intensity. Any combination of process conditions may be used for each of the different sets of process parameters. There may be any number of sets of process conditions, and the sets of process conditions may be used to generate different profiles for each shape of the simulated wafer image.

[0065] FIG6 illustrates an example of a multi-layer interface overhang design, showing the nominal, inner, and outer contours for the nominal, minimum, and maximum process condition sets, respectively. The figure illustrates contours of three sets of metal line ends and via shapes for the multi-layer interface overhang design of FIG5 . Here, contours of the tall narrow metal layer (line segment) shape are illustrated, and the three contours corresponding to the nominal process condition set and the two process extremes are clearly visible, especially near the line tops (the ends of the illustrated rectangles). Similarly, the figure illustrates three contours for each via, which appear similar to concentric circles.

[0066] FIG. 7 shows an example of a multi-layer interface overhang design, showing only the inner contours (i.e., the nominal process condition contours and the maximum process condition contours have been removed). These figures are drawn assuming optimal alignment between the metal line ends and the via holes. In all cases, these via holes tend to be completely overlapped by the metal lines, and the intersection between the metal contours and the via hole contours is shown as a thick circular line in FIG. 8. The top center via, while completely overlapped, has a smaller printed area than the others, which is a potential cause of concern (e.g., increased via resistance).

[0067] However, if via-metal misalignments are introduced during manufacturing, full overlap may not be achieved. FIG. 9 illustrates an example of a possible manufacturing scenario, showing the inner via hole outline and the inner metal outline for a dual misalignment case. Here, the metal layer has been shifted downward, and the via layer has been shifted to the left (relative to the original drawn design (rectangular and square)). As shown, in this scenario, the left edge of the via hole is not completely covered by the left edge of the metal line end, and "clipping" is evident, especially for the leftmost, upper via location. The area of the via hole to the left of the bold dashed line is the uncovered area.

[0068] Other misalignments may also occur during manufacturing. FIG. 10 illustrates an example of a second misalignment scenario, where the metal layer is misaligned to the left and the via layer is misaligned to the top. This time, the area of the via to the right of the bold dashed line is the uncovered area. The metal line ends are misaligned to the left and to the north (i.e., substantially misaligned in the northwest direction). In some embodiments, the via holes are misaligned to the right (i.e., misaligned in the east direction).

[0069] Depending on the degree of misalignment, the directions involved, and the actual shapes of the metal and via profiles being fabricated (shapes at specific locations or contexts), different amounts of via coverage or overlap exist in some embodiments during the actual fabrication of each via example. Due to the way the metal and via are printed, some vias are necessarily more susceptible to coverage issues than others. Alternatively, some vias are more resilient to coverage issues than others. The thick circle line in FIG. 8 shows the amount of via and metal overlap that would be fabricated in an ideal, no-misalignment scenario. Due to the way the metal and via are printed, some vias are also more susceptible to coverage issues with their corresponding via pads than others.

[0070] Due to the way the metal and via layers are printed, different via coverage can occur as a function of adjacent area. The scenario above shows that shapes with more surrounding "white space" have more room to include sub-resolution assist features (SRAFs) in the mask layout, and therefore the sub-resolution assist features are more reliably printed over a variety of process variables. Ignoring the effects of multi-layer decomposition to simplify this discussion, the top, center-most shape has the least amount of surrounding white space, so that appropriate SRAFs may not be inserted during mask image optimization, and thereby may result in reduced via coverage.

[0071] DFM rules that do not consider such neighboring design scenarios often set the rules for the worst case scenario, such as the center-center via in the example of FIG8 . The rules may therefore be overly pessimistic, placing an additional burden on the layout engineer to achieve DFM compliance in specific areas where DFM compliance is not required. In FIG8 , the left, right, and bottom via overlaps should be sufficient due to the high adaptability values. However, an overly conservative design rule set so that the center top via is also adequately covered would require longer overhangs in all cases.

[0072] DRC rules and DFM rules are typically constructed based on knowledge of masks and wafer lithography limitations. They are typically overly pessimistic, and efforts to make such rules more context aware (and thus slightly less pessimistic) have led to an explosion in the size of the rule deck, and thereby the corresponding computational cost when evaluating the rules for a particular design layout. The optimization performed during mask image optimization when optimizing a set of one or more mask images for a layer is performed for a single layer at a time in some embodiments. For example, a simple loss function determined when optimizing a layer is in some embodiments the integral of the absolute value of the difference between the wafer image and the target wafer image over the area of the region of the wafer image. In some embodiments, one or more additional elements are included in the loss function. Examples of such additional elements include wafer images for various operating conditions across the process window (i.e., over or under exposure and out of focus), normalized image log slope of the image, robustness to mask error enhancement factors, etc.

[0073] Due to the considerable computational cost of mask image optimization (albeit for a single layer), mask images optimized by typical known mask image optimization procedures do not explicitly consider adjacent layers above or below the layer being optimized. Thus, conventional mask image optimization does not produce a mask layout that is optimized for manufacturability of a design with respect to silicon wafer shape interactions between multiple layers. Therefore, some embodiments advantageously consider adjacent layers when performing mask image optimization to produce a mask layout that not only meets known single layer requirements, but also improves the manufacturability of the design from a multi-layer perspective. For example, some embodiments improve mask image optimization such that a mask produced for a metal (e.g., routing) layer is fully aware of the impact of manufacturing on an adjacent via layer mask, such that a metal layer mask image is optimized not only from a metal layer manufacturing standpoint, but also from a via closure (adaptability) standpoint. Some embodiments further advantageously perform optimization in a fully context-aware manner (i.e., adjacent layout context of both metal and via layers is fully considered). These embodiments may use z-axis analysis, joint analysis, or simplified joint analysis to optimize the mask image.

[0074] In some embodiments, the mask image optimization process obtains a set of mask images of a layer (e.g., a metal layer) or a set of mask images of a layer stack (e.g., a via-metal-via layer stack or a metal-via-metal layer stack) that are substantially locally optimized at each context-related location to obtain maximum via coverage compliance (e.g., via pad and via hole compliance and / or via pad and metal line end compliance). Alternatively or in addition, the mask image optimization process in some embodiments obtains a mask image (or a set of mask images) such that the sensitivity of each individual via hole to the impact of the via coverage problem is minimized.

[0075] During conventional mask image optimization, in some embodiments, a three-dimensional (3D) representation of the wafer illumination intensity is calculated, comprising a weighted sum of terms. The weight of each term is multiplied across a pixel field (i.e., pixel domain) by a factor related to the difference between a simulated wafer image and a target wafer image. In some embodiments, the loss function terms comprise contributions from various printed image characteristics. An iterative optimization is pursued to reduce the size of the loss function. In computational mathematics, an iterative method is a mathematical procedure that uses an initial value to produce a sequence of improved approximate solutions to a class of problems, where the nth approximation is derived from the previous approximation. An explicit implementation of an iterative method, including termination criteria, is an algorithm for the iterative method.

[0076] FIG. 11 conceptually illustrates an example of a high-level mask image optimization process having inputs corresponding to a single layer to produce an optimized mask image of the single layer. For conventional mask image optimization, the primary inputs are an initial single layer mask 1105 and a target wafer image 1110 (i.e., a wafer image representing how the wafer should look when manufactured using the input mask image). In some embodiments, the target wafer image 1110 is a corner-rounded version of a layout drawn by a designer (also referred to as a design layout). Secondary inputs are process information 1115 of the wafer (e.g., process model, process variability or conditions, etc.) and masking rules that the single layer mask image typically follows. This information is provided to an iterative optimization process 1100, the primary output of which is a single layer mask image 1120, which, when combined with a lithography or forward process, is optimized to produce as close to the input target wafer image as possible.

[0077] In some embodiments, secondary outputs of the optimization process 1100 include wafer spatial images 1125. For example, the secondary outputs in some embodiments include images of the wafer at a nominal set of process conditions. Additional images in some embodiments include images of the wafer at other process conditions (representing wafer images produced in response to manufacturing dose and depth of focus variations) and in some embodiments include indicators of various errors, such as areas where mask image optimization failed to produce sufficient wafer process windows or areas where mask rules were violated.

[0078] FIG. 12 conceptually illustrates an example of an iterative mask image optimization process 1200. There are a variety of known OPC and ILT methods, including the use of deep learning, to infer mask images. Thus, different embodiments may use any of these OPC or ILT methods. As shown, the mask image 1205 (denoted by ψ in the above equation) is converted (at 1210) to a grayscale mask image (i.e., pixel image) using a process called rasterization. This grayscale (rasterized) image is used to perform a set of wafer simulation operations 1212, collectively referred to as the forward operator f in the above equation.

[0079] The forward operator 1212 includes multiple operations, which may vary in different embodiments. In this example, the grayscale mask image is combined with the light source model, mask bias, and 3D effect model (at 1215-1220). The exposure is simulated (at 1225) to obtain a spatial intensity image. Next, the photoresist development and etching operations are simulated (at 1230-1235) to obtain a grayscale wafer image (i.e., a pixel-based wafer image) (at 1240).

[0080] In some embodiments, contour operations are performed (at 1245) to obtain a wafer contour image (referred to as ω in the above equation) from the grayscale wafer image. This wafer contour image is compared (at 1250) to a target wafer contour image, and the difference is then used to update the wafer image. Some embodiments use a design layout corresponding to the mask image to calculate the target wafer image. Examples of methods for generating a target wafer image from a design layout include performing low pass filtering, performing one or more Gaussian convolutions, and applying one or more rounding algorithms to interconnect layers of the design layout. That is, various operations are performed on the design layout (e.g., various corner rounding operations, etc.), rather than comparing a simulated wafer image to a straight design layout (based on the current mask image), so that the target wafer image is a more realistic image of the wafer as it is manufactured.

[0081] The comparison of the simulated wafer image and the target wafer image is performed by calculating a loss function that represents the difference between the simulated wafer profile image and the desired wafer profile image Φ. Other embodiments do not perform a profile calculation, and the loss function calculates the difference between the simulated grayscale wafer image and the desired (target) grayscale wafer image. After calculation of the loss function, some embodiments calculate gradients based on the loss function, and the mask image is updated based on these calculated gradients. Further information about the loss function, the terms included in the loss function, and the gradients performed using the loss function will be described below. After updating the mask image based on the comparison, the iterative optimization process 1200 of some embodiments begins to repeat operations 1210-1250 with the updated mask image (the desired target image remains unchanged across iterations).

[0082] Process 1200 is performed iteratively in some embodiments until the simulated wafer profile image ω (or simulated grayscale wafer image) is as close as possible to the target wafer image Φ (or target grayscale wafer image). That is, process 1200 terminates when a local minimum of the loss function is reached, indicating an optimal mask image for the layer. Alternatively or in addition, process 1200 is performed iteratively until a different termination condition is met (e.g., a specified number of iterations have been performed). At the end of process 1200, the optimized mask image ψ* represents the optimal iterative inverse of the wafer processing sequence for the given target mask image.

[0083] As described above, some embodiments perform wafer simulations to optimize a mask image corresponding to a design layout. This mask image optimization, in some embodiments, includes utilizing (and optimizing) SRAFs in the mask image. FIG. 13 illustrates an example design layout 1300 for a metal layer (or a region of a metal layer) of an IC. As illustrated, design layout 1300 shows interconnect segments designed for use in the region of the metal layer. In this example, design layout 1300 includes piecewise linear interconnect segments (i.e., interconnect segments having only straight segments), however, the design layout may also or alternatively have one or more curved segments (i.e., interconnect segments having at least one curved segment). As illustrated, design layout 1300 includes interconnect segments 1301-1306, which are representative of the shapes of conductive lines to be fabricated for this metal layer.

[0084] Although design layout 1300 includes shapes with sharp edges and corners, in some embodiments, due to manufacturing constraints of the IC, line segments created from design layout 1300 may have rounded corners. To create these line segments, one or more masks are used. More specifically, one or more masks are made for each layer of the IC so that light can be shone through the holes of the mask to create that layer of the IC (after applying photoresist).

[0085] FIG. 14A illustrates a mask image 1410 created from the design layout 1300 of FIG. 13 , and optimization of the mask image 1410 has not yet been performed. The mask image 1410 will be used to produce one or more masks, and these masks will be used to produce line segments as designed in the design layout 1300. In this example, one mask image 1410 is created for the design layout 1300 of the metal layer. However, in other embodiments, multiple mask images are created to produce the design layout 1300. In such embodiments, each mask image includes a set of shapes that will be used to produce different portions of the line segments (e.g., different line segments, different portions of the same line segment).

[0086] In this figure, mask image 1410 includes a set of mask shapes 1411-1419, each mask shape 1411-1419 representing a transparent area that will be made on the mask to make line segments that correspond to design shapes 1301-1306 in design layout 1300. Mask shapes 1411-1419 illustrate areas where the mask is about to be removed to allow light to shine through the mask and onto the substrate (after application of photoresist) to fabricate at least a portion of an IC. In this example, mask shapes 1411-1419 may simply be related to design shapes 1301-1306. However, in many cases, a mask image may include one or more shapes that do not clearly map (e.g., to a human observer) to a specific design shape of the design layout to which it corresponds.

[0087] As described above, the mask image 1410 shown in FIG. 14A is a state before mask image optimization is performed. FIG. 14B illustrates the mask image 1410 after at least one round of mask image optimization. In this figure, the mask image 1410 now includes a set of SRAFs 1420-1427, which represent additional transparent areas that will be manufactured as part of the corresponding mask. These SRAFs 1420-1427 will be manufactured as part of the mask to allow additional light to pass through the mask, which will better manufacture the IC on the substrate. The SRAFs 1420-1427 add additional light so that the manufactured IC features (e.g., line segments) on the substrate will be closer to the design layout 1300.

[0088] SRAFs 1420-1427 may have been added and / or modified during any iteration of mask image optimization. For example, SRAFs 1420-1424 may in some embodiments be added to mask image 1410 during a first mask image optimization iteration, while SRAFs 1425-1427 may be added to mask image 1410 during a later mask image optimization iteration. As another example, one or more other SRAFs may be added to mask image 1410 during one optimization iteration but then removed and / or modified during one or more later optimization iterations (e.g., if a mask image including a particular SRAF produces a locally worse wafer image than a mask image without the particular SRAF).

[0089] Simulated annealing is a probabilistic optimization technique that is used in some embodiments to iteratively modify a mask image (e.g., SRAFs of a mask image) to improve the mask image. In these embodiments, each iteration may add, move, modify, and / or remove one or more SRAFs of a particular mask image and the larger key features of the particular mask image, and then use the particular mask image to perform wafer simulation again. Based on the results of the wafer simulation, the SRAFs of the particular mask image are modified.

[0090] FIGS. 15A-15B illustrate another example mask image 1500 at different times during mask image optimization. In this example, mask image 1500 corresponds to a through-hole layer of a design layout (not shown). FIG. 15A illustrates mask image 1500 after at least one iteration of mask image optimization. In this figure, mask image 1500 includes a set of IC components 1510-1512 representing transparent areas to be fabricated on a corresponding mask. IC components 1510-1512 illustrate areas where the mask will be removed to allow light to shine through the mask and onto the substrate to fabricate at least a portion of the IC.

[0091] This figure also illustrates SRAFs 1520-1523 that have been added to the mask 1500. In some embodiments, these SRAFs 1520-1523 are added to the mask 1500 during one iteration of the optimization. In other embodiments, the SRAFs 1520-1523 are added to the mask 1500 during multiple iterations of the optimization.

[0092] FIG. 15B illustrates mask image 1500 after at least one or more iterations of mask image optimization. In this figure, additional SRAFs 1524-1526 are now included in mask image 1500. These SRAFs 1524-1526 may have been added during one or more additional optimizations. Additionally, SRAF 1521 was removed from mask image 1500 as shown in FIG. 15A (e.g., because an optimization iteration determined that SRAF 1521 made mask image 1500 less optimal, rather than more optimal).

[0093] In some embodiments, some embodiments also consider other layers during the optimization process for a mask for a particular layer, rather than focusing on a mask image of a single layer during optimization. FIG. 16 conceptually illustrates an example of a high-level mask image optimization process that uses input corresponding to multiple layers to produce an optimized mask image of a single layer (or a set of optimized mask images of multiple layers). As illustrated, the input to the optimization process 1600 includes a target wafer image 1605 of a single layer (the single layer being optimized). In addition, the input includes an initial mask 1610 for the single layer being optimized and layer masks 1612 for additional (e.g., adjacent) layers (which may have been optimized in some embodiments). In some embodiments, the complete set of mask images 1610, 1612 includes multiple masks for a set of adjacent layers (e.g., a via layer and an adjacent metal layer, a metal layer and its two adjacent via layers, or a via layer and its two adjacent metal layers). Secondary inputs are process information 1615 of the wafer (eg, process model, process variability or conditions, etc.) and mask rules that the single-layer mask image usually follows.

[0094] The iterative mask image optimization process 1600 includes one or more operations in which information about adjacent layers is considered as well as the primary layer being optimized, rather than just the operations shown in FIG. 12 . For example, in some embodiments, the iterative optimization process also performs wafer simulations for adjacent layers (at least for the first iteration, since wafer simulations do not need to be performed at each iteration if the masks of the adjacent layers are not changed between iterations). In addition, the loss function may include additional terms (i.e., in addition to the comparison terms for the layer being optimized) that affect the analysis of the simulated wafer of multiple layers (e.g., analysis of the overlap between the metal layer shape and the via layer shape). In some embodiments, this analysis may include a z-axis analysis, a joint analysis, and / or a simplified joint analysis.

[0095] The primary output of the iterative optimization is also a single mask image 1620, which is optimized to produce a wafer image that is as close as possible to the input target wafer image 1605. Secondary outputs include one or more wafer spatial images 1625, such as a wafer image at a nominal set of process conditions. In some embodiments, the secondary outputs include one or more additional wafer images at other process conditions (representing wafer images produced in response to manufacturing dose and depth of focus variations).

[0096] Prior to optimizing the mask image of the primary layer, some embodiments perform conventional (single layer) mask image optimization for the adjacent layers. In these embodiments, a standard loss function (e.g., Equation 3 above) is used by the optimizer for the adjacent layers, where each adjacent layer is optimized independently of any other layer. In some embodiments, conventional optimization of each adjacent layer produces a corresponding wafer image as a secondary output. When performing mask image optimization for the primary layer based on the mask images of the primary layer and the adjacent layers, some embodiments use additional loss or error terms calculated based on multiple wafer images (i.e., simulated wafer images of the primary layer and the adjacent layers) and included in the loss function.

[0097] FIG. 17 conceptually illustrates a process 1700 of performing wafer simulations to optimize a mask layout of a single (primary) layer of an IC design layout while simultaneously considering other layers of the design layout. The design layout is a design for manufacturing an IC (i.e., for manufacturing multiple layers of the IC), and the mask layout is used to generate a set of masks to be used to manufacture the IC based on the design layout. In some embodiments, a mask design or mask production tool (or other EDA tool) performs process 1700 to optimize a mask image corresponding to the primary layer to produce one or more optimized masks for use in manufacturing the layer. In other embodiments, process 1700 is performed to optimize a set of multiple mask images of the primary layer to produce a set of masks for use in manufacturing the single layer. In optimizing the masks, the mask design process considers the predicted manufacturing shapes of components of multi-layer interfaces (MLIs) that span the primary layer by simultaneously considering the predicted manufacturing shapes (or ideal manufacturing shapes) of components of MLIs in other layers.

[0098] As mentioned above, an MLI exists when two or more IC components (e.g., vias and interconnect segments, contacts and interconnect segments, two segments in two different metal / routing layers) in two or more layers of a design layout form z-axis components and need to be aligned. Thus, for a metal layer, each portion of an interconnect segment overlapping a z-axis connection belongs to the MLI that includes the interconnect segment and the z-axis connection. For a via layer, each via belongs to two different MLIs that have two metal layer interconnect segments connected by the via (in two different layers).

[0099] Process 1700 begins by first receiving (at 1705) a mask layout that includes an array of mask images for a primary layer, and in some embodiments, the mask layout includes mask images for one or more adjacent layers. The mask layout includes mask images for the layers (including the primary layer and adjacent layers) that will be used to produce the design layout. In some embodiments, any layer adjacent to the primary layer is included (e.g., for a metal (routing) layer, one or more via layers). In some embodiments, MLIs may span more than two layers or may span non-adjacent layers (e.g., a capacitor formed between two metal layers). The mask images are used in some embodiments after optimization to generate an array of one or more masks for each layer. Specifically, each mask is used in the fabrication of its corresponding layer. For example, a mask made from the set of mask images for the primary layer is used to fabricate the primary layer, and a mask made from the set of mask images for each adjacent layer is used to fabricate each adjacent layer.

[0100] Next, the process 1700 rasterizes (at 1710) the set of mask images into respective sets of mask pixel images. Because the set of mask images defines at least a portion of the mask layout in the geometry domain, the mask images are rasterized (pixelized) to define the portion of the mask layout in the pixel domain. Each mask pixel image corresponds to a different mask image in the respective set of mask images. It should be understood that other embodiments perform all operations in the contour domain, in which case the rasterization operation 1710 may be skipped.

[0101] In some embodiments, the image rasterization generates white pixels for fully filled pixels (e.g., pixels that are not covered by any transparent shapes and thereby represent fully opaque areas of the corresponding mask), black pixels for fully empty pixels (e.g., pixels that are fully covered by transparent shapes and thereby represent fully transparent areas of the corresponding mask), and gray pixels for partially filled pixels (i.e., pixels that are partially covered by one or more transparent shapes). In some such embodiments, fully filled pixels are represented by a value of 1.0, fully empty pixels are represented by a value of 0.0, and partially filled pixels are represented by a value in the range of [0,1], which represents the area of the pixel filled by transparent areas (e.g., a pixel that is 50% filled would have a value of 0.5). Prior to rasterizing the mask image, some embodiments decompose the mask image into a number of segments (e.g., a number of transparent areas or portions of transparent areas), which are then rasterized individually.

[0102] The rasterized mask image is also called a pixel dose map, and the values are called pixel dose values. FIG. 18 shows an example of a curved edge 1805 converted to a pixel dose map 1810 by rasterization. This is an example of a raster tone map (RTM), where the pixel data generated by rasterization has three kinds of pixels: outer pixels with a pixel dose value of 0, inner pixels with a pixel dose value of 1, and edge pixels with a pixel dose value greater than 0 and less than 1.

[0103] In some embodiments, edge pixels correspond to regions where the original geometric data has edges, and the dose value of any pixel corresponds to the region of the pixel covered by the geometric data. The accuracy of rasterization depends on the pixel size used to sample the geometry, so that the pixel value (or dose) indicates the normalized area of the geometric data overlapping the corresponding pixel region. As shown in Figure 18, contouring is the reverse process of rasterization. Contouring reconstructs the geometric data from the pixel data.

[0104] Other embodiments use continuous tone maps (CTMs) or quantized tone maps (QTMs) instead of RTMs. In such tone maps, pixel values are in a range that starts below a threshold and ends above a threshold. In a CTM or QTM, the data typically changes more gradually from pixel to pixel than does rasterized data. Additionally, in some embodiments of a CTM or QTM, pixels with values below a threshold are exterior pixels, pixels with values above a threshold are interior pixels, and pixels with values at or near the threshold are edge pixels. CTM and QTM values are often used when the source of the pixel data is computational lithography. QTM values are quantized two-dimensional values of a continuous function, and the quality of the image does not directly encode area coverage.

[0105] Because both rasterization and contour extraction operations are computationally intensive, some embodiments operate in a pixel-based computational domain for efficiency. For example, some embodiments perform mask image optimization entirely in the pixel domain (i.e., the mask pixel image is optimized, rather than the mask contour image that is rasterized to produce the mask pixel image) to eliminate the need for conversion to or from the contour domain.

[0106] In some embodiments, a machine-trained (MT) network (e.g., a neural network) is used to rasterize the set of mask images. In these embodiments, the MT network receives the set of mask images and generates the set of mask pixel images as output. Other embodiments use other algorithms or other suitable procedures to rasterize the set of mask images.

[0107] Next, the process 1700 performs (at 1715) wafer simulation operations to generate wafer images from the set of mask pixel images for each layer (the primary layer and one or more adjacent layers). The process 1700 generates a corresponding set of one or more wafer images from a given set of mask images for a layer, including representative images of IC components predicted to be manufactured on that layer (i.e., the predicted manufactured shapes of those IC components). That is, the wafer simulation simulates objects that will be manufactured on a wafer using masks generated from the set of mask images for a layer.

[0108] Some embodiments perform a set of operations (such as those mathematically referred to above as antecedent operators) to perform wafer simulations that simulate different steps in manufacturing an IC using a set of masks. Further information about these wafer simulation operations to generate wafer images from mask pixel images is described below. In other embodiments, the wafer simulation operations are performed using an MT network (such as a neural network that is different from the network used to generate the mask pixel images). In these embodiments, the MT network receives each set of mask pixel images for a layer as input and produces a corresponding set of wafer images for the layer as output. In other embodiments, the wafer simulation operations are performed using other algorithms or any other suitable procedures.

[0109] In some embodiments, wafer simulation is performed for the primary layer at each iteration of operations 1715-1740 because the mask pixel image of the primary layer may be modified at each iteration. On the other hand, the mask pixel images of the adjacent layers are not modified during this process, so wafer simulation only needs to be performed once for these adjacent layers in some embodiments. In some such embodiments, the wafer simulation operation can be performed in advance so that the mask images of the adjacent layers do not need to be used as input to the process (i.e., pre-calculated wafer images are used as input for these adjacent layers). In addition, some embodiments use idealized versions of other adjacent layers (e.g., design layouts or target images based on the design layout) instead of simulated wafer images of adjacent layers. In addition, if MLIs are used to inform the weight of the comparison of the simulated wafer image with the target image of the primary layer, some embodiments only simulate the wafer image of the primary layer.

[0110] Next, having simulated the wafer image based on the mask pixel image, the process 1700 compares (at 1720) the simulated wafer image of the primary layer with one or more additional wafer images. This may involve comparing the simulated wafer image of the primary layer with a target image of that layer and simulated and / or idealized images of one or more additional layers.

[0111] As at least part of these comparisons, the optimizer compares the simulated wafer image of the primary layer with a target wafer image. The target wafer image, in some embodiments, represents the desired placement of IC components on the corresponding wafer. For example, the target wafer image of a metal layer shows the desired placement and shape of each metal segment of the layer. Therefore, in order to determine whether the simulated wafer image of the metal layer meets the requirements of how the specified metal segments should be manufactured, the simulated wafer image is compared with the target wafer image. As described above, because the design layout may have straight lines and sharp corners that cannot be manufactured, the target wafer image often does not completely match the design layout. Instead, the manufacturing process often results in some curved features, such as rounded corners. The target wafer image can be generated from the layer of the design layout using various methods to convert these sharp lines and corners into more rounded (and thereby more physically manufacturable) features, such as low-pass filtering, low-pass filtering, or other corner rounding algorithms.

[0112] In some embodiments, simulated and target wafer images are compared by calculating a loss function term that quantifies the difference between a simulated wafer image of a primary layer and a target wafer image of the primary layer. The loss function of some embodiments includes a different term for each wafer image of the layer and each target wafer image of the layer when optimizing a layer.

[0113] The loss function term comparing the simulated image of the primary layer to the target image of that layer also takes into account overlap with other layers in some embodiments. Specifically, some embodiments do not treat all differences between the simulated image and the target image equally, but rather weight different portions of the simulated wafer shape more heavily based on their relevance to the MLI. Specifically, in some embodiments, segments along each contour (e.g., each pixel or subset of pixels) are assigned a weight value based on the cost of weighting that segment different from the target image. Overlapping regions are assigned higher weight values than non-overlapping regions, and within an overlap, more critical regions are assigned higher weight values than less critical regions. The loss function thus weights differences in more critical regions most highly, and the optimization process thus favors solutions (i.e., mask images) that are most focused on aligning the most critical regions with the target image.

[0114] Some embodiments compare the simulated image of the primary layer and the target image simultaneously and perform additional comparisons of at least some portions of the simulated image of the primary layer with simulated (or idealized) images of other layers to account for MLIs. In some such embodiments, all portions of the simulated wafer shape are treated equally in the single-layer comparison. Different embodiments use different techniques to perform additional (multi-layer perceptual) comparisons involving comparing shapes of components on the primary layer with shapes of components on other layers. Specifically, some embodiments compare the predicted shape (or shapes) in the simulated wafer image of components on the primary layer with predicted shapes in simulated wafer images of components on other layers to quantify the predicted aggregate shape of the MLI. Different embodiments compare predicted shapes in different layers by measuring the similarities and / or differences of the shapes (e.g., finding contours of shapes to align) or the degree of association between the shapes. Other embodiments compute the intersection of shapes (i.e., the overlap of two shapes, whether the contours align or not).

[0115] When making comparisons, some embodiments treat overlapping regions of predicted shapes as being more important than non-overlapping regions for loss function calculation. Furthermore, when making comparisons within overlapping regions (i.e., when directly measuring the MLI), some embodiments treat certain portions of the overlapping regions (e.g., portions that are more critical to maintaining sufficient overlap) as being more important than other portions of the overlapping regions (e.g., edges that are less likely to affect sufficient overlap if moved). Some embodiments assign weight values to different portions of a component's predicted shape that quantify the importance of different portions of the shape to establish and maintain the MLI (i.e., their importance to resilience against overlap between shapes from multiple layers). Different embodiments may make these comparisons in different ways.

[0116] Some embodiments compare a single predicted shape of a feature of a primary layer of an MLI with a single predicted shape of features of other layers. Specifically, such embodiments use a nominal predicted shape without any misalignment for each feature to make this comparison. However, other embodiments consider multiple variations of the predicted shape for all layers evaluated, or at least the primary layer. For example, some embodiments consider process variation in at least two different dimensions: (i) feature shape size (e.g., due to different exposures and / or depth of focus variations) and (ii) feature misalignment. As described above, some embodiments calculate predicted shapes that consider minimum, nominal, and maximum process variation (where minimum and maximum process variation may represent a certain number of standard deviations in different directions from the nominal process variation, or may represent another measure of possible process variation that is not necessarily the most extreme). In addition, some embodiments calculate predicted shapes that consider potential misalignments in at least four cardinal directions within the plane of the layer. Thus, some embodiments calculate fifteen different predicted shapes for each layer and consider five different options in the misalignment dimension of process variation (four cardinal directions and an option with no misalignment) and three different options in the size dimension of process variation (maximum, nominal, and minimum). Other embodiments may also include different or additional options in the size dimension of process variation and / or additional misalignments, such as misalignments in ordinal (intercardinal) directions.

[0117] Whether one comparison or multiple such comparisons are performed, different embodiments also use different techniques for making the comparisons and generating a value that can be measured in the loss function for a given MLI. For example, some embodiments list different possible predicted shapes (as described above) and the intersection between these shapes in different layers. Some such embodiments calculate the adaptability score based on the minimum overlap of predicted shapes from the main layer and other layers. If, for example, fifteen different comparisons are made between predicted shapes in two layers, some embodiments identify the worst case (e.g., minimum area) of these fifteen comparisons and use it to calculate the score for the MLI. As described below with reference to Figure 24, other embodiments take each comparison and then calculate the intersection between them, which is equal to or worse than the worst case of the individual comparisons. Some embodiments calculate the area of this minimum overlap and use this area to calculate the score for the MLI.

[0118] Other embodiments use a set of evaluation points for each shape in the primary layer that is part of the MLI. In this case, some embodiments weight the evaluation points based on whether they are part of an overlap region of the shapes and thereby influence the MLI. For evaluation points within the overlap region, some embodiments designate multiple points as being more or less critical to the overlap (as described above for assigning weights to multiple points when comparing the target image). Weights are assigned to the evaluation points based on these different classifications, and the evaluation points for each shape are compared to simulated wafer images of the appropriate adjacent layer. In some embodiments, an optimization procedure evaluates whether each evaluation point is on the correct side of the boundary of a shape in another layer (e.g., inside or outside the shape). Some embodiments assign a cost to each evaluation point, and these costs are then weighted (i.e., using the assigned weights).

[0119] Still other embodiments may use other and different techniques to calculate the loss function terms that take into account the MLI. For example, some embodiments calculate tolerance regions for each main layer component shape in the simulation area, and the tolerance regions are used to restrict the boundaries of the main layer shape (by assessing the cost of the main layer shape that exceeds the tolerance region). Some embodiments define the tolerance region for a given main layer shape based on the location of the shapes in the other layers (the other layers that form the MLI with the main layer shape) and the shapes (and the shapes of the main layer components). Under this framework, the main layer shape can be anywhere within the boundaries of the tolerance region (although the location of the main layer shape is still restricted based on the single layer cost). Some such embodiments do not assess the cost of the main layer shape that is restricted to the tolerance region, and then assess additional costs based on the degree to which the main layer shape exceeds the tolerance region.

[0120] Returning to FIG. 17 , the process 1700 then calculates (at 1730) a value for a loss function based at least on (i) the comparison of the simulation of the primary layer and the target wafer image and (ii) the interaction of the primary layer and the wafer simulation of an adjacent layer (e.g., with the primary layer). In some embodiments, the loss function is a variation of Equation 3, where each evaluation point is weighted based on its importance to the MLI. Other embodiments use Equation 5 below, which includes terms for the weights of the single layer comparison and MLIs (and has additional optional weights for each MLI within the MLI term).

[0121] More specifically, to incorporate cross-layer alignment issues (MLIs), the penalty function of some embodiments includes manufacturability scores for various locations of the simulated wafer (i.e., where the MLIs are located). Alternatively or in addition, in some embodiments, the penalty function also includes extreme process variation scores associated with all layers (layers for which wafer images were generated during wafer simulation). In other embodiments, consideration of process variation is incorporated into both the comparison term (i.e., comparing simulated and target wafer images) and the total manufacturability score term of the penalty function.

[0122] When split into two separate terms, the total manufacturability score is associated with misalignment issues that may occur when manufacturing multiple layers of the IC, and the extreme process variation score is associated with varying process conditions that may occur when manufacturing one or more layers of the IC. In some embodiments, both the total manufacturability score and the extreme process variation score may be calculated based on a z-axis analysis (e.g., z-axis analysis, joint analysis, simplified joint analysis).

[0123] Process 1700 then determines (at 1735) whether to retain the previous set of modifications to the mask pixel image. In some embodiments, this is an estimate of how much better or worse the previous set of modifications made the simulated wafer image (e.g., as measured by a loss function). Some embodiments make this estimate based on the entire wafer image (i.e., total loss function calculation). Other embodiments estimate each predicted wafer shape and / or each MLI individually and determine for each predicted wafer shape and / or each MLI whether to retain the modifications to the mask layout that were identified as being associated with that shape and / or MLI.

[0124] Some embodiments rigidly maintain a mask layout modification when the modification makes the predicted wafer shape worse, and revert a modification when the modification improves the predicted wafer shape. Other embodiments sometimes accept modifications that degrade the predicted wafer shape (or the overall simulated wafer) in order to escape from a local minimum of the loss function (i.e., in order to find a better local minimum). In general, iterative optimization procedures are more willing to accept such poor solutions at earlier times in the optimization procedure (i.e., earlier iterations) than at later times in the optimization procedure, while other parts of the solution space continue to be explored.

[0125] If the optimization process determines that the modification to the mask pixel image is not to be retained, the process 1700 restores (at 1740) the previous modification. As described, some embodiments perform this evaluation and restoration for the entirety of the modifications to the mask image, while other embodiments perform this evaluation and restoration for each modification to the mask image (e.g., for each shape and / or MLI in the predicted wafer) individually.

[0126] Process 1700 then determines (at 1745) whether additional pixel image optimization is required. Some embodiments use a set of one or more criteria to determine whether mask pixel image modification is required. Specifically, some embodiments require a minimum variance of the primary layer wafer image from the target image for that layer. Such a criterion specifies how close a simulated wafer image based on the current mask image should be to the target image in order to consider the mask image optimized.

[0127] In some embodiments, the set of criteria for determining whether to perform additional modification on the mask image specifies a minimum threshold of the loss function, such that if the total loss function is below the threshold, no further modification is required. In other embodiments, mask image modification is performed for a specific number of iterations, and then the process 1700 exits the iterative modification loop. Other embodiments perform modification for a maximum number of iterations, but may exit the loop earlier if the loss function value falls below the threshold.

[0128] If additional mask pixel optimization is desired, the process 1700 then modifies (at 1750) the mask pixel image for the primary layer. In some embodiments, the modification of the mask pixel image includes the addition, removal, modification, or relocation of one or more SRAFs in a mask pixel image (by changing one or more pixel values of one or more pixels in the mask pixel image). SRAFs are additional transparent areas in the mask that allow light to pass through to the substrate (i.e., wafer) without having to make additional shapes for any layer on the substrate. The modification may also add, remove, or modify the primary shapes of the desired IC components in the mask corresponding to the primary layer (e.g., enlarging or reducing one or more edges of such shapes).

[0129] To identify modifications to the mask image, some embodiments use a loss function and its terms to compute a set of one or more gradients. In some such embodiments, the process computes the gradient of the loss function relative to each pixel in the mask pixel image. In other embodiments, the process computes the gradient of the loss function (i) relative to each pixel in each primary layer wafer simulation image and (ii) relative to each region of intersection between a predicted IC component in the primary layer and a component in an adjacent layer.

[0130] In some such embodiments, the optimizer computes the gradient of the wafer image comparison term of the loss function with respect to each pixel of the mask image. The mask image optimizer also computes the gradient of the cross-layer interaction term with respect to each MLI. These gradients allow the optimizer to identify which pixel or pixels in the mask image should be modified and the degree to which the identified pixels should be modified.

[0131] Based on these gradients, one or more predicted IC components and one or more pixels of the predicted IC components are identified as requiring modification. In identifying that the placement of one or more predicted IC components must be modified based on the placement of one or more other predicted IC components, the optimizer identifies at least one modification to at least one mask pixel image in the first set of mask pixel images.

[0132] When performing multiple iterations of optimization, in some embodiments, the gradients also indicate to the optimizer which previously modified pixels are producing a better or worse shape in the simulated layout than before the most recent modification. For example, during a first iteration of optimization, the optimizer may identify that a particular pixel value of a particular mask image should be raised (e.g., pushing an edge of a mask shape in a particular direction). During a second iteration of optimization, if the optimizer identifies from the newly calculated gradients that the particular pixel is producing a worse corresponding predicted manufacturing shape in the simulated wafer than before the attempted optimization (i.e., the new value of the pixel causes the mask image to result in a simulated wafer image that is less like the target wafer image), then the optimizer will lower the particular pixel during the second optimization iteration.

[0133] To determine the modifications to the mask shapes (i.e., the shapes in the mask pixel image or indirectly in the mask image), some embodiments use the association between the design layout shapes (which correspond to the components of the IC to be finally manufactured and the predicted component shapes of the simulated wafer) and the mask shapes. Referring to FIG. 13 and FIG. 14A-14B, each design layout shape 1301-1306 has a corresponding set of one or more mask shapes 1411-1419. For example, the mask shapes 1414, 1418 in FIG. 14A (and the SRAF shapes 1420, 1421 in FIG. 14B) are used to produce the components corresponding to the design layout shape 1304.

[0134] Thus, if application of the loss function identifies that specific changes need to be made to specific portions of the predicted feature shape in the simulated wafer image, the optimization process converts those changes into changes to the corresponding mask shape. Such changes may include modification or movement of existing mask shapes and addition of new mask shapes or removal of existing mask shapes (e.g., addition or removal of SRAFs). Some embodiments convert directly from gradients to mask shape modifications. For example, in some embodiments, such gradients specify directions in which pixels of the mask pixel image are modified, resulting in a modified mask shape.

[0135] In other embodiments, the mask shape modification is based more drastically on the correlation of the predicted manufacturing component shapes to the mask shapes. Specifically, some embodiments calculate changes that should be made to the predicted manufacturing component shapes (e.g., enlarging certain portions of such shapes, shrinking some portions of such shapes, stretching such shapes, etc.) to simultaneously satisfy two loss function components (matching the target wafer image and ensuring overlay adaptability to handle variations such as misalignment). From these desired changes to the predicted manufacturing shapes, the optimization process determines changes to the mask shapes that are likely to result in the desired changes during manufacturing and applies these changes to the mask pixel image.

[0136] FIG. 19 conceptually illustrates an optimizer modifying the profile of a circular metal plate shape 1902 (e.g., representing a plate of a capacitor). As illustrated, the optimizer 1900 takes as input the circular shaped metal plate 1902 and a current mask layout shape 1905 that corresponds (at least in part) to the metal plate shape 1902 in a simulated wafer image. As discussed above, in some embodiments, the shapes in the mask layout do not necessarily map 1:1 to the shapes fabricated on the wafer (or predicted on the simulated wafer). Additional mask shapes (e.g., smaller SRAFs and adjacent mask shapes that primarily affect other wafer shapes) may also affect the fabricated (and simulated) wafer shape.

[0137] The metal plate shape 1902 now does not overlap the through hole shape 1903, so it is important that the loss function used by the optimizer 1900 indicates that the boundary of the metal plate shape 1902 is moved outward in the upper left region of its shape. As such, the optimizer 1900 outputs a modified mask shape 1910 (while also modifying other mask layout shapes in the same adjacent region of the mask layout). The modified mask shape 1910 is depicted as a solid line compared to the dashed line used for the previous mask shape 1905. The arrows show that the right side of the mask shape 1910 is pulled inward, but the right side is pulled outward (toward the left). The modification to the right side may be due to the target wafer shape being narrower than the simulated wafer shape 1902, and because the multi-layer overlap is on the left side of the shape, there is no restriction on the right side of the shape 1902. The figure also shows that when the new mask shape 1910 (and the remaining area of the mask layout or at least a region of the mask layout) is provided to the wafer simulator 1925, the wafer simulator 1925 outputs a modified elliptical shape 1930, which will now completely overlap the through-hole shape.

[0138] After modifying the mask pixel image of the main layer, the process 1700 then returns to operation 1715 to perform wafer simulation using the modified set of mask pixel images of the main layer. As described, in some embodiments, since only the main layer mask image is modified, wafer simulation only needs to be performed with the main layer in each iteration.

[0139] On the other hand, once the process 1700 determines that no mask pixel image modification is required, the process 1700 may optionally perform (at 1755) a contour extraction operation to convert the mask pixel image of the main layer into an updated set of mask images. In some embodiments, this operation is performed when at least one modification to at least one mask pixel image is performed. In the unlikely event that no modification is performed, the set of mask images still corresponds to the set of mask pixel images, and a contour extraction operation is not necessary. After this conversion is performed, the process 1700 ends.

[0140] The above process 1700 describes modifying the mask pixel image at each iteration. It should be understood that other embodiments modify the mask image (i.e., the mask image extracted by contours) rather than the mask pixel image. In some such embodiments, modifications are made to the mask image by modifying, adding and / or removing mask shapes in the mask image, as opposed to the pixel value changes that can be made to the mask pixel image. Because the mask image itself is modified in these embodiments, after modifying at least one mask pixel image of the main layer, the process 1700 returns to operation 1710 to rasterize the modified set of mask images into a modified set of mask pixel images, which is then used in the wafer simulation operation.

[0141] In some embodiments, the primary layer (i.e., the layer being optimized) is a metal layer of the design layout, and at least one adjacent layer is a via layer of the design layout. In such embodiments, the simulated wafer image of the primary layer includes metal line end features, via pads (if any) of the metal layer, and via holes of the adjacent layer. If there is no proper overhang of a particular metal line end over its corresponding via hole (or over its corresponding via pad (if any)), the mask image of the primary layer is modified to correct this problem. Addition, removal, modification, and / or migration of SRAFs may be performed on one or more mask images in an attempt to correct these overhang issues. It should be understood that optimization of line segments and overhangs between adjacent vias are merely examples, and other types of interfaces between layers (e.g., between a metal layer and a contact layer) may also be optimized.

[0142] In some embodiments, the primary layer is adjacent to multiple layers of the design layout (e.g., a metal layer adjacent to two via layers or a via layer and a contact layer, a via layer adjacent to two metal layers, etc.). In some such embodiments, the program considers the interaction between the primary layer and the two or more layers. For example, one end of a line segment in a metal layer may intersect a via in a first via layer, while the other end of the same line segment intersects a via in a second via layer, and both intersections are considered for optimization purposes (i.e., both intersections affect the loss function used for optimization). Some embodiments consider not only layers adjacent to the primary layer during mask image optimization, but also interactions with other layers in the design layout (e.g., alignment between a metal layer (primary layer) and a subsequent metal layer connecting the primary layer to the via). One of ordinary skill in the art to which the present invention pertains will appreciate that any group of a design layout (e.g., adjacent layers, non-adjacent layers, all layers of the design layout) may be considered when performing wafer simulations to optimize the mask image of one or more layers.

[0143] As described above, various schemes may be used to incorporate consideration of additional layers into the optimization problem for a primary layer. As previously mentioned, some embodiments use a loss function term that compares a simulated image of a primary layer with a target image of that layer while taking into account overlap with other layers. Specifically, some embodiments do not treat all differences between simulated and target images equally, but rather weight different portions of the simulated wafer shape more heavily based on their relevance to the MLI.

[0144] FIG20 conceptually illustrates a process 2000 of some embodiments for comparing a simulated image of a layer to a target image of a layer while taking into account overlap. Process 2000 is performed in some embodiments with an optimizer at operation 1720 of FIG17 (i.e., at each iteration of process 1700). Rather than directly comparing shapes in the simulated image of a primary layer to shapes in an adjacent layer, this approach uses the presence of MLIs formed with features in the primary layer and the adjacent layer to weight the comparison between the simulated wafer of the primary layer and the target image.

[0145] As shown, process 2000 begins by selecting (at 2005) a shape in the primary layer (i.e., the layer being optimized). In some embodiments, operations 2005-2015 are performed for each shape in the primary layer, regardless of whether the shape belongs to an MLI. Other embodiments perform operations only on shapes that belong to MLIs. Furthermore, it should be understood that this is a conceptual process, and some embodiments perform these operations on multiple shapes simultaneously in parallel.

[0146] Process 2000 then selects (at 2010) a plurality of evaluation points for the selected shape. In some embodiments, the evaluation points are along the contour of the shape, while in other embodiments, the evaluation points also include the interior of the shape. In addition, some embodiments compare the areas between shapes and thereby also include evaluation points outside of each shape when calculating the loss monolayer loss function. In some embodiments, the evaluation points are each a pixel in the wafer image (along the contour or across the entirety of the shape (e.g., for a pixelized wafer image)) or a specific subset of pixels (e.g., every other pixel, every fourth pixel, etc.). In other embodiments, the evaluation points are located at different distances along the contour (for contour-based wafer images). For example, in some embodiments, the distance between the evaluation points is based on the gate pitch and / or metal pitch used in the process for the IC (e.g., a specific number of nm).

[0147] FIG. 21 conceptually illustrates a multilayer interface 2100 between shapes in adjacent layers, with a set of evaluation points identified along the outline of a primary layer shape in a simulated wafer image. The left side of this figure illustrates a larger circular shape 2105, which represents a plate (e.g., one half of a pair of plates forming a capacitor) in a metal layer (in the case where shape 2105 uses multiple other layers to form a multilayer component). The capacitor plate represented by shape 2105 is connected to a line represented by shape 2115 (i.e., in another metal layer) through a via (represented by shape 2110 (i.e., in an adjacent via layer)). In this example, the overlap considered is the metal plate and the via (the via layer can be separately optimized to ensure overlap with both the wire and the metal plate). The right side of this figure illustrates a set of evaluation points (represented by Xs) that are defined for the primary layer shape 2105, which represents the capacitor plate component. In this case, the evaluation points are selected along the outline of shape 2105.

[0148] FIG22 conceptually illustrates another example of selection of evaluation points for a through-hole shape 2205 that forms a multi-layer interface with a line segment shape 2210. The through-hole shape is located at the bend of the line segment such that the bottom and left sides of the through-hole abut the side of the line segment, while the top and right sides of the through-hole abut the interior of the line segment. The right side of this figure illustrates a set of evaluation points (denoted by Xs) that are defined along the outline of the primary layer shape 2205 (the through-hole feature).

[0149] The process 2000 then assigns (at 2015) weights to the evaluation points based on (i) whether the evaluation point is part of the overlap region of the MLI and (ii) the importance of the evaluation point to the overlap region. In some embodiments, evaluation points that are not part of the overlap region (e.g., all points of a component that is not part of any MLI) are assigned the lowest weight values. Within the overlap region, evaluation points that are more critical to the adaptability of the MLI are weighted more highly than less critical evaluation points.

[0150] Thus, in FIG. 21 , the evaluation points closest to the through-hole (shown as the thickest line) are given the highest weights. Evaluation points farther from the through-hole but still within the overlap region (shown as lines of intermediate thickness) are given intermediate weight values, and evaluation points completely outside the overlap region are given the lowest weight values. The total overlap region in this case is based on the area of the through-hole 2110 connecting the metal plate 2105 to the line segment 2115. It should be understood that the lowest weight values for those points outside the overlap region are not necessarily zero. The optimizer will still attempt to adjust the mask image to match these portions of the shape to the target image, but the optimizer will be more willing to accept errors in these portions than in more critical areas of the shape.

[0151] In FIG. 22 , since the through hole is completely enclosed by the line segment shape 2210, all evaluation points along the through hole shape 2205 are part of the overlap region. However, due to the curved nature of the line segment 2210 and the location of the through hole 2205, two sides of the through hole 2205 abut the line segment (bottom and left side), while the other two sides abut the interior of the line segment (top and right side). Thus, the left side and bottom side of the through hole shape 2205 are identified as more critical to the maintenance of the MLI, and the evaluation points located on these sides are considered more critical (shown as thicker Xs in this figure).

[0152] In some embodiments, to identify criticality and assign weight values to evaluation points, the optimizer determines a distance between the evaluation point and a shape in another layer. For example, if the evaluation point is located on a first shape, some embodiments identify a line that is orthogonal to the tangent line of the shape at the evaluation point and determine the distance (i.e., the distance in the xy plane) from the evaluation point to the second shape (the shape in the other layer). It should be understood that the simulated wafer images of the two layers each have their own xy plane, but these planes can be aligned by ignoring the z-axis and treating the two sets of shapes as being located in the same xy plane (as long as the xy planes themselves are aligned based on the design layout). If the evaluation point is located inside the second shape or should be located inside the second shape (such as the case of through-hole shape 2205), some embodiments always consider this portion of the overlap area and then assign criticality (weight value) based on the distance. In the case of FIG. 22, the distance from the evaluation point to the line segment at the top of through-hole shape 2205 and to the right of the through-hole shape is significantly greater than the distance from the evaluation point to the line segment at the bottom and left of through-hole shape 2205. If the evaluation point is outside the second shape and should be so (such as the case of metal plate 2105), the point can be a non-overlapping evaluation point. Other embodiments may use different calculation techniques, or the user (such as a chip designer) may manually specify the weight value.

[0153] Returning to FIG. 20 , the process 2000 determines (at 2020) whether there are additional shapes in the main layer. Some embodiments assign evaluation points to all shapes representing all components in the layer (including components that are not part of the MLI). For such shapes, all evaluation points are part of the non-overlapping region and are assigned weights accordingly. If there are additional shapes, the process 2000 returns to 2005 to select the next shape and assign weights to the evaluation points of that shape.

[0154] Once weights have been assigned to the evaluation points for the entire layer, the process uses (at 2025) the weighted evaluation points to compare a simulated image of the layer and a target image of the layer. In some embodiments, the simulated wafer image and the target image are compared by determining the difference between the simulated wafer image pixel values for each evaluation point (i.e., each xy coordinate). Some embodiments use the pixel dose value for each evaluation point (e.g., each pixel or a subset of pixels) and compare the values between the simulated wafer image and the target wafer image, where a larger difference equals a higher cost. Other embodiments determine the distance between the evaluation points along the contour of each shape in the simulated wafer image and the equivalent contour in the target image, where a larger distance equals a higher cost.

[0155] Regardless of the difference calculation method used, the cost is then multiplied by the weight value of each evaluation point, so that those points that are considered more important (i.e., more critical to the MLI, and thereby more critical to the proper operation of the IC) are given higher weights in the loss function. Therefore, when the loss function is used to (i) evaluate the effects of previous modifications to the mask image of the primary layer and (ii) judge subsequent modifications to those mask images, the optimizer gives higher priority to modifications that move evaluation points that are considered more critical to the target image. In other words, the goal of the optimizer is to identify changes to the mask image that will cause the entirety of the simulated wafer image to match the target image (all differences from the target image are important for various other reasons, such as parasitic effects), but the points that are most critical to the MLI are considered the most important.

[0156] As discussed, some embodiments do not only compare the simulated wafer image to the target image. Instead, other embodiments use both (i) a loss term that compares the simulated image of the primary layer to the target image and (ii) an additional loss term that takes into account the MLIs. Different embodiments may apply different weights to these two loss terms. In some embodiments, all portions of the simulated wafer shape are treated equally in the first (single-layer) loss term (i.e., in contrast to the above-described scheme of using different weights for different regions in the simulated wafer image). Different embodiments use different techniques to compute an additional (multi-layer-aware) loss term that involves comparing the shape of features on the primary layer to the shapes of features on other layers.

[0157] For example, for a given MLI including a shape in a primary layer and a shape in another layer, some embodiments compute the intersection of these shapes and define a cost for the MLI based on the area of the intersection (e.g., inversely proportional to the intersection). Some embodiments generate a number of simulated wafer images of the primary layer (and in some cases simulated wafer images of other layers) based on different possible misalignment and / or process variation errors. For at least a subset of these wafer image pairs (i.e., a simulated wafer image of the primary layer and a simulated or optimized wafer image of the other layer), the optimizer computes the intersection of the two shapes. Different embodiments use the minimum of these intersections as the overlap area (representing the worst case), or compute the logical intersection of all intersection areas as the overlap area (representing a highly unlikely but potentially worse case), or compute the average area (representing an expected area), and then determine the cost based on the computed area.

[0158] FIG23 conceptually illustrates a process 2300 of assigning costs to MLIs in a simulated wafer image based on intersections of components of the MLIs in some embodiments. Process 2300 is performed in some embodiments with an optimizer at operation 1720 of FIG17 (i.e., each iteration of process 1700). This approach is one of many different approaches that compare the shape in the simulated image of the primary layer with the shape in one or more adjacent layers.

[0159] As depicted, process 2300 begins by selecting (at 2305) an MLI that includes a component shape in the primary layer. That is, in some embodiments, operations 2310, 2315 are performed for each MLI in the design layout that includes (i) a component in the primary layer and (ii) a component in at least one additional layer. Some embodiments calculate a separate cost for each MLI in the design layout. Furthermore, it should be understood that this is a conceptual process and that some embodiments perform these operations simultaneously for multiple MLIs in parallel.

[0160] Next, the process 2300 calculates (at 2310) intersections between the main layer feature shapes and feature shapes in other layers (i.e., intersections of shapes that form MLIs). As further described with reference to FIG. 24 , some embodiments calculate multiple such intersections based on multiple different simulated images generated for the main layer (or for both the main layer and other layers). In some embodiments, each intersection may be calculated using pixel dose values for shapes in the rasterized simulated wafer image.

[0161] The process 2300 then assigns (at 2315) a cost to the MLI based on the computed intersection(s). Some embodiments base the cost on the minimum intersection (ie, minimum overlap), while other embodiments base the cost on the logical intersection of the computed intersections (ie, overlapping intersections).

[0162] Process 2300 then determines (at 2320) whether there are additional MLIs with components in the main layer. If there are additional MLIs, process 2300 returns to 2305 to select the next MLI and calculate the cost for the next MLI. Some embodiments calculate the cost for each MLI with a component in the main layer.

[0163] In some embodiments, a superimposed wafer image of multiple layers of wafer images is generated to determine the overlap of components of an MLI (e.g., line segments, line ends, and vias) for each image. This superimposed wafer image is calculated in some embodiments based on the wafer images, and, using a wafer shape intersection operation, a "location-specific adaptability score" is calculated to represent the successful overhang or partial overhang (when there is misalignment) of each via location. These location-specific adaptability scores can be calculated as separate loss function terms for each intersection region of the primary layer and the adjacent layer.

[0164] FIG. 24 illustrates an example of resilience and susceptibility to misalignment of multiple different intersections 2405-2420 between components on multiple layers. In this case, four examples are provided, showing interfaces between vias and metal line ends. In this figure, the thick dashed lines depict polygonal graphs representing the resilience of each via hole to coverage issues when there is misalignment, where all misalignment directions and magnitudes are considered up to a certain maximum misalignment value. Higher resilience to misalignment is indicated in these cases by the larger area of the dashed polygon, showing that the top center via-line intersection 2410 has the lowest resilience to manufacturing variation and misalignment (having the smallest dashed polygon). On the other hand, the bottom via-line intersection 2420 has the greatest resilience to manufacturing variation and misalignment. While this figure explicitly depicts intersections between via holes and metal line ends, it should be understood that multiple layer intersections may include intersections between via holes and via pads, via pads and metal line ends, contacts and metal line ends, etc.

[0165] In some embodiments, the compliance of a component intersection example of two components on adjacent layers (e.g., represented by the dashed polygon in FIG. 24 ) is calculated using simulated wafer images by determining the intersection (i.e., overlap) of the two components across various different manufacturing conditions and then determining all such overlapping intersections (i.e., polygons that are portions of all individual two-component intersections). A single intersection between two components, for example, is calculated between the minimum via profile and the minimum metal profile for a single misalignment condition. Similar intersections may be calculated for various combinations of process conditions and misalignment conditions. For example, the nominal or maximum profile is used for some intersections instead of the minimum profile. In addition, reasonably expected misalignments in various different directions (i.e., left, right, up, down) are considered. Some embodiments consider various combinations of (i) misalignment directions (or no misalignment) and (ii) process condition sets and determine the intersection polygon of the two components for each of these combinations, and then determine the total intersection of these intersection polygons as the total compliance polygon. For example, for a total of twelve intersection polygons between a given pair of components, some embodiments consider three different sets of process conditions and four different misalignment directions for each set of process conditions. The area of the resulting component coverage resilience polygon indicates the resilience of the associated components to coverage issues in the presence of manufacturing variations and misalignment. As further described below, when performing the calculations, some embodiments also provide different weights to different segments of the intersection area (i.e., based on the importance of handling misalignment at different segments).

[0166] To calculate the area of an intersection (cross-sectional overlap) between two components of an MLI (i.e., between a first predicted shape in the primary layer and a second predicted shape in the other layer), some embodiments multiply the pixel dose value of each pixel in the primary layer simulated wafer image (i.e., in the region of the MLI where the intersection is calculated) by the pixel dose value of the equivalent pixel in the other layer (i.e., having the same coordinates in the x,y plane). Thus, coordinates that are in the interior region of both shapes will have a value of 1.0 (1.0 x 1.0), and coordinates that are outside of one of the two shapes will have a value of 0.0 (0.0 x any dose value). Pixels along the outline of one or both shapes will have smaller values, where at least one of the pixel dose values is in the range of (0, 1). Coordinates of pixels that are completely within one of the shapes but at the edge of the other shape will have the value of the pixel dose value of the other shape (because that value is multiplied by 1.0). Coordinates at the edge of two shapes may have the two values multiplied together; in the case where the product of the pixel dose values of these overlapping edge pixels does not fully represent the area of intersection, the introduced error is usually minimal over the scale of the entire shape. Other embodiments take the average of the two pixel dose values rather than multiplying the edge pixels together.

[0167] Some embodiments perform these intersection calculations for each pair of intersection features in the main layer (the layer being optimized) and adjacent layers of an IC. Some such embodiments then assign a resilience score that is proportional to the area of these intersection polygons. The resilience score (which is essentially inversely related to cost) can then be further calculated for different process conditions, and the results are aggregated to produce a single location-specific resilience score S li for a single location (i.e., for a single overlap of a via and a line segment). The single location-specific resilience score S li is further scaled to vary between values between 0 and 1 (inclusive) in some embodiments.

[0168] For example, in FIG. 24 , the coverage adaptability polygon 2410 of the top central via hole is assigned a single-position adaptability score closer to zero in some embodiments, while the coverage adaptability polygon of the bottom central via hole is assigned a single-position adaptability score of 1.0 or close to 1.0. In other embodiments, scores closer to 1.0 indicate lower adaptability, while scores closer to zero indicate higher adaptability (e.g., the goal is to minimize the score in the loss function). In some embodiments, multiple single-position scores are then aggregated into a combined via component adaptability component, which is then applied to a weight and included in the loss function for optimization of a primary layer mask image (e.g., a mask image of a metal layer or a via layer). Additional scores are similarly calculated in some embodiments for other manufacturability issues (e.g., manufacturability issues related to spacing between shapes on the same layer or related to width of shapes on the same layer), so that the overall process of optimizing one or more mask images of one or more IC layers is not limited to the calculation of overlap adaptability.

[0169] In some embodiments, the aggregate combination of all resilience scores for all multi-layer interfaces is labeled as an overall manufacturability score. An example of aggregating scores to arrive at an overall manufacturability score includes first taking the sum of all specific location scores Si (across all offending locations) for each specific manufacturability issue (e.g., overhang resilience or line width), and summing these values to produce an issue-specific overall manufacturability score ISC: ISC = ΣS i(4)

[0170] In some embodiments, the issue-specific manufacturability scores are then further weighted and combined to produce an overall manufacturability score: Total manufacturability score = Σα i ISC, It is assigned a further weight and included in the loss function: H =∫ ∫ |(𝜓)-𝜙|+𝑤 tms∗ 𝛴𝛼i𝐼𝑆𝐶 (5)

[0171] The weights α i are included in the overall manufacturability score in some embodiments to weight certain problem-specific manufacturability scores more heavily. For example, the overlap between a line segment and a via may be weighted differently than the overlap between a line segment and a contact, or for a via layer, the overlap between a via and a line segment in a first metal layer may be weighted differently than the overlap between a via and a line segment in a second metal layer. When calculating the problem-specific manufacturability score for a given manufacturing problem, some embodiments weight each location-specific score (S i) differently.

[0172] The final weight value 𝑤 tms is applied to the total manufacturability score within the loss function to influence the degree to which various multi-layer manufacturability issues are simulated more than the primary layer comparison of the target wafer image influences the optimization of the mask image. If the total manufacturability score weight is assigned a value of 0.1, the single layer wafer image comparison has more influence on the total loss function and thereby has more influence on the modifications used to optimize the mask image. Some embodiments apply weight values less than 1 to other comparison terms in the loss function, rather than applying the weight value to the total manufacturability term (i.e., causing the total manufacturability score to have more influence on the loss function than the comparison term). In some embodiments, the weighting between the loss function terms and the particular problem is specified by the mask designer. It should be understood that the example equations shown here are exemplary and other aggregation methods may be used in other embodiments to calculate the total manufacturability score for a layer.

[0173] The total manufacturability score is used in some embodiments to direct the optimizer to optimize one or more mask images for one or more portions of the silicon profile more than other portions, and to do so automatically. In some embodiments the optimizer produces an optimized mask image that results in a wafer profile that extends more in one direction than in other directions (e.g., such that multi-layer interface coverage is maximized on an interface (e.g., in the case of a via feature) basis). The optimizer operates in this manner in anticipation of misalignment between layers during silicon wafer processing. More specifically, the mask image is optimized in some embodiments in anticipation of various misalignment possibilities and in anticipation of compensating for any or all of them.

[0174] Once the loss function is calculated, its single-value output indicates the degree of similarity of the appearance of the simulated wafer image to the target wafer image (i.e., it indicates the degree of similarity of the appearance of the representative image of the IC components in the simulated wafer image to the representative image of the IC components in the target wafer image). This information indicates how effective the mask image is in generating a mask to produce an IC that is as close to the design layout of the IC as possible. In some embodiments, the smaller the loss function value, the closer the simulated wafer image is to the target wafer image. In such embodiments, the purpose of the optimizer is to iteratively modify one or more mask images to reduce the loss function value as much as possible (i.e., reduce the loss function to 0 as much as possible). In other embodiments, the larger the loss function value, the closer the simulated wafer image is to the target wafer image. In such embodiments, the purpose of the optimizer is to iteratively modify one or more mask images to increase the loss function value as much as possible (i.e., increase the loss function to a defined value, such as 1 or 100 as much as possible).

[0175] Using the loss function and the terms in the loss function, the optimizer can modify one or more mask images. For example, the optimizer in some embodiments calculates one or more gradients of the loss function terms to determine how to modify the mask image. In such embodiments, when optimizing a mask image, the optimizer calculates the gradient of the |(𝜓)-𝜙| term with respect to each pixel of the mask image and the gradient of the 𝑤 tms∗𝛴𝛼i𝐼𝑆𝐶 term with respect to each multi-layer interface used to generate the overall manufacturability score. When optimizing multiple mask images, the optimizer calculates these gradients for each mask image it is optimizing.

[0176] These gradients allow the optimizer to identify which pixel or pixels of the mask image should be modified and the degree to which the identified pixels should be modified. When performing multiple iterations of optimization of a mask image, the gradients also indicate to the optimizer which pixels it previously modified were worse than before being modified. For example, during a first iteration of optimization of a particular mask image, the optimizer sees from the gradients that a particular pixel should be lowered. During a second iteration of optimization, the optimizer sees from the newly calculated gradients that the particular pixel is worse than before the first optimization iteration (i.e., the new value of the pixel causes the mask image to result in a simulated wafer image that is less like the target wafer image). Thus, the optimizer knows that the particular pixel should be lowered during this second optimization iteration.

[0177] The above technique of measuring resilience to misalignment and other process variations by computing minimum intersection is one potential approach to comparing a primary layer to one or more other layers and incorporating this comparison into the loss function used in the optimization process. Other embodiments, however, use different techniques to add additional multi-layer aware costs to the loss function being optimized.

[0178] For example, when comparing a particular predicted manufacturing shape in a simulated wafer image of one layer to a shape in another layer, the optimizer assigns a higher importance to a particular portion of the primary layer shape than to other portions of the shape. This higher importance assignment may be due to the portion of the shape having a different level of importance to overlay compliance for a particular multi-layer interface region.

[0179] Some such embodiments use a set of evaluation points for each shape in the primary layer that is part of the MLI. Some embodiments weight the evaluation points based on whether they are part of an overlap region of a shape and thereby influence the MLI. For evaluation points within the overlap region, some embodiments designate multiple points as being more or less critical to the overlap (as described above for assigning weights to multiple points when comparing target images). Weights are assigned to the evaluation points based on these different classifications, and the evaluation points for each shape are compared to simulated wafer images of the appropriate adjacent layer. In some embodiments, an optimization procedure evaluates whether each evaluation point is on the correct side of the boundary of a shape in another layer (e.g., inside or outside the shape). Some embodiments assign a cost to each evaluation point, and these costs are then weighted (i.e., using the assigned weights).

[0180] Some embodiments identify a set of evaluation points for each predicted manufacturing shape in a simulated wafer image and then calculate a cost for each evaluation point. These evaluation points may be individual pixels or subsets of pixels (e.g., in a pixelated wafer image) or may be located at different distances along a contour (in a contour-based wafer image). In the latter case, each evaluation point may be associated with a region of the contour.

[0181] FIG. 25 conceptually illustrates a process 2500 of some embodiments for using multiple evaluation points for each of multiple shapes to compare a simulated image of a primary layer with other images. Process 2500 is performed by a mask optimizer in some embodiments (e.g., performed in real time during optimization). Specifically, in some embodiments, process 2500 is performed by the optimizer at operation 1720 of FIG. 17 (i.e., at each iteration of process 1700). This approach is another approach for some embodiments to compare shapes in a simulated image of a primary layer with shapes in one or more adjacent layers.

[0182] As shown, process 2500 begins by selecting (at 2505) a shape in the primary layer (i.e., the layer being optimized) that is part of the MLI. In some embodiments, operations 2505-2515 are performed for each shape in the primary layer. Again, it should be understood that this is a conceptual process, and some embodiments perform these operations simultaneously for multiple simulated wafer shapes in parallel.

[0183] Next, the process selects (at 2510) a plurality of evaluation points for the selected shape. In some embodiments, the evaluation points are along the contour of the shape, while in other embodiments, the evaluation points also include the interior of the shape. Additionally, in some embodiments, the evaluation points are also located in the region around the contour of the shape. In some embodiments, the evaluation points are each a pixel in the wafer image (e.g., for a pixelated wafer image) or a specific subset of pixels (e.g., every other pixel, every fourth pixel, etc.). In other embodiments, the evaluation points are located at different distances (e.g., along the contour for contour-based wafer images) and / or at different distances inside the shape. For example, in some embodiments, the distance between the evaluation points is based on the gate pitch and / or metal pitch used in the process for manufacturing the IC (e.g., a specific number of nm). FIGS. 21 and 22 (described above and related to the selection of evaluation points for comparison of simulated wafer images to target wafer images) illustrate a multilayer interface having evaluation points defined along the contour of a primary layer shape (although, as noted, in some embodiments, the evaluation points are also located inside the shape).

[0184] The process 2500 then assigns (at 2515) weights to the evaluation points based on their relative importance in ensuring overlap between the selected shape and shapes on other layers forming the multi-layer component. The set of evaluation points in some embodiments includes (i) evaluation points that have no overlap with other layers, (ii) evaluation points that overlap with another layer but are less critical to accommodate the overlap, and (iii) evaluation points that are critical to accommodate the overlap.

[0185] In some embodiments, to identify criticality and assign weight values to evaluation points, the optimizer uses a set of lookup tables that specify such weight values (or specify how to assign weight values) based on (i) the layers involved in the MLI and (ii) the type of MLI. For example, some embodiments distinguish between MLIs formed by vias and line ends, vias and capacitor plates, pairs of capacitor plates, vias that intersect the middle of a line segment, vias that intersect the corner of a line segment, etc. In general, the number of different types of MLIs is a relatively small number, and it is reasonable to specify a lookup table for each type of MLI. In addition, because different wiring layers typically have different wire thicknesses, it is important to specify the layers.

[0186] Lookup tables for a specific layer group (such as layer pairs) as well as MLI types are used by the optimizer to determine the weight of each evaluation point in the main layer shape. For each MLI type as well as the layer group, different lookup tables are used according to which parts of the MLI are located in the main layer. For example, a consistent hole as well as a line segment will have weights assigned differently for their respective evaluation points. In some embodiments, weights are found for a subset indicating a definite evaluation point, and the optimizer interpolates between these assigned weights for the remaining evaluation points.

[0187] 26 conceptually plots a consistent hole shape 2605 as well as a line segment shape 2610 , where the through hole is slightly close to the end of the line segment (but not so close that the corner of the through hole is beyond the end of the line segment). This figure also plots nine evaluation points of the through-hole shape 2605—one in the center of the shape, four in the various "corners" of the approximate square shape, and four in the middle of each side of the shape. In some embodiments, for this type of shape, the lookup indicates that the evaluation point positioned in the middle of the shape is least important for the shape to be completely within (and large enough) within the line segment and will thereby be assigned the lowest weight value. The two evaluation points located in the middle of the left and right sides were assigned the highest weight values because they were most important for the shape to be within the line segment. The two evaluation points located in the middle of the top and bottom sides are more important than the central evaluation point, while the four corner evaluation points are more important than the top and bottom points but less important than the right and left points. For other evaluation point weights, in some embodiments, the optimizer interpolates between the specified weights based on the look-up table. In this example, evaluation points closer to the center will have lower weight values, and evaluation points closer to the right and left edges will have higher weights than those closer to the top and bottom edges. Other embodiments may use different computational techniques, or a user (e.g., a chip designer) may specify the weight values manually.

[0188] Procedure 2500 then determines (at 2520) whether the design layout contains additional shapes belonging to the multilayer component. It should be understood that shapes that do not contain any multilayer connections are still optimized, but only to match the target wafer image (i.e. multilayer alignment considerations need not be considered for this shape). Furthermore, procedure 2800 should be understood as a conceptual procedure and the optimizer in some embodiments practically simultaneously targets multiple shape judgment evaluation points simultaneously in parallel. If additional shapes are available for portions of multilayer components in the design layout, procedure 2800 returns to 2805 to select another such shape.

[0189] Once the evaluation points have been selected and grouped (or ranked) for all shapes, the process 2500 uses (at 2525) the grouped evaluation points to compare the simulated image of the primary layer with the images of the other layers. That is, the evaluation points are used to generate costs for each point or for the MLI as a whole. Different embodiments may use different techniques to calculate these costs.

[0190] For example, some embodiments identify for each evaluation point whether the evaluation point is inside, at the boundary of, or outside the shape of the other layer. In some embodiments, this may be determined based on the pixel dose value of the corresponding pixel in the other layer. That is, if the corresponding pixel has a value of 1.0, the evaluation point is inside the other shape; if the corresponding pixel has a value of 0.0, the evaluation point is outside the other shape; if the corresponding pixel has a value between 0 and 1, the evaluation point is at the boundary of the other shape.

[0191] For shapes that should be outside of the other shapes (e.g., a line end that intersects a via), some embodiments apply a cost based on the contour evaluation point being inside the shape. Thus, some embodiments only specify evaluation points along the contours of specific shapes in specific MLIs (e.g., shapes outside of an MLI). For shapes that should be inside of the other shapes (e.g., a via inside a line end), a cost is applied based on the evaluation point being outside of the shape. Some embodiments also apply a cost for being at a boundary, while other embodiments do not apply such a cost (because boundaries should be aligned in certain situations). In some embodiments, a cost is applied if the evaluation point is at the boundary of a shape in the other layer.

[0192] FIG27 conceptually illustrates a simulated through-hole shape 2705 partially outside of a line shape 2710 of another layer. This figure also illustrates a first evaluation point of the through-hole shape 2705 located inside the line shape 2710, a second evaluation point located at the boundary of the line shape, and a third evaluation point located outside the boundary of the line shape, some embodiments may impose a significant cost on the third evaluation point. Because this is an important (highly weighted) evaluation point, modifications to the mask that result in such misalignment are heavily penalized.

[0193] In some such embodiments, the loss function is expressed as a sum across each evaluation point, where each evaluation point has two costs that can be weighted differently for each point. More specifically, some embodiments define a single-layer cost for the evaluation point (i.e., based on the difference between a shape in a simulated wafer image and a shape in a target wafer image) and a multi-layer perceptual cost for the evaluation point (based on overlap with another shape in a simulated wafer image of a different layer). In some such embodiments, for each evaluation point, each cost is weighted based on relative importance. Some embodiments have the same weight for all single-layer costs, where the cost is simply based on the difference between a shape (or pixel value) in a simulated wafer image and a shape (or pixel value) in a target wafer image. In other embodiments, certain points may be weighted more heavily than other points. As discussed above, design layouts typically have rectilinear or straight-line edge features, but actual manufactured shapes are partially curvilinear, and therefore certain contours of manufactured shapes never perfectly match the design layout. Using corner rounding and other techniques to generate the target wafer image can improve this problem, but in certain cases, the target wafer image may have certain portions that cannot be perfectly matched despite corner rounding. Therefore, some embodiments weight the cost of these points less than the cost of points that should more closely match the target wafer image, so that the gradient causes the mask update to push the latter evaluation points more than the former evaluation points.

[0194] The optimizer then modifies the mask pixel image of the main layer based on this loss function. As described above, this involves taking the gradient of each pixel (or contour) of the mask image relative to the loss function in an attempt to push the loss function towards a local minimum (however, this process may involve making the loss function worse in the short term to escape from a suboptimal local minimum and to find a better local minimum). Examples of mask image modification (addition, removal and movement of SRAFs) are described above with reference to FIGS. 14A-14B and 15A-15B.

[0195] The above description provides several different schemes used by different embodiments to calculate the loss function using information from other layers to inform the modification of the mask layout of the main layer. It should be understood by those skilled in the art that other embodiments may use other different techniques to calculate the loss function terms that take into account MLIs.

[0196] For example, some embodiments calculate one or more tolerance regions for each primary layer component shape in a simulation area, the tolerance regions being used to constrain the boundaries of the primary layer shape (by assessing the cost of the primary layer shape that exceeds the tolerance region). In some embodiments, the tolerance region is specifically used to account for misalignment of a shape. Some such embodiments do not assess the cost of the primary layer shapes that are contained within the tolerance region, and then assess additional cost based on the extent to which the primary layer shape extends outside the tolerance region.

[0197] Some embodiments define a set of multiple tolerance zones for a given master layer shape based on the positions of shapes in the other layers (the other layers that form the MLI with the master layer shape) and shapes (as well as the shapes of the master layer components). In some such embodiments, a first tolerance zone represents an acceptable range of misalignment, a second tolerance zone represents a slightly acceptable range of misalignment, and a third tolerance zone represents an unacceptable range of misalignment. In this scheme, if the master layer shape is anywhere within the boundaries of the first tolerance zone, no cost is applied (however, the position of the master layer shape is still restricted based on the single layer cost). If the master layer shape is partially outside the first tolerance zone but within the second tolerance zone, a first level cost is applied. If any part of the master layer shape is outside the second tolerance zone (and therefore within the third tolerance zone), a much higher cost is applied, so that mask image modifications that lead to such a scenario are likely to be rejected. Some embodiments apply the third tolerance zone as a restriction, so that any mask image modification that leads to a scenario where the master layer shape extends into the third tolerance zone is directly rejected.

[0198] FIG. 28 conceptually illustrates a process 2800 of using tolerances of shapes in a layer of simulated wafers to calculate costs of MLIs containing shapes in the layer in some embodiments. Process 2800 is performed by a mask optimizer in some embodiments (e.g., performed in real time during optimization). In other embodiments, process 2800 is performed partially before optimization (i.e., determination of tolerances) and partially during optimization (i.e., adjustment of masks based on evaluation points).

[0199] As shown, process 2800 begins by selecting (at 2805) a shape in the current layer (i.e., the layer being optimized) that is part of a multi-layer component in the design layout. If performed before the optimizer generates a simulated wafer image, these shapes may refer to specific shapes in the design layout. In other embodiments, process 2800 is performed during optimization, and the shapes refer to predicted manufacturing shapes in the simulation and / or target wafer image (which should correspond to the design layout shapes).

[0200] Process 2800 then selects (at 2810) one or more tolerance zones for the selected shape to ensure that the shape overlaps one or more shapes on other layers forming the multi-layer component. In some embodiments, the tolerance zone is an area in the wafer image where the outer boundaries of the outline can be moved while the overlap is still resilient to misalignment and / or other process variations. The tolerance zone is automatically generated by the optimizer in some embodiments by determining where the selected shape can be located and still completely overlap with shapes in other layers where the selected shape forms the multi-layer component. In other embodiments, the tolerance zone can be manually defined (e.g., by a user of a mask production tool that includes the optimizer).

[0201] FIG. 29 conceptually illustrates an example of a tolerance region for an elliptical shape 2905 overlapping a via shape 2910. The left side of the figure illustrates an elliptical shape 2905, which represents a plate (e.g., one half of a pair of capacitor plates forming a capacitor) in a metal layer (in the case where the shape 2905 uses multiple other layers to form a multi-layer component). The capacitor plate represented by shape 2905 is connected to a line represented by shape 2915 (i.e., in another metal layer) through a via (represented by shape 2910 (i.e., in an adjacent via layer)). In this example, the overlap considered is the metal plate and the via (the via layer can be optimized separately to ensure overlap with both the wire and the metal plate). As such, the optimizer defines a tolerance region 2900 (represented by the gray area on the right side of the figure). This tolerance region 2900 is the area that should be included in the outline of the elliptical shape 2905 so that the elliptical shape 2905 overlaps the entirety of the via shape 2910. The tolerance region 2900 in this case shares a boundary with the actual shape 2905 at the lower right, but is significantly larger than the shape 2905 at the upper left region (because if the outline of the elliptical shape 2905 is moved in this direction, the compliance of the overlap will be maintained (or potentially improved)). It should be understood that the outline of the shape 2905 may also be constrained by other factors, such as ensuring sufficient overlap with the locations of other capacitive plates forming the capacitor.

[0202] In some embodiments, the tolerance zone is calculated using the pixel coordinates (i.e., xy coordinates) of the main layer and other layer shapes. For a given MLI (where the main layer shape needs to completely contain the shape in the other layer), some embodiments substantially move the main layer shape in the xy plane to completely surround the smaller shape in the other layer while aligning with the boundary of the smaller shape on one side (or at a point). The union of the main layer shape's outer boundary across these movements can then form the tolerance zone. In the example shown in FIG. 29 , if shape 2905 is moved across the xy plane while always meeting the boundary of shape 2910 at a point, then the tolerance zone shape 2900 is identified.

[0203] Other embodiments calculate a set of distances across the main layer shape in various different directions (e.g., four cardinal and four inter-cardinal directions or a larger set of directions). For each particular direction, a line can be drawn from the center of the enclosed shape in the other layer to the edge of the shape in the opposite direction, and then the calculated distance in the particular direction measured from that point is used to identify the boundary of the tolerance zone. In the example shown in FIG. 29 , for example, the distance across the elliptical shape 2905 in the left-right (east-west) direction and through the center of the shape can be measured. The right boundary of the tolerance zone 2900 is then calculated as this measured distance from the left edge of the through-hole shape 2910.

[0204] FIG. 30 conceptually illustrates another example of a tolerance region for a through hole shape 3005 connecting two conductors in different metal layers. The left side of the figure illustrates the through hole shape 3005 and line segment shapes 3010, 3015. The two line segments represented by these shapes are located in two different metal layers and connected by the through hole. As shown, the simulated through hole shape 3005 is currently completely located within the first line segment 3010 (which extends in the left-right direction) but is too far to the right and is therefore partially located outside the boundary of the line segment 3015 (which extends in the up-down direction). In this example, the overlap of the through hole shape 3005 is considered to be the overlap with these line segments. Thus, the tolerance region 3000 is illustrated in gray on the right side of the figure as the intersection of these two line segments. That is, the through hole shape 3005 should be within this square (or approximately square) area 3000. The through hole shape 3005 is currently partially outside of this region, so a cost will be imposed on the through hole shape which will result in a mask image modification that attempts to move the outline back to the left (preferably without directly shrinking the through hole shape).

[0205] In some embodiments, when the main layer shape should be completely enclosed by one or more shapes in other layers (such as FIG. 30 ), the tolerance region is simply the boundaries of these shapes. In other words, the main layer shape is constrained to ensure that this shape completely overlaps the shapes in other layers that should enclose it.

[0206] Returning to FIG. 28 , process 2800 then determines (at 2815) whether the simulated wafer image includes additional shapes that are part of the MLI. It should be understood that shapes that do not include any multi-layer connections are still optimized, but only to match the target wafer image (i.e., multi-layer alignment considerations need not be considered for such shapes). Furthermore, it should be understood that process 2800 is a conceptual process, and the optimizer actually determines tolerances for multiple shapes (rather than just one shape) simultaneously in parallel in some embodiments. If there are additional shapes that are part of the multi-layer components in the design layout, process 2800 returns to 2805 to select another such shape.

[0207] Once the tolerance domain has been specified for all shapes, the process 2800 uses the tolerance domain to calculate (at 2820) the cost of the shape. This process, in some embodiments, involves identifying the cost of each shape in the layer that belongs to the MLI. Specifically, some embodiments ensure that a shape is completely within its tolerance domain. If a shape is completely within its tolerance domain, the cost is zero. If a shape is partially or completely outside its tolerance domain, a higher cost is applied.

[0208] To determine whether a shape is inside or outside of a tolerance domain, some embodiments compare the pixel values of the shape with the pixel values assigned to the tolerance domain. In some embodiments, the tolerance domain is considered to be a shape that has a value of 1.0 inside, a value between 0 and 1 at the boundary, and a value of 0.0 outside the boundary. Pixel locations that form the outline of the primary layer shape (i.e., pixels with pixel values between 0 and 1) are identified in the tolerance domain, and ideally, all such pixel locations have non-zero values in the tolerance domain. Costs are applied based on, for example, the primary layer shape outline being outside of the tolerance domain. Some embodiments also define a second tolerance zone that is concentric with the first tolerance zone but located outside the first tolerance zone, and applies different amounts of cost based on the following conditions: whether the main layer shape is outside the first tolerance zone but within the second tolerance zone (a higher cost than being completely within the tolerance zone), or whether the main layer shape also exceeds the second tolerance zone (a higher cost than if the shape is completely outside the boundary area but exceeds the first tolerance zone) and is therefore within a third tolerance zone (which can be defined as the area outside the second tolerance zone).

[0209] Additionally, in some embodiments, modifications to the mask layout image are at least partially constrained by tolerance domains. For example, modifications that may result in a shape being moved or otherwise modified outside of a first tolerance domain are discouraged, and modifications that may result in a shape being moved or otherwise modified outside of a second tolerance domain are prohibited. In some embodiments, this may be achieved by applying a cost due to a gradient calculated relative to the mask layout shape.

[0210] The above description provides examples of various different techniques that can be used to incorporate additional (e.g., adjacent) layers into consideration for iterative mask optimization of simulated wafer images. These different techniques use different loss functions, which are essentially one term that considers single layer cost (i.e., the difference between the simulated wafer image and the target wafer image) and a second term that considers multi-layer aware costs and is used to produce a mask that makes the multi-layer overlap region resistant to process variations during processing.

[0211] When optimizing one or more mask images for a layer, the optimizer of some embodiments uses a penalty function that takes into account misalignment between features of adjacent layers (as specified in the overall manufacturability score). In some embodiments, this penalty function term (as well as the comparison term) takes into account extreme process conditions that may occur during the fabrication of the primary layer or adjacent layers (e.g., due to the depth of focus used when passing the mask through the mask during wafer processing or the dose used during mask processing).

[0212] In other embodiments, the penalty function includes separate terms that account for extreme process conditions that may occur when manufacturing adjacent layers. That is, the first term (e.g., the total manufacturability score) accounts for process variation caused by misalignment, while the second term (described below) accounts for other process variations during the process. Misalignment variation can cause the manufactured parts (or the predicted manufactured shapes of these parts during simulation) to shift left, right, up, down, or a combination thereof in the plane of a layer. Other process variations (e.g., depth of focus and exposure intensity) can cause the manufactured parts (or the predicted manufactured shapes of these parts during simulation) to be larger or smaller than the optimal condition. As such, some embodiments consider minimum, nominal (average), and maximum process variations for each predicted manufactured shape and take these possibilities into account in separate terms in the penalty function.

[0213] Thus, a simulated wafer image of a layer may include multiple sets of predicted shapes, or multiple wafer images are simulated, wherein each set of predicted shapes in the wafer image is associated with a different set of process conditions. These sets of process conditions in some embodiments include at least one set of minimum process conditions, a set of maximum process conditions, and a set of nominal process conditions. These different sets of process conditions represent different process parameters, and each set of process conditions includes different values of each process parameter.

[0214] The set of process parameters in some embodiments includes one or more process parameters related to at least one of the depth of focus and the exposure intensity used during the wafer processing. In such embodiments, each mask image in each mask image set is generated to represent a different process parameter that may occur during the wafer processing. Alternatively or in addition, the set of process parameters includes one or more process parameters related to the dose used in the mask process. In such embodiments, each mask image in each mask image set is generated to represent a different process parameter that may occur during the wafer processing (e.g., the mask generation process).

[0215] In order to calculate the penalty function that takes into account extreme process parameters (i.e., extreme sets of process conditions), some embodiments calculate additional terms (e.g., called extreme process variation scores) that specifically take into account the extreme process parameters of adjacent layers to include in the penalty function. The calculation of the extreme process variation score is similar in some embodiments to the calculation of the overall manufacturability score described above. For example, some embodiments use the maximum profile of the via and the minimum profile of the metal line segment (since these sets of profiles will show the minimum overlap of the line segment on the via pad that may occur based on different process conditions). Other embodiments use the minimum profile of each component belonging to a specific MLI or use various combinations of minimum, nominal, and maximum profiles when evaluating a specific MLI.

[0216] Using these different profiles, some embodiments compute resilience polygons (as described above) that are assigned resilience scores to cluster extreme process variation scores. ßjPVS. This score can then be included in the following loss function: H =∫ ∫ |(𝜓)-𝜙|+𝑤 tms∗𝛴𝛼i𝐼𝑆𝐶+ 𝑤 pvs∗𝛴ßjPVS (6)

[0217] Those skilled in the art will appreciate that other clustering methods are used in some embodiments to calculate process variation for multi-layer interfaces of layers, and the above description is exemplary. Weighting factors ßj are included in the extreme process variation score in some embodiments to weight the individual resilience scores of different MLIs to different degrees. Weights 𝑤 pvs are applied to the extreme process variation score in the loss function in some embodiments, and the weights 𝑤 pvs can be defined by the mask layout designer to specify the degree to which this value affects the resulting value of the loss function.

[0218] FIG31 conceptually illustrates an example of a multilayer interface including an intersection of a metal layer (shown in solid lines) and a via (shown in dashed lines) in an adjacent via layer. This figure illustrates these components in a design layout 3100, a first wafer simulation 3105 for a first extreme process variation, and a second wafer simulation 3110 for a second extreme process variation. The design layout 3100 shows that the interconnect line segments are straight line segments with a jog in the middle of the line segment. The via locations are rectangles that fit into this jog.

[0219] The first wafer simulation 3105 shows the results of the first extreme process variation producing a larger feature shape; in this case, the overlap area between the via and the interconnect segment is large and does not cause manufacturing issues. However, the second wafer simulation 3110 shows the results of the first extreme process variation producing a smaller feature shape. In this latter case, not only is the feature shape predicted to be smaller, but because of the corners of the interconnect segment, this results in significantly less overlap. Thus, this multilayer interface is not ideally resistant to extreme process variation (at least at the low end of feature shape size), and the mask image should be adjusted to compensate.

[0220] In some embodiments, some embodiments optimize mask images of multiple layers (e.g., through-via-metal or metal-through-via-metal layers) simultaneously while non-optimizing the mask of one layer of the design layout at a time to produce multiple optimized mask images for multiple layers at a time. Specifically, some implementations simulate wafer images for multiple layers (e.g., multiple adjacent layers) based on the mask images of the layers and use the simulated wafer images to update the mask images of the layers.

[0221] FIG. 32 conceptually illustrates an example of a high-level mask image co-optimization process that uses inputs corresponding to multiple layers to produce optimized mask images of the multiple layers (or optimized sets of mask images). As shown, the inputs to the optimization process 3200 include target wafer images 3205 of the multiple layers (rather than a single primary layer) to be optimized and initial masks 3210 for each of the layers. In some embodiments, each set of mask images is optimized individually as a single layer (i.e., without considering multi-layer interactions) using conventional mask image optimization prior to performing the co-optimization operation. In other embodiments, individual layer mask image optimizations are neighbor-layer aware, as described above. After the initial optimization, additional iterations are performed in some embodiments to perform the co-optimization. The second input is process information 3215 (e.g., process model, process variation or conditions, etc.).

[0222] With reference to FIG. 17 , which only optimizes a single-layer mask, the optimization process 3200 of some embodiments may modify multiple layers of masks at each iteration. In some embodiments, the layers for which the mask is optimized are adjacent layer pairs (e.g., a through-hole layer and a metal layer, a contact layer and a metal layer), a group of three consecutive layers (e.g., a metal layer and two through-hole layers, a through-hole layer and two metal layers, a metal layer with a through-hole layer on one side and a contact layer on the other side, etc.).

[0223] Because the mask for each layer may change at each iteration, the optimization process 3200 in some embodiments performs a wafer simulation for each layer during each iteration. The predicted manufacturing shapes of the simulated wafer images are compared to the target wafer images (where each layer is considered independently), and the interaction between the predicted manufacturing shapes of multiple layers is considered. Some embodiments use the same fitness score for each overlap to evaluate the cost of the overlap area of the simulated wafer images, but apply the optimization to the mask images of multiple layers during at least some iterations. As shown, the output of the iterative optimization process 3200 is a set of optimized masks 3220 for each layer and optionally includes one or more wafer volume images 3225 for each layer.

[0224] In essence, this optimization is a co-optimization of multiple layers of mask images simultaneously. In some embodiments, at each iteration, multiple layers of wafer space images are processed and aggregated to produce a composite overhang compliance feature at each layer interface, which is then weighted and included in the multi-layer loss function Hm to optimize the layers in that layer interface. The multi-layer loss function Hm thus sums up the individual layer loss functions (e.g., summing up multiple instances of the |𝑓(𝜓)-𝜙| term, where one instance of this term for each layer is optimized) and then summing up the weighted total manufacturability score: Hm =𝛴∫ ∫ |(𝜓)-𝜙| + 𝑤 tms∗ 𝛴𝛼i𝐼𝑆𝐶 (7)

[0225] Thus, the resulting layer mask images are essentially co-optimized on a per-location (or in some embodiments per-wafer shape-edge) basis to ensure that each specific shape location or edge of the design layout is manufacturable (i.e., interactions between wafer shapes on multiple layers (e.g., multi-layer interface overhang areas) are fully accounted for during the optimization process).

[0226] In some embodiments, the iterative optimizer 3200 performs a process similar to the process 1700 shown in FIG. 17 , but with some changes that should be noted. Specifically, because no layer is necessarily unchanged from one iteration to another, the optimizer simulates a wafer image for each layer being optimized during each iteration. In addition, the loss function used to determine how to modify the various images includes a term comparing the simulated wafer image to the target wafer image for each layer (as shown in Equation 7) and a term including all MLIs across the layers. In some embodiments, for each mask image (e.g., for a particular layer) for which the wafer image comparison term |𝑓(𝜓)-𝜙| is included in the loss function, the optimizer calculates the gradient of the term with respect to each pixel of the mask image for the particular layer. The mask image optimizer also calculates the gradient of the term 𝑤 tms∗𝛴𝛼i𝐼𝑆𝐶 with respect to each MLI.

[0227] Since the explicit position of a component in one layer is related to the position of other components in other layers in some embodiments, simultaneous modification of multiple mask images may be advantageous. In some such embodiments, the mask image is optimized and used to generate one or more masks, wherein each mask is used for the fabrication of its corresponding layer.

[0228] As discussed above, some embodiments perform wafer simulation to generate a simulated wafer image from a mask pixel image, and then use the simulated wafer image to modify the mask pixel image (or a mask image corresponding to the mask pixel image). FIG. 33 conceptually illustrates a process 3300 for performing wafer simulation in some embodiments. Process 3300 is performed in some embodiments by a wafer simulator (e.g., part of a mask production or other EDA tool) that uses an input mask image to perform wafer simulation as part of a mask layout optimization process. In other embodiments, however, other algorithmic processes may perform process 3300.

[0229] Process 3300 begins by receiving (at 3305) a set of mask pixel images. In some embodiments, the set of mask pixel images corresponds to one or more layers of a design layout. The design layout, in some embodiments, is a final version of the design layout of an IC (i.e., physical design and layout verification have been completed at this point). The mask pixel images, in some embodiments, are based on mask images (e.g., outline mask images) of attempts to generate a mask layout for manufacturing an IC according to the design layout.

[0230] In some embodiments, the wafer simulator receives the set of one or more mask pixel images from a rasterizer that rasterizes a set of mask images to produce the set of mask pixel images. In other embodiments, the wafer simulator receives the mask pixel images from a machine trained (MT) network (e.g., a neural network) that rasterizes the set of mask pixel images from the set of mask images. In other embodiments, the wafer simulator itself performs the rasterization of the mask images to produce the set of mask pixel images.

[0231] Next, the process 3300 performs a set of operations 3310-3325, which may be collectively referred to as the antecedent operator 3307. As described above, the antecedent operator 3307 is a simulation process that calculates simulated wafer images from mask images. First, at 3310, the process 3300 combines the set of mask pixel images with a light source model, mask bias, and 3D effect model. At 3315, the process 3300 simulates exposure to produce a set of spatial intensity images. At 3320, the process 3300 performs simulated photoresist development operations, and at 3325, the process 3300 performs simulated etching operations to produce a set of wafer images. These wafer images provide a simulation of what a wafer would look like if it were actually manufactured using a mask associated with the set of mask pixel images.

[0232] Finally, the process 3300 provides (at 3330) the set of wafer images as outputs of the set of mask pixel images. When the set of wafer images is output from the preceding operator 3307, the wafer simulator outputs the set of wafer images as outputs. The process 3300 then ends. The set of wafer images may be used to modify a mask image corresponding to the set of wafer images, for example, by calculating a loss function that specifies the difference between the set of wafer images and a set of target wafer images (the target wafer images are generated by, for example, applying a low pass filter, Gaussian convolution, and / or corner rounding algorithm to the interconnect layers of the design layout). In some embodiments, a set of wafer contours is generated from the set of wafer images after the wafer simulator generates the set of wafer images. In some such embodiments, the set of wafer contours is used to modify the mask image, for example, by calculating a loss function that specifies the difference between the set of wafer contours and a set of target wafer contours.

[0233] The above process 3300 is performed by a wafer simulator that uses mask images to generate simulated wafer images. Some embodiments use an MT network (e.g., a neural network) to generate simulated wafer images that are subsequently used to modify one or more mask images, rather than using a wafer simulator. Because multiple wafer spatial images (e.g., simulated wafer images) for various different process conditions (including misalignment and different process extremes) are generated for each layer being optimized and adjacent layers, some embodiments use the MT network to increase the speed and efficiency of wafer simulation (and therefore the speed and efficiency of the optimization process).

[0234] FIG. 34 conceptually illustrates an example of a high-level mask image optimization process of some embodiments that uses inputs corresponding to multiple layers and simultaneously utilizes deep learning (e.g., an MT network) to produce an optimized mask image (or set of mask images) for a single layer. Similar to optimization process 1600, iterative optimization process 3400 receives as input a target wafer image 3405 of a single layer (a primary layer to be optimized), an initial mask 3410 for the primary layer, one or more masks 3412 of one or more adjacent layers (which have already been optimized in some embodiments), and process information 3415 (e.g., a process model, process variations or conditions, etc.). The outputs of optimization process 3400 are the same as the outputs of process 1600: a mask image 3420 of the optimized set of primary layers and one or more wafer spatial images 3425 generated from the optimized mask layout.

[0235] The iterative optimization process 3400 generates these simulated wafer images using an MT network (e.g., a trained neural network) rather than performing a dedicated set of operations (e.g., as shown in FIG. 33 ) to determine the wafer spatial image of the input layer target. Such an MT network (or other deep learning model) can quickly infer the wafer image of each layer based on the mask image accepted as input. In some embodiments, the implementations and schemes described in U.S. Patent Application No. 16 / 949,270 (now published as U.S. Patent Publication No. 2022 / 0128899) are used to determine the wafer spatial image from the layout design.

[0236] Because the MT network (or multiple MT networks to generate different wafer simulations for different process variations) is only used for speculation during optimization (i.e., training has been completed previously), the optimization process of such embodiments can operate quickly. As discussed above, the simulation of adjacent layers (whether performed by the MT network or traditional wafer simulation) only needs to be performed once (i.e., as a preliminary operation) rather than being performed at each optimization iteration. After using the MT network to determine the wafer simulation of the adjacent layer once, some embodiments use lithography simulation to calculate the main layer wafer simulation from the current mask image at each iteration. Other embodiments use the MT network for each simulated wafer image (i.e., across each iteration of the optimization process). The implementation and scheme described in U.S. Patent Publication No. 2022 / 0128899 are based on convolutional neural networks, particularly convolutional neural networks with a U-net based architecture. In some embodiments, other high-performance and computer vision based neural networks are also used without departing from the spirit of this technology.

[0237] Some embodiments use an MT network for a multi-layer co-optimization procedure similar to Figure 32. In this case, given the mask images of the layer groups for the current iteration, the mask wafer digital twin (trained MT network) is used to quickly infer the simulated wafer space images corresponding to the layers being co-optimized.

[0238] In some embodiments, each set of mask images is individually optimized in a single-layer fashion (i.e., without considering multi-layer interactions) using conventional mask image optimization prior to performing a co-optimization operation. In other embodiments, individual layer mask image optimization is neighbor-layer aware, as described above. After the initial optimization, additional iterations are performed in some embodiments to perform co-optimization. In some such embodiments, given the mask images for each iteration, a mask wafer digital twin MT network is used to produce wafer space images for each layer. In some embodiments, these wafer images are then processed and aggregated to generate manufacturability loss terms or terms in a multi-layer loss function H m that are included in the co-optimization loop iterations. In some embodiments, one or more additional iterations may optionally be used using a full lithography simulation operation (e.g., as shown in FIG. 33 ) rather than a mask wafer digital twin MT network.

[0239] Thanks to these procedures, multiple layers of mask images are optimized for optimal manufacturability, taking into account all interactions between the wafer shapes on each layer (e.g. overhangs based on z-axis analysis, joint analysis or simplified joint analysis). Furthermore, the speed of the digital twin inference operation significantly improves the overall yield and ensures traceability.

[0240] FIG. 35 conceptually illustrates the use of a neural network 3500 to produce an output of a wafer image 3510 from a set of mask pixel images 3520. The figure illustrates the inference of wafer images 3510 using digital input data (mask pixel images) 3520. When the neural network is executed on a modern GPU architecture, the inference time, even for relatively large designs, can be reduced to interactive time frames (i.e., seconds). In some embodiments, each set of one or more mask pixel images 3520 for a particular layer of the design layout is provided as input to the neural network 3500, which outputs one or more wafer images 3510 for that layer (e.g., multiple different wafer images for different sets of process conditions). It should be understood that while some embodiments use neural networks, other embodiments use other machine learning procedures to develop predictions of the final shape that will be obtained once the IC is manufactured.

[0241] Other embodiments use N neural networks instead of one neural network, where each neural network produces one of N different predicted output wafer images for one or more mask pixel images for a layer. For example, if multiple simulated wafer images are generated from a set of mask pixel images (e.g., for different sets of process conditions), multiple different copies of a single output network may be used. For example, for each possible set of process conditions and misalignments, one network may generate a simulated wafer image for a minimum set of process conditions and a first misalignment, a second network may generate a simulated wafer image for a maximum set of process conditions and a first misalignment, a third network may generate a simulated wafer image for a nominal set of process conditions and a second misalignment, and so on. These multiple networks may be trained in parallel such that the networks have the same network architecture but have different training weight values. FIG. 36 conceptually illustrates multiple networks 3600, each network 3600 being trained to generate a different wafer image for a layer given a set of one or more mask pixel images 3620 received as input.

[0242] Although FIGS. 35 and 36 illustrate the use of one or more neural networks to generate wafer images from mask pixel images, other embodiments use other algorithms to generate wafer images. Other embodiments use machine trained networks to generate a first set of wafer images while using other algorithms to generate a second set of wafer images. Any suitable combination of machine trained networks (e.g., neural networks) and other algorithms may be used to perform the operations described throughout this specification.

[0243] In addition, some embodiments use a machine trained network (e.g., a neural network) to rasterize the mask image into a mask pixel image. A machine trained network similar to the neural network 3500 or the neural network 3600 can be used for rasterization. Examples of neural network models are described in U.S. Patent Application Nos. 16 / 949,270 and 17 / 992,870 (now published as U.S. Patent Publication Nos. 2022 / 0128899 and 2023 / 0168660), which are incorporated herein by reference.

[0244] FIG. 37 illustrates a novel scheme 3700 for performing mask image optimization using a wafer-simulated neural network. In this scheme, at 3715, image rasterization is performed on a mask layout 3710 (or a layer of a mask layout) to produce one or more mask pixel images (e.g., a mask pixel image for each mask image in the mask layout 3710), otherwise referred to as a 2-D image (e.g., a multi-channel 2-D image). The rasterization process is to take an image in a geometric / vector graphic format (a shape) and convert the image into a raster image (a series of pixels, points, or lines that when presented together produce an image represented using a shape). In some embodiments, a machine trained network performs the image rasterization 3715. In other embodiments, other algorithms perform the rasterization 3715. An example of such a multi-channel 2-D image is a pixel dose map (e.g., pixel dose map 1810 of FIG. 18).

[0245] In some embodiments, the image rasterizer 3715 generates white pixels for completely filled pixels (e.g., pixels that do not cover any shapes representing holes that will be generated in the mask from the mask layout), black pixels for completely empty pixels (e.g., pixels that are completely covered by shapes representing holes that will be generated in the mask from the mask layout), and gray pixels for partially filled pixels. In some such embodiments, completely filled pixels are represented by a value of 1.0, completely empty pixels are represented by a value of 0.0, and partially filled pixels are represented by a value in the range of [0,1] representing the area of the pixel filled by the shape (e.g., a pixel that is 50% filled would have a value of 0.5). Prior to rasterizing the mask image of the mask layout 3710, some embodiments decompose the mask image into a number of components (e.g., a number of transparent areas, a number of SRAFs, etc.), which are then rasterized individually.

[0246] The multi-channel 2-D image 3720 is then used as the primary input to a wafer simulation neural network 3725 (or a set of multiple neural networks), which in some embodiments generates one or more wafer images 3730. The neural network 3725 generates wafer pixel images, which are then converted to wafer outlines in a post-processing operation 3735. In other embodiments, the neural network 3725 directly generates wafer outlines. Different wafer images 3730 generated for a single layer correspond to different sets of process conditions and / or misalignments; in addition, some embodiments generate wafer images 3730 for multiple different layers of the design layout (based on different sets of mask images corresponding to mask layers). The machine training network 3725 is referred to in some embodiments as a "digital twin" of the lithography simulation process that uses mask pixel images for wafer simulation.

[0247] In some embodiments, the wafer image 3730 generated by the trained neural network 3725 is analyzed to generate the value of the loss function 3740. To this end, the wafer image 3730 is supplied to a wafer image analysis operation 3735, which produces a loss function 3740 as an output. As shown, this loss function 3740 (e.g., Equation 6 above) includes terms that take into account each set of mask images of the mask layout 3710 being optimized. In this example, the loss function 3740 is the sum of individual loss functions, where each individual loss function is included to optimize the mask images of different layers of the mask layout 3710. When only one layer of the mask layout 3710 is optimized, the loss function 3740 uses Equation 5. When extreme process conditions are also taken into account as separate loss function terms, the loss function 3740 includes additional terms for extreme process variation scores (e.g., Equation 7).

[0248] After generating the loss function 3740, some embodiments perform mask layout modifications at 3745 to modify the mask layout 3710 using the loss function 3740. To perform these modifications, some embodiments compute a set of gradient calculations based on the terms of the loss function that indicate how to modify one or more mask images of the mask layout 3710. The mask layout 3710 may then be modified based on these calculated gradients. The result of this modification is an updated mask layout 3750. In some embodiments, multiple iterations of mask layout optimization are performed. In some such embodiments, after the mask layout is updated at 3750, the updated mask layout is rasterized again (at 3715) to generate a new set of mask pixel images, which are used to update the mask layout again.

[0249] In some embodiments, other embodiments modify the mask pixel image 3720 rather than modifying the mask layout 3710 (at 3745). In such embodiments, the mask pixel image is iteratively updated, and once optimization has concluded, a contour extraction operation is performed to generate an optimized mask layout from the optimized mask pixel image. For example, in some embodiments, the mask layout 3710 is rasterized into pixel dose maps (one pixel dose map for each mask image), the set of pixel dose maps is modified at 3745, and once optimization is complete, the optimized pixel dose maps are converted back into the contour domain to obtain the optimized mask layout.

[0250] To train the neural network 3725, some embodiments use a known set of inputs (e.g., known mask layouts) and a known set of outputs (e.g., corresponding wafer images). To produce these known input / output sets, some embodiments use an algorithmic wafer simulation scheme, such as the lithography simulation process 3300 of FIG. 33. During training, groups of known input sets are latticed, passed through the neural network 3725, and post-processed to produce groups of output sets. The difference between the produced set of output sets and the known set of outputs for each group of known input sets is an error value, which is backpropagated through the neural network 3725 to train its trainable parameters (e.g., its weight values, bias values, etc.). Some embodiments perform training once for each process technique, and then perform the operation of FIG. 37 to perform mask layout optimization once or more times during IC design.

[0251] FIG38 conceptually illustrates a process 3800 of some embodiments for generating training data to train one or more MT networks (e.g., one or more neural networks) to generate wafer images based on mask pixel images of a mask layout of an IC design or a portion of an IC design. The process 3800 is performed in some embodiments to generate training data for use in training configurable parameters of one or more MT networks (e.g., the networks shown in FIGS. 35-37 ) so that these MT networks can be used to optimize mask layouts for design layout production of an IC.

[0252] The process 3800 begins by first selecting (at 3805) a portion of a sample set of mask pixel images as sample inputs for which the process is to generate one or more predicted output wafer images. In some embodiments, the process 3800 uses a plurality of different sample mask layouts from which sample input mask pixel images are captured. The captured input mask pixel image set corresponds to a previously defined physical design that may or may not have been used to fabricate an IC on a substrate (e.g., a silicon wafer). In some embodiments, the process 3800 selects a portion of a sample set of mask images from one or more mask layouts and then rasterizes the mask images into mask pixel images.

[0253] Next, the process 3800 combines (at 3810) the sample set of the selected mask pixel images with the light source model, the mask bias, and the 3D effect model, and simulates (at 3815) exposure to produce a set of spatial intensity images. The process 3800 then simulates (at 3820) photoresist development and etching to produce a set of known output wafer images. These known output wafer images indicate how a wafer would appear when manufactured using the masks associated with the set of mask pixel images.

[0254] At 3825, the process 3800 determines whether a sufficient number of input mask pixel images and output wafer images have been generated. If not, the process returns to 3805 to select another input set of mask pixel images from one or more previously defined mask layouts, and then repeats operations 3810-3820 to generate a simulated set of wafer images for this set of input mask pixel images. As described above, the selected input mask pixel images and their corresponding generated output wafer images represent known inputs and known outputs used to train the MT neural network in some embodiments.

[0255] Calculating a pattern to be fabricated on a substrate by calculating a plurality of wafer simulation patterns from a plurality of calculated mask images (derived from a plurality of calculations) can be very time consuming. Therefore, some embodiments use process 3800 of FIG. 38 to generate an array of known inputs / outputs, and then use these known inputs / outputs (at 3830) to train an MT network (e.g., a neural network) so that the MT network can subsequently be used to quickly produce predicted wafer images from input mask pixel images examined during a mask optimization process.

[0256] The above process 3800 uses the sampled mask pixel image as the input of the training data of the MT network. In other embodiments, the sampled mask image (i.e., the mask image that has not been rasterized into the mask pixel image) is used as the input of the training data. In such embodiments, the mask image is used as the input of the MT network to produce the predicted wafer image.

[0257] FIG. 39 conceptually illustrates a process 3900 of some embodiments for training configurable parameters of an MT network having a plurality of processing nodes, the MT network being used during optimization of a mask layout of a design layout being produced for an IC. The process 3900 is performed in some embodiments to train the MT network so that the network can be used during optimization of the mask image to produce wafer images from mask images of one or more layers of the corresponding design layout. The wafer image represents the components that will be manufactured for that layer using masks manufactured based on the mask image. Once optimized, the mask image is used to produce masks for manufacturing ICs having layers of the design layout.

[0258] The process 3900 begins by receiving (at 3905) a plurality of sets of known input mask images and known associated simulated wafer images. The process 3900 of some embodiments receives a plurality of sets of known input mask images from one or more mask layouts of one or more design layouts to train the MT network. For example, the sets of known input mask images in some embodiments include different known input mask images for different IC layer types (e.g., a via layer between two metal layers, a contact layer between a metal layer and a device layer, etc.). Using mask images of different layer types when training the MT network ensures that the MT network will be able to generate wafer images for different types of layers.

[0259] In order to generate known associated simulated wafer images, some embodiments perform process 3900 before (1) rasterizing the sets of known input mask images into multiple sets of known input mask pixel images and (2) performing wafer simulation operations to generate known associated simulated wafer images from the sets of known input mask pixel images (e.g., the above-mentioned process 3800).

[0260] The process 3900 then rasterizes (at 3910) the set of known input mask images into a plurality of sets of known input mask pixel images. Some embodiments use another pre-trained MT network that rasterizes the images into pixel images. In other embodiments, this process is performed by using an algorithm. Other embodiments do not rasterize the known input mask images into known input mask pixel images, but instead use the mask images as input to the MT network.

[0261] The process 3900 then supplies (at 3915) known input mask pixel images to the MT network. These input mask pixel images are propagated through the MT network to produce output wafer images. For each input mask pixel image, the output wafer image (or set of images) is compared to a known simulated wafer image of the input mask pixel image to calculate an error value. Some embodiments calculate the error value based on the difference between the output wafer image and the known associated simulated wafer image. After calculating the error, the process 3900 uses (at 3920) the error values calculated for all known input mask images to calculate the value of the loss (error) function.

[0262] Next, process 3900 uses (at 3925) the value of the loss function to adjust configurable parameters of the processing nodes of the MT network. Once the loss function value is calculated, some embodiments back-propagate the value through the processing nodes of the MT network to determine the gradient of the loss function with respect to each parameter, and then use these gradients to adjust the configurable parameters (e.g., weight values) of the processing nodes.

[0263] Finally, process 3900 determines (at 3930) whether additional training of the MT network processing nodes is required. In some embodiments, multiple iterations (e.g., batches) of known input mask images are propagated through the network to iteratively adjust configurable parameters until a set of criteria for completing training is met. This set of criteria may specify a minimum error threshold, a number of iterations, etc.

[0264] If the process 3900 determines that additional training is needed, the process 3900 returns to 3915 to supply another batch of known input mask pixel images to the MT network and continue to adjust the configurable parameters. If the set of conditions for ending the iteration are not met, the process 3900 continues to repeat steps 3915-3925. Once the process 3900 determines that additional training is not needed, the process 3900 ends.

[0265] Some embodiments optimize mask layouts more efficiently and accurately by considering multiple layers at a time for mask layout optimization. In such embodiments, because mask layout optimization already considers the effects of adjacent layers on the layer, DFM rules defined for mask layout and / or design layout do not need to consider these effects as conventionally. Thus, these optimization methods allow for more tolerant DFM rules.

[0266] The above embodiments describe using multiple layers of mask layouts to optimize one or more of those mask layouts. Mask layout optimization (and more generally mask production) is a step in the overall process of designing and manufacturing ICs. FIG. 40 conceptually illustrates an example of such a process for designing and manufacturing ICs. The process 4000 of this figure uses the mask optimization techniques described above to ensure that the masks produced from the process (i.e., the masks used to manufacture the wafers of the IC) are accurate and that the overlap between layers is resilient to process variations.

[0267] Process 4000 begins (at 4005) by defining code that specifies an IC design and performing functional verification and testing on the code. In some embodiments, this process uses one of the common hardware description languages (HDL) to specify the code. HDL code in some embodiments describes the desired structure, behavior, and timing of the IC. To perform functional verification and testing on the code of the IC, some embodiments specify one or more modules and / or circuit elements in the code and check the functional accuracy of the specified modules and / or circuit elements.

[0268] Next, the process 4000 performs (at 4010) a synthesis operation to convert the HDL description into a circuit representation that typically includes digital circuit elements such as logic gates, flip-flops, and other larger digital elements such as adders, multipliers, etc. The synthesis operation is typically performed using a synthesis tool.

[0269] At 4015, the process 4000 performs verification and testing on the circuit representation generated by the synthesis operation. In some embodiments, the verification and testing checks the circuit representation to determine whether the representation meets the desired timing constraints and satisfies any other constraints of the HDL code. When the verification and testing fails (e.g., if a portion of the circuit representation fails to meet a constraint), the process 4000 returns to step 4010 (indicated by the dashed arrow) to perform synthesis again to modify the circuit representation to resolve the failure.

[0270] When the verification and testing of 4015 pass, the process 4000 performs a set of physical design operations 4018, including operations 4020-4035. The process 4000 can be repeated multiple times during operations 4020-4035, as further described below. At 4020, the process 4000 performs a floorplanning operation to define the approximate locations of some or all of the circuit blocks (e.g., various large circuit blocks). For example, in some embodiments, the floorplanning divides the design layout into one or more blocks of different uses (e.g., ALU, memory, decode, etc.) and assigns some or all of the circuit blocks to the blocks based on the uses of the blocks.

[0271] At 4025, process 4000 performs a placement operation that is based on the floorplan data and defines a specific location and orientation of each circuit block in the design layout. The placement operation, in some embodiments, is an automated process that attempts to find an optimal placement for each circuit block based on one or more optimization criteria, such as congestion or an estimated length of interconnect (e.g., metal wire) required to connect a net associated with the circuit block. In some embodiments, a net includes a set of two or more pins of one or more circuit blocks that are electrically connected (e.g., through a set of wires, contacts, and / or vias). After performing the placement operation, if process 4000 determines that the floorplan should be revised, process 4000 may return to the floorplan operation to improve the results of the placement operation.

[0272] Once the placement operation is satisfactorily completed, the program performs (at 4030) a routing operation to define the routing required to connect the nets (i.e., to connect the groups of pins to be interconnected). Each defined routing includes one or more interconnect segments (also called line segments) spanning one or more interconnect layers (also called routing layers) and one or more vias and / or contacts connecting pins and / or line segments on different routing layers.

[0273] To define routing, some embodiments divide routing operations into global routing operations and detailed routing operations. For each net, global routing defines a global routing that generally defines the routing of the net (e.g., defines the approximate area that the routing spans in the design layout). For example, in some embodiments, global routing divides the IC into individual global routing regions, called Gcells. Then, a global routing (Groute) is generated for each net by listing the Groutes that should pass through the global routing regions (Gcells).

[0274] The detail routing defines the actual routing of each net (e.g., the routing that connects the set of pins that form the net). As mentioned above, each defined routing includes one or more interconnect segments spanning one or more interconnect layers and one or more vias and / or contacts that connect pins and / or segments on different interconnect layers. When performing its detail routing calculations, the detail routing of some embodiments uses the Groute data of the global routing (e.g., by having its detail routing for the net search for Groute region deviations that span Groutes defined by the global routing).

[0275] During or after the detailed routing operation, the process 4000 performs a design rule check (DRC) operation to ensure that the defined routing does not violate the design rules. An example of a design rule check performed on a routing is to ensure that the routing is not closer to another routing or another component in the design layout on the layer than the acceptable minimum spacing requirement for each layer that the routing line spans. Routes that violate the minimum spacing restrictions may result in improper capacitance values and in some cases, electrical shorts on the IC.

[0276] In some embodiments, the process 4000 may repeat the global and detailed routing multiple times to identify better Groutes for some nets to improve the detailed routing of these nets or other nets. In addition, in some embodiments, the process 4000 may return from any of these routing operations to an earlier operation in the EDA flow (e.g., a placement operation) to improve the results of the earlier operation, thereby improving the routing defined by the later routing operation.

[0277] After routing, process 4000 performs (at 4035) a compaction operation. In some embodiments, the compaction operation compresses the design layout in one or more directions to reduce the size of an IC die that will be manufactured based on the design layout (e.g., to reduce the two-dimensional area of the IC die). Reducing the size of the IC improves the performance of the IC in some embodiments. A compact design layout also reduces the cost of manufacturing an IC using the design layout by allowing more ICs to be produced for a given wafer size.

[0278] After the compression operation, the process 4000 performs a layout verification operation (at 4040) to ensure that the compressed design layout (e.g., the compressed routing in the design) meets one or more verification requirements. The verification operation includes a DRC operation to ensure that the compressed design layout does not violate the design rules. An example of a DRC performed on a routing is to ensure that the routing is not closer to another routing or another component in the design layout on the layer than the acceptable minimum spacing requirement for each layer spanned by the routing thread. Other examples of DRC include performing minimum area, minimum width, and maximum curvature of shapes of objects in the design layout (e.g., routing, pins, contacts, vias, or other components).

[0279] Layout verification includes other operations in some embodiments, such as extraction. In some embodiments, extraction calculates parasitic values (such as parasitic capacitance or parasitic inductance) applied to objects (such as line segments) in the design layout. In some embodiments, extraction calculates capacitance coefficients for one or more conductive components in the design layout (such as for each line segment of a winding in the design layout, or for the entirety of each winding in the design layout), and uses the capacitance coefficients to calculate parasitic effects (such as capacitance, resistance, or inductance) on the conductive components.

[0280] After the compression operation at 4035 or the subsequent verification operation 4040, the process 4000 may in some embodiments return to an earlier operation in the EDA flow (e.g., to a placement operation, to a general routing operation, or to a detailed routing operation) to improve the results of the earlier operation, thereby improving the compressed design defined by the later compression operation. For example, when the design is not verified at 4040 (e.g., or a problem with the design is detected during verification), the process 4000 returns to the earlier physical design operation 4020-4035 to perform the physical design operation and any subsequent physical design operation again on a portion or the entirety of the design layout. In some embodiments, the design layout on the layout that exists after the compression operation and passes the subsequent verification operation 4040 is the final result of the physical design process, and this design layout is referred to as the physical design layout and is used as input to the subsequent processes 4045-4055 that form the manufacturing subprocess of the process 4000.

[0281] In some embodiments, the physical design subroutine includes other operations not shown in FIG. 40 . These other operations are not shown for simplicity. Examples of these operations include partitioning, power planning, and clock tree synthesis (CTS). In some embodiments, partitioning divides the design layout into subsets of similar size and ensures a minimum number of connections between the sub-segments. Power planning defines a power delivery network (PDN) including interconnects for delivering power from a power supply circuit to the circuits defined by the IC design layout. The CTS in some embodiments defines a clock delivery network for delivering one or more clock signals to the circuits defined by the IC design layout. The CTS in some embodiments also inserts buffers and / or inverters along the clock signal path on the clock delivery network to balance the load and reduce or eliminate any clock skew or delay.

[0282] The manufacturing subroutine includes a mask generation operation (at 4045). Once the physical design verification operation (at 4040) is performed, the mask generation operation is performed in some embodiments and the physical design layout is verified to pass one or more verification criteria. In some embodiments, mask generation includes mask layout generation, mask simulation, and wafer simulation. Mask layout generation uses conventional techniques (e.g., OPC (optical proximity correction) and / or ILT (inverse lithography technology) operations) to define the mask layout.

[0283] During or after the mask layout is generated, the process 4000 performs an MRC (Manufacturing Rule Check) operation to ensure that the shapes defined in the mask layout do not violate MRC rules. Examples of MRC rules include minimum spacing, minimum width, maximum curvature, and minimum area of shapes in the mask layout.

[0284] The mask simulation operation simulates mask production using the generated mask layout. The mask simulation includes operations such as mask data preparation (MDP) and mask process correction (MPC) in some embodiments. MDP prepares the mask layout for the mask writer in some embodiments. This operation includes "fracturing" the data into trapezoids, rectangles, or triangles in some embodiments. MPC geometrically modifies the shape and / or assigns dose to the shape so that the resulting shape on the mask is closer to the desired shape. MDP can take as input the generated mask layout or the results of MPC. MPC can be performed as part of fracturing or other MDP operations. Other corrections can also be performed as part of fracturing or other MDP operations. In addition, in some embodiments, the mask simulation operation uses charged particle beam simulation to calculate several possible mask images.

[0285] The wafer simulation operation in some embodiments calculates possible patterns that will be produced on the manufactured IC using masks that will be generated based on the mask layout. In some embodiments, the wafer simulation operation includes lithography simulation using the calculated mask image. Additional description of mask generation, mask simulation, and wafer simulation operation is provided in U.S. Patent No. 8,719,739, entitled "Method and System for Forming Patterns Using Charged Particle Beam Lithography", which is incorporated herein by reference.

[0286] After wafer simulation is performed for a given mask layout, the resulting wafer pattern is reviewed to determine whether the mask layout should be modified and / or to determine whether one or more physical design operations should be repeated to modify the physical design layout. In some embodiments, wafer pattern review involves comparing the resulting simulated wafer pattern to an ideal target pattern (e.g., to ensure that the predicted wafer image is within a minimum deviation of the target wafer image). In some embodiments, the multi-layered awareness mask layout optimization technique described above is also part of the wafer pattern review.

[0287] Alternatively or concurrently, this review may involve performing a DRC check on the produced wafer patterns that the wafer simulator predicts will appear on the IC die. In some embodiments, the process 4000 may iteratively repeat the sub-operations of the mask production operation 4045 (e.g., mask layout generation, mask simulation, and wafer simulation) to improve the overall quality of the produced masks or may return to one of the earlier physical design operations 4018, as described above.

[0288] Once the mask layout is generated and verified, process 4000 generates masks specified for all layers of the IC based on the mask layout. Mask generation in some embodiments converts each mask image (also referred to as a mask layer in some embodiments) of the mask layout into one or more lithography masks. Once the masks are generated, process 4000 proceeds (at 4050) to wafer fabrication, which uses the generated masks to fabricate a plurality of IC dies on an IC wafer (e.g., a silicon wafer). The masks of the substrate and each winding layer are used to generate devices and windings on the substrate and each winding layer of each IC die. Each IC die is typically tested. During the testing of the IC die, if it is determined that the IC is defective due to its design or mask, process 4000 must return to an earlier operation to improve its design layout, its mask layout, or its mask production operation. Finally, process 4000 proceeds (at 4055) to packaging, which places each IC die in a wafer package. In some embodiments, packaging includes dicing the wafer into a plurality of IC dies and placing each of the dies on a substrate, which is then encapsulated to form a wafer package. After packaging, the process 4000 ends.

[0289] Although several embodiments are described above with reference to methods for performing mask layout optimization to optimize a mask layout for an IC design used to design and / or manufacture an IC, a person skilled in the art to which the present invention relates will understand that other embodiments are used to perform mask layout optimization for a mask layout to manufacture a silicon interposer (e.g., a routing pattern on a silicon interposer).

[0290] Other embodiments are used to design and manufacture other patterns on other types of substrates. For example, some embodiments use the above-described mask optimization process to produce optimized mask layouts for designing displays such as flat displays (such as screens, televisions, glasses, etc.) or curved displays (such as displays for virtual reality or augmented reality headsets). Such design layouts define controllable pixel patterns on the display substrate. Other embodiments use the above-described multi-layer perceptual mask optimization process to produce mask layouts for manufacturing other patterns of other elements on other substrates.

[0291] Many of the above features and applications are implemented in the form of a software program that is specified as a set of instructions recorded on a computer-readable storage medium (also called computer-readable medium). When these instructions are executed by one or more processing units (such as one or more processors, processing cores or other processing units), they cause the processing units to perform the actions indicated in the instructions. Examples of computer-readable media include but are not limited to CD-ROMs, flash disks, RAM chips, hard disks, EPROMs, etc. Computer-readable media do not include carrier waves and electronic signals that move wirelessly or through wired connections.

[0292] In this specification, the term "software" includes firmware residing in read-only memory or applications stored in magnetic storage that can be read into memory for processing by a processor. In addition, in some embodiments, multiple software inventions can be implemented as sub-parts of a larger program and still be unique software inventions. In some embodiments, multiple software inventions can also be implemented as separate programs. Finally, any combination or separate programs that together implement the software inventions described herein fall within the scope of the present invention. In some embodiments, one or more specific machine implementations are defined that execute and perform the operations of the software programs when the software programs are installed to run on one or more electronic systems.

[0293] FIG. 41 conceptually illustrates a computer system 4100, with which some embodiments of the present invention are implemented. The computer system 4100 can be used to implement any of the above-described computers and servers. As such, it can be used to execute any of the above-described programs. The computer system includes various types of non-transitory machine-readable media and interfaces for various other types of machine-readable media. The computer system 4100 includes a bus 4105, a processing unit 4110, a system memory 4125, a read-only memory 4130, a permanent storage device 4135, an input device 4140, and an output device 4145.

[0294] Bus 4105 collectively represents all system, peripheral, and chipset buses that communicatively connect the various internal devices of computer system 4100. For example, bus 4105 communicatively connects processing unit 4110 to read-only memory 4130, system memory 4125, and permanent storage device 4135.

[0295] From these various memory units, the processing unit 4110 retrieves instructions to be executed and data to be processed to execute the program of some embodiments of the present invention. The processing unit can be a single processor or a multi-core processor in different embodiments. The read-only memory 4130 stores static data and instructions required by the processing unit 4110 and other modules of the computer system. The permanent storage device 4135 is a read-write memory device. This device is a non-volatile memory unit that stores instructions and data even when the computer system 4100 is turned off. Some embodiments of the present invention use a large number of storage devices (such as disks or optical disks and their corresponding disk drives or optical disk drives) as permanent storage devices 4135.

[0296] Other embodiments use a removable storage device (e.g., a flash disk, etc.) as a permanent storage device. Similar to permanent storage device 4135, system memory 4125 is a read-write memory device. However, unlike storage device 4135, system memory is a volatile read-write memory, such as random access memory. System memory stores instructions and some of the data required by the processor during operation. In some embodiments, the program of the present invention is stored in system memory 4125, permanent storage device 4135 and / or read-only memory 4130. From these various memory units, processing unit 4110 retrieves instructions to be executed and data to be processed to execute the program of some embodiments of the present invention.

[0297] Bus 4105 is also connected to input and output devices 4140, 4145. Input devices allow a user to communicate information and select commands to the computer system. Input devices 4140 include alphanumeric keyboards and pointing devices (also called "cursor controls"). Output devices 4145 display images generated by the computer system. Output devices include printers and display devices such as cathode ray tubes (CRT) or liquid crystal displays (LCD). Some embodiments include devices such as touch screens that function as both input and output devices.

[0298] Finally, as shown in FIG. 41 , bus 4105 also couples computer system 4100 to network 4165 via a network adapter (not shown). In this manner, the computer may be part of a computer network (e.g., a local area network (“LAN”), a wide area network (“WAN”), or an intranet, or one of multiple networks, such as the Internet). Any or all components of computer system 4100 may be used in conjunction with the present invention.

[0299] Some embodiments include electronic components such as microprocessors, storage and memory (or computer-readable storage media, machine-readable media or machine-readable storage media) that store computer program instructions in machine-readable or computer-readable media. Some examples of such computer-readable media include RAM, ROM, CD-ROM, CD-R, CD-RW, digital versatile disks (e.g., DVD-ROM, dual-layer DVD-ROM), various recordable / rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., SD card, mini SD card, micro SD card, etc.), magnetic and / or solid-state hard drives, Blu-ray discs and recordable Blu-ray discs, ultra-high density optical discs, and any other optical or magnetic media. The computer-readable media may store a computer program that is executable by at least one processing unit and includes a plurality of sets of instructions for performing various operations. Examples of computer programs or computer code include machine code (such as produced by a compiler) and files including higher level code that are executed by a computer, electronic component or microprocessor using an interpreter.

[0300] Although the above discussion is primarily about microprocessors or multi-core processors that execute software, some embodiments are implemented using one or more integrated circuits (such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs)). In some embodiments, such integrated circuits execute instructions stored in the circuits themselves.

[0301] As used in this specification, the terms "computer", "server", "processor" and "memory" refer to electronic or other technological devices. These terms exclude people or groups of people. For the purposes of this specification, the terms display or displaying refer to displaying on an electronic device. As used in this specification, "computer-readable medium" and "machine-readable medium" are entirely limited to tangible, physical objects that store information in a form that can be read by a computer. These terms exclude any wireless signals, wired download signals, and other peripheral or transient signals.

[0302] Although the present invention has been described with reference to several specific details, a person skilled in the art will appreciate that the present invention can be implemented in other forms without departing from the spirit of the present invention. Accordingly, a person skilled in the art will appreciate that the present invention is not limited to the foregoing illustrative details but is defined by the appended claims.

[0303] 305: Design layout shape 310: Target wafer image shape 315: Mask layout shape 320: Simulate wafer shape 410, 430: metal layer 412, 432: Metal wire segment 420: through hole layer 422:Through hole 424, 424A, 424B: Through hole pad 1100, 1200, 1600, 1700, 2000, 2300, 2500, 2800, 3200, 3300, 3400, 3800, 3900, 4000: Program 1105, 1605, 3205, 3405: Target wafer image 1110, 1610, 3210, 3410: Initial mask 1115, 1615, 3215, 3415: Process information 1120, 1620, 3220, 3420: Mask 1125, 1625, 3225, 3425: Wafer space imaging 1205, 1410, 1500: Mask image 1210, 1212, 1215, 1220, 1225, 1230, 1235, 1240, 1245, 1250, 1705, 1710, 1715, 1720, 1730, 1735, 1740, 1745, 1750, 1755, 2005, 2010, 2015, 2020, 2025, 2305, 2310, 2315, 2320, 2505, 2510, 2515, 2520, 2525, 2805, 2810 810, 2815, 2820, 3305, 3307, 3310, 3315, 3320, 3325, 3330, 3715, 3745, 3805, 3810, 3815, 3820, 3825, 3830, 3905, 3910, 3915, 3920, 3925, 3930, 4005, 4010, 4015, 4020, 4025, 4030, 4035, 4040, 4045, 4050, 4055: Steps 1300, 3100: Design layout 1301-1306: Interconnection segment (design shape) 1411-1419, 1902, 1903, 1905, 1910, 1930, 2105, 2110, 2115, 2205, 2210, 2605, 2610, 2705, 2710, 2905, 2910, 2915, 3005, 3010, 3015: shape 1420-1427, 1520-1526: SRAF 1510-1512: IC components 1612, 3412: Layer mask 1805: Curved Edges 1810: Pixel dose map 1900:Optimizer 1925: Wafer Simulator 2100: Multi-layer interface 2405, 2410, 2415, 2420: Intersection 2900, 3000: tolerance range 3105, 3110: Wafer simulation 3500, 3600, 3725: Neural Network 3520, 3620: mask pixel image 3510, 3730: Wafer imaging 3700:Scheme 3710:Mask Layout 3720:Multi-channel 2-D imaging 3735: Wafer Image Analysis Computing 3740: Loss function 4100: Computer Systems 4105:Bus 4110: Processing unit 4125:System memory 4130: Read-only memory 4135: Permanent storage device 4140: Input device 4145: Output device 4165: Internet

Claims

1. A method for optimizing a mask layout for producing a plurality of masks for manufacturing an integrated circuit (IC) comprising multiple layers of components, the method comprising: receiving a mask layout comprising a set of mask images corresponding to components of a first layer of the IC, the components of the first layer being at least adjacent to components of a second layer. Generate a first wafer image containing multiple representative images of multiple IC components predicted to be manufactured for use in the first layer, the prediction being based on a set of mask images received corresponding to the first layer; identify an objective function that considers (i) a difference between the first wafer image and a target wafer image of the first layer and (ii) a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image of the second layer, the interaction between the multiple predicted IC components in the first wafer image and the multiple predicted IC components in the second wafer image; and modify at least one mask image in the set of mask images of the first layer based on a calculated value of the objective function.

2. A method for optimizing a mask layout for producing a plurality of masks for fabricating an integrated circuit (IC) comprising multiple layers of components, the method comprising: receiving a mask layout comprising a set of mask images corresponding to components of a first layer of the IC, the components of the first layer being at least adjacent to components of a second layer; generating a first wafer image based on the received set of mask images corresponding to the first layer, the generation step comprising simulating a set of lithography processes for fabricating the first layer of the IC using the set of masks based on the received set of mask images, wherein the first wafer image comprises a plurality of representative images predicted to be fabricated for use in the first layer of the IC; and modifying at least one mask image in the set of mask images of the first layer based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image of the second layer.

3. A method for optimizing a mask layout for producing a plurality of masks for fabricating an integrated circuit (IC) comprising multiple layers of components, the method comprising: receiving a mask layout comprising a set of mask images corresponding to components of a first layer of the IC, the components of the first layer being at least adjacent to components of a second layer; generating a first wafer image based on the received set of mask images corresponding to the first layer, the step being performed by providing the received set of mask images as input to a machine-readable network outputting the first wafer image, wherein the first wafer image comprises a plurality of representative images predicted to be fabricated for a plurality of IC components of the first layer; and modifying at least one mask image in the set of mask images of the first layer based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image of the second layer.

4. A method for optimizing a mask layout for producing a plurality of masks for fabricating an integrated circuit (IC) comprising multiple layers of components, the method comprising: receiving a mask layout comprising a set of mask images corresponding to components of a first layer of the IC, the components of the first layer being at least adjacent to components of a second layer; generating a first wafer image comprising a plurality of representative images predicted to be fabricated for a plurality of IC components of the first layer, the prediction being based on the received set of mask images corresponding to the first layer, wherein the step of generating the first wafer image comprises: rasterizing the set of mask images into a set of mask pixel images; and generating the first wafer image into a pixel image from the set of mask pixel images; and modifying at least one mask image in the set of mask images of the first layer based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image of the second layer.

5. The method of any one of claims 1 to 4, wherein when the set of mask images is optimized, the set of mask images is used to manufacture a set of masks for manufacturing the first layer of the IC.

6. The method described in any one of claims 1 to 4, wherein: The first layer is a metal layer, and the second layer is a via layer; the predicted IC component in the first wafer image is a representative image of an interconnect segment, and the predicted IC component in the second wafer image is a representative image of a via connected to the interconnect segment.

7. The method described in any one of claims 1 to 4, wherein: The first layer is a through-hole layer, and the second layer is a metal layer; the predicted IC component in the first wafer image is a representative image of a through-hole, and the predicted IC component in the second wafer image is a representative image of an interconnect segment connected to the through-hole.

8. The method of any one of claims 1 to 4, wherein the step of modifying the at least one masking image comprises modifying a mask shape of one of the masking images used to produce the IC component to modify a shape of the IC component being produced.

9. The method of any one of claims 2 to 4, further comprising, iteratively: generating an updated wafer image comprising a plurality of representative images of the shapes of the IC components, the representative images representing the shapes of the IC components to be manufactured using a set of masks for the first layer, the representative images being based on a modified set of mask images corresponding to the first layer; and modifying at least one mask image in the set of mask images based on a positional relationship between at least one IC component representative image in the updated wafer image and at least one IC component representative image in the second wafer image.

10. The method of claim 9 further comprises generating the second wafer image of the second layer based on a set of mask images corresponding to the second layer, wherein the second wafer image is generated once in each iteration and used to modify the at least one mask image.

11. A machine-readable medium storing a program that, when executed by at least one processing unit, optimizes a mask layout for producing a plurality of masks for manufacturing an integrated circuit (IC) comprising multiple layers of components, the program comprising a plurality of instructions to: receive a mask layout comprising a set of mask images corresponding to components of a first layer of the IC, the components of the first layer being at least adjacent to components of a second layer; Generate a first wafer image containing multiple representative images of multiple IC components predicted to be manufactured for use in the first layer, the prediction being based on a set of mask images received corresponding to the first layer; identify an objective function that considers (i) a difference between the first wafer image and a target wafer image of the first layer and (ii) a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image of the second layer, the interaction between the multiple predicted IC components in the first wafer image and the multiple predicted IC components in the second wafer image; and modify at least one mask image in the set of mask images of the first layer based on a calculated value of the objective function.

12. A machine-readable medium storing a program that, when executed by at least one processing unit, optimizes a mask layout for producing a plurality of masks for manufacturing an integrated circuit (IC) comprising multiple layers of components, the program comprising a plurality of instructions to: receive a mask layout comprising a set of mask images corresponding to components of a first layer of the IC, the components of the first layer being at least adjacent to components of a second layer; Based on the received set of mask images corresponding to the first layer, a first wafer image is generated. This generation step is achieved by simulating a set of lithography processes used to manufacture the first layer of the IC using a set of masks based on the received set of mask images. The first wafer image includes a plurality of representative images of a plurality of IC components predicted to be manufactured for the first layer. At least one mask image in the set of mask images of the first layer is modified based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image of the second layer.

13. A machine-readable medium storing a program that, when executed by at least one processing unit, optimizes a mask layout for producing a plurality of masks for manufacturing an integrated circuit (IC) comprising multiple layers of components, the program comprising a plurality of instructions to: receive a mask layout comprising a set of mask images corresponding to components of a first layer of the IC, the components of the first layer being at least adjacent to components of a second layer; generate a first wafer image based on the received set of mask images corresponding to the first layer, the generation step being by providing the received set of mask images as input to a machine-readable network outputting the first wafer image, wherein the first wafer image comprises a plurality of representative images predicted to be manufactured for a plurality of IC components of the first layer; and modify at least one mask image in the set of mask images of the first layer based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image of the second layer.

14. A machine-readable medium storing a program that, when executed by at least one processing unit, optimizes a mask layout for producing a plurality of masks for fabricating an integrated circuit (IC) comprising multiple layers of components, the program comprising a complex set of instructions to: receive a mask layout comprising a set of mask images corresponding to components of a first layer of the IC, the components of the first layer being at least adjacent to components of a second layer; generate a first wafer image comprising a plurality of representative images predicted to be fabricated for a plurality of IC components of the first layer, the prediction being based on the received set of mask images corresponding to the first layer, wherein the set of instructions generating the first wafer image comprises a complex set of instructions to: The set of mask images is rasterized into a set of mask pixel images; and the first wafer image is generated from the set of mask pixel images into a pixel image; and at least one mask image in the set of mask images of the first layer is modified based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image of the second layer.

15. The machine-readable medium as claimed in any one of claims 11 to 14, wherein when the set of masking images is optimized, the set of masking images is used to create a set of masks for creating the first layer of the IC.

16. The machine-readable medium as claimed in any one of claims 11 to 14, wherein the set of instructions for modifying the at least one masking image comprises a set of instructions for modifying a mask shape of one of the masking images used to produce the IC component to modify a shape of the IC component being produced.

17. The machine-readable medium as claimed in any one of claims 12 to 14, wherein the program further comprises a complex set of instructions to: iteratively: generate an updated wafer image containing a complex number of representative images of IC components predicted to be manufactured for the first layer, the prediction being based on a modified set of mask images corresponding to the first layer; and modify at least one mask image in the set of mask images based on a positional relationship between at least one IC component representative image in the updated wafer image and at least one IC component representative image in the second wafer image.

18. The machine-readable medium as claimed in claim 17, wherein the program further includes a set of instructions to generate the second wafer image of the second layer based on a set of mask images corresponding to the second layer, wherein the second wafer image is generated once in each iteration and used to modify the at least one mask image.

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