Managing error corrections for data storage systems and devices

Abstract

This case discloses a data storage system, method, and apparatus for managing error correction. The data storage system includes one or more data storage devices. Each data storage device has at least one memory and a memory controller including at least one first error correction code (ECC) decoder. The memory controller is configured to: read data from the at least one memory; perform an ECC test on the read data using the at least one first ECC decoder; and, in response to determining that the read data fails the ECC test, transmit the read data to an external device having at least one second ECC decoder to decode the read data. The external device is located outside the data storage device. The at least one second ECC decoder has a stronger ECC capability than the at least one first ECC decoder.

Description

[Technical Field]

[0001] This invention relates to a data storage system, and more particularly to error correction management of a data storage system. [Previous Technology]

[0002] Once a storage cell in a data storage device (e.g., a memory device) is programmed, data can be read from the storage cell by sensing the programming state of each memory cell and comparing the cell threshold voltage with one or more read voltages. However, due to one or more factors, such as read interference or data retention, the cell threshold voltage may change, which may cause the sensed programming state to differ from the written programming state, resulting in bit errors in the read output data. [Summary of the Invention]

[0003] This case describes error correction management systems, apparatus, methods and techniques for data storage systems, such as data storage systems including multiple data storage devices (e.g., solid-state drives (SSDs), high-density drives (HDDs), NAND flash memory modules or combinations thereof).

[0004] According to a first aspect of the present invention, a data storage system is provided, comprising: one or more data storage devices; and a system controller coupled to the data storage devices. One of the data storage devices includes at least one memory and a memory controller coupled to the at least one memory, the memory controller including at least one first error correction code (ECC) decoder. The memory controller is configured to: read data from the at least one memory; perform a first ECC test on the read data using the at least one first ECC decoder; and, in response to determining that the read data fails the first ECC test, transmit the read data to an external device having at least one second ECC decoder to decode the read data. The external device is located outside the data storage device, and the at least one second ECC decoder has stronger ECC functionality than the at least one first ECC decoder.

[0005] In some instances, the at least one memory includes one or more memory chips.

[0006] In some instances, the memory controller is configured to: in response to determining that the read data failed the first ECC test and before transmitting the read data to the external device, determine whether the number of times the read data failed the first ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, change one or more read parameters to reread the data from the at least one memory or perform software decoding on the data; and if the number reaches the predetermined threshold, transmit the read data to the external device having the at least one second ECC decoder to decode the read data.

[0007] In some instances, the memory controller is configured to, in response to determining that the read data failed the first ECC test and before transmitting the read data to the at least one second ECC decoder, based on a result of the first ECC test, do one of the following: i) change one or more parameters for reading the data from the at least one memory or perform software decoding on the data, and perform the first ECC test again using the at least one first ECC decoder, or ii) transmit the read data to the external device having the at least one second ECC decoder to decode the read data.

[0008] In some instances, the external device is configured to: perform a second ECC test on the read data using at least one second ECC decoder; and, in response to determining that the read data passes the second ECC test, transmit a corrected read data to the system controller.

[0009] In some instances, the external device is configured to: in response to determining that the read data failed the second ECC test, determine whether the number of times the read data failed the second ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, send a notification to the memory controller to i) change one or more parameters for reading the data from the at least one memory, or ii) perform software decoding on the data; and if the number reaches the predetermined threshold, trigger a RAID (Redundant Array of Independent Disks) circuit to correct errors in the read data.

[0010] In some instances, the external device is configured to, in response to determining that the read data failed the second ECC test and before triggering a RAID circuit, perform one of the following operations based on a result of the second ECC test: i) change one or more parameters for reading the data from the at least one memory, or perform software decoding on the data, and perform at least one of the following again: perform the first ECC test using at least one first ECC decoder, or perform the second ECC test using at least one second ECC decoder, or ii) trigger the RAID circuit to correct errors in the read data.

[0011] In some instances, the RAID circuitry is included within the memory controller and is used to perform error correction on read data within the data storage device.

[0012] In some instances, the RAID circuitry is included within the data storage devices and is used to perform error correction on read data within the data storage devices.

[0013] In some instances, the memory controller is configured to: perform an ECC decoding operation on the read data using at least one first ECC decoder; determine whether the number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold; if the number of error bits is less than the predetermined threshold, determine that the read data passes the first ECC test; and if the number of error bits is equal to or greater than the predetermined threshold, determine that the read data fails the first ECC test.

[0014] In some instances, the system controller is configured to: receive an instruction from a host device located outside the data storage system, the instruction instructing to read data from the data storage device or the data storage devices; send the instruction to the data storage device to read the data; and, in response to a corrected read data received from the data storage device or the external device, transmit the corrected read data to the host device.

[0015] In some instances, the external device is independent of the data storage devices and coupled to the data storage devices and the system controller.

[0016] In some instances, the data storage device includes only the at least one first ECC decoder, but does not have a second ECC decoder.

[0017] In some instances, the external device includes only the at least one second ECC decoder, but does not have a first ECC decoder.

[0018] In some instances, a second data storage device of the data storage device or the data storage devices includes the external device, and the second data storage device includes one or more first ECC decoders and the at least one second ECC decoder.

[0019] In some instances, the data storage devices include: one or more first data storage devices, each of the first data storage devices including only one or more first ECC decoders; and one or more second data storage devices, each of the second data storage devices including one or more first ECC decoders and one or more second ECC decoders.

[0020] In some instances, the system controller is configured to: store a first type of data in the one or more first data storage devices; and store a second type of data in the one or more second data storage devices. The first type of data is read more frequently than the second type of data.

[0021] In some instances, the first data storage devices and the second data storage devices are configured to operate under a protocol. Each of the first data storage devices is configured to, in response to the first ECC decoder in the first data storage device being unable to correct a first data read from a related first memory, transmit the read first data to the second data storage device. Each of the second data storage devices is configured to, in response to receiving related read data from the first data storage device, decode the related read data using the second ECC decoder in the second data storage device.

[0022] In some instances, the external device is included in the system controller.

[0023] In some instances, the data storage system further includes one or more external devices having the external device, each of the external devices including one or more second ECC decoders.

[0024] In some instances, the system controller is configured to generate a warning message to replace the data storage device based on at least one result of a first ECC test performed using at least one first ECC decoder or a second ECC test performed using at least one second ECC decoder.

[0025] In some instances, the memory controller includes a first ECC encoder for encoding the data to generate first ECC data, and the memory controller is configured to store the data together with the first ECC data in the at least one memory. The at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the first ECC data.

[0026] In some instances, the memory controller includes a first ECC encoder for encoding the data to generate first ECC data, and the external device includes a second ECC encoder for encoding the data to generate second ECC data. The memory controller is configured to: store the data together with the first ECC data and the second ECC data in the at least one memory; read the data, the first ECC data, and the second ECC data from the at least one memory; and, in response to determining that the read data fails the first ECC test, transmit the read data and the second ECC data to the external device having at least one second ECC decoder. The at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the second ECC data received from the memory controller.

[0027] In some instances, the memory controller is configured to store the first ECC data and the second ECC data as concatenated codes of the data of the at least one memory.

[0028] In some instances, the system controller is configured to transmit multiple portions of specific data to multiple data storage devices of the data storage devices or the data storage devices respectively. Each of the data storage devices includes a first ECC encoder and one or more first ECC decoders, wherein the first ECC encoder is configured to encode a relevant portion of the specific data to generate relevant first ECC data. The external device includes a second ECC encoder for encoding the portions of the specific data to generate second ECC data. Each of the data storage devices includes a memory controller for storing the relevant portion of the specific data together with the relevant first ECC data and the second ECC data in a relevant memory. For each of the data storage devices, the first ECC decoder or the data storage devices is configured to decode the relevant portion of the specific data read from the relevant memory based on the relevant first ECC data. The at least one second ECC decoder of the external device is configured to, in response to receiving a portion of the specific data and the second ECC data from one of the data storage devices, decode the portion of the specific data based on the second ECC data.

[0029] In some instances, the at least one first ECC decoder and the at least one second ECC decoder include the same type of decoder but different ECC capabilities.

[0030] In some instances, the at least one first ECC decoder and the at least one second ECC decoder include different types of decoders but different ECC capabilities.

[0031] In some instances, the at least one first ECC decoder includes a low-power (LP) low-density parity check (LDPC) decoder, and the at least one second ECC decoder includes a min-sum (MS) LDPC decoder.

[0032] In some instances, the at least one first ECC decoder and at least one of the at least one second ECC decoder are configured to perform Bose-Chaudhuri-Hocquenghem (BCH) decoding or LDPC decoding.

[0033] In some instances, the power consumption of the first ECC decoder is lower than that of the second ECC decoder.

[0034] According to a second aspect of this case, a data storage device is disclosed, comprising: at least one memory; and a memory controller coupled to the at least one memory. The memory controller includes at least one first ECC decoder. The memory controller is configured to: read data from the at least one memory; perform a first error correction code (ECC) test on the read data using the at least one first ECC decoder; and, in response to determining that the read data fails the first ECC test, transmit the read data to an external device having at least one second ECC decoder for decoding. The external device is located outside the data storage device, and the at least one second ECC decoder has stronger ECC functionality than the at least one first ECC decoder.

[0035] In some instances, the memory controller includes only the at least one first ECC decoder and does not include a second ECC decoder.

[0036] In some instances, the memory controller is configured to: in response to determining that the read data failed the first ECC test and before transmitting the read data to the external device, determine whether the number of times the read data failed the first ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, change one or more read parameters to reread the data from the at least one memory or perform software decoding on the data; and if the number reaches the predetermined threshold, transmit the read data to the external device having the at least one second ECC decoder to decode the read data.

[0037] According to a third aspect of this case, an error correction code apparatus is disclosed, comprising: at least one first error correction code (ECC) decoder externally connected to at least one data storage device, the data storage device including at least one memory for storing data. The at least one data storage device includes at least one second ECC decoder, the at least one first ECC decoder having stronger ECC functionality than the at least one second ECC decoder. The at least one first ECC decoder is configured to: in response to receiving read data from the at least one data storage device, perform an ECC test on the read data using the at least one first ECC decoder; and in response to determining that the read data passes the ECC test, generate corrected read data for the at least one data storage device.

[0038] In some instances, the device is configured to: in response to determining that the read data failed the second ECC test, determine whether the number of times the read data failed the second ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, send a notification to the memory controller to i) change one or more parameters for reading the data from the at least one memory, or ii) perform software decoding on the data; and if the number reaches the predetermined threshold, trigger a RAID (Redundant Array of Independent Disks) circuit to correct errors in the read data.

[0039] In some instances, the at least one second ECC decoder is configured to decode the read data based on ECC data associated with a stored data in the at least one memory, and the at least one first ECC decoder is configured to decode the read data based on the ECC data.

[0040] In some embodiments, the apparatus further includes a first ECC encoder configured to encode the data to generate first ECC data and transmit the first ECC data to the at least one data storage device. The at least one data storage device includes a second ECC encoder configured to encode the data to generate second ECC data. The at least one data storage device is configured to: store the data, the first ECC data, and the second ECC data together in the at least one memory; read the data, the first ECC data, and the second ECC data from the at least one memory; and, in response to determining that the at least one second ECC decoder cannot decode the read data based on the second ECC data, transmit the read data and the first ECC data to the at least one first ECC decoder. The at least one first ECC decoder is configured to: in response to receiving the read data and the first ECC data from the at least one data storage device, decode the read data based on the first ECC data.

[0041] In some instances, the data comprises a plurality of portions, and the at least one data storage device comprises a plurality of data storage devices configured to store the portions respectively. The device further comprises a first ECC encoder configured to encode the portions of the data to generate first ECC data and transmit the first ECC data to each of the data storage devices. Each of the data storage devices comprises a second ECC encoder configured to encode a related portion of the data to generate related second ECC data. Each of the data storage devices is configured to store the related portion of the data, the related second ECC data, and the first ECC data together in a related memory. The at least one first ECC decoder is configured to decode the portion of the data based on the first ECC data in response to receiving a portion of the data and the first ECC data from one of the data storage devices.

[0042] Implementations of the above-described technology include methods, systems, computer program products, and computer-readable media. For example, a method may be performed by a data storage system including a plurality of data storage devices and a system controller coupled to the data storage devices. The method may include the operations described above performed by the system controller and the data storage devices, such as error correction management operations of the data storage devices. In another example, a computer program product is suitably implemented in a non-transitory machine-readable medium storing instructions executable by one or more processors. These instructions are configured to cause one or more processors to perform the operations described above. The computer-readable medium stores instructions configured to cause one or more processors to perform the operations described above when executed by the one or more processors.

[0043] The above or more implementation details are set forth in the accompanying drawings and the description below. Other features, aspects and advantages will become apparent from the description, illustrations and claims.

[0044] In order to better understand the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:

Implementation Method

[0047] Due to frequent read operations or long-term storage, the data stored in memory may be affected by read interference or data retention, which can cause changes in the threshold voltage of memory cells (e.g., cleared state and one or more programmed states). Read interference or data retention can lead to bit errors (or erroneous bits) in the read output. These problems are exacerbated in data storage systems that include multiple data storage devices (e.g., SSDs, HDDs, flash memory modules, or combinations thereof).

[0048] To ensure data accuracy, various methods can be employed. In some cases, read optimization (or calibration) methods, such as read retries, valley-tracking reads, and machine learning-based reads, can be used to reduce erroneous bits. In other cases, an Error Correction Code (ECC) decoder can be configured to decode data read from memory to detect and correct any bit errors within the ECC error correction capability.

[0049] In some cases, erasure coding is implemented in storage systems to enhance fault tolerance and recover data from errors in memory chips and / or storage devices. In storage systems using erasure coding, data can still be reconstructed even if some storage nodes become unavailable or data loss occurs. Erasure coding is particularly valuable in distributed storage environments where hardware failures or network problems are common. While erasure coding offers compelling advantages, it comes with high computational demands. The encoding and decoding processes involve complex mathematical calculations that can impact system performance. In some cases, RAID (Redundant Array of Independent Disks) is a data storage virtualization technology that combines multiple physical disk drives into one or more logical units to achieve data redundancy, performance improvements, or both. Unlike ECC data, which is stored on the same page as user data, RAID redundant data is stored on different physical disk drives. Therefore, RAID can provide inter-page or inter-disk RAID protection as an additional protection to recover data that ECC cannot correct. However, performing cross-page or cross-disk RAID protection requires reading all pages to recover failed data, which takes longer than ECC data recovery. The probability of triggering RAID can be set to an extremely low level to meet the performance requirements of the data storage system.

[0050] To avoid the high computational demands of long recovery times and / or erasure coding in RAID programs, the error handling process of a data storage system can be optimized by repeatedly reading and decoding the ECC code using different parameter settings. Error correction in read optimization and ECC decoding can also be improved to effectively reduce the trigger rate of RAID and / or erasure coding. Typically, read optimization and ECC decoding methods are implemented on the device controller (e.g., SSD controller) of the data storage device (e.g., SSD controller). However, achieving high ECC capability requires significant hardware resources (e.g., the number of logic gates in the ASIC of the SSD controller). In some cases, the data storage device may include a dual-mode ECC decoder, for example, having both a weaker and a stronger ECC decoder, to reduce the overall hardware cost and power consumption of the ECC decoder. However, the hardware overhead of the stronger ECC decoder remains a major component of the device controller. Furthermore, the power consumption of the stronger ECC decoder dominates the total power consumption of the data storage device.

[0051] This embodiment provides error correction techniques for data storage systems, such as by providing i) cost-effective data storage devices with weak built-in ECC decoders to handle most read requests, and ii) one or more external devices with strong ECC decoders, to ensure the overall reliability of the data storage system. These techniques can be implemented through a new data storage system error correction architecture, thereby effectively reducing the cost of data storage devices (e.g., SSDs) while ensuring the same (or similar) reliability of the entire data storage system.

[0052] In some examples, the data storage system includes a rack cabinet or rack mount for the storage system, which may include multiple data storage devices (e.g., SSDs or HDDs). In some examples, the data storage system is an all-flash memory array. A processing unit (e.g., an FPGA or DPU) may act as a controller for multiple memory chips (e.g., NAND flash memory chips), and the combination of the processing unit and the multiple memory chips can be considered as a storage module (or flash module). An all-flash memory array may include multiple storage modules. The data storage system may include a system controller configured to manage data allocation among multiple data storage devices or multiple storage modules, which can improve read / write performance and storage lifespan.

[0053] A data storage device (or a single storage module) may include a built-in (or local) ECC decoder for detecting and correcting faulty bits in one or more memory modules (e.g., NAND flash memory chips). The built-in (or local) ECC decoder may use only weaker ECC decoders, which are low-cost, low-power, and small in size. If the weaker ECC decoder cannot decode read data from one or more memory modules, the data storage device may transfer the read data to an external device within the data storage system. The external device may be considered a reliability assurance device or an accelerator. The external device may be located outside the data storage device and may include a stronger ECC decoder to decode the read data. The stronger ECC decoder has greater ECC capability than the built-in (or local) ECC decoder. The built-in (or local) ECC decoder can handle most read requests with low power consumption, while the stronger ECC decoder ensures the reliability of the entire data storage system. The number of stronger ECC decoders can be expanded to improve the terminal performance of the entire data storage system. The data storage system may include one or more external devices, each of which includes one or more powerful ECC decoders.

[0054] The external device can be implemented using a Field Programmable Gate Array (FPGA) device or any processing unit (e.g., a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Data Processing Unit (DPU), or a complete SSD). In a data storage system, data storage devices or flash modules (e.g., SSDs or NAND flash modules) are consumables due to their limited lifespan (e.g., durability, total bytes written (TBW)). Therefore, implementing data storage devices or flash modules using a lower-cost, weaker ECC decoder can effectively reduce the total cost of ownership (TCO) of the data storage system. These technologies allow the main burden of the SSD / flash module (e.g., a stronger ECC decoder) to be moved to an external device, thereby maintaining the reliability of the entire data storage system. This can significantly reduce the cost of consumable components in the entire data storage system. Furthermore, by adding a stronger ECC decoder to the external device, the read performance of the terminal device can be improved. Furthermore, read optimization methods can be performed locally or globally when the external device has a strong ECC decoder, such as machine learning-based read optimization, which is online inference performed by the external device.

[0055] In some embodiments, as shown in Figure 2, the external device is located outside the data storage device and the system controller, but is connected to the data storage device and the system controller. In some embodiments, as shown in Figure 4, the external device is included in the system controller.

[0056] In some embodiments, as shown in Figure 3, the external device is integrated into a data storage device that has its own memory chip and provides normal data storage device functionality (e.g., a conventional SSD, HDD, or NAND flash module). This data storage device may include only a stronger ECC decoder, or it may include a dual-mode ECC decoder (e.g., both a weaker and a stronger ECC decoder). This data storage device can assist in decoding failed data in other data storage devices that only have a weaker ECC decoder. In some cases, the data storage system includes one or more first data storage devices with only a weaker ECC decoder and one or more second data storage devices with a stronger ECC decoder (optionally including a weaker ECC decoder). The data storage system can store hot data (e.g., data that is read more frequently) in the more frequently replaced first data storage device and cold data (e.g., data that is read less frequently) in the less frequently replaced second data storage device, which can reduce the total cost of ownership (TCO) of the data storage system. The data storage system may include a protocol that allows a stronger ECC decoder in the second data storage device to help decode data that failed to be decoded in the first data storage device.

[0057] In this case, a weaker ECC decoder represents an ECC decoder with weaker ECC capabilities, which consumes less power and costs less compared to a stronger ECC decoder with stronger ECC capabilities. In some examples, a weaker ECC decoder is an ECC decoder with ECC capabilities below a certain threshold, while a stronger ECC decoder is an ECC decoder with ECC capabilities equal to or above the certain threshold. In some examples, a weaker ECC decoder and a stronger ECC decoder are decoders of the same type but with different ECC capabilities. For example, a weaker ECC decoder could be a low-power (LP) low-density parity check (LDPC) decoder, and a stronger ECC decoder could be a min-sum (MS) LDPC decoder. In some examples, a weaker ECC decoder and a stronger ECC decoder are decoders of different types with different ECC capabilities. For example, a weaker ECC decoder could be a Bose-Chaudhuri-Hocquenghem (BCH) decoder, and a stronger ECC decoder could be an LDPC decoder. ECC encoding is not limited to LDPC encoding. In this case, any linear block ECC can be used, such as algebraic codes, concatenated codes, and product codes.

[0058] In some examples, the same ECC decoder (e.g., an LDPC decoder) can be configured as a weaker or stronger ECC decoder. For example, an ECC encoder is configured to generate ECC data of a predetermined size (e.g., 512B) using data of a predetermined length or size (e.g., 4KB). The ECC data may include ECC parity bits. An ECC decoder is configured to decode ECC data of a predetermined size (e.g., 512B) using data of a predetermined length or size (e.g., 4KB). For data of the same size, larger ECC data can provide higher error correction capability than smaller ECC data. For ECC data of the same size, ECC data can provide higher error correction capability for smaller data than for larger data. For example, a 4KB ECC encoder generates 512B of ECC data. If an ECC encoder is used to encode 2KB of data and 2KB of predetermined (or fixed) values ​​(e.g., 1 or 0) to generate 512B of ECC data. When an ECC decoder uses ECC data to decode data, 512B ECC data generated based on 2KB data can provide higher error correction capability than 512B ECC data generated based on 4KB data.

[0059] These technologies can be applied to various types of semiconductor devices, volatile memory devices, or non-volatile memory (NVM) devices, such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) such as phase-change random access memory (PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc. These technologies can also be applied to charge-trapping based memory devices, such as silicon-oxygen-nitrogen-oxygen-silicon (SONOS) memory devices and floating-gate memory devices. These technologies can be applied to two-dimensional (2D) memory devices or three-dimensional (3D) memory devices. These technologies can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., 2-level cell devices), TLC (triple-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. Alternatively, these technologies can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), solid-state drives (SSDs), and embedded systems. These technologies can be applied to SSD- or HDD-based storage systems or all-flash arrays.

[0060] Figure 1A is a schematic diagram of system 100, which includes a data storage system 110 and a host device 120. The data storage system 110 may include a system controller 112 and multiple data storage devices 130-1, 130-2, ..., 130-n (also referred to as data storage devices 130), where n is an integer not less than 1. The system controller 112 and the data storage devices 130 may be connected to a communication bus 115, through which the system controller 112 can communicate with each data storage device 130, and the data storage devices 130 can also communicate with each other. In some examples, the communication bus 115 includes a PCIe-based bus or interface. In some embodiments, the system controller 112 and the data storage devices 130 communicate wirelessly or via a wired connection.

[0061] The system controller 112 is configured to manage data distribution among the data storage devices 130. For example, the system controller 112 may receive data and write commands from the host device 120 and store the data in one or more data storage devices 130. The system controller may also receive read commands from the host device 120 to read data from one or more data storage devices 130.

[0062] The host device 120 includes a host controller, which may include at least one processor and at least one memory coupled to the processor, and stores program instructions for execution by the at least one processor to perform one or more corresponding operations. The system controller 112 may include at least one memory and at least one processor configured to execute instructions and process data in the memory. These instructions may include firmware instructions and / or other program instructions, stored in the form of firmware code and / or other program code, respectively. The data includes program data corresponding to the firmware and / or other programs executed by the at least one processor, as well as other suitable data. In some implementations, the at least one processor is a general-purpose microprocessor or an application-specific microcontroller, such as a CPU, GPU, or DPU.

[0063] The data storage device 130 may be a solid-state drive (SSD), an embedded multimedia card (eMMC), a secure digital card (SD card), a flash module (e.g., a NAND flash memory module), or any other suitable storage device. As discussed in further detail below, the data storage device 130 may be the same or different, for example, as shown in Figure 3.

[0064] In some implementations, the data storage device 130 includes a memory controller and one or more memory modules. Each memory module may include one or more memory chips (e.g., NAND flash memory chips). The memory controller is configured to receive data and instructions from the system controller 112 and send data to the system controller 112. The memory controller may also be configured to send data and instructions to one or more memory modules and receive data from one or more memory modules. For example, the memory controller may be configured to send data and write instructions to instruct one or more memory modules to store data at a specified address. As another example, the memory controller may be configured to receive a read request (or read instruction) from the system controller 112 and send a corresponding read instruction to one or more memory modules to read data from a specified address of one or more memory modules.

[0065] In some implementations, the memory controller includes one or more ECC encoders and one or more ECC decoders. In some implementations, the one or more ECC encoders and one or more ECC decoders may also be configured to be externally coupled to the memory controller. The ECC encoder may be configured to receive data to be stored in memory and generate check bits, for example, by encoding the data using an ECC encoding scheme. These check bits may be referred to as ECC data. The ECC encoder may include a Reed Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, or any combination thereof. The ECC decoder may be configured to decode data read from memory to detect and correct any bit errors that may exist in the data, up to the error correction capability of the ECC scheme. The ECC decoder may perform BCH decoding or LDPC decoding. The ECC decoder may be a BCH decoder, a low-power (LP) LDPC decoder, or a minimum sum (MS) LDPC decoder. The ECC decoder may use any linear block ECC, such as algebraic encoding, concatenation encoding, product encoding, etc.

[0066] In some implementations, the data storage system 110 includes a RAID circuit (or RAID circuit device) configured to protect data using RAID technology. The RAID circuit can distribute data across different disk drives within the data storage device 130, or across multiple data storage devices 130. If read optimization and ECC protection in the data storage system 110 fail, the RAID circuit can be configured to provide further error protection.

[0067] Figure 1B is a schematic diagram of the first data storage device 150, which includes a weaker ECC decoder and a stronger ECC decoder. The first data storage device 150 may be an SSD, HDD, or NAND flash module.

[0068] The first data storage device 150 may be implemented as the data storage device 130 of Figure 1A. The first data storage device 150 may include one or more memory modules 152 and a memory controller 151. Each memory module 152 may include one or more memory chips 153, such as NAND flash memory chips. The memory controller 151 may include one or more first ECC decoders 154 (e.g., weaker ECC decoders) and one or more second ECC decoders 156 (e.g., stronger ECC decoders). The second ECC decoders may have stronger ECC capabilities than the first ECC decoders. When one or more first ECC decoders 154 are unable to decode data read from one or more memory modules 152, the memory controller 151 may control one or more second ECC decoders 156 to decode and read the data, which is performed within the first data storage device 150.

[0069] Figure 1C is a schematic diagram of the second data storage device 160, which includes only a weaker ECC decoder. The second data storage device 160 may be an SSD, HDD, or NAND flash module. The second data storage device 160 may be implemented as the data storage device 130 of Figure 1A.

[0070] Similar to the first data storage device 150 of Figure 1B, the second data storage device 160 may include a memory controller 161 and one or more memories 152. Unlike the memory controller 151 of Figure 1B, the memory controller 161 includes only one or more first ECC decoders 154 (e.g., weaker ECC decoders), without other ECC decoders such as a second ECC decoder 156. As discussed in further detail in Figures 2 through 5, if one or more first ECC decoders 154 cannot decode data read from one or more memories 152, the memory controller 161 may transfer the read data to an external device that includes a stronger ECC decoder (e.g., the second ECC decoder 156). This external device is located outside the second data storage device 160.

[0071] Figure 1D is a schematic diagram of external device 170, which includes only a stronger ECC decoder. External device 170 can be considered as a reliability assurance device or accelerator. External device 170 may include only a stronger ECC decoder for decoding read data. External device 170 may include a controller configured to control the stronger ECC decoder. The stronger ECC decoder may be the same as the second ECC decoder 156 in Figure 1B. The stronger ECC decoder has a stronger ECC capability than a built-in (or local) ECC decoder (e.g., the first ECC decoder 154 in data storage device 150 in Figure 1B or data storage device 160 in Figure 1C). External device 170 may be implemented by a field-programmable gate array (FPGA) device or any processing unit (such as a central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), or a complete SSD).

[0072] In some embodiments, such as those discussed in further detail in Figure 2, the external device 170 may be located outside the data storage device 130 (e.g., the second data storage device 160 in Figure 1C) and the system controller 112. In some embodiments, such as those discussed in further detail in Figure 3, the external device 170 may be one of the data storage devices 130, or may be included within one of the data storage devices 130 (e.g., the first data storage device 150 in Figure 1B). In some embodiments, such as those discussed in further detail in Figure 4, the external device 170 may be included within the system controller 112.

[0073] As shown in Figure 1A, the data storage system 110 may include one or more auxiliary devices 140, which may be connected to the data storage device 130 and the system controller 112 via bus 115. In some implementations, the one or more auxiliary devices 140 may include one or more external devices 170 as shown in Figure 1D, each external device may include one or more stronger ECC decoders (e.g., the second ECC decoder 156 in Figure 1B or 1D). If a data storage device 130 in the data storage system 110 (e.g., data storage device 160 in Figure 1C) is unable to decode and read data using its built-in ECC decoder (e.g., the first ECC decoder 154 in Figure 1C), the data storage device 130 may transfer the read data to one or more auxiliary devices 140, which may use one or more stronger ECC decoders to decode and read the data.

[0074] Figure 2 is a schematic diagram of a data storage system 200 including one or more external devices 220, which have a stronger ECC decoder 222 for use with a data storage device 210 that only has a weaker ECC decoder 214. The data storage system 200 may be implemented as the data storage system 110 of Figure 1A. The data storage system 200 includes a system controller 202 (e.g., system controller 112 of Figure 1A) that communicates with the data storage device 210 via a bus 204 (e.g., communication bus 115 of Figure 1A). The data storage device 210 and one or more external devices 220 may also communicate with each other via bus 204.

[0075] Each data storage device 210 may be the data storage device 160 of Figure 1C, comprising only one or more weaker ECC decoders 214 (e.g., the first ECC decoder 154 of Figure 1B or 1C). Each external device 220 may be the external device 170 of Figure 1D, and may comprise only one or more stronger ECC decoders 222 (e.g., the second ECC decoder 156 of Figure 1B or 1D). If one or more weaker ECC decoders 214 are unable to decode data read from one or more memories 212, the data storage device 210 may transfer the read data to one or more external devices 220 for decoding using one or more stronger ECC decoders 222.

[0076] Compared to a data storage system including all of the first data storage devices 150 in Figure 1B, data storage system 200 includes a data storage device 210 with only a weaker ECC decoder 214 and one or more external devices 220 with a stronger ECC decoder 222, resulting in lower cost and lower power consumption. The weaker ECC decoder 214 is configured to process most read requests in the data storage device 210 with low power consumption, while the one or more external devices 220 are configured to ensure the reliability of the entire data storage system 200 through the stronger ECC decoder 222. The number of stronger ECC decoders 222 and / or the number of external devices 220 can be expanded to improve the lifetime (EOL) performance of the data storage system 200.

[0077] Figure 3 is a schematic diagram of a data storage system 300 including data storage devices with stronger ECC decoders, which are used for data storage devices with only weaker ECC decoders. The data storage system 300 can be implemented as the data storage system 110 of Figure 1A. The data storage system 300 includes a system controller 302 (e.g., system controller 112 of Figure 1A), which can communicate with the first data storage device 310 and the second data storage device 320 via a bus 304 (e.g., communication bus 115 of Figure 1A). The first data storage device 310 and the second data storage device 320 can also communicate with each other via the bus 304.

[0078] Each second data storage device 320 may be the first data storage device 150 of Figure 1B, and may include a weaker ECC decoder 324 (e.g., the first ECC decoder 154 of Figure 1B or Figure 1C) and a stronger ECC decoder 326 (e.g., the second ECC decoder 156 of Figure 1B or Figure 1D). When the weaker ECC decoder 324 is unable to decode data read from one or more memories 322 (e.g., one or more memories 152 of Figure 1B or Figure 1C), the stronger ECC decoder 326 within the second data storage device 320 may decode and read the data, which is performed within the second data storage device 320 itself.

[0079] Each first data storage device 310 may be the data storage device 160 of Figure 1C, comprising only one or more weaker ECC decoders 314 (e.g., the first ECC decoder 154 of Figure 1B or Figure 1C). When the weaker ECC decoder 314 is unable to decode data read from one or more memories 312 in the first data storage device 310 (e.g., one or more memories 152 of Figure 1B or Figure 1C), the first data storage device 310 may be configured to transfer the read data to one or more second data storage devices 320 to decode the read data using a stronger ECC decoder 326 in the second data storage device 320.

[0080] The data storage system 300 may include an agreement that allows a stronger ECC decoder 326 in the second data storage device 320 to assist in decoding data that failed to be decoded in the first data storage device 310. For example, each first data storage device 310 is configured to transmit the first data read from the corresponding first memory 312 to one or more second data storage devices 320 for decoding when it is determined that a weaker ECC decoder 314 in the first data storage device 310 cannot correct the first data read from the corresponding first memory 312. Each second data storage device 320 is configured to decode the corresponding read data using one or more stronger ECC decoders 326 in the second data storage device 320 when it receives corresponding read data from one or more first data storage devices 310.

[0081] In some implementations, the system controller 302 may be configured to store a first type of data (e.g., hot data) in one or more first data storage devices 310 and a second type of data (e.g., cold data) in one or more second data storage devices 320. The first type of data may be accessed more frequently than the second type of data. In this way, the data storage system 300 can reduce the total cost of ownership (TCO) because the first data storage device 310 is cheaper than the second data storage device 320 and can be replaced more frequently than the second data storage device 320.

[0082] Figure 4 is a schematic example of a data storage system 400, which includes a system controller 402. The system controller includes one or more external devices 420 with a powerful ECC decoder 422 for the data storage device 410. The data storage system 400 can be implemented as the data storage system 110 of Figure 1A.

[0083] Similar to the data storage system 200 of Figure 2, each data storage device 410 may be the data storage device 160 of Figure 1C, the data storage device 210 of Figure 2, or the first data storage device 310 of Figure 3. The data storage device 410 may include only one or more weaker ECC decoders 414 (e.g., the first ECC decoder 154 of Figure 1B or 1C, 214 of Figure 2, or 314 of Figure 3). Each external device 420 may be the external device 170 of Figure 1D or 220 of Figure 2, and may include only one or more stronger ECC decoders 422 (e.g., the second ECC decoder 156 of Figure 1B or 1D, 222 of Figure 2, or 326 of Figure 3). If the weaker ECC decoder 414 in the data storage device 410 is unable to decode data read from one or more memories 412 (e.g., memory 152 of Figure 1B or Figure 1C, 212 of Figure 2, or 312 or 322 of Figure 3), the data storage device 410 may transfer the read data to one or more external devices 420 to use one or more stronger ECC decoders 422 to decode the read data.

[0084] Unlike the data storage system 200 in Figure 2, where one or more external devices 220 are located outside the system controller 202, the data storage system 400 may include one or more external devices 420 within the system controller 402. The number of one or more external devices 420 may be increased to improve the overall read performance of the data storage system 400.

[0085] Figure 5 is an example flowchart 500 for error correction in the management of a data storage system. The data storage system may be the data storage system 110 in Figure 1A, the data storage system 200 in Figure 2, the data storage system 300 in Figure 3, or the data storage system 400 in Figure 4. The data storage system may include a system controller and one or more data storage devices. The system controller may be, for example, the system controller 112 in Figure 1A, the system controller 202 in Figure 2, the system controller 302 in Figure 3, or the system controller 402 in Figure 4. The data storage devices may be, for example, the data storage device 130 in Figure 1A, the data storage device 150 in Figure 1B, the data storage device 160 in Figure 1C, the data storage device 210 in Figure 2, the first data storage device 310 in Figure 3, the second data storage device 320 in Figure 3, or the data storage device 410 in Figure 4.

[0086] In step 502, the system controller receives a read request from a host device (e.g., host device 120 in Figure 1A). The read request may be a read command for reading data from one or more data storage devices in the data storage system. The system controller may transmit the read command to one or more data storage devices.

[0087] In step 504, in response to the data storage device receiving a read command from the system controller, the memory controller in the data storage device (e.g., memory controller 161 in Figure 1C) reads data from at least one memory in the data storage device (e.g., memory 152 in Figure 1C, memory 212 in Figure 2, memory 312 in Figure 3, or memory 412 in Figure 4). The memory controller may include at least one first ECC decoder, i.e., a weaker ECC decoder, such as ECC decoder 154 in Figure 1B or Figure 1C, ECC decoder 214 in Figure 2, ECC decoder 314 in Figure 3, or ECC decoder 414 in Figure 1C.

[0088] In step 506, the memory controller performs weak ECC decoding in the data storage device using at least one first ECC decoder, and in step 508 determines whether the read data passes the first ECC test. In some implementations, the memory controller performs ECC decoding on the read data using at least one first ECC decoder. In some implementations, the memory controller includes a first ECC encoder configured to encode data to generate first ECC data (e.g., ECC parity bits), and the memory controller can store the data and the first ECC data together in at least one memory, and read the data and the first ECC data from at least one memory. At least one first ECC decoder can use the first ECC data to decode the data read from at least one memory.

[0089] The memory controller can determine whether the read data has passed the first ECC test by determining whether the number of error bits in the data read after the ECC decoding operation is less than a predetermined threshold. If the number of error bits is less than the predetermined threshold, the memory controller can determine that the read data has passed the first ECC test. If the number of error bits is equal to or greater than the predetermined threshold, the memory controller determines that the read data has failed the first ECC test.

[0090] If the memory controller determines that the read data has passed the first ECC test, in step 510, the memory controller returns the corrected read data to the system controller, and the system controller transmits the corrected read data to the host device.

[0091] If the memory controller determines that the data read fails the first ECC test, there are two possible approaches in step 512, and either approach can be chosen or both can be performed. The first approach in step 512 is: the memory controller determines whether the number of times the data read fails the first ECC test is less than a predetermined threshold, for example, by comparing the number in the counter with the predetermined number; if the number is less than the predetermined threshold (yes in the first approach of step 512), in step 514, the memory controller changes one or more read parameters to read data from at least one memory again or performs software decoding on the data (in step 504), and accordingly, the counter can be incremented by 1. The second approach in step 512 is: when it is determined that the data read fails the first ECC test, it is determined whether the result of the first ECC test shows that the number of error bits in the read data is less than or equal to a first predetermined value; if yes, the process continues to step 514; if no, the process continues to step 518.

[0092] If the number of times in the first approach of step 512 reaches a predetermined threshold (if the first approach of step 512 is not performed), the memory controller will read data and transmit it to an external device including at least one second ECC decoder for stronger ECC decoding (step 518). The external device may be, for example, the external device 170 in Figure 1D, the external device 220 in Figure 2, the second data storage device 320 in Figure 3, or the external device 420 in the system controller in Figure 4. The at least one second ECC decoder may be, for example, the second ECC decoder 156 in Figure 1B, the second ECC decoder 156 in Figure 1D, the stronger ECC decoder 222 in Figure 2, the stronger ECC decoder 326 in Figure 3, or the stronger ECC decoder 422 in Figure 4. The at least one second ECC decoder in the external device may have a stronger ECC capability than the at least one first ECC decoder in the data storage device.

[0093] In step 518, the external device performs strong ECC decoding on the read data using at least one second ECC decoder, and in step 520 determines whether the read data passes the second ECC test. In some implementations, the external device performs ECC decoding on the read data using at least one second ECC decoder. As shown in Figures 6A, 6B, or 6C, at least one second ECC decoder may perform ECC decoding based on first ECC data generated by at least one first ECC decoder (e.g., as shown in Figure 6A), or based on second ECC data (based on the data to be read) generated using a second ECC encoder in the external device or data storage device (e.g., as shown in Figure 6B), or based on second ECC data generated using the second ECC decoder of the external device from multiple data portions of data to be read from multiple data storage devices (e.g., as shown in Figure 6C).

[0094] The external device can determine whether the read data has passed the second ECC test by determining whether the number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold. If the number of error bits is less than the predetermined threshold, the external device can determine that the read data has passed the second ECC test. If the number of error bits is equal to or greater than the predetermined threshold, the external device determines that the read data has failed the second ECC test.

[0095] If the external device determines that the read data passes the second ECC test, in step 510, the external device returns the corrected read data to the system controller, and the system controller transmits the corrected read data to the host device. In some implementations, the external device returns the corrected read data to the data storage device.

[0096] If the external device determines that the read data has failed the second ECC test, there are two approaches in step 522, and one or both approaches can be performed. The first approach in step 522 is: the external device determines whether the number of times the read data has failed the second ECC test is less than a predetermined threshold, for example, by comparing a counter with a predetermined number of times. If the number of times is less than the predetermined threshold (yes in the first approach of step 522), the process continues to step 514, and the counter can be incremented by 1. The second approach in step 522 is: when it is determined that the read data has failed the second ECC test, it determines whether the result of the second ECC test shows that the number of error bits in the read data is less than or equal to a second predetermined value. If yes, the process continues to step 514; if no, the process continues to step 524.

[0097] If the number of reads reaches a predetermined threshold (if the first approach in step 522 is not successful), in step 524, the external device may trigger the RAID (Redundant Independent Disk Array) circuitry to perform error correction on the read data for data recovery. For example, the external device may send a message to the system controller instructing the RAID circuitry to be triggered, and the system controller may trigger the RAID circuitry accordingly. In some implementations, the RAID circuitry may be included in the memory controller and configured to perform error correction on the read data within the data storage device. In some implementations, the RAID circuitry may be included in the system controller and configured to perform error correction on the read data within one or more data storage devices. The RAID circuitry may also be located in an external device (e.g., accessory device 140 in Figure 1A), which is located outside the data storage device and the system controller.

[0098] In some implementations, the system controller is configured to generate an alarm message for replacing the data storage device based on one of the results of a first ECC test using at least one first ECC decoder or a second ECC test using at least one second ECC decoder. For example, the data storage device may be designed to be cheap and replaceable when the first ECC decoder and / or the second ECC decoder has difficulty correcting erroneous bits.

[0099] Figures 6A to 6C illustrate different examples of encoding and decoding data in the data storage system implemented in this case. The data storage system may be the data storage system 110 of Figure 1A, the data storage system 200 of Figure 2, the data storage system 300 of Figure 3, or the data storage system 400 of Figure 4. The data storage system may include a system controller and one or more data storage devices. The system controller may be, for example, the system controller 112 of Figure 1A, the system controller 202 of Figure 2, the system controller 302 of Figure 3, or the system controller 402 of Figure 4. The data storage devices may be, for example, the data storage device 130 of Figure 1A, the data storage device 150 of Figure 1B, the data storage device 160 of Figure 1C, the data storage device 210 of Figure 2, the first data storage device 310 of Figure 3, the second data storage device 320 of Figure 3, or the data storage device 410 of Figure 4.

[0100] Figure 6A is a schematic diagram of an exemplary process 600 for encoding data 601 and decoding data in a data storage system, for example, using the same ECC data for a weaker ECC decoder and a stronger ECC decoder. The data storage device may include a memory controller and a memory 604. The memory controller may be, for example, the memory controller 161 of Figure 1C. The memory controller may include an ECC encoder 602 and a weaker ECC decoder 606. The weaker ECC decoder 606 may be, for example, the ECC decoder 154 of Figure 1B or Figure 1C, the ECC decoder 214 of Figure 2, the ECC decoder 314 of Figure 3, or the ECC decoder 414 of Figure 1C.

[0101] ECC encoder 602 can encode data 601 to produce ECC data 603 (e.g., ECC parity bits). Memory controller can write data 601 and ECC data 603 into memory 604. Data 601 and ECC data 603 can be read from memory 604 together, for example, in response to a read command from the system controller. Reading data 605 may result in error bits.

[0102] As described above, the weaker ECC decoder 606 in the data storage device can first decode the read data 605 based on the ECC data 603. If the weaker ECC decoder 606 fails to decode the read data 605, the memory controller can transfer the read data 605 and the ECC data 603 to an external device including an ECC decoder 608 (stronger than the weaker ECC decoder 606). The external device can be, for example, the external device 170 of Figure 1D, the external device 220 of Figure 2, the second data storage device 320 of Figure 3, or the external device 420 in the system controller of Figure 4. The stronger ECC decoder 608 can be, for example, the second ECC decoder 156 of Figure 1B, the second ECC decoder 156 of Figure 1D, the stronger ECC decoder 222 of Figure 2, the stronger ECC decoder 326 of Figure 3, or the stronger ECC decoder 422 of Figure 4. A more powerful ECC decoder 608 can decode the read data 605 based on the ECC data 603 to generate the corrected read data 609.

[0103] In some implementations, the bit-flipping-based LDPC decoder (as a low-power decoding mode) and the min-sum LDPC decoder (as a stronger decoding mode) are implemented as a pair of a weaker ECC decoder 606 and a stronger ECC decoder 608. As shown in Figure 6A, the strong and weak decoding modes use the same ECC encoder 602, and the ECC data 603 (e.g., ECC parity bits) is shared by the weaker ECC decoder 606 and the stronger ECC decoder 608.

[0104] Figure 6B is a schematic diagram of another example process 630 for encoding and decoding data in a data storage system. Unlike process 610 in Figure 6A, process 630 includes two different types of ECC data. In some implementations, the memory controller in the data storage device may include an internal ECC encoder 634 and an internal ECC decoder 638. An external device may include an external ECC encoder 632 and an external ECC decoder 640. In some implementations, the memory controller includes an internal ECC encoder 634, an external ECC encoder 632, and an internal ECC decoder 638, while the external device includes only an external ECC decoder 640. The internal ECC encoder 634 may correspond to the internal ECC decoder 638, and the external ECC encoder 632 may correspond to the external ECC decoder 640. The internal ECC decoder 638 is configured to decode data using the ECC data generated by the internal ECC encoder 634, while the external ECC decoder 640 is configured to decode data using the ECC data generated by the external ECC encoder 632.

[0105] The external device may be, for example, the external device 170 in Figure 1D, the external device 220 in Figure 2, the second data storage device 320 in Figure 3, or the external device 420 in the system controller in Figure 4. The external ECC decoder 640 may have a higher ECC capability than the internal ECC decoder 638. The internal ECC decoder 638 may be a weaker ECC decoder, such as the ECC decoder 154 in Figure 1B or 1C, the ECC decoder 214 in Figure 2, the ECC decoder 314 in Figure 3, or the ECC decoder 414 in Figure 1C. The external ECC decoder 640 may be a stronger ECC decoder, such as the second ECC decoder 156 in Figure 1B, the second ECC decoder 156 in Figure 1D, the stronger ECC decoder 222 in Figure 2, the stronger ECC decoder 326 in Figure 3, or the stronger ECC decoder 422 in Figure 4.

[0106] Data 631 to be stored in memory 636 of the data storage device can first be encoded by an external ECC encoder 632 to generate external ECC data 633 (e.g., external ECC parity bits). An external device can then transfer data 631 along with ECC data 633 to the data storage device. An internal ECC encoder 634 can encode data 631 to generate internal ECC data 635 (e.g., internal ECC parity bits). The memory controller can store data 631 along with external ECC data 633 and internal ECC data 635 in memory 636 of the data storage device. The memory controller can store internal ECC data 635 and external ECC data as a concatenated encoding of data 631 in memory 636. The internal ECC decoder 638 can handle most read requests, while the external ECC decoder 640, although having stronger ECC capabilities, suffers from longer latency and consumes more power, and is therefore rarely used.

[0107] The memory controller can read data 631 from memory 636, along with external ECC data 633 and internal ECC data 635, to obtain read data 637, which may include error bits. The memory controller can decode the read data 637 using internal ECC decoder 638, as shown in Figure 5, for example. If internal ECC decoder 638 successfully decodes the read data 637 using internal ECC data 635, the memory controller generates corrected read data 639. If internal ECC decoder 638 cannot decode the read data 637 using internal ECC data 635, the memory controller can send the read data 637 and external ECC data 633 to an external device. External ECC decoder 640 in the external device can then decode the read data 637 according to external ECC data 633 to generate corrected read data 639.

[0108] Figure 6C is a schematic diagram of another example process 650 for encoding and decoding data in a data storage system. Unlike process 630 in Figure 6B, process 650 involves storing multiple data portions into multiple data storage devices in a data storage system.

[0109] In some implementations, each data storage device includes a memory controller (e.g., memory controller 161 of Figure 1C) and a corresponding memory 656. The memory controller in the data storage device may include an internal ECC encoder 654 and an internal ECC decoder 658. External devices may include an external ECC encoder 652 and an external ECC decoder 660. The internal ECC encoder 654 may correspond to the internal ECC decoder 658, and the external ECC encoder 652 may correspond to the external ECC decoder 660. The internal ECC decoder 658 is configured to decode data using ECC data generated by the internal ECC encoder 654, while the external ECC decoder 660 is configured to decode data using ECC data generated by the external ECC encoder 652.

[0110] The external device may be, for example, the external device 170 in Figure 1D, the external device 220 in Figure 2, the second data storage device 320 in Figure 3, or the external device 420 in the system controller in Figure 4. The external ECC decoder 660 may have a stronger ECC capability than the internal ECC decoder 658. The internal ECC decoder 658 may be a weaker ECC decoder, such as the ECC decoder 154 in Figure 1B or 1C, the ECC decoder 214 in Figure 2, the ECC decoder 314 in Figure 3, or the ECC decoder 414 in Figure 1C. The external ECC decoder 660 may be a stronger ECC decoder, such as the second ECC decoder 156 in Figure 1B, the second ECC decoder 156 in Figure 1D, the stronger ECC decoder 222 in Figure 2, the stronger ECC decoder 326 in Figure 3, or the stronger ECC decoder 422 in Figure 4.

[0111] Data in multiple data portions 651 to be stored in multiple data storage devices can first be encoded by an external ECC encoder 652 in an external device to generate external ECC data 653 (e.g., external ECC parity bits of multiple data portions 651) for multiple data portions 651. Then, each data portion 651 and the external ECC data 653 can be transmitted, for example, via an external device or a system controller, to a corresponding data storage device in the multiple data storage devices. An internal ECC encoder 654 in a corresponding data storage device can encode the data portion 651 to generate internal ECC data 655 (e.g., internal ECC parity bits of data portion 651) for the data portion 651. A memory controller in a corresponding data storage device can store the data of the data portion 651, together with the internal ECC data 655 and the external ECC data 653, into the memory 656 of the corresponding data storage device.

[0112] Upon receiving a read request from a host device (e.g., host device 120 in Figure 1A), the system controller can transmit read instructions to multiple data storage devices. For each of the multiple data storage devices, the memory controller can read the corresponding data portion 651 from memory 656, as well as the corresponding internal ECC data 655 and external ECC data 653. The internal ECC decoder 658 first decodes the read data portion 657 based on the corresponding internal ECC data 655. If the internal ECC decoder 658 successfully decodes the read data portion 657 using the internal ECC data 655, the memory controller generates a corrected read data portion 659. If the internal ECC decoder 658 cannot decode the read data portion 657 using the internal ECC data 655, the memory controller can transmit the read data portion 657 and the external ECC data 653 to an external device. Then, the external ECC decoder 660 in the external device decodes the corresponding data portion 657 based on the external ECC data 653 to generate the corrected read corresponding data portion 659.

[0113] In process 650, weaker and stronger ECC encoders and decoders can be implemented in pairs. The two types of ECC encoders 652 and 654 generate two types of parity bits, for example, internal ECC data for a corresponding data section and external ECC data for the entire data or multiple data sections. Encoding and decoding of the external (stronger) ECC are performed by an external device. Encoding and decoding of the internal (weaker or low-power) ECC are performed within a single data storage device. The internal ECC decoder can handle most read requests, while the external ECC decoder, despite having stronger ECC capabilities, suffers from higher latency and consumes more power, and is therefore rarely used.

[0114] The above and other examples can be implemented as one or more computer program products, such as one or more computer program instruction modules encoded on a computer-readable medium for execution by or control of the operation of a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination thereof. The term "data processing device" includes all means and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, the device includes code that creates an execution environment for the computer program in question, such as processor firmware, a protocol stack, a database management system, an operating system, or a combination thereof.

[0115] The system may include all means and machines for processing data, such as programmable processors, computers, or multiple processors or computers. In addition to hardware, the system may also include code that creates an execution environment for the computer program in question, such as processor firmware, protocol stack, database management system, operating system, or a combination of one or more of them.

[0116] A computer program (also known as a program, software, software application, script, or code) can be written in any programming language, including compiled or interpreted languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored as part of a file that includes other programs or materials (e.g., one or more scripts stored in a markup language file), or it can be stored in a single file dedicated to the program in question, or it can be stored in multiple coordinated files (e.g., a file storing one or more modules, subroutines, or code portions). A computer program can be deployed on a single computer or on multiple computers located at a single site or distributed across multiple sites and interconnected by a communication network.

[0117] The processes and logic described in this case can be executed by one or more programmable processors, which execute one or more computer programs to perform the functions described herein. These processes and logic can also be executed by special purpose logic circuits, such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits).

[0118] Processors suitable for executing computer programs include general-purpose and special-purpose microprocessors, and one or more processors of any kind of digital computer. For example, typically, a processor receives instructions and data from read-only memory or random access memory, or both. Basic components of a computer may include a processor to execute instructions and one or more storage devices to store instructions and data. Typically, a computer may also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical discs. However, a computer does not necessarily need to have these devices. Computer-readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory, media, and storage devices, including, for example, semiconductor storage devices such as EPROM, EEPROM, flash memory, and magnetic disks. Processors and memory may additionally include or be integrated with special-purpose logic circuitry.

[0119] While this document may describe many specific details, these details should not be construed as limiting the scope of the claimed invention or any possible scope claimed, but rather as descriptions of features of particular embodiments. Certain features described herein in the context of different embodiments may also be combined and implemented in a single embodiment. Conversely, various features described herein in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, although a particular order of operations is depicted in the illustrations, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to obtain the desired result.

[0120] Only some examples and implementations are shown. Changes, modifications, enhancements, and other implementations can be made based on what is shown. [Simplified Explanation of the Diagram]

[0045] Figure 1A is a schematic diagram of a system including a data storage system. Figure 1B is a schematic diagram of a first data storage device including a weaker ECC decoder and a stronger ECC decoder. Figure 1C is a schematic diagram of a second data storage device including only a weaker ECC decoder. Figure 1D is a schematic diagram of an external device including only a stronger ECC decoder. Figure 2 is a schematic diagram of a data storage system including one or more external devices with stronger ECC decoders for use with a data storage device having only a weaker ECC decoder. Figure 3 is a schematic diagram of a data storage system including data storage devices with stronger ECC decoders for use with a data storage device having only a weaker ECC decoder. Figure 4 is a schematic example of a data storage system including a system controller that includes one or more external devices with a stronger ECC decoder 422 for use with the data storage device. Figure 5 is an example flowchart of error correction management for the data storage system. Figure 6A is a schematic diagram of an exemplary process for encoding and decoding data in the data storage system. Figure 6B is a schematic diagram of another exemplary process for encoding and decoding data in a data storage system. Figure 6C is a schematic diagram of another exemplary process for encoding and decoding data in a data storage system.

[0046] The same reference numbers and labels in each figure represent the same elements. It should also be understood that the various exemplary embodiments shown in the figures are only schematic representations and are not necessarily drawn to scale.

Claims

1. A data storage system, comprising: One or more data storage devices; The system controller is coupled to the data storage devices, wherein one of the data storage devices includes at least one memory and a memory controller coupled to the at least one memory, the memory controller including at least one first error correction code (ECC) decoder, wherein the memory controller is configured to: read data from the at least one memory; perform a first ECC test on the read data using the at least one first ECC decoder; and in response to determining that the read data failed the first ECC test, decide, based on the number of times the read data failed the first ECC test, to either reread the data from the at least one memory, perform software decoding on the data, or transmit the read data to an external device having at least one second ECC decoder to decode the read data, wherein the external device is located outside the data storage devices, and the at least one second ECC decoder has a stronger ECC capability than the at least one first ECC decoder.

2. The data storage system as claimed in claim 1, wherein the memory controller is configured to: in response to determining that the read data failed the first ECC test and before transmitting the read data to the external device, determine whether the number of times the read data failed the first ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, change one or more read parameters to reread the data from the at least one memory or perform software decoding on the read data; and if the number reaches the predetermined threshold, transmit the read data to the external device having the at least one second ECC decoder to decode the read data.

3. The data storage system as claimed in claim 1, wherein the memory controller is configured to: in response to determining that the read data failed the first ECC test and before transmitting the read data to the at least one second ECC decoder, based on a result of the first ECC test, perform one of the following operations: i) change one or more parameters for reading the data from the at least one memory or perform software decoding on the data, and perform the first ECC test again using the at least one first ECC decoder, or ii) transmit the read data to the external device having the at least one second ECC decoder to decode the read data.

4. The data storage system as claimed in claim 1, wherein the external device is configured to: perform a second ECC test on the read data using at least one second ECC decoder, and in response to determining that the read data passes the second ECC test, transmit a corrected read data to the system controller.

5. The data storage system as described in claim 4, wherein the external device is configured to: in response to determining that the read data failed the second ECC test, determine whether the number of times the read data failed the second ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, send a notification to the memory controller to i) change one or more parameters for reading the data from the at least one memory, or ii) perform software decoding on the data; and if the number reaches the predetermined threshold, trigger a RAID (Redundant Array of Independent Disks) circuit to correct errors in the read data.

6. The data storage system as claimed in claim 4, wherein the external device is configured to: in response to determining that the read data failed the second ECC test and before triggering a RAID circuit, based on a result of the second ECC test, perform one of the following: i) change one or more parameters for reading the data from the at least one memory, or perform software decoding on the data, and perform at least one of the following again: perform the first ECC test using at least one first ECC decoder, or perform the second ECC test using at least one second ECC decoder, or ii) trigger the RAID circuit to correct the error in the read data.

7. The data storage system as claimed in claim 1, wherein the memory controller is configured to: perform an ECC decoding operation on the read data using at least one first ECC decoder; determine whether the number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold; if the number of error bits is less than the predetermined threshold, determine that the read data has passed the first ECC test; and if the number of error bits is equal to or greater than the predetermined threshold, determine that the read data has failed the first ECC test.

8. The data storage system as described in claim 1, wherein the data storage devices or the data storage devices comprise: One or more first data storage devices, each or the first data storage devices including only one or more first ECC decoders, and one or more second data storage devices, each or the second data storage devices including one or more first ECC decoders and one or more second ECC decoders.

9. The data storage system as claimed in claim 8, wherein the system controller is configured to: store a first type of data in the one or more first data storage devices and store a second type of data in the one or more second data storage devices, wherein the first type of data is read more frequently than the second type of data.

10. The data storage system as described in claim 8, wherein the first data storage device and the second data storage device are configured to operate under a protocol, wherein: Each of the first data storage devices is configured to, in response to the inability of the first ECC decoder in the first data storage device to correct a first data read from a related first memory, transmit the read first data to the second data storage device, and each of the second data storage devices is configured to, in response to receiving related read data from the first data storage device, decode the related read data using the second ECC decoder in the second data storage device.

11. The data storage system as described in claim 1, wherein the external device is included in the system controller.

12. The data storage system of claim 1, wherein the memory controller includes a first ECC encoder for encoding the data to generate a first ECC data, and the memory controller is configured to store the data together with the first ECC data in the at least one memory; and the at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the first ECC data.

13. The data storage system as described in claim 1, wherein, The memory controller includes a first ECC encoder for encoding the data to generate first ECC data, and the external device includes a second ECC encoder for encoding the data to generate second ECC data. The memory controller is configured to: store the data together with the first ECC data and the second ECC data in at least one memory; read the data, the first ECC data, and the second ECC data from the at least one memory; and, in response to determining that the read data fails the first ECC test, transmit the read data and the second ECC data to the external device having at least one second ECC decoder, wherein the at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the second ECC data received from the memory controller.

14. The data storage system as described in claim 1, wherein, The system controller is configured to transmit multiple portions of specific data to multiple data storage devices, each of which includes a first ECC encoder and one or more first ECC decoders. The first ECC encoder is configured to encode a relevant portion of the specific data corresponding to each data storage device to generate first ECC data. The external device includes a second ECC encoder for encoding the portions of the specific data to generate second ECC data. Each data storage device includes a memory controller for storing the relevant portion of the specific data together with the first ECC data and the second ECC data in a associated memory. For each of the data storage devices, the first ECC decoder is configured to decode the relevant portion of the specific data read from the associated memory based on the first ECC data. The at least one second ECC decoder of the external device is configured to decode the portion of the specific data based on the second ECC data in response to receiving a portion of the specific data and the second ECC data from one of the data storage devices.

15. A data storage device, comprising: At least one memory cell; and a memory controller coupled to the at least one memory, the memory controller including at least one first ECC decoder, wherein the memory controller is configured to: read data from the at least one memory; perform a first error correction code (ECC) test on the read data using the at least one first ECC decoder; and, in response to determining that the read data failed the first ECC test, decide, based on the number of times the read data failed the first ECC test, to either reread the data from the at least one memory, perform software decoding on the data, or transmit the read data to an external device having at least one second ECC decoder for decoding, wherein the external device is located outside the data storage device, and the at least one second ECC decoder has a stronger ECC capability than the at least one first ECC decoder.

16. The data storage device as claimed in claim 15, wherein the memory controller is configured to: in response to determining that the read data failed the first ECC test and before transmitting the read data to the external device, determine whether the number of times the read data failed the first ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, change one or more read parameters to reread the data from the at least one memory or perform software decoding on the read data; and if the number reaches the predetermined threshold, transmit the read data to the external device having the at least one second ECC decoder to decode the read data.

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