Semiconductor structure and method of forming the same

Abstract

A semiconductor fabrication is provided. The semiconductor fabrication includes a first set of nanostructures located between a first source / drain structure and a second source / drain structure, a first gate portion surrounding the first set of nanostructures, and a wall structure adjacent to the first gate portion. The first nanostructure in the first set of nanostructures includes a substrate portion and a protrusion portion, wherein the protrusion portion protrudes from a first sidewall of the substrate portion toward the wall structure.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to semiconductor construction, and particularly to the location of the gate structure formed in a self-aligned manner between active regions. [Previous Technology]

[0002] The electronics industry continues to demand smaller, faster electronic devices capable of supporting a large number of complex functions simultaneously. In summary, the ongoing trend in the semiconductor industry is to manufacture low-cost, high-performance, and low-power integrated circuits. The main method to achieve these goals is to reduce the size of semiconductor integrated circuits (such as minimum structural dimensions), thereby improving production capacity and reducing related costs. However, minimization also significantly increases the complexity of semiconductor manufacturing processes. Therefore, for the continued advancement of semiconductor integrated circuits and devices, semiconductor manufacturing processes and technologies also need similar advancements.

[0003] Recently, multi-gate devices have been introduced to improve gate control, reduce off-state current, and mitigate short-channel effects by increasing gate-channel coupling. One such multi-gate device is the fully wound gate transistor. The name "fully wound gate" comes from its gate structure, which extends around the channel region and contacts both sides or all four sides of the channel. Fully wound gates are compatible with associated complementary metal-oxide-semiconductor (CMOS) processes, and their structure can be significantly miniaturized while maintaining gate control and mitigating short-channel effects. Fully wound gate devices provide channels for silicon nanowires or nanosheets. However, the fabrication method of integrating the fully wound gate structure around the nanowire or nanosheet presents a significant challenge. For example, existing methods are applicable in many areas, but continuous improvement is still needed. [Summary of the Invention]

[0004] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first fin structure and a second fin structure. Each of the first fin structure and the second fin structure includes an alternating stack of a plurality of first semiconductor layers and a plurality of second semiconductor layers. The method also includes forming a dummy gate structure across the first fin structure and the second fin structure; partially etching the dummy gate structure to form an opening exposing the first fin structure and the second fin structure; selectively forming a plurality of first semiconductor structures on the second semiconductor layers of each of the first fin structure and the second fin structure; and forming a wall structure in the opening.

[0005] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a stack of interleaved first semiconductor layers and a stack of interleaved second semiconductor layers on a substrate; patterning a portion of the stack and the substrate to form an active region; and forming a dummy gate portion on the active region. The method also includes growing a plurality of semiconductor structures on a plurality of first sidewalls of the second semiconductor layers of the active region; forming a wall structure to adjoin the dummy gate portion and the active region; and removing the dummy gate portion and the first semiconductor layer of the active region.

[0006] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures in a first group located between a first source / drain structure and a second source / drain structure; a first gate portion surrounding the nanostructures in the first group; and a wall structure adjacent to the first gate structure. The first nanostructure in the first group of nanostructures includes a substrate portion and a protrusion portion, and the protrusion portion in a plan view protrudes from a first sidewall of the substrate portion toward the wall structure.

Implementation Method

[0008] The following detailed description is illustrated in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0009] It is understood that the different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or that the two are separated by other additional components rather than in direct contact. Furthermore, various embodiments of the present invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] Some variations of the embodiments are described below. In various drawings and illustrative embodiments, similar reference numerals are used to identify similar units. It should be understood that additional steps may be provided before, during, and after the method, and other embodiments of the method may replace or omit some of the stated steps.

[0011] The patterning method for nanostructured transistors such as nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nano-beam field-effect transistors, and fully wound gate transistor structures can be any suitable method. For example, one or more photolithography processes can be used to pattern the structure, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, resulting in a pattern pitch smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern a fully wound gate structure.

[0012] Embodiments of a semiconductor fabrication and its formation method are provided. The semiconductor fabrication includes a wall structure that can be self-aligned and formed at the location of a gate structure between active regions. Forming the wall structure facilitates achieving a minimum space between the active regions and the gate cleaving structure. Furthermore, the semiconductor fabrication further includes a semiconductor structure grown on the sidewall of a channel layer facing the active regions of the wall structure. The semiconductor structure and the channel layer can together serve as a channel for the final transistor. Therefore, the total cell capacitance of the final semiconductor device can be reduced, the size of the final semiconductor device can be reduced, and / or the turn-on current of the final semiconductor device can be increased.

[0013] FIG1 is a perspective view of a semiconductor structure 100 in some embodiments. In some embodiments, the semiconductor structure 100 includes a lower fin unit 104L located on a substrate 102, an isolation structure 110 surrounding the lower fin unit 104L, and a nanostructured transistor (such as a fully wound gate transistor) formed on the lower fin unit 104L. In some embodiments, the nanostructured transistor includes a plurality of nanostructures 154, a source / drain structure 134 adjacent to the nanostructures 154, and a gate stack 170 covering each nanostructure 154.

[0014] To better understand the semiconductor structure, XYZ reference coordinates are provided in the drawings of embodiments of the present invention. The X-axis and Y-axis are generally along a transverse (or horizontal) direction and are parallel to the main surface of the substrate. The Y-axis is transverse to (or substantially perpendicular to) the X-axis. The Z-axis is generally along a vertical direction and is perpendicular to the main surface of the substrate (or the XY plane).

[0015] In some embodiments, the nanostructure 154 extends in the X direction between the source / drain structures 134. In some embodiments, the nanostructure 154 serves as a channel for the nanostructured transistor. The X direction can also be considered as the direction in which the channel extends. The current of the final semiconductor device (i.e., the nanostructured transistor) flows through the channel in the X direction. It is worth noting that in embodiments of the present invention, the source / drain regions of the source / drain structure can be considered individually or together as sources or drains, depending on the context.

[0016] In some embodiments, the longitudinal axis of the gate stack 170 is parallel to the Y direction, extends over the lower fin unit 104L, and surrounds the nanostructure 154. In some embodiments, the Y direction can also be regarded as the gate wiring direction.

[0017] In some embodiments, the semiconductor structure 100 further includes a gate spacer layer 118 along the sides of the two sidewalls of the gate stack 170, a fin spacer layer 120 along the sides of the two sidewalls of the lower portion of the source / drain structure 134, and an inner spacer layer 128 vertically sandwiched between the nanostructures 154 and laterally located between the source / drain structure 134 and the gate stack 170. In some embodiments, the semiconductor structure 100 further includes a wall structure 144 adjacent to the gate stack 170 and the nanostructures 154, and sandwiched between the gate spacer layers 118.

[0018] FIG2 shows the layout of the semiconductor structure 100 in some embodiments. In some embodiments, the semiconductor structure 100 includes an active region 104 (including 104 1 to 104 4) on a substrate (substrate 102 as shown in FIG1), and a final gate stack 170 (including 170 1 to 170 3) extending over the active region 104. In some embodiments, the active region 104 extends in the X direction. In some embodiments, the longitudinal axis of the active region 104 is parallel to the X direction.

[0019] In some embodiments, the substrate includes p-type wells PW formed therein in active regions 104 1 and 104 2, and n-type wells NW formed therein in active regions 104 3 and 104 4. In some embodiments, each active region 104 includes a lower fin unit (lower fin unit 104L as shown in FIG. 1) and a nanostructure (nanostructure 154 as shown in FIG. 1) formed on the lower fin unit.

[0020] In some embodiments, the final gate stack 170 extends in the Y direction beyond the lower fin unit and covers the nanostructure. In some embodiments, the longitudinal axis of the final gate stack 170 is parallel to the Y direction. In some embodiments, the final gate stack 170 is combined with the active region 104 to form a nanostructure transistor. In some embodiments, the nanostructure transistor is formed at the intersection between the active region 104 and the final gate stack 170. For example, the nanostructure transistor formed in the p-well PW is an n-channel nanostructure transistor NMOSFET, while the nanostructure transistor formed in the n-well NW is a p-channel nanostructure transistor PMOSFET.

[0021] In some embodiments, the area of ​​the substrate may be defined as a plurality of cell regions. Several nanostructured transistors are located in each cell region to construct a functional circuit. In some embodiments, FIG2 shows the boundaries C1 and C2 of the cell regions. Boundaries C1 and C2 extend in the X direction. Although not shown, the boundaries of the cell regions may extend in the Y direction.

[0022] In some embodiments, the semiconductor fabrication 100 further includes a wall structure 144 and a gate cleaving structure 172. In some embodiments, both the wall structure 144 and the gate cleaving structure 172 are configured to divide the gate stack 170. In some embodiments, the gate cleaving structures 172 each extend in the X direction and are aligned with the boundary C1 or C2 of the cell region. In some embodiments, the wall structures 144 each extend in the Y direction and are aligned with the gate stack 170 and formed in the cell region. In some embodiments, the wall structure 144 is located on the boundary between the n-type well NW and the p-type well PW. In some other embodiments, the wall structure 144 may be aligned with the boundary of the cell region, while the gate cleaving structure 172 is located in the cell region.

[0023] In some embodiments, the space S1 between active regions 1041 and 1042 and the space S3 between active regions 1043 and 1044 are approximately 30 nm to approximately 60 nm. In some embodiments, the space S2 between active regions 1042 and 1043 is approximately 20 nm to approximately 40 nm. In some embodiments, spaces S1 and S3 are larger than space S2. In some other embodiments, space S2 is greater than or equal to spaces S1 and S3.

[0024] The space between the active region 104 and the gate slicing structure (such as the wall structure 144 or the gate slicing structure 172) can be considered as the end cap size. The wall structure 144 can be configured to cut the gate in a way that minimizes the end cap size. In this way, the total cell capacitance of the final semiconductor device can be reduced, and the performance of the final semiconductor device, such as speed, can be improved.

[0025] Furthermore, compared to the method of forming the gate-cutting structure 172, the method of forming the wall structure 144 is less limited by the stacking and / or critical dimension consistency required by the photolithography process, as detailed below. Therefore, forming the wall structure 144 is beneficial for reducing the space S2, thereby continuously reducing the cell height H of the cell region. In some embodiments, the cell height can be reduced by about 25% to about 35%.

[0026] Figure 2 also shows reference cross-sections used in the following figures. In some embodiments, cross-section XX is parallel to the longitudinal axis (X direction) of active region 104 and passes through active region 104 1. Cross-section Y1-Y1 is parallel to the longitudinal axis (Y direction) of final gate stack 170 and crosses the source / drain regions of active regions 104 2 and 104 3. Cross-section Y2-Y2 is parallel to the longitudinal axis (Y direction) of final gate stack 170 and passes through final gate stack 170 1. Cross-section Y3-Y3 is parallel to the longitudinal axis (Y direction) of final gate stack 170 and crosses the source / drain regions of active regions 104 1 to 104 4. Cross-section Y4-Y4 is parallel to the longitudinal axis (Y direction) of final gate stack 170 and passes through final gate stack 170 3.

[0027] Figures 3A to 3Q-5 are diagrams illustrating various intermediate stages in forming the semiconductor structure 100 of Figure 2 in some embodiments of the present invention. Figures 3A, 3B, 3D-2, 3E-2, 3F-2, and 3G-3 are cross-sectional views of the semiconductor structure 100 corresponding to section line Y1-Y1 in Figure 2. Figures 3C, 3G-1, and 3H-1 are perspective views of the semiconductor structure 100. Figures 3D-1, 3E-1, 3F-1, 3G-2, 3M-1, 3P-1, and 3Q-1 are cross-sectional views of the semiconductor structure 100 corresponding to section line XX in Figure 2. Figures 3H-3, 3I-1, 3J, 3K, 3L, 3M-2, 3N-1, 3O, and 3P-2 are cross-sectional views of the semiconductor structure 100 corresponding to section line Y2-Y2 in Figure 2. Figure 3Q-2 is a cross-sectional view of the semiconductor structure 100 corresponding to section line Y3-Y3 in Figure 2. Figure 3 shows a cross-sectional view of the Q-3 semiconductor structure 100 corresponding to section Y4-Y4 in Figure 2.

[0028] FIG3A is a diagram of a semiconductor structure 100 after the formation of the active region 104 in some embodiments of the present invention. In some embodiments, a semiconductor structure 100 is provided. The semiconductor structure 100 includes a substrate 102 and an active region 104 located on the substrate 102, as shown in some embodiments of FIG3A.

[0029] The substrate 102 may be part of a semiconductor wafer, semiconductor wafer (or die), or the like. In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the substrate 102 includes semiconductor elements (such as germanium), semiconductor compounds (such as gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), or combinations thereof. Furthermore, the substrate 102 may, where appropriate, include an epitaxial layer, stresses that enhance performance, silicon structures on an insulating layer, and / or other suitable enhancing structures.

[0030] In some embodiments, the method of forming n-type wells and p-type wells (n-type well NW and p-type well PW as shown in FIG. 2) in the substrate 102 may employ an ion implantation process. In some embodiments, the individual concentrations of dopants in the n-type wells and p-type wells are from about 10¹⁶ / cm⁻³ to about 10¹⁸ / cm⁻³. In some embodiments, multiple ion implantation processes with different doses and different energy densities may be performed. In some embodiments, the ion implantation process may include breakdown-resistant implantation.

[0031] In some embodiments, the active region 104 may also be regarded as a fin or fin structure. In some embodiments, the active region 104 is defined as a plurality of channel regions and a plurality of source / drain regions, wherein the channel regions and source / drain regions are alternately arranged. In some embodiments, the active region 104 each includes a lower fin unit 104L, an upper fin unit, and a masking layer 109. In some embodiments, the lower fin unit 104L is formed from a portion (or well) of the substrate 102. In some embodiments, the upper fin unit is formed from an epitaxial stack containing an interlaced first semiconductor layer 106 and a second semiconductor layer 108.

[0032] In some embodiments, the method of forming the active region 104 includes forming an epitaxial stack on the substrate 102 using an epitaxial growth process, and forming a dielectric layer for the masking layer 109 on the epitaxial stack. The method of forming the epitaxial stack may be to deposit a first semiconductor layer 106 on the substrate 102, deposit a second semiconductor layer 108 on the first semiconductor layer 106, and repeat the deposition of the first semiconductor layer 106 and the second semiconductor layer 108 multiple times. In some embodiments, the first semiconductor layer 106 and the second semiconductor layer 108 are stacked alternately. In some embodiments, the number of first semiconductor layers 106 is greater than the number of second semiconductor layers 108. The epitaxial growth process may be molecular beam epitaxy, metal-organic chemical vapor deposition, vapor phase epitaxy, or another suitable technique.

[0033] In some embodiments, the first semiconductor layer 106 is composed of a first semiconductor material, and the second semiconductor layer 108 is composed of a second semiconductor material, and the compositions of the first semiconductor material and the second semiconductor material are different. In some embodiments, the first semiconductor material used in the first semiconductor layer 106 and the second semiconductor material used in the second semiconductor layer 108 have different lattice constants. In some embodiments, the first semiconductor material and the second semiconductor material have different oxidation rates and / or etching selectivity. In some embodiments, the first semiconductor layer 106 is composed of silicon germanium, and the germanium percentage in the silicon germanium is about 20 atomic% to about 50 atomic%. The second semiconductor layer 108 is composed of pure silicon or substantially pure silicon. In some embodiments, the first semiconductor layer 106 is Si 1-xGe x (x is greater than about 0.3) or Ge (x = 1.0), and the second semiconductor layer 108 is Si or Si 1-yGe y (y is less than about 0.4), and x > y.

[0034] In some embodiments, the first semiconductor layer 106 is configured as a sacrificial layer and is subsequently removed to form a gap for accommodating gate material. In some embodiments, the second semiconductor layer 108 will form a nanostructure (such as a nanowire or nanosheet) that extends laterally between the source / drain structures and serves as a channel for the final semiconductor device (such as a nanostructured transistor). The term "nanostructure" as used herein refers to a cylindrical, rod-shaped, and / or sheet-shaped semiconductor layer. Although three second semiconductor layers 108 are shown in the figures, the number is not limited to three but may be two or four, and less than ten.

[0035] The masking layer 109 is composed of a dielectric material with a low dielectric constant (e.g., less than 7.9), such as silicon nitride, silicon oxide, oxynitride, silicon carbide, oxygen-doped silicon carbide, silicon carbonitride, oxygen-doped silicon carbonitride, or a combination thereof. In some embodiments, the dielectric material is deposited using chemical vapor deposition (e.g., low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, or high aspect ratio process), atomic layer deposition, another suitable technique, or a combination thereof.

[0036] In some embodiments, the thickness T1 of each of the first semiconductor layers 106 is about 4 nm to about 14 nm. In some embodiments, the thickness T2 of the second semiconductor layer 108 is about 3 nm to about 9 nm. The thickness of the second semiconductor layer 108 may be greater than, equal to, or less than the thickness of the first semiconductor layer 106, depending on the amount of gate material required to fill the space removed from the first semiconductor layer 106. In some embodiments, the thickness T3 of the masking layer 109 is about 1 nm to about 8 nm.

[0037] In some embodiments, the method of forming the active region 104 further includes forming a patterned mask layer 105 on a dielectric material using a photolithography process, and etching the dielectric layer, epitaxial stack, and underlying well, thereby forming trenches and active regions 104 protruding from the trenches. The patterned mask layer 105 may be a patterned photoresist layer and / or a patterned hard mask layer. In some embodiments, the well portion protruding from the trenches may serve as the lower fin unit 104L of the active region 104. In some embodiments, the remaining epitaxial stack (including the first semiconductor layer 106 and the second semiconductor layer 108) serves as the upper fin unit of the active region 104.

[0038] FIG3B is a diagram of the semiconductor structure 100 after the isolation structure 110 is formed in some embodiments of the present invention. In some embodiments, the isolation structure 110 is formed on the substrate 102 and surrounds the lower fin unit 104L of the active region 104. In some embodiments, the isolation structure 110 is provided to electrically isolate the active region 104 of the semiconductor structure 100 and can be regarded as a shallow trench isolation structure.

[0039] In some embodiments, the method of forming the isolation structure 110 includes forming an insulating material to overfill the trench. In some embodiments, the insulating material is composed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, oxygen-doped silicon carbide, oxygen-doped silicon carbonitride, or a combination thereof. In some embodiments, the deposition method of the insulating material may employ chemical vapor deposition (such as flowable chemical vapor deposition, low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, or high aspect ratio process), atomic layer deposition, another suitable technique, or a combination thereof.

[0040] Some embodiments involve a planarization process on the insulating material to remove portions of the insulating material above the active region 104. The planarization process may be chemical mechanical polishing, etch-back, or a combination thereof. In some embodiments, the planarization process also removes the patterned mask layer 105. In some embodiments, the insulating material may then be recessed by an etching process such as dry plasma etching and / or wet chemical etching to expose the mask layer 109 and the sidewalls of the upper fin units of the active region 104. In some embodiments, the top sidewalls of the lower fin units 104L may be partially exposed.

[0041] FIG3C is a diagram of the semiconductor structure 100 after forming the dummy gate structure 112 in some embodiments of the present invention. The dummy gate structure 112 extends across the active region 104 and the isolation structure 110, as shown in some embodiments of FIG3C. In some embodiments, the dummy gate structure 112 surrounds the channel region of the active region 104. In some embodiments, the dummy gate structure 112 is configured as a sacrificial structure, which will later be replaced by the final gate stack.

[0042] Each of the dummy gate structures 112 includes a dummy gate dielectric layer 114 and a dummy gate layer 116 formed on the dummy gate dielectric layer 114, as shown in some embodiments of FIG3C. In some embodiments, the dummy gate dielectric layer 114 extends along the masking layer 109, the upper fin-shaped unit of the active region 104, and the isolation structure 110. In some embodiments, the dummy gate dielectric layer 114 is composed of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium zirconium oxide, hafnium silicon oxide, hafnium titanium oxide, and / or hafnium aluminum oxide. In some embodiments, the dummy gate layer 116 is composed of a semiconductor material such as polycrystalline silicon or polycrystalline silicon germanium.

[0043] In some embodiments, the method of forming the dummy gate structure 112 includes comprehensively and compliantly depositing the dielectric material used for the dummy gate dielectric layer 114 on the semiconductor structure 100, depositing the material used for the dummy gate layer 116 on the dielectric material, planarizing the material used for the dummy gate layer 116, and patterning the material used for the dummy gate layer 116 and the dielectric material using photolithography and etching processes to form the dummy gate structure 112. The patterning process may include forming patterned hard mask layers 111 and 113. In some embodiments, the patterned hard mask layer 111 is a silicon nitride layer, and the patterned hard mask layer 113 is a silicon oxide layer.

[0044] Figures 3D-1 and 3D-2 are diagrams of a semiconductor structure 100 formed after the formation of a gate spacer layer 118, a fin spacer layer 120, and a source / drain recess 126, in some embodiments of the present invention. The gate spacer layer 118 runs along both sidewalls of the dummy gate structure 112, while the fin spacer layer 120 runs along both sidewalls of the active region 104, as shown in some embodiments of Figures 3D-1 and 3D-2. In some embodiments, the gate spacer layer 118 extends in the Y direction and crosses the active region 104 and the isolation structure 110. In some embodiments, the fin spacer layer 120 extends in the X direction.

[0045] In some embodiments, the gate spacer layer 118 is used to offset the subsequently formed source / drain structures and separate the source / drain structures from the dummy gate structure 112. In some embodiments, the fin spacer layer 120 is used to restrict the growth of epitaxial material to prevent adjacent source / drain structures from merging with each other.

[0046] In some embodiments, the gate spacer layer 118 and the fin spacer layer 120 are formed from one or more continuous dielectric materials. For example, some embodiments of forming the gate spacer layer 118 and the fin spacer layer 120 include comprehensively and compliantly depositing spacer layers 122 and 124 on the semiconductor structure 100, and the deposition method may employ atomic layer deposition, chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, or high-density plasma chemical vapor deposition), or a combination thereof, followed by an anisotropic etching process.

[0047] In some embodiments, spacer layers 122 and 124 are composed of dielectric materials such as silicon nitride, silicon oxynitride, silicon oxide, oxygen-doped silicon carbide, oxygen-doped silicon carbonitride, silicon carbide, or another suitable dielectric material. In some embodiments, spacer layers 122 and 124 are composed of different materials and have different dielectric constants. For example, spacer layers 122 and 124 are composed of silicon carbonitride with different compositions (e.g., different carbon concentrations) and have different dielectric constants. In some other embodiments, spacer layers 122 and 124 are made of the same material.

[0048] In some embodiments, after the anisotropic etching process, the vertical portions of spacer layers 122 and 124 are retained on both sides of the dummy gate structure 112 to form a gate spacer layer 118. In some embodiments, the vertical portions of spacer layers 122 and 124 are retained on both sides of the active region 104 to form a fin spacer layer 120.

[0049] An etching process is performed to recess the source / drain regions of the active region 104, thereby forming source / drain recesses 126, as shown in some embodiments of FIG3D-1 and 3D-2. The etching process may be anisotropic etching (such as dry plasma etching), isotropic etching (such as dry chemical etching, distal plasma etching, or wet chemical etching), and / or a combination thereof. In some embodiments, the gate spacer layer 118 and the dummy gate structure 112 may serve as an etching mask to self-align the source / drain recesses on both sides of the dummy gate structure 112. In some embodiments, the bottom of the source / drain recess 126 extends into the lower fin unit 104L.

[0050] In some embodiments, the etching process also recesses the isolation structure 110, thereby forming a shallow trench isolation recess. In some embodiments, the bottom of the shallow trench isolation recess extends downwards to a depth deeper than the bottom of the source / drain recess 126. In some other embodiments, the isolation structure 110 is slightly recessed or not recessed at all. Furthermore, the etching process also recesses the fin spacer layer 120.

[0051] Figures 3E-1 and 3E-2 are diagrams of the semiconductor structure 100 after the formation of the inner spacer layer 128 in some embodiments of the present invention. An etching process is performed to laterally recess the first semiconductor layer 106 of the active region 104 from the source / drain recess 126, thereby forming a groove. The inner spacer layer 128 is then formed in the groove, as shown in some embodiments of Figure 3E-1. In some embodiments, the inner spacer layer 128 is formed adjacent to the recessed side surface of the first semiconductor layer 106. In some embodiments, the inner spacer layer 128 extends directly below the gate spacer layer 118.

[0052] In some embodiments, the inner spacer layer is a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, and / or oxygen-doped silicon carbonitride. In some embodiments, the method of forming the inner spacer layer 128 includes depositing the dielectric material used for the inner spacer layer on the semiconductor structure 100 with overfilling grooves, and then etching away portions of the dielectric material outside the grooves.

[0053] Figures 3F-1 and 3F-2 are diagrams of the semiconductor structure 100 after forming the semiconductor isolation structure 130, the dielectric isolation structure 132, and the source / drain structures 134N and 134P in some embodiments of the present invention. The semiconductor isolation structure 130 is formed in the source / drain recess 126 on the lower fin unit 104L, and the formation method employs an epitaxial growth process, as shown in some embodiments of Figures 3F-1 and 3F-2. The epitaxial growth process may be molecular beam epitaxy, metal-organic chemical vapor deposition, vapor phase epitaxy, another suitable technique, or a combination thereof. In some embodiments, the semiconductor isolation structure 130 is composed of an undoped epitaxial material such as intrinsic silicon, intrinsic silicon germanium, and / or another suitable semiconductor material.

[0054] In some embodiments, a dielectric isolation structure 132 is formed on a semiconductor isolation structure 130. In some embodiments, the dielectric isolation structure 132 is composed of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, and / or oxygen-doped silicon carbonitride. In some embodiments, the dielectric isolation structure 132 is formed by performing an etch-back process after a deposition process. In some embodiments, the dielectric isolation structure 132 may be further formed on the upper surface of the isolation structure 110 in a shallow trench isolation recess.

[0055] Source / drain structures 134N and 134P are formed in and / or on the source / drain regions of the active region 104, as shown in some embodiments of Figures 3F-1 and 3F-2. Source / drain structures 134N and 134P are grown from the exposed surface of the second semiconductor layer 108 in the source / drain recess 126, and the growth method may employ an epitaxial growth process, as shown in some embodiments of Figures 3F-1 and 3F-2. In some embodiments, source / drain structure 134N is formed in a p-type well, while source / drain structure 134P is formed in an n-type well. The epitaxial growth process may be molecular beam epitaxy, metal-organic chemical vapor deposition, vapor phase epitaxy, another suitable technique, or a combination thereof.

[0056] In some embodiments, the source / drain structure 134N is formed on a p-type well, while the source / drain structure 134P is formed on an n-type well. In some embodiments, the source / drain structures 134N and 134P are adjacent to the inner spacer layer and the second semiconductor layer 108. In some embodiments, the source / drain structures 134N and 134P may be composed of any suitable semiconductor material used in n-type or p-type semiconductor devices.

[0057] The source / drain structure 134N may be composed of semiconductor materials such as silicon phosphide, silicon arsenide, silicon carbide, silicon carbide, silicon, gallium arsenide, another suitable semiconductor material, or a combination thereof. In some embodiments, an n-type dopant may be doped into the source / drain structure 134N during the epitaxial growth process. For example, the n-type dopant may be phosphorus or arsenic. For example, the source / drain structure 134N may be epitaxially grown silicon, which may be doped with phosphorus to form a phosphorus-doped silicon source / drain structure, and / or doped with arsenic to form an arsenic-doped silicon source / drain structure.

[0058] The source / drain structure 134P is composed of a semiconductor material such as germanium silicon, silicon, gallium arsenide, another suitable semiconductor material, or a combination thereof. In some embodiments, a p-type dopant may be doped into the source / drain structure 134P during the epitaxial growth process. For example, the p-type dopant may be boron or boron difluoride. For example, the source / drain structure 134P may be epitaxially grown germanium silicon, which is doped with boron to form a boron-doped germanium silicon source / drain structure.

[0059] The n-type source / drain structure 134N and the p-type source / drain structure 134P can be formed separately. The individual concentrations of the dopants in the source / drain structures 134N and 134P can be from about 1 × 10¹⁹ cm⁻³ to about 6 × 10²¹ cm⁻³. In some embodiments shown in FIG3F-1, the source / drain structures 134N and 134P can be multilayer structures, such as including sequentially formed epitaxial layers L1 and L2. In some embodiments, the dopant concentration in epitaxial layer L2 is higher than the dopant concentration in epitaxial layer L1, for example, by one to two orders of magnitude. In some embodiments, an annealing process can be performed on the semiconductor fabrication 100 to activate the dopants in the source / drain structures 134N and 134P.

[0060] Figures 3G-1, 3G-2, and 3G-3 are diagrams of a semiconductor structure 100 after the formation of a contact etch stop layer 136 and an interlayer dielectric layer 138 in some embodiments of the present invention. The contact etch stop layer 136 is formed on the semiconductor structure 100 to cover the source / drain structures 134N and 134P, as shown in some embodiments of Figures 3G-1, 3G-2, and 3G-3. In some embodiments, the contact etch stop layer 136 may be further formed along the sidewalls of the gate spacer layer 118 and the fin spacer layer 120, as well as the exposed surfaces of the isolation structure 110 and the dielectric isolation structure 132, to cover the aforementioned surfaces.

[0061] In some embodiments, the contact etch stop layer 136 is composed of a dielectric material such as silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, oxygen-doped silicon carbide, oxygen-doped silicon carbonitride, or a combination thereof. In some embodiments, the dielectric material used for the contact etch stop layer 136 can be deposited conformally on the semiconductor structure 100, and the deposition method can be chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, or high aspect ratio process), atomic layer deposition, another suitable method, or a combination thereof.

[0062] Subsequently, an interlayer dielectric layer 138 is formed on the contact etch stop layer 136, as shown in some embodiments of FIG3G-1, 3G-2, and 3G-3. In some embodiments, the interlayer dielectric layer 138 overfills shallow trenches to isolate the space between the recess and the dummy gate structure 112. In some embodiments, the interlayer dielectric layer 138 is composed of a dielectric material such as undoped silicate glass, doped silica (such as borosilicate glass, fluorosilicone glass, phosphosilicone glass, borosilicate glass, and / or another suitable dielectric material).

[0063] In some embodiments, the deposition method for the dielectric material used in the interlayer dielectric layer 138 may employ chemical vapor deposition (such as high-density plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), another suitable technique, or a combination thereof. In some embodiments, processes such as chemical mechanical polishing are used to remove the dielectric material of the contact etch stop layer 136 and the interlayer dielectric layer 138 above the upper surface of the dummy gate layer 116. In some embodiments, the patterned hard mask layers 111 and 113 may also be removed.

[0064] Figures 3H-1, 3H-2, and 3H-3 are diagrams of the semiconductor structure 100 after the gate dicing opening 140A is formed in some embodiments of the present invention. A patterning process is performed on the semiconductor structure 100 to form the gate dicing opening 140A through the dummy gate structure 112, as shown in some embodiments of Figures 3H-1 and 3H-3. The gate dicing opening 140A cuts the dummy gate structure 112 into a plurality of dummy gate portions 112A, as shown in some embodiments of Figure 3H-3.

[0065] In some embodiments, the patterning process includes forming a patterned mask layer (not shown) on the semiconductor structure 100. In some embodiments, the patterned mask layer may be a patterned photoresist layer and / or a patterned hard mask layer. In some embodiments, the patterned mask layer has a trench pattern directly located on the isolation structure 110 between the active regions 104. In some embodiments, the trench pattern extends in the X direction and crosses one or more dummy gate structures 112. The trench pattern may also be considered as a cleaved polysilicon gate pattern. In some embodiments, the width of the trench pattern in the Y direction is smaller than the space S2 between the active regions 104 2 and 104 3.

[0066] In some embodiments, the patterning process further includes employing a patterned mask layer and performing an etching process on the semiconductor fabrication 100. In some embodiments, the etching process may include anisotropic etching steps and isotropic etching steps. The anisotropic etching step may be dry plasma etching. In some embodiments, the isotropic etching step may vertically etch a portion of the dummy gate layer 116 exposed from the trench pattern to form an opening between the active regions 104. In some embodiments, the opening is narrower than the space S2 between the active regions 104 2 and 104 3. In some embodiments, the anisotropic etching step is performed until the opening extends to the upper surface of the isolation structure 110. The patterned mask layer may be removed during the etching process and / or by additional removal processes (such as ashing, etching, or wet stripping processes).

[0067] The isotropic etching step slightly etches portions of the gate spacer layer 118, the contact etch stop layer 136, and the interlayer dielectric layer 138 exposed from the trench pattern to form an opening 140B, as shown in some embodiments of FIG3H-1 and 3H-2. In some embodiments, due to the difference in etch selectivity between the dummy gate layer 116 and the dielectric layer, the opening 140B does not extend between the source / drain structures 134N and 134P. In some other embodiments, the opening 140B may extend between the source / drain structures 134N and 134P.

[0068] In some embodiments, an isotropic etching process is then performed to laterally etch a portion of the dummy gate layer between and immediately adjacent to the active regions 1042 and 1043 from the opening. The opening may be laterally enlarged to form a gate dicing opening 140A, as shown in some embodiments of FIG3H-1 and 3H-3. The isotropic etching process may be dry chemical etching, distal plasma etching, wet chemical etching, and / or a combination thereof. In some embodiments, the isotropic etching process is performed until the dummy gate dielectric layer 114 along the sidewalls of the active regions 1042 and 1043 is exposed.

[0069] In some embodiments, due to differences in etching selectivity, the isotropic etching process substantially does not etch the dummy gate dielectric layer 114, the gate spacer layer 118, the contact etch stop layer 136, and the interlayer dielectric layer 138. The width of the upper portion of the gate dicing opening 140A above the active region 104 in the Y direction may be greater than the width of the lower portion of the gate dicing opening 140A between the active regions 104, as shown in some embodiments of FIG3H-1 and 3H-3.

[0070] FIG3I-1 is a diagram of the semiconductor structure 100 after removing the dummy gate dielectric layer 114 and forming the semiconductor structure 142 in some embodiments of the present invention. FIG3I-2 is a plan view along section line AA of FIG3I-1. In some embodiments, an etching process is used to remove a portion of the dummy gate dielectric layer 114 exposed from the gate dicing opening 140A, as shown in some embodiments of FIG3I-1. In some embodiments, active regions 104 2 and 104 3 are exposed from the gate dicing opening 140A. The etching process may be anisotropic etching process (such as dry plasma etching), isotropic etching process (such as dry chemical etching, far-end plasma etching, or wet chemical etching), or a combination thereof.

[0071] In some embodiments, the edge of the dummy gate portion 112A terminates on the upper surfaces of the active regions 1042 and 1043. In some embodiments, the gate cutting opening 140A is self-aligned at the location of the dummy gate structure 112 between the active regions 1042 and 1043 to achieve a minimized end cap size.

[0072] The semiconductor structure 142 is selectively grown on the sidewalls of the second semiconductor layer 108 exposed in the active regions 104 2 and 104 3 of the gate dicing opening 140A, and the growth method employs an epitaxial growth process, as shown in some embodiments of FIG3I-1 and 3I-2. In some embodiments, the semiconductor structure 142 is also grown on the exposed sidewalls at the top of the lower fin unit 104L. The semiconductor structure 142 is sandwiched in the gate spacer layer 118, as shown in some embodiments of FIG3I-2. The epitaxial growth process may be molecular beam epitaxy, metal-organic chemical vapor deposition, vapor phase epitaxy, another suitable technique, or a combination thereof.

[0073] In some embodiments, semiconductor structure 142 is configured as a portion of the channel layer of the final semiconductor device. In some embodiments, the thickness T4 (e.g., dimension in the Y direction) of semiconductor structure 142 is about 2 nm to about 20 nm. In some embodiments, the semiconductor structure grown on the dummy gate layer 116 is designated as semiconductor structure 143. In some embodiments, the masking layer 109 and the exposed surfaces of the first semiconductor layer 106 of the active regions 104 2 and 104 3 remain exposed.

[0074] In some embodiments, the semiconductor structure 142 is composed of a semiconductor material such as silicon or silicon-germanium. In some embodiments, the semiconductor structure 142 and the second semiconductor layer 108 are composed of the same material and have the same composition. In one embodiment, the semiconductor structure 142 and the second semiconductor layer 108 are composed of pure silicon or substantially pure silicon. In one embodiment, the semiconductor structure 142 and the second semiconductor layer 108 are composed of silicon-germanium with the same germanium concentration.

[0075] In some other embodiments, the semiconductor structure 142 and the second semiconductor layer 108 have different compositions, such as silicon germanium with different germanium concentrations. Although Figures 3I-1 and 3I-2 show the interface between the semiconductor structure 142 and the second semiconductor layer 108, there may be no interface between the semiconductor structure 142 and the second semiconductor layer 108.

[0076] FIG3J is a diagram of the semiconductor fabrication 100 after the formation of the wall structure 144 in some embodiments of the present invention. The wall structure 144 is formed in the gate dicing opening 140A, as shown in some embodiments of FIG3J. In some embodiments, the method of forming the wall structure 144 includes conformally depositing a dielectric pad layer 146 along the semiconductor fabrication 100 to partially fill the gate dicing opening 140A, depositing a dielectric substrate layer 148 on the dielectric pad layer 146 to overfill the gate dicing opening 140A, and planarizing the dielectric pad layer 146 and the dielectric substrate layer 148. In some embodiments, the wavy dielectric pad layer 146 extends vertically along the sidewalls of the active regions 104 2 and 104 3.

[0077] The dielectric pad layer 146 and the dielectric substrate layer 148 are composed of materials with low dielectric constants (e.g., less than 7.9), such as silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, oxygen-doped silicon carbide, oxygen-doped silicon carbonitride, or another suitable dielectric material. In some embodiments, the dielectric pad layer 146 and the dielectric substrate layer 148 are composed of different materials and have different dielectric constants. For example, the dielectric pad layer 146 is composed of silicon oxide, while the dielectric substrate layer 148 is composed of silicon nitride. In some embodiments, the dielectric constant of the dielectric pad layer 146 is lower than that of the dielectric substrate layer 148. In some embodiments, the etch resistance of the dielectric substrate layer 148 is higher than that of the dielectric pad layer 146.

[0078] In some embodiments, the deposition process may be atomic layer deposition, chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, or high-density plasma chemical vapor deposition), or a combination thereof. In some embodiments, the planarization process may be chemical mechanical polishing or etch-back. In some embodiments, the planarization process is performed until the upper surface of the dummy gate layer 116 is exposed. In some embodiments, the dielectric pad layer 146 has a dimension in the Y direction, such as a thickness T5, that is less than 5 nm, for example, 2 nm to 5 nm.

[0079] Figure 3K is a diagram of the semiconductor structure 100 after the gate trench 150 is formed. The dummy gate layer 116 of the dummy gate structure 112 and the semiconductor structure 143 are removed using an etching process to form the gate trench 150, as shown in some embodiments of Figure 3K. In some embodiments, the etching process is performed until the dummy gate dielectric layer 114 is exposed. In some embodiments, the etching process may be an anisotropic etching process (such as dry plasma etching), an isotropic etching process (such as dry chemical etching, far-end plasma etching, or wet chemical etching), or a combination thereof.

[0080] Figure 3L is a diagram of the semiconductor structure 100 after the dummy gate dielectric layer 114 has been removed. The dummy gate dielectric layer 114 of the dummy gate structure 112 can be removed by an etching process until the channel region of the active region 104 is exposed, as shown in some embodiments of Figure 3L. In some embodiments, the etching process can be anisotropic etching process (such as dry plasma etching), isotropic etching process (such as dry chemical etching, far-end plasma etching, or wet chemical etching), or a combination thereof.

[0081] Figures 3M-1 and 3M-2 are diagrams of the semiconductor structure 100 after the first semiconductor layer 106 has been removed. In some embodiments, an etching process is performed on the first semiconductor layer 106 of the active region 104 to form a gap 152, as shown in some embodiments of Figures 3M-1 and 3M-2. The etching process includes anisotropic etching processes (such as dry plasma etching), isotropic etching processes (such as dry chemical etching, distal plasma etching, or wet chemical etching), or combinations thereof. In some embodiments, the inner spacer layer 128 may protect the source / drain structures 134N and 134P from damage. In some embodiments, the gap 152 exposes the inner spacer layer 128's sidewall facing the channel region. In some embodiments, the gate trench 150 exposes the gate spacer layer 118's sidewall facing the channel region.

[0082] After the etching process, the three main surfaces of the second semiconductor layer 108 are exposed, as shown in some embodiments of FIG3M-2. The semiconductor structure 142 maintains coverage over the other main surfaces of the second semiconductor layer 108 facing the wall structure 144. Each second semiconductor layer 108 is bonded to an adjacent corresponding semiconductor structure 142 to form a nanostructure 154, as shown in some embodiments of FIG3M-2.

[0083] In some embodiments, the nanostructures 154 are vertically stacked on the lower fin unit 104L and spaced apart from each other. In some embodiments, the nanostructures 154 serve as a channel layer for the final semiconductor device (such as a nanostructured transistor, for example, a fully wound gate transistor). The method of forming the semiconductor structure 142 can increase the effective channel width, which can increase the transistor current in the on state, thereby promoting the performance of the final semiconductor device, such as DC performance.

[0084] Figure 3N-1 is a diagram of the semiconductor structure 100 after the trimming process. Figure 3N-2 is an enlarged view of Figure 3N-1, showing details of the semiconductor structure 142 and adjacent components. A first trimming process is performed to laterally remove the dielectric substrate layer 146, as shown in some embodiments of Figures 3N-1 and 3N-2. The first trimming process may include isotropic etching processes, such as dry chemical etching, distal plasma etching, wet chemical etching, or a combination thereof. In some embodiments, the first trimming process is performed until the dielectric substrate layer 148 is exposed.

[0085] In some embodiments, the portion of the dielectric pad layer 146 retained between the nanostructure 154 and the dielectric substrate layer 148 can be considered as dielectric structure 146A. In some embodiments, dielectric structure 146A is also located between the masking layer 109 and the dielectric substrate layer 148. In some embodiments, the portion of the dielectric pad layer 146 retained between the isolation structure 110 and the dielectric substrate layer 148 can be considered as dielectric structure 146B.

[0086] In some embodiments, the first trimming process further vertically recesses the dielectric structure 146A from the top and bottom sides. As a result, the space 155 created by the first trimming process is located directly between the inner sidewall (facing wall structure 144) of the second semiconductor layer 108 and the dielectric substrate layer 148, as shown in some embodiments of FIG3N-2. The gate dielectric layer can be filled into the space 155, which helps improve gate control capability on the transistor's channel layer without increasing the size of the end cap.

[0087] In some embodiments, a second trimming process may be performed to shape the nanostructure 154 into the desired profile. For example, sharp corners of the second semiconductor layer 108 may be shaped into rounded corners, as shown in some embodiments of Figures 3N-1 and 3N-2. The second trimming process may include isotropic etching processes, such as dry chemical etching, distal plasma etching, wet chemical etching, or combinations thereof. In some embodiments, the thickness T2' of the trimmed second semiconductor layer 108 is less than the thickness T2 because the second etching process consumes the second semiconductor layer 108.

[0088] In some embodiments, the upper surface of each dielectric structure 146A is lower than the upper surface 108T of the corresponding second semiconductor layer 108. The lower surface of each dielectric structure 146A is higher than the lower surface 108B of the corresponding second semiconductor layer 108, as shown in some embodiments of FIG3N-2. In some embodiments, the dimension of the dielectric structure 146A in the Z direction is smaller than the thickness T2' of the corresponding second semiconductor layer 108.

[0089] In some embodiments, the second trimming process also recesses the semiconductor structure 142. The dimensions of the trimmed semiconductor structure 142 in the Z direction can gradually decrease toward the dielectric structure 146A. In some embodiments, the second trimming process can increase the space 155. This can further improve the gate control capability on the channel layer of the transistor.

[0090] In some embodiments, the upper surface (or the lowest point of the upper surface) of the dielectric structure 146A is separated from the upper surface 108T of the second semiconductor layer 108 by a distance D1. In some embodiments, the lower surface (or the highest point of the lower surface) of the dielectric structure 146A is separated from the lower surface 108B of the second semiconductor layer 108 by a distance D1'. In some embodiments, the distances D1 and D1' are less than about 2 nm, for example, from 0.5 nm to about 2 nm. If the distances D1 and D1' are too small, the gate control capability may not be sufficiently improved. If the distances D1 and D1' are too large, the total cell capacitance may increase. The values ​​of the distances D1 and D1' may depend on the application of the final semiconductor device.

[0091] In some embodiments, the upper surface of each dielectric structure 146A is substantially flush with the upper surface 108T of the corresponding second semiconductor layer 108 (i.e., D1=0), and the lower surface of each dielectric structure 146A is substantially flush with the lower surface 108B of the corresponding second semiconductor layer 108 (i.e., D1'=0).

[0092] In some embodiments, the trimmed semiconductor structure 142 maintains direct contact with the dielectric structure 146A. In some embodiments, after the first trimming process and the second trimming process, the semiconductor structure 142 maintains a thickness T4 in the Y direction, while the dielectric structure 146A maintains a thickness T5 in the Y direction. In some other embodiments, the etching amount of the first trimming process and / or the etching amount of the second trimming process may be increased to separate the trimmed semiconductor structure 142 and the dielectric structure 146A. In other embodiments, the first trimming process may completely remove the dielectric structure 146A.

[0093] Figure 30 is a diagram of the semiconductor structure 100 after the formation of the interface layer 156, the gate dielectric layer 158, and the metal gate layer. In some embodiments, the interface layer 156 is formed on the exposed surface of the nanostructure 154 and the exposed surface of the lower fin unit 104L. In some embodiments, the interface layer 156 covers the nanostructure 154. In some embodiments, the interface layer 156 is composed of chemically formed silicon oxide. In some embodiments, the interface layer 156 is nitrogen-doped silicon oxide. In some embodiments, the method of forming the interface layer 156 employs one or more cleaning processes, such as those comprising ozone, ammonium hydroxide and a mixture of hydrogen peroxide and water, and / or a mixture of hydrogen chloride and hydrogen peroxide and water. In some embodiments, the semiconductor material of the second semiconductor layer 108, the semiconductor structure 142, and the lower fin unit 104L is oxidized to form the interface layer 156.

[0094] In some embodiments, the gate dielectric layer 158 is compliantly formed along the interface layer 156 to encapsulate the nanostructure 154 and the masking layer 109. In some embodiments, the gate dielectric layer 158 is also compliantly formed along the sidewall of the gate spacer layer 118 facing the channel region. In some embodiments, the gate dielectric layer 158 is also compliantly formed along the sidewall of the inner spacer layer 128 facing the channel region. Furthermore, the gate dielectric layer 158 is also compliantly formed along the sidewall of the wall structure 144.

[0095] In some embodiments, the gate dielectric layer 158 fills the space 155 and directly contacts the dielectric structures 146A and 146B and the dielectric substrate layer 148. In this way, in some embodiments, the gate dielectric layer 158 can be closer to the inner surface of the second semiconductor layer 108 (facing the wall structure 144). This improves the gate control capability on the transistor's channel layer, which can mitigate the short-channel effect.

[0096] The gate dielectric layer 158 may be a dielectric layer with a high dielectric constant. In some embodiments, the dielectric layer with a high dielectric constant is a dielectric material having a high dielectric constant (e.g., greater than 10, such as greater than 20 or greater than 30). In some embodiments, the dielectric layer with a high dielectric constant includes hafnium oxide, titanium dioxide, hafnium zirconium oxide, tantalum trioxide, hafnium silicate, zirconium dioxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, zirconium oxide, titanium oxide, yttrium pentoxide, strontium titanate, barium titanate, barium zirconium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, barium strontium titanate, combinations thereof, or another suitable material. The deposition method of the dielectric layer with a high dielectric constant may employ atomic layer deposition, physical vapor deposition, chemical vapor deposition, and / or another suitable technique.

[0097] In some embodiments, a metal gate layer is formed to overfill the remaining portion of the gate trench 150 and the gap 152. In some embodiments, the metal gate layer is composed of various conductive materials, such as a p-type work function layer 162P, an n-type work function layer 162N, a capping layer 164, a barrier layer 166, and a metal filler layer 168, as shown in FIG30.

[0098] In some embodiments, a p-type work function layer 162P is formed on a gate dielectric layer 158 in an n-type well. In some embodiments, an n-type work function layer 162N is formed on both the gate dielectric layer 158 in the p-type well and the p-type work function layer 162P in the n-type well. Patterning processes (including photolithography and etching processes) can be performed on the p-type work function layer 162P to remove the p-type work function layer 162P from the p-type well. In some embodiments, the p-type work function layer 162P and the n-type work function layer 162N have selected work functions to improve the device performance (e.g., threshold voltage) of the n-channel field-effect transistor or the p-channel field-effect transistor. For example, the p-type work function layer 162P is composed of titanium nitride, tungsten nitride, tungsten carbonitride, tantalum nitride, ruthenium, cobalt, tungsten, or another suitable p-type work function metal. The n-type work function layer 162N is composed of titanium, silver, aluminum, titanium aluminum, titanium aluminum nitride, titanium aluminum carbide, tantalum aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, tantalum aluminum carbide, manganese, zirconium, or another suitable n-type work function metal.

[0099] The capping layer 164 protects the n-type work function layer 162N from oxidation, and its composition may be silicon, titanium, or metal nitrides such as titanium nitride or silicon-doped titanium nitride. The barrier layer 166 may be composed of titanium, titanium nitride, tantalum, or tantalum nitride. The metal filler layer 168 may be composed of tungsten, cobalt, or ruthenium. The deposition methods for these gate materials may include atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or another suitable technique.

[0100] Due to the formation of the masking layer 109, the gate material around the topmost nanostructure 154 and the gate material around the lower nanostructure 154 can have similar settings and profiles, which can reduce the performance (such as threshold voltage) variation of the final semiconductor device.

[0101] Figures 3P-1 and 3P-2 are diagrams of the semiconductor structure 100 after a planarization process. Planarization processes such as chemical mechanical polishing can be performed on the semiconductor structure 100 to remove material from the gate dielectric layer 158 and the metal gate layer above the upper surface of the interlayer dielectric layer 138 and the upper surface of the wall structure 144, as shown in some embodiments of Figures 3P-1 and 3P-2. The interface layer 156, the gate dielectric layer 158, and the gate material (including a p-type work function layer 162P, an n-type work function layer 162N, a capping layer 164, a barrier layer 166, and a metal filler layer 168) are combined to form a final gate stack 170, as shown in some embodiments of Figures 3P-1 and 3P-2. In some embodiments, the final gate stack 170 covers the nanostructure 154. In some embodiments, the final gate stack 170 includes gate portions 170A and 170B, which are physically and electrically isolated from each other via a wall structure 144.

[0102] The final gate stack 170 connects the channel region, allowing current to flow between the source / drain structures 134N and 134P during operation. In some embodiments, the gate portion 170A of the nanostructure 154 can be combined with the adjacent source / drain structure 134N to form an n-type channel nanostructure transistor (an n-type metal-oxide-semiconductor field-effect transistor as shown in FIG2) in a p-type well. In some embodiments, the gate portion 170B of the nanostructure 154 can be combined with the adjacent source / drain structure 134P to form a p-type channel nanostructure transistor (a p-type metal-oxide-semiconductor field-effect transistor as shown in FIG2) in an n-type well.

[0103] Figures 3Q-1, 3Q-2, and 3Q-3 are diagrams of the semiconductor structure 100 after the gate dicing structure 172 is formed. Figure 3Q-4 is an enlarged view of Figure 3Q-3, showing more details of the semiconductor structure 142 and adjacent components. Figure 3Q-5 is a plan view along section line AA of Figure 3Q-1. The gate dicing structure 172 passes through the final gate stack 170, the gate spacer layer 118, the interlayer dielectric layer 138, and the contact etch stop layer 136, as shown in some embodiments of Figures 3Q-2 and 3Q-3. The final gate stack 170 is further diced by the gate dicing structure 172 into a plurality of gate portions 170A1, 170A2, 170B1, and 170B2, which can be physically and electrically isolated from each other, as shown in some embodiments of Figure 3Q-3. The gate dicing structure 172 can also be viewed as dicing a metal gate pattern.

[0104] The gate cleaving structure 172 is composed of a low dielectric constant dielectric material (its dielectric constant is less than 7.9), such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, oxygen-doped silicon carbonitride, silicon oxide, or a combination thereof. In some embodiments, the gate cleaving structure 172 includes a dielectric material with a dielectric constant greater than 7.9, such as lanthanum oxide, aluminum oxide, aluminum oxynitride, zirconium oxide, hafnium oxide, zinc oxide, zirconium nitride, aluminum zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, tantalum carbonitride, or a combination thereof.

[0105] In some embodiments, the method of forming the gate dicing structure 172 includes patterning the semiconductor structure 100 using photolithography and etching processes to form a gate dicing opening, and depositing a dielectric material to overfill the gate dicing opening. In some embodiments, the gate dicing opening may extend into the isolation structure 110. A planarization process (such as chemical mechanical polishing, etch-back process, or a combination thereof) is then performed on the dielectric material, the final gate stack 170, the gate spacer layer 118, the contact etch stop layer 136, and the interlayer dielectric layer 138 until the masking layer 109 is exposed, as shown in some embodiments of FIG3Q-3.

[0106] Because the dicing process of the final gate stack 170 may cause changes in the transistor's critical voltage, the consistency of the stacking and / or critical dimensions required for the photolithography process used to form the gate dicing structure 172 (dicing the metal gate pattern) is relatively high. On the other hand, since the wall structure 144 (dicing the polycrystalline gate pattern) is formed before forming the final gate stack 170, and the wall structure 144 is self-aligned with the position of the dummy gate structure 112 between the active regions 104, the method of forming the wall structure 144 is less limited by the stacking and / or critical dimension requirements of the photolithography process. Therefore, forming the wall structure 144 is beneficial to reducing the space S2 between the active regions 104 2 and 104 3, thus helping to reduce the cell height of the cell region.

[0107] Furthermore, the wall structure 144 can achieve a smaller end cap size, thus minimizing the overlap between the source / drain structures 134N and 134P and the final gate stack 170. This reduces the total cell capacitance of the final semiconductor device and improves its performance, such as speed. In some embodiments, the total cell parasitic capacitance can be reduced by about 10% to about 15%, and the power efficiency can be increased by about 10% to about 20%.

[0108] Due to the formation of the interface layer 156, the thickness T2" of the nanostructure 154 is less than the thickness T2', as shown in some embodiments of FIG3Q-4. In some embodiments, a portion of the gate dielectric layer 158 extends above the upper surface of the nanostructure 154 and has a lowermost point 158A1. In some embodiments, the lowermost point 158A1 is located directly between the inner sidewall (facing the wall structure 144) of the second semiconductor layer 108 and the dielectric substrate layer 148. In some embodiments, a portion of the gate dielectric layer 158 extends below the lower surface of the nanostructure 154 and has a apex 158B1. In some embodiments, the apex 158B1 is located directly between the inner sidewall (facing the wall structure 144) of the second semiconductor layer 108 and the dielectric substrate layer 148. In this way, the gate dielectric layer 158 can be closer to the inner surface of the second semiconductor layer 108, thus further improving the gate control capability on the channel layer of the transistor.

[0109] In some embodiments, the lowest point 158A1 is below the upper surface 108T of the second semiconductor layer 108 and is separated from the upper surface 108T by a distance D2. In some embodiments, the highest vertex 158B1 is above the lower surface 108B of the second semiconductor layer 108 and is separated from the lower surface 108B by a distance D2'. In some embodiments, distances D2 and D2' are less than about 2 nm, for example, about 0.5 nm to about 2 nm. If distances D2 and D2' are too small, gate control capability may not be adequately improved. If distances D2 and D2' are too large, parasitic capacitance may be increased. The values ​​of distances D2 and D2' may depend on the application of the final semiconductor device. Although Figures 3Q-4 show the interface between the interface layer 156 and the dielectric structure 146A, there may be no interface between the interface layer 156 and the dielectric structure 146A.

[0110] In some embodiments, the second semiconductor layer 108 can also be considered as the substrate portion of the nanostructure 154, and the semiconductor structure 142 can also be considered as a protrusion of the nanostructure 154. The substrate portion, such as the sidewalls 108S1 and 108S2 of the second semiconductor layer 108, extends in the Y direction and is adjacent to the source / drain structure 134N (or 134P), as shown in some embodiments of FIG3Q-5. In some embodiments, the substrate portion, such as the sidewall 108S3 of the second semiconductor layer 108, extends in the X direction and is adjacent to the gate portion 170A1 (or 170B1). In some embodiments, the substrate portion, such as the sidewall 108S4 of the second semiconductor layer 108, extends in the X direction and faces the wall structure 144, and the protrusion of the nanostructure 154, such as the semiconductor structure 142, protrudes from the sidewall 108S4 toward the wall structure 144. In some embodiments, the protrusion, such as the semiconductor structure 142, is sandwiched between the gate spacer layers 118. The protrusions of the nanostructure 154, such as the semiconductor structure 142, can increase the effective channel width, which can increase the transistor's turn-on current and thus improve the performance of the final semiconductor device. In some embodiments, the DC performance can be increased by about 1% to about 10%.

[0111] It should be understood that subsequent complementary metal-oxide-semiconductor processes can be performed on the semiconductor fabrication 100 to form various structures such as multilayer interconnect structures (such as contact plugs, conductive vias, metal lines, inter-metal dielectric layers, passivation layers, or the like) on the semiconductor fabrication.

[0112] Figures 4A and 4B show adjustments to the semiconductor structures of Figures 3N-2 and 3Q-4 in some embodiments. The embodiments of Figures 4A and 4B are similar to those of Figures 3A to 3Q-5, except that the dielectric structure 146A completely removes the dielectric pad layer in the first trimming process, as shown in Figure 4A. In some embodiments, a gap 202 is formed between the semiconductor structure 142 and the dielectric substrate layer 148. In some embodiments, the dimension D3 of the gap 202 in the Y direction is less than 5 nm, for example, 2 to 5 nm. The dimension D3 can also be considered as the end cap dimension. If the dimension D3 is too large, it may increase the cell capacitance. A gate dielectric layer 158 is formed to fill the gap 202, as shown in some embodiments of Figure 4B. Therefore, the gate dielectric layer 158 covers the nanostructure 154 along the four main surfaces of the nanostructure 154, thus significantly improving gate control capability.

[0113] Figure 5 shows an adjustment of the semiconductor structure of Figure 3Q-4 in some embodiments. The embodiment of Figure 5 is similar to the embodiments of Figures 3A to 3Q-5, except that the etching amount of the first trimming process is increased and / or the etching amount of the second trimming process is increased, and the dielectric structure 146A of the dielectric pad layer is separated from the semiconductor structure 142, as shown in Figure 5. In some embodiments, the gate dielectric layer 158 includes a portion extending between the semiconductor structure 142 and the dielectric structure 146A of the dielectric pad layer.

[0114] Figures 6A to 6D are cross-sectional views of various intermediate stages in forming the semiconductor structure 100 of Figure 2 in some embodiments of the present invention. Figures 6A to 6C correspond to the cross-section Y2-Y2 of Figure 2, and Figure 6D corresponds to the cross-section Y4-Y4 of Figure 2. The embodiments of Figures 6A to 6D are similar to the embodiments of Figures 3A to 3Q-5, except that the semiconductor structure 142 is not formed on the lower fin unit 104L.

[0115] After etching a portion of the dummy gate dielectric layer 114 exposed from the gate dicing opening 140A, a portion 114A of the dummy gate dielectric layer 114 remains on the upper surface of the isolation structure 110, as shown in some embodiments of FIG6A. In some embodiments, the retained portion 114A covers the top sidewall of the lower fin unit 104L. In some embodiments, a semiconductor structure 142 may then be selectively grown on the sidewall of the second semiconductor layer 108.

[0116] Perform the steps described above in Figures 3J to 3M to form a wall structure 144 in the gate dicing opening 140A, and remove the dummy gate structure 112 and the first semiconductor layer 106, as shown in some embodiments of Figure 6B. Perform the steps described above in Figure 3N to trim the dielectric pad layer 146, and trim the nanostructure 154 as needed, as shown in some embodiments of Figure 6C. Perform the steps described above in Figures 3O to 3Q-3 to form the final gate stack 170 and the gate dicing structure 172, as shown in some embodiments of Figure 6D.

[0117] In some embodiments, the semiconductor structure 142 is not formed on the top sidewall of the lower fin unit 104L, thus not increasing the width (i.e., the dimension in the Y direction) of the lower fin unit. As a result, in some embodiments, the width W1 of the nanostructure 154 is greater than the width W2 of the lower fin unit 104L. Therefore, the risk of leakage current caused by the bottom planar transistor formed by the lower fin unit 104L is not increased, which avoids any degradation in the performance of the final semiconductor device (such as shutdown current).

[0118] Figures 7A and 7B-1 are cross-sectional views of various intermediate stages forming the semiconductor structure 100 of Figure 2 in some embodiments of the present invention. Figure 7A corresponds to section line Y1-Y1 of Figure 2, and Figure 7B-1 corresponds to section line Y3-Y3 of Figure 2. Figure 7B-2 is a plan view corresponding to section line AA of Figure 3Q-1. The embodiments of Figures 7A and 7B-1 are similar to the embodiments of Figures 3A to 3Q-5, except that the wall structure 144 extends between the source / drain structures 134N and 134P.

[0119] In some embodiments, after forming the interlayer dielectric layer 138, a patterning process is performed using photolithography and etching to form a gate dicing opening 140A through the dummy gate structure 112. In some embodiments, by adjusting the etch selectivity of the anisotropic etching step between the dummy gate layer 116 and the dielectric layer, the trench pattern (dicing polysilicon gate pattern) of the patterned mask layer pattern can be transferred to the gate spacer layer 118, the contact etch stop layer 136, and the interlayer dielectric layer 138. A portion of the trench pattern in the interlayer dielectric layer 138 is designated as an opening 140B, as shown in some embodiments of FIG7A.

[0120] In some embodiments, opening 140B extends between source / drain structures 134N and 134P and extends to isolation structure 110. In some embodiments, gate dicing opening 140A is connected to opening 140B. In some embodiments, the depth of opening 140B is greater than the depth of gate dicing opening 140A. In some embodiments, source / drain structures 134N and 134P are not exposed from opening 140B. In some other embodiments, source / drain structures 134N and 134P may not be exposed from opening 140B. In some embodiments, due to the isotropic etching steps illustrated in Figures 3H-1 to 3H-3, gate dicing opening 140A in the Y direction is wider than opening 140B.

[0121] The steps described above in Figures 3I-1 to 3Q-3 are performed to form a semiconductor structure 142, a wall structure 144, a final gate stack 170, and a gate dicing structure 172, as shown in some embodiments of Figures 7B and 7B-1. The first portion of the wall structure 144 sandwiched between the gate portion 170A1 and the gate portion 170B1 may be wider than the second portion of the wall structure 144 sandwiched between the source / drain structure 134N and the source / drain structure 134P, as shown in some embodiments of Figure 7B-2.

[0122] Figures 8A and 8B-1 are cross-sectional views of various intermediate stages in forming the semiconductor structure 100 of Figure 2 in some embodiments of the present invention. Figure 8A corresponds to section line Y2-Y2 of Figure 2, while Figure 8B-1 corresponds to section line Y4-Y4 of Figure 2. Figure 8B-2 is a plan view corresponding to section line AA of Figure 3Q-1. The embodiments of Figures 8A and 8B-1 are similar to the embodiments of Figures 3A to 3Q-5, except that the semiconductor structure 204 is formed on the second semiconductor layer 108 and the lower fin unit 104L.

[0123] After removing the dummy gate dielectric layer 114 of the dummy gate structure 112, a semiconductor structure 204 can be selectively grown on the sidewall of the second semiconductor layer 108 exposed from the gate trench 150 in the active region 104. The selective growth method can employ an epitaxial growth process, as shown in some embodiments of FIG8A. In some embodiments, the semiconductor structure 204 is also grown on the exposed sidewall of the lower fin unit 104L. The epitaxial growth process can be molecular beam epitaxy, metal-organic chemical vapor deposition, vapor phase epitaxy, another suitable technique, or a combination thereof.

[0124] In some embodiments, the semiconductor structure 204 and the second semiconductor layer 108 are made of the same material and have the same composition. In one embodiment, the semiconductor structure 204 and the second semiconductor layer 108 are composed of pure silicon or substantially pure silicon. In one embodiment, the semiconductor structure 204 and the second semiconductor layer 108 are composed of silicon-germanium with the same germanium concentration. In some other embodiments, the semiconductor structure 204 and the second semiconductor layer 108 have different compositions, such as being composed of silicon-germanium with different germanium concentrations.

[0125] The steps described above in Figures 3M-1 to 3Q-3 are performed to form the final gate stack 170 and gate dicing structure 172, as shown in some embodiments of Figures 8B and 8B-1. In some embodiments, the semiconductor structure 204 is sandwiched between the gate spacer layers 118. The method of forming the semiconductor structure 204 can further increase the effective channel width, which can increase the transistor's turn-on current, thereby improving the performance of the final semiconductor device.

[0126] As described above, the semiconductor fabrication includes a gate stack 170 and a wall structure 144 extending through the gate stack 170. The wall structure 144 is self-aligned and formed at the location of the dummy gate structure 112 between the active regions 104, thus allowing the gate stack 170 to be cut in a manner that minimizes the end cap size. This reduces the total cell capacitance of the final semiconductor device and shrinks the size of the final semiconductor device.

[0127] Furthermore, the semiconductor structure further includes a semiconductor structure 142 grown on the sidewall of the second semiconductor layer 108 facing the wall structure 144. This increases the effective channel width without negatively impacting the filling effect of the final gate stack 170. Therefore, the turn-on current of the final semiconductor device can be increased.

[0128] Embodiments of a semiconductor structure and a method thereof may be provided. The method of forming the semiconductor structure may include etching a dummy gate structure to form an opening exposing the active region, selectively forming the semiconductor structure on a second semiconductor layer of the active region, and forming a wall structure in the opening. This reduces the total unit capacitance of the final semiconductor device, increases the turn-on current of the final semiconductor device, and reduces the size of the final semiconductor device.

[0129] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first fin structure and a second fin structure. Each of the first fin structure and the second fin structure includes an alternating stack of a plurality of first semiconductor layers and a plurality of second semiconductor layers. The method also includes forming a dummy gate structure over the first fin structure and the second fin structure; partially etching the dummy gate structure to form an opening to expose the first fin structure and the second fin structure; selectively forming a plurality of first semiconductor structures on the second semiconductor layers of each of the first fin structure and the second fin structure; and forming a wall structure in the opening.

[0130] In some embodiments, the wall structure includes a dielectric liner layer and a dielectric substrate layer located on the dielectric liner layer, and the dielectric substrate layer and the dielectric liner layer are composed of different materials.

[0131] In some embodiments, the method further includes removing the dummy gate structure; removing the first semiconductor layer of each of the first fin structure and the second fin structure; and at least partially removing the dielectric pad layer of the wall structure to expose the dielectric substrate layer of the wall structure.

[0132] In some embodiments, the method further includes forming a plurality of second semiconductor structures on the second semiconductor layer after removing the dummy gate structure and before removing the first semiconductor layer.

[0133] In some embodiments, the method further includes trimming the second semiconductor layer and the first semiconductor structure.

[0134] In some embodiments, the first fin structure and the second fin structure each include a lower fin unit located below the staggered first semiconductor layer and the second semiconductor layer, and the first semiconductor structure is further formed on the sidewall of the lower fin unit.

[0135] In some embodiments, the method further includes forming a plurality of gate spacer layers on both sides of the dummy gate structure, wherein the openings further expose the gate spacer layers.

[0136] In some embodiments, the first semiconductor structure is located between gate spacer layers.

[0137] In some embodiments, the first fin structure and the second fin structure each include a masking layer located on the stack of the first semiconductor layer and the second semiconductor layer, and the method of forming the semiconductor structure includes: removing the dummy gate structure and the first semiconductor layer; and forming a gate stack to surround the second semiconductor layer and the masking layer.

[0138] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a stack of interleaved first semiconductor layers and a stack of interleaved second semiconductor layers on a substrate; patterning a portion of the stack and the substrate to form an active region; and forming a dummy gate portion on the active region. The method also includes growing a plurality of semiconductor structures on a plurality of first sidewalls of the second semiconductor layers of the active region; forming a wall structure to adjoin the dummy gate portion and the active region; and removing the dummy gate portion and the first semiconductor layer of the active region.

[0139] In some embodiments, the second semiconductor layer of the active region has a plurality of second sidewalls opposite to the first sidewall, and when the semiconductor structure is grown on the first sidewall of the second semiconductor layer of the active region, the second sidewall of the second semiconductor layer of the active region is covered by a dummy gate portion.

[0140] In some embodiments, the wall structure includes a dielectric pad layer and a dielectric substrate layer located on the dielectric pad layer, and the etching selectivity of the dielectric substrate layer is different from the etching selectivity of the dielectric pad layer.

[0141] In some embodiments, the method further includes etching a dielectric pad layer to form a plurality of dielectric structures, wherein the dielectric structures are in direct contact with the semiconductor structure.

[0142] In some embodiments, the method further includes removing the dielectric liner layer; and forming a gate dielectric layer to surround the second semiconductor layer and the semiconductor structure, wherein a portion of the gate dielectric layer extends between the semiconductor structure and the dielectric substrate layer.

[0143] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first group of multiple nanostructures located between a first source / drain structure and a second source / drain structure; a first gate portion surrounding the first group of nanostructures; and a wall structure adjacent to the first gate structure. The first nanostructure in the first group of nanostructures includes a substrate portion and a protruding portion, and in a plan view, the protruding portion protrudes from a first sidewall of the substrate portion toward the wall structure.

[0144] In some embodiments, the semiconductor structure further includes a plurality of gate spacer layers located on both sides of the first gate portion and on both sides of the wall structure, wherein the protrusions of the first nanostructure are sandwiched between the gate spacer layers.

[0145] In some embodiments, the first gate portion includes a dielectric layer with a high dielectric constant, a first portion of the dielectric layer with a high dielectric constant extending on the first nanostructure, and the lowest point of the first portion of the dielectric layer with a high dielectric constant is lower than the upper surface of the substrate layer of the first nanostructure, and a second portion of the dielectric layer with a high dielectric constant extending under the first nanostructure, and the highest point of the second portion of the dielectric layer with a high dielectric constant is higher than the lower surface of the substrate layer of the first nanostructure.

[0146] In some embodiments, the first gate portion includes a dielectric layer with a high dielectric constant, and a portion of the dielectric layer with a high dielectric constant extends between the protrusion of the first nanostructure and the wall structure.

[0147] In some embodiments, the semiconductor structure further includes fin units located below the first group of nanostructures, wherein the first width of the first group of nanostructures is greater than the second width of the fin units; and an isolation structure surrounding the fin units.

[0148] In some embodiments, the semiconductor structure further includes a second group of multiple nanostructures located between the third source / drain structure and the fourth source / drain structure; and a second gate stack surrounding the second group of nanostructures, wherein a first portion of the wall structure is sandwiched between the first gate portion and the second gate portion, a second portion of the wall structure is sandwiched between the first source / drain structure and the third source / drain structure, and the first portion of the wall structure is wider than the second portion of the wall structure.

[0149] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a perspective view of a semiconductor structure in some embodiments of the present invention. Figure 2 is a layout of a semiconductor structure in some embodiments. Figure 3A is a cross-sectional view of an intermediate stage in forming a semiconductor structure in some embodiments. Figure 3B is a cross-sectional view of an intermediate stage in forming a semiconductor structure in some embodiments. Figure 3C is a perspective view of an intermediate stage in forming a semiconductor structure in some embodiments. Figures 3D-1 and 3D-2 are cross-sectional views of an intermediate stage in forming a semiconductor structure in some embodiments. Figures 3E-1 and 3E-2 are cross-sectional views of an intermediate stage in forming a semiconductor structure in some embodiments. Figures 3F-1 and 3F-2 are cross-sectional views of an intermediate stage in forming a semiconductor structure in some embodiments. Figures 3G-1, 3G-2, and 3G-3 are diagrams of an intermediate stage in forming a semiconductor structure in some embodiments. Figures 3H-1, 3H-2, and 3H-3 are diagrams of an intermediate stage in forming a semiconductor structure in some embodiments. Figures 3I-1 and 3I-2 are diagrams of an intermediate stage in forming a semiconductor structure in some embodiments. Figure 3J is a cross-sectional view of an intermediate stage in forming a semiconductor structure in some embodiments. Figure 3K is a cross-sectional view of an intermediate stage in forming a semiconductor structure in some embodiments. Figure 3L is a cross-sectional view of an intermediate stage in forming a semiconductor structure in some embodiments. Figures 3M-1 and 3M-2 are cross-sectional views of an intermediate stage in forming a semiconductor structure in some embodiments. Figure 3N-1 is a cross-sectional view of an intermediate stage in forming a semiconductor structure in some embodiments. Figure 3O is a cross-sectional view of an intermediate stage in forming a semiconductor structure in some embodiments. Figures 3P-1 and 3P-2 are cross-sectional views of an intermediate stage in forming a semiconductor structure in some embodiments. Figures 3Q-1, 3Q-2, 3Q-3, and 3Q-5 are diagrams of an intermediate stage in forming a semiconductor structure in some embodiments. Figure 3N-2 is an enlarged view of the semiconductor structure of Figure 3N-1 in some embodiments, showing more details of the semiconductor structure and adjacent components. Figure 3Q-4 is an enlarged view of the semiconductor structure of Figure 3Q-1 in some embodiments, showing more details of the semiconductor structure and adjacent components. Figures 4A and 4B show adjustments to the semiconductor structures of Figures 3N-2 and 3Q-4 in some embodiments. Figure 5 shows an adjustment to the semiconductor structure of Figure 3Q-4 in some embodiments. Figures 6A to 6D are cross-sectional views of various intermediate stages in forming the semiconductor structure in some embodiments. Figures 7A, 7B-1, and 7B-2 are diagrams of various intermediate stages in forming the semiconductor structure in some embodiments. Figures 8A, 8B-1, and 8B-2 are diagrams of various intermediate stages in forming the semiconductor structure in some embodiments.

Claims

1. A method for forming a semiconductor structure, comprising: A first fin structure and a second fin structure are formed, each comprising an alternating stack of multiple first semiconductor layers and multiple second semiconductor layers; a dummy gate structure is formed over the first and second fin structures; the dummy gate structure is partially etched to form an opening exposing the first and second fin structures; multiple first semiconductor structures are selectively formed on the respective second semiconductor layers of the first and second fin structures; and a wall structure is formed in the opening, wherein the thickness of the first semiconductor structures gradually decreases from the second semiconductor layers toward the wall structure.

2. The method of forming a semiconductor structure as described in claim 1, wherein the wall structure includes a dielectric pad layer and a dielectric substrate layer located on the dielectric pad layer, and the dielectric substrate layer and the dielectric pad layer are composed of different materials.

3. The method for forming a semiconductor structure as described in claim 2 further includes: Remove the dummy gate structure; Remove the first semiconductor layers of the first fin structure and the second fin structure respectively; And at least partially remove the dielectric liner layer of the wall structure to expose the dielectric substrate layer of the wall structure.

4. The method for forming a semiconductor structure as described in claim 3 further includes: After the dummy gate structure is removed and before the first semiconductor layers are removed, a plurality of second semiconductor structures are formed on the second semiconductor layers.

5. A method for forming a semiconductor structure, comprising: A stack of multiple first semiconductor layers and multiple second semiconductor layers, forming an interlaced arrangement, is formed on a substrate; Pattern the stack and a portion of the substrate to form an active region; form a dummy gate portion on the active region; grow a plurality of semiconductor structures on a plurality of first sidewalls of the second semiconductor layers of the active region; form a wall structure adjacent to the dummy gate portion and the active region, wherein the thickness of the semiconductor structures gradually decreases in the direction from the second semiconductor layers toward the wall structure; And remove the dummy gate portion and the first semiconductor layers of the active region.

6. A method for forming a semiconductor structure as described in claim 5, wherein the second semiconductor layers of the active region have a plurality of second sidewalls opposite to the first sidewalls, and when the semiconductor structure is grown on the first sidewalls of the second semiconductor layers of the active region, the dummy gate portion covers the second sidewalls of the second semiconductor layers of the active region.

7. A method of forming a semiconductor structure as described in claim 5 or 6, wherein the wall structure includes a dielectric pad layer and a dielectric substrate layer located on the dielectric pad layer, and the etch selectivity of the dielectric substrate layer is different from the etch selectivity of the dielectric pad layer.

8. A semiconductor structure comprising: A first group of multiple nanostructures located between a first source / drain structure and a second source / drain structure; a first gate portion surrounding the nanostructures of the first group; and a wall structure adjacent to the first gate portion, wherein a first nanostructure among the nanostructures of the first group includes a substrate portion and a protrusion portion, and in a plan view the protrusion portion protrudes from a first sidewall of the substrate portion toward the wall structure, wherein the thickness of the protrusion portion gradually decreases in the direction from the substrate portion toward the wall structure.

9. The semiconductor structure as described in claim 8 further includes: Multiple gate spacer layers are located on both sides of the first gate portion and on both sides of the wall structure, wherein the protruding portion of the first nanostructure is sandwiched between the gate spacer layers.

10. The semiconductor structure as described in claim 9, wherein: The first gate portion includes a high dielectric constant dielectric layer, a first portion of which extends on the first nanostructure, with the lowest point of the first portion below the upper surface of the substrate portion of the first nanostructure, and a second portion of which extends below the first nanostructure, with the highest point of the second portion above the lower surface of the substrate portion of the first nanostructure.

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