Semiconductor memory device and control method thereof

Abstract

The purpose of this invention is to provide a semiconductor memory device and its control method that can suppress the increase in manufacturing costs of external devices. The solution is a semiconductor memory device, including: a calibration circuit that performs ZQ calibration operation; and a resistor unit for serving as a reference resistor in the ZQ calibration operation; in addition, the control method of the semiconductor memory device including the resistor unit for serving as a reference resistor in the ZQ calibration operation includes the step of the calibration circuit of the semiconductor memory device using the resistor unit to perform the ZQ calibration operation.

Description

[Technical Field]

[0001] This invention relates to a semiconductor memory device and its control method. [Previous Technology]

[0002] In conventional semiconductor memory devices, in order to integrate the impedance of the transmission path with the output impedance of the output circuit, a known method is to connect a resistor (external resistor) located outside the semiconductor memory device to the ZQ terminal of the semiconductor memory device and perform ZQ calibration (e.g., Japanese Patent Application Publication No. 2007-123987). [Summary of the Invention]

[0003] In conventional technology, the manufacturing cost of external devices (external systems) that include external resistors may increase because external resistors need to be connected to the ZQ terminals. Furthermore, if the semiconductor memory device has multiple silicon dies (memory dies) such as a dual-die package (DDP), the manufacturing cost of external devices (external systems) that include external resistors may increase further because different external resistors are needed to connect the multiple silicon dies.

[0004] In view of the above problems, the present invention provides a semiconductor memory device and a control method thereof that can suppress the increase in manufacturing cost of external devices.

[0005] In order to solve the above problems, the present invention provides a semiconductor memory device, including: a calibration circuit for performing ZQ calibration operation; and a resistor for serving as a reference resistor in the ZQ calibration operation.

[0006] According to this invention, since the ZQ calibration operation can be performed using a resistor provided on the semiconductor memory device, the need for an external resistor for ZQ calibration on an external device can be eliminated. This reduces the increase in manufacturing cost of the external device due to the provision of an external resistor.

[0007] Furthermore, the present invention provides a control method for a semiconductor memory device, wherein the semiconductor memory device includes a resistor section for serving as a reference resistor in a ZQ calibration operation; the control method for the semiconductor memory device includes the step of the calibration circuit of the semiconductor memory device using the resistor section to perform a ZQ calibration operation.

[0008] The semiconductor memory device and its control method according to the present invention can suppress the increase in manufacturing costs of external devices.

Implementation Method

[0010] Referring to FIG1, the semiconductor memory device 1 is, for example, a Double-Data-Rate4 Synchronous Dynamic Random Access Memory (DDR4 SDRAM) or a Dynamic Random Access Memory (DRAM), and includes one or more memory chips (die) 10. Furthermore, in this embodiment, the semiconductor memory device 1 has a ZQ terminal 20 on each of the one or more memory chips 10. Although FIG1 shows a semiconductor memory device 1 with only one memory chip 10, the semiconductor memory device 1 may include multiple memory chips 10. Furthermore, for the sake of simplicity, other known structures of the semiconductor memory device 1 (e.g., power supply circuits, command decoders, address decoders, clock generators, etc.) are not shown here.

[0011] In this embodiment, the memory chip 10 includes a calibration circuit 11 and a resistor section 12.

[0012] The calibration circuit 11 includes a plurality of P-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) P1 to Pi (i is an integer greater than or equal to 2) and is configured to perform ZQ calibration operations. The source terminal of each P-channel MOSFET P1 to Pi is connected to the operating voltage VDD, and the drain terminal of each P-channel MOSFET P1 to Pi is connected to the resistor section 12 through node N. In addition, the gate terminal of each P-channel MOSFET P1 to Pi is input with a control signal for controlling the ON / OFF control of each P-channel MOSFET P1 to Pi.

[0013] Furthermore, although this embodiment uses the case where the calibration circuit 11 includes multiple P-channel MOSFETs P1 to Pi as an example, the calibration circuit 11 may include multiple N-channel MOSFETs instead of multiple P-channel MOSFETs P1 to Pi, or it may include multiple other transistors, or it may include multiple switching circuits. The calibration operation performed in the calibration circuit 11 will be described later.

[0014] The resistor section 12 is configured to serve as a reference resistor in the ZQ calibration operation. Furthermore, in this embodiment, the resistor section 12 includes resistor units U1 to Uj (j is an integer greater than or equal to 2) connected in parallel with the calibration circuit 11, as shown in FIG2. Therefore, multiple resistor units U1 to Uj can be used to construct the reference resistor in the ZQ calibration operation.

[0015] In this embodiment, each of the multiple resistor units U1 to Uj includes multiple (four in the example shown in Figure 2) series-connected resistors 12a, 12b, a first resistor R1, a second resistor R2, and multiple (three in the example shown in Figure 2) switch sections SW1, SW2, and SW3. Furthermore, the structure of each of the multiple resistor units U1 to Uj is as follows: one end of the Nth (N is an integer greater than 1) switch section SWN is connected to one end of the Nth resistor RN, one end of the (N+1)th switch section SW(N+1) is connected to the other end of the Nth resistor, and the other ends of the Nth switch section SWN and the (N+1)th switch section SW(N+1) are interconnected. Specifically, in the example shown in Figure 2, one end of the first (N=1) switch section SW1 is connected to one end of the first resistor R1, one end of the second switch section SW2 is connected to the other end of the first resistor R1, and the other ends of the first switch section SW1 and the second switch section SW2 are interconnected. In addition, one end of the second (N=2) switch section SW2 is connected to one end of the second resistor R2, one end of the third switch section SW3 is connected to the other end of the second resistor R2, and the other ends of the second switch section SW2 and the third switch section SW3 are connected to each other.

[0016] Furthermore, in this embodiment, although the case in which each of the multiple resistor units U1 to Uj has three switching sections SW1, SW2, and SW3 is described as an example, the number of switching sections provided in each of the multiple resistor units U1 to Uj can be two or less, or four or more. In addition, the number of switching sections provided in each of the multiple resistor units U1 to Uj can be the same or different among the multiple resistor units U1 to Uj.

[0017] Furthermore, in this embodiment, although the case in which each of the multiple resistor units U1 to Uj is provided with four resistors 12a, 12b, a first resistor R1, and a second resistor R2 is used as an example, the number of resistors provided in each of the multiple resistor units U1 to Uj can be three or less, or five or more. In addition, the number of resistors provided in each of the multiple resistor units U1 to Uj can be the same or different among the multiple resistor units U1 to Uj.

[0018] In this embodiment, each of the plurality of resistor units U1 to Uj is configured such that when any one of the plurality of switch sections SW1, SW2, and SW3 becomes in the on state, it has a resistance value corresponding to the switch section in the on state. Specifically, each of the plurality of resistor units U1 to Uj is controlled such that only one of the plurality of switch sections SW1, SW2, and SW3 is in the on state. For example, when the first switch section SW1 of resistor unit U1 is in the on state and the second switch section SW2 and the third switch section SW3 are in the off state, the resistance value of resistor unit U1 is represented by the sum of the resistance values ​​of resistor 12a and resistor 12b. Furthermore, when the second switch section SW2 of resistor unit U1 is in the on state and the first switch section SW1 and the third switch section SW3 are in the off state, the resistance value of resistor unit U1 is represented by the sum of the resistance values ​​of resistor 12a, resistor 12b, and the first resistor R1. Furthermore, when the third switch SW3 of resistor unit U1 is in the ON state, and the first switch SW1 and the second switch SW2 are in the OFF state, the resistance value of resistor unit U1 is represented by the sum of the resistance values ​​of resistor 12a, resistor 12b, first resistor R1, and second resistor R2. Thus, each of the multiple resistor units U1 to Uj can have a different resistance value depending on the ON state of its switch.

[0019] Furthermore, in this embodiment, the plurality of switching sections SW1, SW2, and SW3 are each configured to include a transfer transistor. Therefore, by turning on any one of the P-channel MOSFETs and N-channel MOSFETs constituting the transfer transistor, the transfer transistor can be easily turned on. Although the case where the plurality of switching sections SW1, SW2, and SW3 each include a transfer transistor is described here as an example, it is also possible for at least one of the plurality of switching sections SW1, SW2, and SW3 to include other switching circuits besides the transfer transistor (e.g., a P-channel MOSFET or an N-channel MOSFET).

[0020] Furthermore, each of the multiple resistor units U1 to Uj may include the same resistance value. Therefore, a reference resistor for the ZQ calibration operation can be easily constructed using resistor units U1 to Uj that include the same resistance value. For example, if the resistance value of the resistor section 12 is 240Ω and the number of resistor units is 10, then the resistance value of each resistor unit can be set to 2400Ω.

[0021] Here, referring to FIG3, an example of a method for adjusting the resistance values ​​of multiple resistor units U1 to Uj is described. As shown in FIG3(a), a specific voltage V1 is applied to resistor unit U1, and the other end of each of the switches SW1, SW2, and SW3 is connected to the input terminal of one end (+ side) of comparator C. Furthermore, a specific reference voltage Vref is input to the input terminal of the other end (- side) of comparator C. Moreover, comparator C compares the voltage Vin input to the input terminal of one end (+ side) with the reference voltage Vref input to the input terminal of the other end (- side) and outputs the comparison result as the output voltage Vout. In this embodiment, it is explained that when the output voltage (i.e., voltage Vin) of resistor unit U1 is equal to the reference voltage Vref, resistor unit U1 has the desired resistance value, and the resistance value of resistor unit U1 is adjusted.

[0022] As shown in Figure 3(b), in resistor unit U1, the first switch SW1 is first set to the on state, then the second switch SW2 is set to the on state, and then the third switch SW3 is set to the on state. Then, it is determined which of the multiple switches SW1, SW2, and SW3, when set to the on state, has voltage Vin equal to the reference voltage Vref (in the example shown in Figure 3(b), it is the second switch SW2), and the determined switch is set to the on state, thereby adjusting the resistance value of resistor unit U1. Furthermore, the resistance values ​​of the other resistor units U2 to Uj can be adjusted in the same way.

[0023] Furthermore, depending on process and temperature characteristics, the resistance values ​​of resistors 12a, 12b, first resistor R1, and second resistor R2 provided in the multiple resistance units U1 to Uj may be different in each of the multiple resistance units U1 to Uj. Therefore, when set to the on state, the switching section that makes the input voltage Vin equal to the reference voltage Vref may be different in each of the multiple resistance units U1 to Uj. In addition, in the example shown in FIG3(b), although the example is to first set the first switching section SW1 to the on state, then set the second switching section SW2 to the on state, and then set the third switching section SW3 to the on state, the order of the switching sections set to the on state can be arbitrarily determined (for example, the third switching section SW3 may be set to the on state first, then the second switching section SW2 may be set to the on state, and then the first switching section SW1 may be set to the on state).

[0024] Referring back to Figure 1, the ZQ terminal 20 is a terminal that can be connected to an external resistor used for ZQ calibration operations. Furthermore, since the resistor section 12, which serves as a reference resistor in the ZQ calibration operation, is disposed within the semiconductor memory device 1, the ZQ terminal 20 does not need to include the same structure as in conventional technology (i.e., a structure that can be individually connected to the calibration circuit 11 and the external resistor). In this embodiment, the ZQ terminal 20 is configured to be in a state where it is not connected to the calibration circuit 11 and the resistor section 12.

[0025] In addition, in conventional semiconductor memory devices, besides the ZQ terminal 20, there are also terminals for data input / output (e.g., DQ terminals). Here, the data input / output terminals (pads) need to be sized to allow contact with the probe pins (or probe needles) of the probe card during wafer testing. However, when the size of the data input / output terminals (pad size) increases, the charging and discharging current on the data input / output terminals increases, which may raise concerns about increased power consumption of the semiconductor memory device. Furthermore, in addition to the data output terminals used during normal operation of the semiconductor memory device, it is also possible to consider providing dedicated data output terminals for wafer testing in the semiconductor memory device. However, in this case, since a new dedicated data output terminal for wafer testing needs to be provided in the semiconductor memory device (memory die), there may be concerns about an increase in the size of the semiconductor memory device (memory die).

[0026] Therefore, in this embodiment, the ZQ terminal 20 is configured for data input / output during wafer testing. This eliminates the need to increase the size (pad size) of the data output terminal (DQ terminal) used by the semiconductor memory device 1 during normal operation, thus suppressing an increase in power consumption of the semiconductor memory device 1. Furthermore, since a dedicated data output terminal for wafer testing is not required, an increase in the size of the semiconductor memory device 1 (memory die 10) can be suppressed.

[0027] In this embodiment, the ZQ terminal 20 can be connected to a data input / output circuit (not shown) for transmitting and receiving data signals (DQ) and data strobe signals (DQS, / DQS) with an external device. Furthermore, the ZQ terminal 20 can be sized to contact the probe pins of a probe card during wafer testing. Thus, the data input / output circuit of the semiconductor memory device 1 can transmit and receive data with the probe card via the ZQ terminal 20 during wafer testing, and can transmit and receive data with an external device via the data output terminal (DQ terminal) during normal operation. Additionally, switching of the terminal used for data transmission and reception can be performed, for example, via a switching circuit.

[0028] In addition, although FIG1 shows the case where one ZQ terminal 20 is provided for one memory chip 10, if the semiconductor memory device 1 includes multiple memory chips 10, each of the multiple memory chips 10 may be provided with a ZQ terminal 20, or a common ZQ terminal 20 may be provided in the multiple memory chips 10.

[0029] Referring to FIG4, the calibration operation performed in the calibration circuit 11 of the semiconductor memory device 1 of this embodiment will be explained. In this embodiment, the calibration circuit 11 uses a resistor 12 to perform the calibration operation. In addition, here, the case in which the calibration operation is performed in the calibration circuit 11 when the voltage V of node N in FIG1 is equal to a specific voltage (e.g., VDD / 2) and the impedance between the resistor 12 is integrated will be explained.

[0030] At the start of the calibration operation, multiple P-channel MOSFETs P1 to Pi are each in the off state. First, P-channel MOSFET P1 is turned on, and the voltage V at node N increases. Next, with P-channel MOSFET P1 in the on state, P-channel MOSFET P2 is turned on, and the voltage V at node N increases further. Furthermore, with P-channel MOSFETs P1 and P2 in the on state, P-channel MOSFET P3 is turned on, and the voltage V at node N increases even further. In this way, by sequentially turning on multiple P-channel MOSFETs P1 to Pi until the voltage V at node N equals a specific voltage (e.g., VDD / 2), the calibration operation can be performed. In addition, although Figure 4 shows the calibration operation performed when the voltage V of node N rises to a specific voltage (e.g., VDD / 2), the calibration operation can also be performed when the voltage V of node N drops to a specific voltage (e.g., VDD / 2). That is, each of the multiple P-channel MOSFETs P1 to Pi is set to the on state at the beginning of the calibration operation and is set to the off state in sequence until the voltage V of node N is equal to the specific voltage (e.g., VDD / 2).

[0031] Furthermore, node N of the calibration circuit 11 can be connected to, for example, a terminal (pad) for data signal (DQ) (not shown) or a terminal (pad) for data select signal (DQS, / DQS) (not shown). In this way, the resistance obtained during the calibration operation (that is, the combined resistance of the on-resistance of at least one P-channel MOSFET set to the on state among the plurality of P-channel MOSFETs P1 to Pi) can be set as the output impedance.

[0032] As described above, according to the semiconductor memory device 1 and its control method of this embodiment, since the ZQ calibration operation can be performed using the resistor section 12 provided in the semiconductor memory device 1, the need to provide an external resistor for ZQ calibration in an external device can be eliminated. This suppresses the increase in manufacturing cost of the external device due to the provision of an external resistor.

[0033] The embodiments described above are provided to make the present invention easier to understand and are not intended to limit the present invention. Therefore, the elements disclosed in the above embodiments include all design changes and equivalents within the technical scope of the present invention.

[0034] For example, although the above embodiment uses DRAM as an example of semiconductor memory device, the present invention is not limited thereto. For example, the semiconductor memory device may be SRAM (Static Random Access Memory), pSRAM (pseudo-Static Random Access Memory), flash memory, or other semiconductor memory devices.

[0035] Furthermore, the structures of the calibration circuit 11 and the resistor section 12 shown in Figures 1 and 2 are just examples and can be appropriately modified, or known structures or other various structures can be used. [Simplified Explanation of the Diagram]

[0009] Figure 1 is a schematic diagram of a semiconductor memory device according to an embodiment of the present invention. Figure 2 is a schematic diagram of a resistor unit. Figure 3(a) is a schematic diagram of a structure for adjusting the resistance value of the resistor unit, and Figure 3(b) is an example of a timing diagram of the voltage value corresponding to the resistance value of the resistor unit. Figure 4 is an example of a timing diagram of the output voltage of the calibration circuit during calibration operation.

Claims

1. A semiconductor memory device, comprising: The calibration circuit performs ZQ calibration. The device includes a resistor section for use as a reference resistor in the ZQ calibration operation, wherein the resistor section includes a plurality of resistor units connected in parallel, each of the plurality of resistor units having the same resistance value; a terminal that can be connected to an external resistor for the ZQ calibration operation, and the terminal is used for data input / output in wafer testing; wherein at least one of the plurality of resistor units includes a plurality of switching sections and is configured to have a resistance value corresponding to the switching section in the on state when any of the plurality of switching sections is in the on state.

2. The semiconductor memory device of claim 1, wherein the terminal is not connected to the calibration circuit and the resistor.

3. The semiconductor memory device as claimed in claim 1, comprising: Multiple memory chips; The resistor is located in each of the plurality of memory chips.

4. The semiconductor memory device of claim 1, wherein at least one of the plurality of switching units includes a transmission transistor.

5. The semiconductor memory device of claim 1, wherein the at least one resistive unit comprises: Multiple resistors are connected in series; the Nth switch is connected at one end to one end of the Nth resistor among the multiple resistors, where N is an integer greater than or equal to 1; And the N+1th switch section, one end of which is connected to the other end of the Nth resistor; the other end of the Nth switch section is connected to the other end of the N+1th switch section.

6. The semiconductor memory device as claimed in claim 1, wherein the semiconductor memory device is a dynamic random access memory.

7. A method for controlling a semiconductor memory device, wherein the semiconductor memory device includes a resistor section for use as a reference resistor in a ZQ calibration operation; the method for controlling the semiconductor memory device includes the step of a calibration circuit of the semiconductor memory device using the resistor section to perform the ZQ calibration operation; wherein the semiconductor memory device further includes a terminal that can be connected to an external resistor for the ZQ calibration operation, and the terminal is used for data input / output in wafer testing; wherein the resistor section further includes a plurality of resistor units connected in parallel, each of the plurality of resistor units including the same resistance value; and wherein at least one of the plurality of resistor units includes a plurality of switching sections, and is configured to have a resistance value corresponding to the switching section in the on state when any one of the plurality of switching sections is in an on state.

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