Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a substrate and a capacitor structure. The capacitor structure includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, and a first conductive plug. The first electrode layer is located on the substrate. The first dielectric layer is located on the first electrode layer. The second electrode layer is located on the first dielectric layer. The second dielectric layer is located on the second electrode layer. The third electrode layer is located on the second dielectric layer. The first conductive plug is located between the first electrode layer and the third electrode layer. The first conductive plug is electrically connected to the first electrode layer and the third electrode layer. The bottom surface of the first conductive plug is directly connected to the upper surface of the first electrode layer. The top surface of the first conductive plug is directly connected to the lower surface of the third electrode layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure including a capacitor structure and a method for manufacturing the same. [Previous Technology]

[0002] Capacitors are a type of component widely used in electronic products. However, with the continuous miniaturization of capacitor size, further increasing capacitor capacitance remains a continuous goal. [Summary of the Invention]

[0003] The present invention provides a semiconductor structure and a method for manufacturing the same, which can effectively improve the capacitance of a capacitor structure.

[0004] This invention proposes a semiconductor structure, including a substrate and a capacitor structure. The capacitor structure includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, and a first conductive plug. The first electrode layer is located on the substrate. The first dielectric layer is located on the first electrode layer. The second electrode layer is located on the first dielectric layer. The second dielectric layer is located on the second electrode layer. The third electrode layer is located on the second dielectric layer. The first conductive plug is located between the first electrode layer and the third electrode layer. The first conductive plug is electrically connected to the first electrode layer and the third electrode layer. The bottom surface of the first conductive plug is directly connected to the upper surface of the first electrode layer. The top surface of the first conductive plug is directly connected to the lower surface of the third electrode layer.

[0005] According to an embodiment of the present invention, in the above semiconductor structure, the first dielectric layer may cover the sidewall of the first electrode layer.

[0006] According to an embodiment of the present invention, in the above semiconductor structure, the first dielectric layer may not cover the sidewall of the first electrode layer.

[0007] According to an embodiment of the present invention, the above-described semiconductor structure may further include a wire and a second conductive plug. The wire is located on one side of the third electrode layer. The second conductive plug is located between the second electrode layer and the wire. The second conductive plug is electrically connected to the second electrode layer and the wire.

[0008] According to an embodiment of the present invention, in the above-described semiconductor structure, the bottom surface of the third electrode layer may be lower than the bottom surface of the wire.

[0009] According to an embodiment of the present invention, the above-described semiconductor structure may further include a first conductive wire, a second conductive wire, and a second conductive plug. The first conductive wire is located on one side of the first electrode layer. The second conductive wire is located on the first conductive wire. The second conductive plug is located between the first conductive wire and the second conductive wire. The second conductive plug is electrically connected to the first conductive wire and the second conductive wire.

[0010] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: Providing a substrate. Forming a capacitor structure on the substrate. The capacitor structure includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, and a first conductive plug. The first electrode layer is located on the substrate. The first dielectric layer is located on the first electrode layer. The second electrode layer is located on the first dielectric layer. The second dielectric layer is located on the second electrode layer. The third electrode layer is located on the second dielectric layer. The first conductive plug is located between the first electrode layer and the third electrode layer. The first conductive plug is electrically connected to the first electrode layer and the third electrode layer. The bottom surface of the first conductive plug is directly connected to the upper surface of the first electrode layer. The top surface of the first conductive plug is directly connected to the lower surface of the third electrode layer.

[0011] According to an embodiment of the present invention, in the above-described method for manufacturing a semiconductor structure, the method for forming a capacitor structure may include the following steps: A first electrode material layer is formed on a substrate. The first electrode material layer is patterned to form a first electrode layer. A first dielectric layer is formed on the first electrode layer. A second electrode material layer and a dielectric material layer are sequentially formed on the first dielectric layer. The dielectric material layer and the second electrode material layer are patterned to form a second dielectric layer and a second electrode layer, exposing the first dielectric layer. A third dielectric layer is formed on the first dielectric layer, the second electrode layer, and the second dielectric layer. A first conductive plug is formed in the third dielectric layer and the first dielectric layer. An opening is formed in the third dielectric layer. The opening exposes the second dielectric layer. A third electrode material layer is formed on the third dielectric layer and in the opening. The third electrode material layer is patterned to form a third electrode layer.

[0012] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following steps: A second conductive plug is formed in the third dielectric layer and the second dielectric layer. The second conductive plug is electrically connected to the second electrode layer. A third electrode material layer is patterned to form a wire. The wire is electrically connected to the second conductive plug.

[0013] According to an embodiment of the present invention, in the above-described method for manufacturing a semiconductor structure, the method for forming a capacitor structure may include the following steps: A first electrode material layer, a first dielectric material layer, a second electrode material layer, and a second dielectric material layer are sequentially formed on a substrate. The second dielectric material layer and the second electrode material layer are patterned to form a second dielectric layer and a second electrode layer, exposing the first dielectric material layer. The first dielectric material layer and the first electrode material layer are patterned to form a first dielectric layer and a first electrode layer. A third dielectric layer is formed on the first electrode layer, the first dielectric layer, the second electrode layer, and the second dielectric layer. A first conductive plug is formed in the third dielectric layer and the first dielectric layer. An opening is formed in the third dielectric layer. The opening exposes the second dielectric layer. A third electrode material layer is formed on the third dielectric layer and in the opening. The third electrode material layer is patterned to form a third electrode layer.

[0014] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following steps: A second conductive plug is formed in the third dielectric layer and the second dielectric layer. The second conductive plug is electrically connected to the second electrode layer. A third electrode material layer is patterned to form a wire. The wire is electrically connected to the second conductive plug.

[0015] Based on the above, in the semiconductor structure and manufacturing method of the present invention, the capacitor structure includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, and a first conductive plug. The first dielectric layer is located on the first electrode layer. The second electrode layer is located on the first dielectric layer. The second dielectric layer is located on the second electrode layer. The third electrode layer is located on the second dielectric layer. The first conductive plug is located between the first electrode layer and the third electrode layer. The first conductive plug is electrically connected to the first electrode layer and the third electrode layer. The bottom surface of the first conductive plug is directly connected to the upper surface of the first electrode layer. The top surface of the first conductive plug is directly connected to the lower surface of the third electrode layer. Since the first electrode layer and the third electrode layer can be electrically connected to each other through the first conductive plug, the effective area of ​​the capacitor electrode can be effectively increased, thereby effectively improving the capacitance of the capacitor structure.

[0016] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0018] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be indicated by the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0019] Figures 1A to 1J are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention.

[0020] Referring to FIG1A, a substrate 100 is provided. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 100 may have desired semiconductor elements, dielectric layers and / or interconnect structures, the description of which is omitted here.

[0021] Next, an electrode material layer 102 may be formed on the substrate 100. The electrode material layer 102 may be a single-layer structure or a multi-layer structure. In some embodiments, the electrode material layer 102 may include a barrier material layer 104, a conductive material layer 106, and a barrier material layer 108. The barrier material layer 104 is located on the substrate 100. In some embodiments, the material of the barrier material layer 104 is, for example, titanium nitride. In some embodiments, the barrier material layer 104 is formed by, for example, physical vapor deposition or chemical vapor deposition. The conductive material layer 106 is located on the barrier material layer 104. In some embodiments, the material of the conductive material layer 106 is, for example, aluminum. In some embodiments, the conductive material layer 106 is formed by, for example, physical vapor deposition. The barrier material layer 108 is located on the conductive material layer 106. In some embodiments, the material of the barrier material layer 108 is, for example, titanium nitride. In some embodiments, the barrier material layer 108 is formed by, for example, physical vapor deposition or chemical vapor deposition.

[0022] Referring to FIG1B, a patterned photoresist layer 110 may be formed on the electrode material layer 102. In some embodiments, the patterned photoresist layer 110 may be formed by a photolithography process.

[0023] Next, using the patterned photoresist layer 110 as a mask, a portion of the barrier material layer 108, a portion of the conductive material layer 106, and a portion of the barrier material layer 104 are removed to form barrier layers 108a, 108b, 106a, 106b, 104a, and 104b. This allows the electrode material layer 102 to be patterned, forming electrode layer 102a and wire 102b. In some embodiments, electrode layer 102a may include barrier layer 104a, conductive layer 106a, and barrier layer 108a. Barrier layer 104a is located on substrate 100. Conductive layer 106a is located on barrier layer 104a. Barrier layer 108a is located on conductive layer 106a. In some embodiments, wire 102b may include barrier layer 104b, conductive layer 106b, and barrier layer 108b. Barrier layer 104b is located on substrate 100. Conductive layer 106b is located on barrier layer 104b. Barrier layer 108b is located on conductive layer 106b. In some embodiments, the removal method for a portion of barrier material layer 108, a portion of conductive material layer 106, and a portion of barrier material layer 104 is, for example, dry etching.

[0024] Referring to FIG1C, the patterned photoresist layer 110 can be removed. In some embodiments, the method for removing the patterned photoresist layer 110 may include dry stripping or wet stripping.

[0025] Next, a dielectric layer 112 may be formed on the electrode layer 102a. The dielectric layer 112 may also be formed on the wire 102b. The dielectric layer 112 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the dielectric layer 112 is, for example, silicon nitride, silicon oxide, a high dielectric constant material, or a combination thereof. In some embodiments, the dielectric layer 112 may be formed by, for example, atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD).

[0026] Referring to FIG1D, an electrode material layer 114 and a dielectric material layer 116 may be sequentially formed on the dielectric layer 112. The electrode material layer 114 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the electrode material layer 114 is, for example, titanium, titanium nitride, or a combination thereof. In some embodiments, the method for forming the electrode material layer 114 is, for example, physical vapor deposition or chemical vapor deposition. The dielectric material layer 116 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the dielectric material layer 116 is, for example, silicon nitride, silicon oxide, a high dielectric constant material, or a combination thereof. In some embodiments, the method for forming the dielectric material layer 116 is, for example, atomic layer deposition or plasma-enhanced chemical vapor deposition.

[0027] Referring to FIG1E, a patterned photoresist layer 118 may be formed on the dielectric material layer 116. In some embodiments, the patterned photoresist layer 118 may be formed by a photolithography process.

[0028] Next, a portion of the dielectric material layer 116 and a portion of the electrode material layer 114 can be removed using the patterned photoresist layer 118 as a mask. This allows the dielectric material layer 116 and the electrode material layer 114 to be patterned, forming a dielectric layer 116a and an electrode layer 114a, and exposing the dielectric layer 112. In some embodiments, the method for removing a portion of the dielectric material layer 116 is, for example, dry etching. In some embodiments, the method for removing a portion of the electrode material layer 114 is, for example, wet etching. For example, an SC1 cleaning agent (containing water, hydrogen peroxide, and ammonium hydroxide) can be used to remove a portion of the electrode material layer 114.

[0029] Referring to Figure 1F, the patterned photoresist layer 118 can be removed. In some embodiments, the method for removing the patterned photoresist layer 118 may include dry stripping or wet stripping.

[0030] Next, a dielectric layer 120 may be formed on the dielectric layer 112, the electrode layer 114a, and the dielectric layer 116a. In some embodiments, the material of the dielectric layer 120 is, for example, silicon oxide (e.g., tetraethoxysilane (TEOS) silicon oxide). In some embodiments, the method for forming the dielectric layer 120 is, for example, chemical vapor deposition (e.g., high-density plasma chemical vapor deposition (HDP-CVD)).

[0031] Then, a planarization process can be performed on the dielectric layer 120. In some embodiments, the planarization process is, for example, a chemical mechanical polishing process.

[0032] Referring to FIG1G, conductive plugs 122 may be formed in dielectric layers 120 and 112. Conductive plugs 122 may be electrically connected to electrode layer 102a. In some embodiments, conductive plugs 124 may be formed in dielectric layers 120 and 116a. Conductive plugs 124 may be electrically connected to electrode layer 114a. In some embodiments, conductive plugs 126 may be formed in dielectric layers 120 and 112. Conductive plugs 126 may be electrically connected to wire 102b. Conductive plugs 122, 124, and 126 may be single-layer or multi-layer structures. In some embodiments, the materials of conductive plugs 122, 124, and 126 are, for example, tungsten, titanium, titanium nitride, or combinations thereof.

[0033] Referring to FIG1H, a patterned photoresist layer 128 may be formed on the dielectric layer 120, conductive plug 122, conductive plug 124 and conductive plug 126. In some embodiments, the patterned photoresist layer 128 may be formed by a photolithography process.

[0034] Next, a portion of the dielectric layer 120 can be removed using the patterned photoresist layer 128 as a mask. This forms an opening OP1 in the dielectric layer 120. The opening OP1 exposes the dielectric layer 116a. In some embodiments, the method for removing a portion of the dielectric layer 120 is, for example, wet etching. For instance, hydrofluoric acid can be used to remove a portion of the dielectric layer 120.

[0035] Referring to FIG1I, the patterned photoresist layer 128 can be removed. In some embodiments, the method for removing the patterned photoresist layer 128 may include dry stripping or wet stripping.

[0036] Next, an electrode material layer 130 may be formed on the dielectric layer 120 and in the opening OP1. The electrode material layer 130 may further be formed on the conductive plugs 122, 124, and 126. The electrode material layer 130 may be a single-layer structure or a multi-layer structure. In some embodiments, the electrode material layer 130 may include a barrier material layer 132, a conductive material layer 134, and a barrier material layer 136. The barrier material layer 132 is located on the dielectric layer 120, the conductive plugs 122, 124, and 126. In some embodiments, the material of the barrier material layer 132 is, for example, titanium nitride. In some embodiments, the barrier material layer 132 is formed by, for example, physical vapor deposition or chemical vapor deposition. The conductive material layer 134 is located on the barrier material layer 132. In some embodiments, the material of the conductive material layer 134 is, for example, aluminum. In some embodiments, the conductive material layer 134 is formed by, for example, physical vapor deposition. The barrier material layer 136 is located on the conductive material layer 134. In some embodiments, the material of the barrier material layer 136 is, for example, titanium nitride. In some embodiments, the barrier material layer 136 is formed by, for example, physical vapor deposition or chemical vapor deposition.

[0037] Referring to Figure 1J, the electrode material layer 130 can be patterned to form an electrode layer 130a, a wire 130b, and a wire 130c. The electrode layer 130a can be electrically connected to the conductive plug 122. In some embodiments, the electrode layer 130a may include a barrier layer 132a, a conductive layer 134a, and a barrier layer 136a. The barrier layer 132a can be electrically connected to the conductive plug 122. The conductive layer 134a is located on the barrier layer 132a. The barrier layer 136a is located on the conductive layer 134a. The wire 130b can be electrically connected to the conductive plug 124. The wire 130b may include a barrier layer 132b, a conductive layer 134b, and a barrier layer 136b. The barrier layer 132b can be electrically connected to the conductive plug 124. The conductive layer 134b is located on the barrier layer 132b. Barrier layer 136b is located on conductive layer 134b. Wire 130c is electrically connected to conductive plug 126. Wire 130c may include barrier layer 132c, conductive layer 134c, and barrier layer 136c. Barrier layer 132c is electrically connected to conductive plug 126. Conductive layer 134c is located on barrier layer 132c. Barrier layer 136c is located on conductive layer 134c.

[0038] By the above method, a capacitor structure C1, an interconnect structure IS1, and an interconnect structure IS2 can be formed on the substrate 100. The capacitor structure C1 includes an electrode layer 102a, a dielectric layer 112, an electrode layer 114a, a dielectric layer 116a, an electrode layer 130a, and a conductive plug 122. The interconnect structure IS1 may include a conductive plug 124 and a wire 130b. The interconnect structure IS2 may include a wire 102b, a conductive plug 126, and a wire 130c.

[0039] Next, a dielectric layer 138 may be formed on the capacitor structure C1, the interconnect structure IS1, and the interconnect structure IS2. In some embodiments, the material of the dielectric layer 138 is, for example, silicon oxide. The method for forming the dielectric layer 138 is, for example, chemical vapor deposition.

[0040] Hereinafter, the semiconductor structure 10 in the above embodiment will be described with reference to FIG1J. Furthermore, although the method for forming the semiconductor structure 10 is described using the above method as an example, the present invention is not limited thereto.

[0041] Referring to FIG1J, the semiconductor structure 10 includes a substrate 100 and a capacitor structure C1. The capacitor structure C1 includes an electrode layer 102a, a dielectric layer 112, an electrode layer 114a, a dielectric layer 116a, an electrode layer 130a, and a conductive plug 122. The electrode layer 102a is located on the substrate 100. The dielectric layer 112 is located on the electrode layer 102a. In this embodiment, the dielectric layer 112 may cover the sidewalls of the electrode layer 102a, but the present invention is not limited thereto. The electrode layer 114a is located on the dielectric layer 112. The dielectric layer 116a is located on the electrode layer 114a. In some embodiments, the thickness of the dielectric layer 112 and the thickness of the dielectric layer 116a may be the same or different. The electrode layer 130a is located on the dielectric layer 116a. The electrode layer 130a may directly contact the dielectric layer 116a. A conductive plug 122 is located between electrode layer 102a and electrode layer 130a. The conductive plug 122 is electrically connected to electrode layer 102a and electrode layer 130a. The bottom surface S1 of the conductive plug 122 is directly connected to the upper surface S3 of electrode layer 102a. The top surface S2 of the conductive plug 122 is directly connected to the lower surface S4 of electrode layer 130a.

[0042] In some embodiments, the semiconductor structure 10 may further include a wire 130b and a conductive plug 124. The wire 130b is located on one side of the electrode layer 130a. In some embodiments, the bottom surface S5 of the electrode layer 130a may be lower than the bottom surface S6 of the wire 130b. The conductive plug 124 is located between the electrode layer 114a and the wire 130b. The conductive plug 124 may be electrically connected to the electrode layer 114a and the wire 130b. Furthermore, the wire 130b and the conductive plug 124 may form an interconnect structure IS1.

[0043] In some embodiments, the semiconductor structure 10 may further include a wire 102b, a wire 130c, and a conductive plug 126. The wire 102b is located on one side of the electrode layer 102a. The wire 130c is located on the wire 102b. The conductive plug 126 is located between the wire 102b and the wire 130c. The conductive plug 126 may be electrically connected to the wire 102b and the wire 130c. Furthermore, the wire 102b, the wire 130c, and the conductive plug 126 may form an interconnect structure IS2.

[0044] In some embodiments, electrode layer 102a and wire 102b may be formed simultaneously by the same process. In some embodiments, conductive plug 122, conductive plug 124 and conductive plug 126 may be formed simultaneously by the same process. In some embodiments, electrode layer 130a, wire 130b and wire 130c may be formed simultaneously by the same process.

[0045] Furthermore, the remaining components in the semiconductor structure 10 can be described with reference to the above embodiments. In addition, the details of each component in the semiconductor structure 10 (e.g., materials and formation methods) have been described in detail in the above embodiments, and will not be described again here.

[0046] Based on the above embodiments, in the semiconductor structure 10 and its manufacturing method, the capacitor structure C1 includes an electrode layer 102a, a dielectric layer 112, an electrode layer 114a, a dielectric layer 116a, an electrode layer 130a, and a conductive plug 122. The dielectric layer 112 is located on the electrode layer 102a. The electrode layer 114a is located on the dielectric layer 112. The dielectric layer 116a is located on the electrode layer 114a. The electrode layer 130a is located on the dielectric layer 116a. The conductive plug 122 is located between the electrode layer 102a and the electrode layer 130a. The conductive plug 122 is electrically connected to the electrode layer 102a and the electrode layer 130a. The bottom surface S1 of the conductive plug 122 is directly connected to the upper surface S3 of the electrode layer 102a. The top surface S2 of the conductive plug 122 is directly connected to the lower surface S4 of the electrode layer 130a. Since electrode layer 102a and electrode layer 130a can be electrically connected to each other through conductive plug 122, the effective area of ​​capacitor electrode can be effectively increased, thereby effectively improving the capacitance of capacitor structure C1.

[0047] Figures 2A to 2E are cross-sectional views of the manufacturing process of semiconductor structures according to other embodiments of the present invention.

[0048] Referring to FIG2A, a substrate 200 is provided. In some embodiments, the substrate 200 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 200 may have desired semiconductor elements, dielectric layers and / or interconnect structures, the description of which is omitted here.

[0049] Next, an electrode material layer 202, a dielectric material layer 204, an electrode material layer 206, and a dielectric material layer 208 may be sequentially formed on the substrate 200. The electrode material layer 202 may be a single-layer structure or a multi-layer structure. In some embodiments, the electrode material layer 202 may include a barrier material layer 210, a conductive material layer 212, and a barrier material layer 214. The barrier material layer 210 is located on the substrate 200. In some embodiments, the material of the barrier material layer 210 is, for example, titanium nitride. In some embodiments, the barrier material layer 210 is formed by, for example, physical vapor deposition or chemical vapor deposition. The conductive material layer 212 is located on the barrier material layer 210. In some embodiments, the material of the conductive material layer 212 is, for example, aluminum. In some embodiments, the conductive material layer 212 is formed by, for example, physical vapor deposition. The barrier material layer 214 is located on the conductive material layer 212. In some embodiments, the material of the barrier material layer 214 is, for example, titanium nitride. In some embodiments, the barrier material layer 214 is formed by, for example, physical vapor deposition or chemical vapor deposition.

[0050] The dielectric material layer 204 may be a single-layer or multi-layer structure. In some embodiments, the material of the dielectric material layer 204 is, for example, silicon nitride, silicon oxide, a high dielectric constant material, or a combination thereof. In some embodiments, the method for forming the dielectric material layer 204 is, for example, atomic layer deposition or plasma-enhanced chemical vapor deposition. The electrode material layer 206 may be a single-layer or multi-layer structure. In some embodiments, the material of the electrode material layer 206 is, for example, titanium, titanium nitride, or a combination thereof. In some embodiments, the method for forming the electrode material layer 206 is, for example, physical vapor deposition or chemical vapor deposition. The dielectric material layer 208 may be a single-layer or multi-layer structure. In some embodiments, the material of the dielectric material layer 208 is, for example, silicon nitride, silicon oxide, a high dielectric constant material, or a combination thereof. In some embodiments, the method for forming the dielectric material layer 208 is, for example, atomic layer deposition or plasma-enhanced chemical vapor deposition.

[0051] Referring to Figure 2B, a patterned photoresist layer 216 can be formed on the dielectric material layer 208. In some embodiments, the patterned photoresist layer 216 can be formed by a photolithography process.

[0052] Next, using the patterned photoresist layer 216 as a mask, a portion of the dielectric material layer 208 and a portion of the electrode material layer 206 can be removed to form a dielectric layer 208a and an electrode layer 206a. This allows the dielectric material layer 208 and the electrode material layer 206 to be patterned, forming the dielectric layer 208a and the electrode layer 206a, and exposing the dielectric material layer 204. In some embodiments, the method for removing a portion of the dielectric material layer 208 is, for example, dry etching. In some embodiments, the method for removing a portion of the electrode material layer 206 is, for example, wet etching. For example, an SC1 cleaning agent (containing water, hydrogen peroxide, and ammonium hydroxide) can be used to remove a portion of the electrode material layer 206. In some embodiments, during the process of removing a portion of the electrode material layer 206, a portion of the dielectric material layer 204 is also removed.

[0053] Referring to Figure 2C, the patterned photoresist layer 216 can be removed. In some embodiments, the method for removing the patterned photoresist layer 216 may include dry stripping or wet stripping.

[0054] Next, a patterned photoresist layer 218 may be formed on the dielectric layer 208a, the electrode layer 206a and the dielectric material layer 204. In some embodiments, the patterned photoresist layer 218 may be formed by a photolithography process.

[0055] Then, using the patterned photoresist layer 218 as a mask, a portion of the dielectric material layer 204, a portion of the barrier material layer 214, a portion of the conductive material layer 212, and a portion of the barrier material layer 210 are removed to form dielectric layer 204a, dielectric layer 204b, barrier layer 214a, barrier layer 214b, conductive layer 212a, conductive layer 212b, barrier layer 210a, and barrier layer 210b. This allows the dielectric material layer 204 and the electrode material layer 202 to be patterned to form dielectric layer 204a, dielectric layer 204b, electrode layer 202a, and wire 202b. In some embodiments, electrode layer 202a may include barrier layer 210a, conductive layer 212a, and barrier layer 214a. Barrier layer 210a is located on substrate 200. Conductive layer 212a is located on barrier layer 210a. Barrier layer 214a is located on conductive layer 212a. In some embodiments, wire 202b may include barrier layer 210b, conductive layer 212b, and barrier layer 214b. Barrier layer 210b is located on substrate 200. Conductive layer 212b is located on barrier layer 210b. Barrier layer 214b is located on conductive layer 212b. In some embodiments, the removal method for a portion of dielectric material layer 204, a portion of barrier material layer 214, a portion of conductive material layer 212, and a portion of barrier material layer 210 is, for example, dry etching.

[0056] Referring to Figure 2D, the patterned photoresist layer 218 can be removed. In some embodiments, the method for removing the patterned photoresist layer 218 may include dry stripping or wet stripping.

[0057] Next, a dielectric layer 220 may be formed on the electrode layer 202a, dielectric layer 204a, electrode layer 206a, dielectric layer 208a, wire 202b, and dielectric layer 204b. In some embodiments, the material of the dielectric layer 220 is, for example, silicon oxide (e.g., tetraethoxysilane (TEOS) silicon oxide). In some embodiments, the method for forming the dielectric layer 220 is, for example, chemical vapor deposition (e.g., high-density plasma chemical vapor deposition (HDP-CVD)).

[0058] Then, a planarization process can be performed on the dielectric layer 220. In some embodiments, the planarization process is, for example, a chemical mechanical polishing process.

[0059] Referring to FIG2E, the steps shown in FIG1G to FIG1J can be performed to obtain the semiconductor structure 20 of FIG2E. Furthermore, in the semiconductor structure 10 of FIG1J and the semiconductor structure 20 of FIG2E, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0060] By the above method, a capacitor structure C2, an interconnect structure IS1, and an interconnect structure IS3 can be formed on the substrate 20. The capacitor structure C2 includes an electrode layer 202a, a dielectric layer 204a, an electrode layer 206a, a dielectric layer 208a, an electrode layer 130a, and a conductive plug 122. The interconnect structure IS1 may include a conductive plug 124 and a wire 130b. The interconnect structure IS3 may include a wire 202b, a conductive plug 126, and a wire 130c.

[0061] Hereinafter, the semiconductor structure 20 in the above embodiment will be described with reference to FIG2E. Furthermore, although the method for forming the semiconductor structure 20 is described using the above method as an example, the present invention is not limited thereto.

[0062] Referring to FIG2E, the semiconductor structure 20 includes a substrate 200 and a capacitor structure C2. The capacitor structure C2 includes an electrode layer 202a, a dielectric layer 204a, an electrode layer 206a, a dielectric layer 208a, an electrode layer 130a, and a conductive plug 122. The electrode layer 202a is located on the substrate 200. The dielectric layer 204a is located on the electrode layer 202a. In this embodiment, the dielectric layer 204a may not cover the sidewalls of the electrode layer 202a, but the present invention is not limited thereto. The electrode layer 206a is located on the dielectric layer 204a. The dielectric layer 208a is located on the electrode layer 206a. In some embodiments, the thickness of the dielectric layer 204a and the thickness of the dielectric layer 208a may be the same or different. The electrode layer 130a is located on the dielectric layer 208a. The electrode layer 130a may directly contact the dielectric layer 208a. The conductive plug 122 is located between electrode layer 202a and electrode layer 130a. The conductive plug 122 is electrically connected to electrode layer 202a and electrode layer 130a. The bottom surface S1 of the conductive plug 122 is directly connected to the upper surface S7 of electrode layer 202a. The top surface S2 of the conductive plug 122 is directly connected to the lower surface S4 of electrode layer 130a.

[0063] In some embodiments, the semiconductor structure 20 may further include a wire 130b and a conductive plug 124. The wire 130b is located on one side of the electrode layer 130a. In some embodiments, the bottom surface S5 of the electrode layer 130a may be lower than the bottom surface S6 of the wire 130b. The conductive plug 124 is located between the electrode layer 206a and the wire 130b. The conductive plug 124 may be electrically connected to the electrode layer 206a and the wire 130b. Furthermore, the wire 130b and the conductive plug 124 may form an interconnect structure IS1.

[0064] In some embodiments, the semiconductor structure 20 may further include a wire 202b, a wire 130c, and a conductive plug 126. The wire 202b is located on one side of the electrode layer 202a. The wire 130c is located on the wire 202b. The conductive plug 126 is located between the wire 202b and the wire 130c. The conductive plug 126 may be electrically connected to the wire 202b and the wire 130c. Furthermore, the wire 202b, the wire 130c, and the conductive plug 126 may form an interconnect structure IS3.

[0065] In some embodiments, electrode layer 202a and wire 202b may be formed simultaneously by the same process. In some embodiments, conductive plug 122, conductive plug 124 and conductive plug 126 may be formed simultaneously by the same process. In some embodiments, electrode layer 130a, wire 130b and wire 130c may be formed simultaneously by the same process.

[0066] Furthermore, the remaining components in the semiconductor structure 20 can be described with reference to the above embodiments. In addition, the details of each component in the semiconductor structure 20 (e.g., materials and formation methods) have been described in detail in the above embodiments, and will not be described again here.

[0067] Based on the above embodiments, in the semiconductor structure 20 and its manufacturing method, the capacitor structure C2 includes an electrode layer 202a, a dielectric layer 204a, an electrode layer 206a, a dielectric layer 208a, an electrode layer 130a, and a conductive plug 122. The dielectric layer 204a is located on the electrode layer 202a. The electrode layer 206a is located on the dielectric layer 204a. The dielectric layer 208a is located on the electrode layer 206a. The electrode layer 130a is located on the dielectric layer 208a. The conductive plug 122 is located between the electrode layer 202a and the electrode layer 130a. The conductive plug 122 is electrically connected to the electrode layer 202a and the electrode layer 130a. The bottom surface S1 of the conductive plug 122 is directly connected to the upper surface S7 of the electrode layer 202a. The top surface S2 of the conductive plug 122 is directly connected to the lower surface S4 of the electrode layer 130a. Since electrode layer 202a and electrode layer 130a can be electrically connected to each other through conductive plug 122, the effective area of ​​capacitor electrode can be effectively increased, thereby effectively improving the capacitance of capacitor structure C2.

[0068] In summary, in the semiconductor structure and manufacturing method of the above embodiments, the capacitor structure includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, and a first conductive plug. The first dielectric layer is located on the first electrode layer. The second electrode layer is located on the first dielectric layer. The second dielectric layer is located on the second electrode layer. The third electrode layer is located on the second dielectric layer. The first conductive plug is located between the first electrode layer and the third electrode layer. The first conductive plug is electrically connected to the first electrode layer and the third electrode layer. The bottom surface of the first conductive plug is directly connected to the upper surface of the first electrode layer. The top surface of the first conductive plug is directly connected to the lower surface of the third electrode layer. Since the first electrode layer and the third electrode layer can be electrically connected to each other through the first conductive plug, the effective area of ​​the capacitor electrode can be effectively increased, thereby effectively improving the capacitance of the capacitor structure.

[0069] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0017] Figures 1A to 1J are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention. Figures 2A to 2E are cross-sectional views of the manufacturing process of semiconductor structures according to other embodiments of the present invention.

Claims

1. A semiconductor structure, comprising: Base; A capacitor structure includes: a first electrode layer located on the substrate; The first dielectric layer is located on the first electrode layer; A second electrode layer is located on the first dielectric layer; a second dielectric layer is located on the second electrode layer; a third electrode layer is located on the second dielectric layer; The first conductive plug is located between the first electrode layer and the third electrode layer and is electrically connected to the first electrode layer and the third electrode layer, wherein the bottom surface of the first conductive plug is directly connected to the upper surface of the first electrode layer and the top surface of the first conductive plug is directly connected to the lower surface of the third electrode layer; and a first wire is located on one side of the third electrode layer. And a second conductive plug, located between the second electrode layer and the first wire, and electrically connected to the second electrode layer and the first wire, wherein the top surface of the third electrode layer is higher than the bottom surface of the first wire.

2. The semiconductor structure as claimed in claim 1, wherein the first dielectric layer covers the sidewall of the first electrode layer.

3. The semiconductor structure as claimed in claim 1, wherein the first dielectric layer does not cover the sidewalls of the first electrode layer.

4. The semiconductor structure as claimed in claim 1, wherein the bottom surface of the third electrode layer is lower than the bottom surface of the first conductor.

5. The semiconductor structure as described in claim 1, further comprising: The second conductor is located on one side of the first electrode layer; The third conductor is located on top of the second conductor; And a third conductive plug, located between the second wire and the third wire, and electrically connected to the second wire and the third wire.

6. A method for manufacturing a semiconductor structure, comprising: Provide a base; A capacitor structure is formed on the substrate, wherein the capacitor structure includes: a first electrode layer located on the substrate; a first dielectric layer located on the first electrode layer; a second electrode layer located on the first dielectric layer; a second dielectric layer located on the second electrode layer; a third electrode layer located on the second dielectric layer; and a first conductive plug located between the first electrode layer and the third electrode layer and electrically connected to the first electrode layer and the third electrode layer, wherein the bottom surface of the first conductive plug is directly connected to the upper surface of the first electrode layer, and the top surface of the first conductive plug is directly connected to the lower surface of the third electrode layer; a wire is formed on one side of the third electrode layer; and a second conductive plug is formed between the second electrode layer and the wire, wherein the top surface of the third electrode layer is higher than the bottom surface of the wire.

7. A method for manufacturing a semiconductor structure as claimed in claim 6, wherein the method for forming the capacitor structure comprises: A first electrode material layer is formed on the substrate; The first electrode material layer is patterned to form the first electrode layer; A first dielectric layer is formed on the first electrode layer; a second electrode material layer and a dielectric material layer are sequentially formed on the first dielectric layer; the dielectric material layer and the second electrode material layer are patterned to form the second dielectric layer and the second electrode layer, and the first dielectric layer is exposed. A third dielectric layer is formed on the first dielectric layer, the second electrode layer, and the second dielectric layer; The first conductive plug is formed in the third dielectric layer and the first dielectric layer; An opening is formed in the third dielectric layer, wherein the opening exposes the second dielectric layer; a third electrode material layer is formed on the third dielectric layer and in the opening; and the third electrode material layer is patterned to form the third electrode layer.

8. The method for manufacturing a semiconductor structure as described in claim 7 further includes: The second conductive plug is formed in the third dielectric layer and the second dielectric layer, wherein the second conductive plug is electrically connected to the second electrode layer; The third electrode material layer is patterned to form the wire, wherein the wire is electrically connected to the second conductive plug.

9. A method for manufacturing a semiconductor structure as claimed in claim 6, wherein the method for forming the capacitor structure comprises: A first electrode material layer, a first dielectric material layer, a second electrode material layer, and a second dielectric layer are sequentially formed on the substrate. The second dielectric material layer and the second electrode material layer are patterned to form the second dielectric layer and the second electrode layer, exposing the first dielectric material layer; the first dielectric material layer and the first electrode material layer are patterned to form the first dielectric layer and the first electrode layer; a third dielectric layer is formed on the first electrode layer, the first dielectric layer, the second electrode layer, and the second dielectric layer; the first conductive plug is formed in the third dielectric layer and the first dielectric layer; An opening is formed in the third dielectric layer, wherein the opening exposes the second dielectric layer; a third electrode material layer is formed on the third dielectric layer and in the opening; and the third electrode material layer is patterned to form the third electrode layer.

10. The method for manufacturing a semiconductor structure as described in claim 9, further comprising: The second conductive plug is formed in the third dielectric layer and the second dielectric layer, wherein the second conductive plug is electrically connected to the second electrode layer; The third electrode material layer is patterned to form the wire, wherein the wire is electrically connected to the second conductive plug.

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