Integrated chip and method of forming the same

Abstract

An integrated wafer includes a semiconductor waveguide layer. A core portion of the semiconductor waveguide layer projects upward from a base portion of the semiconductor waveguide layer. A first thermal radiator is spaced apart on the semiconductor waveguide layer and laterally spaced apart from the core portion in a first direction. A second thermal radiator is spaced apart on the semiconductor waveguide layer and laterally spaced apart from the core portion in a second direction. A first dielectric layer is located between the first thermal radiator and the semiconductor waveguide layer and between the second thermal radiator and the semiconductor waveguide layer. The distance between the first thermal radiator and the semiconductor waveguide layer is less than the distance between the first thermal radiator and the core portion. The distance between the second thermal radiator and the semiconductor waveguide layer is less than the distance between the second thermal radiator and the core portion.

Description

[Previous Technology]

[0001] Optical waveguides are commonly used as components in integrated optical paths. Optical waveguides are used to confine and guide light from a first point on an integrated circuit (IC) to a second point on the IC with minimal attenuation. Many modern optical waveguides are formed using semiconductors. Semiconductor waveguides may include optical transducers or optical couplers for coupling fiber optics to the semiconductor waveguide.

Implementation Method

[0005] The following discloses numerous different embodiments or examples of various features provided for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby allowing the first and second features to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the elements during use or operation. Devices may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0007] An integrated wafer includes a semiconductor waveguide layer on a substrate. A base portion of the semiconductor waveguide layer extends laterally on the substrate. A core portion of the semiconductor waveguide layer protrudes upward from the base portion and forms the core of the waveguide. Optical radiation signals propagate in and are typically confined within the core portion of the semiconductor waveguide layer.

[0008] The performance of a waveguide can be affected by the temperature of the core portion of the semiconductor waveguide layer. For example, the temperature of the core portion can affect its refractive index, which in turn can affect the phase and / or wavelength of the optical radiation signal propagating in the core portion. Therefore, in some instances, heaters are directly spaced above the core portion of the semiconductor waveguide layer to control the temperature of the core portion. A dielectric layer is located between the heaters and the core portion. Heat emitted from the heaters is transferred to the core portion of the semiconductor waveguide layer through the dielectric layer.

[0009] In some cases, if the heater is too close to the core, it may cause light radiation loss. Therefore, increasing the thickness of the dielectric layer between the heater and the core can reduce the possibility of light loss caused by the heater. However, since the dielectric layer has relatively low thermal conductivity, increasing the thickness of the dielectric layer may increase the thermal resistance between the heater and the core. Therefore, it may be necessary to increase the heater temperature to heat the core. Increasing the heater temperature will increase the heater's power consumption. Therefore, the power efficiency of the heater may decrease. In addition, heating the heater to high temperatures may reduce the reliability of the integrated wafer. For example, the dielectric layer and / or nearby interconnect structures may be damaged by the high heat emitted by the heater.

[0010] In various embodiments disclosed herein, increasing the lateral distance between the heater and the core portion and decreasing the vertical distance between the heater and the semiconductor waveguide layer improves the efficiency of the heater and the reliability of the integrated wafer without increasing optical loss at the core portion. For example, the heater includes a first thermal radiator laterally spaced from the core portion in a first direction and a second thermal radiator laterally spaced from the core portion in a second direction. By laterally spacing the thermal radiators from the core portion, the distance between the thermal radiators and the core portion is increased, reducing the likelihood of optical loss at the core portion. Furthermore, the thickness of the dielectric layer between the first and second thermal radiators and the semiconductor waveguide layer is reduced to decrease the thermal resistance between the thermal radiators and the core portion of the semiconductor waveguide layer. For example, heat emitted from the thermal radiators is transferred through a thin dielectric layer to a lateral portion (e.g., a pickup portion) of the semiconductor waveguide layer below the thermal radiators. By reducing the thickness of the dielectric layer, the thermal resistance between the thermal radiators and the lateral portion of the semiconductor waveguide layer is reduced. The heat is then transferred from the lateral portion of the semiconductor waveguide layer to the core portion of the semiconductor waveguide layer through a base portion of the semiconductor waveguide layer. Because the thermal conductivity of the semiconductor waveguide layer is much higher than that of the dielectric layer, the thermal resistance between the lateral portion and the core portion of the semiconductor waveguide layer is lower. Therefore, the total thermal resistance between the thermal radiator and the core portion of the semiconductor waveguide layer is also reduced.

[0011] By reducing the thermal resistance between the heater and the core portion of the semiconductor waveguide layer, the temperature of the heater can be reduced. Lowering the heater temperature reduces the heater's power consumption. Therefore, the power efficiency of the heater can be improved. Furthermore, by reducing the heater temperature, reliability issues caused by high heater temperature can be reduced or avoided.

[0012] FIG1 shows a cross-sectional view 100 of some embodiments of an integrated wafer including a heater above a waveguide. FIG2 shows a top view 200, and FIG3 shows a top view 300 of some embodiments of the integrated wafer of FIG1. ​​In some embodiments, the top view 200 of FIG2 is taken along line A-A' in FIG1, and the top view 300 of FIG3 is taken along line B-B' in FIG1.

[0013] The base dielectric layer 104 is located above the base semiconductor layer 102. The semiconductor waveguide layer 106 is located above the base dielectric layer 104. The base portion 108 of the semiconductor waveguide layer 106 extends laterally above the base dielectric layer 104. The first pickup portion 110, the second pickup portion 112, and the core portion 114 of the semiconductor waveguide layer 106 protrude upward from the base portion 108. The first pickup portion 110 is laterally spaced from the core portion 114 in a first direction, and the second pickup portion 112 is laterally spaced from the core portion 114 in a second direction opposite to the first direction, so that the core portion 114 is laterally located between the first pickup portion 110 and the second pickup portion 112.

[0014] A first dielectric layer 116 is located above the base portion 108 and between the core portion 114 and the pickup portions 110 and 112. A second dielectric layer 118 (e.g., a resist-protected dielectric layer) is located above the semiconductor waveguide layer 106 and the first dielectric layer 116. The second dielectric layer 118 extends laterally to the top of the first pickup portion 110, the top of the core portion 114, and the top of the second pickup portion 112. A third dielectric layer 120 (e.g., an interlayer dielectric (ILD)) is located above the semiconductor waveguide layer 106 and the second dielectric layer 118.

[0015] The heater is located within the third dielectric layer 120 and spaced apart from the semiconductor waveguide layer 106. In some examples, the heater is directly spaced above the core portion 114, as shown in feature 130 (indicated by "dashed lines"). In these examples, the distance between the heater and the semiconductor waveguide layer 106 is the same as the distance between the heater and the core portion 114, as shown in distance 132. Increasing the distance between the heater and the core portion 114 avoids optical losses. Therefore, the amount of dielectric material between the heater and the core portion 114 (e.g., the combined thickness of dielectric layers 120 and 118) increases. However, the thermal conductivity of the second dielectric layer 118 and the third dielectric layer 120 decreases. Therefore, increasing the amount of dielectric material between the heater and the core portion 114 increases the thermal resistance between the heater and the core portion 114.

[0016] In various embodiments disclosed herein, the heater includes a first thermal radiator 122 and a second thermal radiator 124. The temperature of the thermal radiators 122 and 124 is increased by allowing current to flow through them. The resistance of the thermal radiators 122 and 124 converts some electrical energy into heat energy. As the temperature of the thermal radiators 122 and 124 increases, heat is released from them. Increasing the lateral distance between the thermal radiators 122 and 124 and the core portion 114, and decreasing the vertical distance between the thermal radiators 122 and 124 and the semiconductor waveguide layer 106, improves heater efficiency and integrated wafer reliability without increasing the optical loss of the core portion 114.

[0017] For example, the first thermal radiator 122 is located directly above the first pickup portion 110, and the second thermal radiator 124 is located directly above the second pickup portion 112. By laterally spacing the thermal radiators 122 and 124 from the core portion 114, the distance between the thermal radiators 122 and 124 and the core portion 114 is increased, thereby reducing the possibility of optical loss in the core portion 114. The thermal radiators 122 and 124 do not extend directly above the core portion 114 to avoid optical loss.

[0018] Furthermore, the heat radiators 122 and 124 are located on the second dielectric layer 118 and separated from the semiconductor waveguide layer 106 by the second dielectric layer 118. The thickness of the second dielectric layer 118 is reduced to decrease the thermal resistance between the heat radiators 122 and 124 and the pickup portions 110 and 112. For example, the thickness of the second dielectric layer 118 is reduced such that the distance 134 between the first heat radiator 122 and the semiconductor waveguide layer 106 (e.g., the first pickup portion 110) is smaller than the distance 136 between the first heat radiator 122 and the core portion 114, and the distance 138 between the second heat radiator 124 and the semiconductor waveguide layer 106 (e.g., the second pickup portion 112) is smaller than the distance 140 between the second heat radiator 124 and the core portion 114. The heat released from the heat radiators 122 and 124 is transferred to the pickup portions 110 and 112 through the thin second dielectric layer 118. Heat is then transferred from the pickup portions 110, 112 through the base portion 108 to the core portion 114, as indicated by arrow 142. The thermal conductivity of the semiconductor waveguide layer 106 is substantially higher (e.g., about 10 times) than that of the second and third dielectric layers 118, 120. Therefore, the thermal resistance between the pickup portions 110, 112 and the core portion 114 is low. As a result, the total thermal resistance between the heat radiators 122, 124 and the core portion 114 of the semiconductor waveguide layer 106 is reduced.

[0019] By reducing the thermal resistance between the heater and the core portion 114 of the semiconductor waveguide layer 106, the temperature of the heater can be reduced. Reducing the heater temperature reduces the power consumption of the heater. Therefore, the power efficiency of the heater can be improved. Furthermore, by reducing the heater temperature, reliability problems caused by high temperatures at the heater can be reduced or avoided.

[0020] The core portion 114 is partially defined by a pair of sidewalls and the top surface of the semiconductor waveguide layer 106. The first pickup portion 110 is partially defined by the sidewalls and the top surface of the semiconductor waveguide layer 106. The second pickup portion 112 is partially defined by the sidewalls and the top surface of the semiconductor waveguide layer 106. The base portion 108 is partially defined by the top surface of the semiconductor waveguide layer 106 located between the core portion 114 and the first pickup portion 110, and by the top surface of the semiconductor waveguide layer 106 located between the core portion 114 and the second pickup portion 112.

[0021] In some embodiments, the base semiconductor layer 102 and the base dielectric layer 104 are referred to as a substrate. In some embodiments, the base semiconductor layer 102, the base dielectric layer 104 and the semiconductor waveguide layer 106 are semiconductor-on-insulator (SOI) substrates or a portion thereof, wherein the semiconductor waveguide layer 106 is a "device" layer of the SOI substrate.

[0022] In some embodiments, the base semiconductor layer 102 and / or the semiconductor waveguide layer 106 comprise silicon or some other suitable semiconductor. In some embodiments, the base dielectric layer 104, the first dielectric layer 116, and / or the third dielectric layer 120 comprise silicon dioxide or some other suitable dielectric material. In some embodiments, the second dielectric layer 118 comprises silicon dioxide, silicon nitride, or some other suitable dielectric material. In some embodiments, the thickness of the second dielectric layer 118 is less than about 500 nanometers, ranging from about 1 nanometer to 500 nanometers, or some other suitable thickness. In some embodiments, the heat radiators 122, 124 comprise metals (e.g., tungsten, titanium, copper, or the like), semiconductors (e.g., doped or undoped polycrystalline silicon, doped or undoped silicon, etc.), silicides, or some other suitable material. In some embodiments, the heat radiators 122, 124 are also referred to as heater lines, heater structures, or heating features.

[0023] FIG4 shows a cross-sectional view 400 of some embodiments of the integrated wafer of FIG1, wherein the semiconductor waveguide layer 106 is doped.

[0024] The semiconductor waveguide layer 106 includes a first doped region 402 and a second doped region 404. The first doped region 402 and the second doped region 404 fill the core portion 114 of the semiconductor waveguide layer 106. The first doped region 402 is adjacent to the second doped region 404 near the center of the core portion 114. The first doped region 402 extends laterally in one lateral base portion 108 of the core portion 114, and the second doped region 404 extends laterally in another lateral base portion 108 of the core portion 114. The first doped region 402 has a first doping type (e.g., n-type), while the second doped region 404 has a second doping type opposite to the first doping type (e.g., p-type). The first doped region 402 and the second doped region 404 form a pn junction in the core portion 114. The first doped region 402 and the second doped region 404 have relatively low doping concentrations (n-doped and p-doped, respectively).

[0025] The semiconductor waveguide layer 106 includes a third doped region 406 and a fourth doped region 408. The third doped region 406 is located in the first pickup portion 110 of the semiconductor waveguide layer 106 and extends laterally into the base portion 108 to the first doped region 402. The fourth doped region 408 is located in the second pickup portion 112 of the semiconductor waveguide layer 106 and extends laterally into the base portion 108 to the second doped region 404. The third doped region 406 has a first doping type, and the fourth doped region 408 has a second doping type. A first thermal radiator 122 is located directly above the third doped region 406, and a second thermal radiator 124 is located directly above the fourth doped region 408. The third and fourth doped regions 406 and 408 have relatively high doping concentrations (n+ doping and p+ doping, respectively).

[0026] In some embodiments, the semiconductor waveguide layer 106 includes a body region 410 located directly beneath the third doped region 406 and the fourth doped region 408. In some embodiments, the body region 410 is undoped (e.g., intrinsic). In some other embodiments, the body region 410 has a first doping type.

[0027] Figure 5 shows 500 of some embodiments of the integrated wafer of Figure 1, wherein the etch stop layer 502 is located above the second dielectric layer 118.

[0028] An etch stop layer 502 is located between the second dielectric layer 118 and the third dielectric layer 120, and between the semiconductor waveguide layer 106 and the third dielectric layer 120. The etch stop layer 502 extends along the top surface and sidewalls of the second dielectric layer 118. Thermal radiators 122, 124 extend through the etch stop layer 502 to the second dielectric layer 118. In some embodiments, the etch stop layer 502 comprises silicon dioxide, silicon nitride, silicon carbide, aluminum oxide, or other suitable materials.

[0029] Silicone layers 504 and 506 are located at pick-up portions 110 and 112, respectively, between the semiconductor waveguide layer 106 and the etch stop layer 502. Silicone layers 504 and 506 extend into (e.g., below the top of) and above the semiconductor waveguide layer 106. In some embodiments, silicone layers 504 and 506 extend along the sidewalls of the second dielectric layer 118. In some embodiments, silicone layers 504 and 506 comprise nickel silicon, tungsten silicon, titanium silicon, or other suitable materials.

[0030] Figure 6 shows a cross-sectional view 600 of some embodiments of the integrated wafer of Figure 1, wherein waveguide contacts contact the semiconductor waveguide layer 106.

[0031] The first waveguide contact 602 is located on the first pickup portion 110, and the second waveguide contact 604 is located on the second pickup portion 112. In some embodiments, waveguide contacts 602 and 604 contact silicon layers 504 and 506, respectively. In some embodiments, silicon layers 504 and 506 are directly located between waveguide contacts 602 and 604 and doped regions 406 and 408, respectively. In some other embodiments, waveguide contacts 602 and 604 directly contact doped regions 406 and 408, respectively. Silicon layers 504 and 506 and doped regions 406 and 408 with high doping concentrations reduce the contact resistance between waveguide contacts 602 and 604 and the semiconductor waveguide layer 106.

[0032] FIG7 shows a top view 700 of some embodiments of an integrated wafer including a heater over a waveguide, wherein the waveguide forms a ring modulator. In some embodiments, the cross-sectional view 400 of FIG4 is taken along line A-A' of FIG7. To clearly show the semiconductor waveguide layer 106 and the heater, the base portion 108, the first dielectric layer 116, the second dielectric layer 118, and the third dielectric layer 120 are not shown in FIG7.

[0033] Figures 8-9 show cross-sectional views 800-900 of some embodiments of the integrated wafer of Figure 7. In some embodiments, cross-sectional view 800 of Figure 8 is taken along line B-B' of Figure 7, and cross-sectional view 900 of Figure 9 is taken along line C-C' of Figure 7.

[0034] Referring to Figures 7-9, the ring modulator includes a ring waveguide 702 and a bus waveguide 704 extending alongside the ring waveguide 702. A semiconductor waveguide layer 106 forms the bus waveguide 704 and the ring waveguide 702. A core portion 114 of the semiconductor waveguide layer 106 forms the core of the ring waveguide 702. A first pickup portion 110 is surrounded by the core portion 114. A second pickup portion 112 partially surrounds the core portion 114 and the first pickup portion 110. A second core portion 706 of the semiconductor waveguide layer 106 forms the core of the bus waveguide 704.

[0035] The first thermal radiator 122 extends in an arc shape over the first pickup portion 110 along the outer periphery of the first pickup portion 110. The second thermal radiator 124 extends in an arc shape over the second pickup portion 112 along the inner periphery of the second pickup portion 112. The first thermal radiator 122 and the second thermal radiator 124 are coupled in parallel via a first heater electrode 708 and a second heater electrode 710 of the heater. For example, the first heater electrode 708 couples a first end of the first thermal radiator 122 to a first end of the second thermal radiator 124, and the second heater electrode 710 couples a second end of the first thermal radiator 122 to a second end of the second thermal radiator 124. By coupling the first heater electrode 708 to a first voltage supply terminal (not shown) and the second heater electrode 710 to a second voltage supply terminal (not shown), a voltage difference can be applied between the heater electrodes 708 and 710, causing current to flow through the parallel-coupled heat radiators 122 and 124 and from the first heater electrode 708 to the second heater electrode 710, resulting in the heat radiators 122 and 124 heating up. The heat emitted by the heat radiators 122 and 124 heats the ring waveguide 702 to control the performance of the ring waveguide 702.

[0036] Figures 10-11 show cross-sectional views 1000-1100 of some other embodiments of the integrated wafer of Figures 7-9. In some embodiments, cross-sectional view 1000 of Figure 10 is taken along line A-A' of Figure 7. In some embodiments, cross-sectional view 1100 of Figure 11 is taken along line C-C' of Figure 7.

[0037] Referring to Figures 10-11, the heat radiators 122 and 124 have plate-like or pad-like structures, wherein the width of the heat radiators 122 and 124 is greater than the height of the heat radiators 122 and 124. The heater electrodes 708 and 710 have transverse portions spaced apart above the heat radiators 122 and 124, and have vertical contact portions extending vertically from the transverse portions to the heat radiators 122 and 124 to couple the transverse portions of the heater electrodes 708 and 710 to the heat radiators 122 and 124. In some cases, increasing the width of the heat radiators 122 and 124, thereby increasing the surface area of ​​the heat radiators 122 and 124 above the pickup portions 110 and 112, can improve heat transfer between the heat radiators 122 and 124 and the semiconductor waveguide layer 106.

[0038] In some cases, when the radiators 122 and 124 are coupled in parallel via heater electrodes 708 and 710, the resistance of the heater at the point where the heater electrodes 708 and 710 contact the radiators 122 and 124 is higher than the resistance along the parallel-coupled radiators 122 and 124. Therefore, in these cases, the connection between the heater electrodes 708 and 710 and the radiators 122 and 124 may release more heat than along the radiators 122 and 124 themselves. As a result, the efficiency of the radiators 122 and 124 may be reduced (e.g., more power may be required to raise the temperature of the radiators 122 and 124). Furthermore, in some cases, when the radiators 122 and 124 are coupled in parallel through the heater electrodes 708 and 710, the resistance along the first radiator 122 may be different (e.g., less) than the resistance along the second radiator 124 because the radiators 122 and 124 have different lengths (e.g., the length of the radiator 122 between heater electrodes 708 and 710 is less than the length of the radiator 124 between heater electrodes 708 and 710). Therefore, in these cases, the heat released along the radiator 122 may differ from the heat released along the radiator 124. This can reduce the uniformity of heating. Additionally, in some cases, when the radiators 122 and 124 are coupled in parallel through the heater electrodes 708 and 710, it may be difficult to adjust the resistance of the radiators 122 and 124.

[0039] In some embodiments disclosed herein, the first thermal radiator 122 and the second thermal radiator 124 are coupled in series between the first heater electrode 708 and the second heater electrode 710 to further improve the performance of the heater. For example, FIG12 shows a top view 1200 of some embodiments of the integrated wafer of FIG7, wherein the first thermal radiator 122 and the second thermal radiator 124 are coupled in series between the first heater electrode 708 and the second heater electrode 710. FIG13 shows a cross-sectional view 1300 of some embodiments of the integrated wafer of FIG12. In some embodiments, the cross-sectional view 1300 of FIG13 is taken along line A-A' of FIG12. FIG14 shows a cross-sectional view 1400 of some other embodiments of the integrated wafer of FIG12. In some embodiments, the cross-sectional view 1400 of FIG14 is taken along line A-A' of FIG12. FIG15 shows a top view 1500 of some other embodiments of the integrated wafer of FIG12.

[0040] Referring to Figures 12-15, the first thermal radiator 122 and the second thermal radiator 124 are coupled in series between the heater electrodes 708 and 710 via a heater bridge 1202. For example, the first end of the second thermal radiator 124 is coupled to the first heater electrode 708, the second end of the second thermal radiator 124 is coupled to the first end of the heater bridge 1202, the first end of the first thermal radiator 122 is coupled to the second end of the heater bridge 1202, and the second end of the first thermal radiator 122 is coupled to the second heating electrode 710. In some embodiments, as shown in Figure 13, the heater bridge 1202 extends laterally between the thermal radiators 122 and 124. In some embodiments, as shown in Figure 14, the heater bridge 1202 has a lateral portion spaced apart above the thermal radiators 122 and 124, and a vertical portion extending from the lateral portion to the thermal radiators 122 and 124. A voltage difference can be applied between heater electrodes 708 and 710 so that current flows from the first heater electrode 708 through the heat radiator 124, then through the heater bridge 1202, then through the heat radiator 122, and finally to the heater electrode 710.

[0041] By using heater bridge 1202 to series-couple heat radiators 122 and 124 between heater electrodes 708 and 710, the efficiency of heat radiators 122 and 124 can be improved (e.g., less power may be needed to raise the temperature of heat radiators 122 and 124). Furthermore, by using heater bridge 1202 to series-couple heat radiators 122 and 124 between heater electrodes 708 and 710, the resistance along the heater is improved uniformity because the current has only one path instead of two. Therefore, the heating uniformity along heat radiators 122 and 124 can be improved. Moreover, by using heater bridge 1202 to series-couple heat radiators 122 and 124 between heater electrodes 708 and 710, the resistance of heat radiators 122 and 124 can be more easily adjusted by changing the length of heat radiators 122 and 124 (and moving heater bridge 1202 accordingly). For example, as shown in Figure 15, the resistance of the heater can be adjusted by adjusting the lengths of the heat radiators 122 and 124 (and the heater bridge 1202 can be moved accordingly). By adjusting the resistance of the heater, the performance of the heater (e.g., the amount of heat dissipated, the power consumed, etc.) can be adjusted.

[0042] The heater bridge 1202 is spaced a considerable distance above the core portion 114 to avoid increasing the possibility of optical loss along the core portion 114. In some embodiments, the heater bridge 1202 includes a metal (e.g., tungsten, titanium, copper or the like), a semiconductor (e.g., polycrystalline silicon, silicon or the like), a silicate or other suitable material.

[0043] FIG16 shows a top view 1600 of some other embodiments of the integrated wafer of FIG12.

[0044] The ring modulator includes a second bus waveguide 1602, which extends adjacent to the ring waveguide 702 and on the opposite side of the bus waveguide 704. A semiconductor waveguide layer 106 forms the second bus waveguide 1602. A third core portion 1604 of the semiconductor waveguide layer 106 forms the core of the second bus waveguide 1602.

[0045] The heater includes a first heater electrode 708, a second heater electrode 710, a first thermal radiator 122, a second thermal radiator 124, a third thermal radiator 1610, a first heater bridge 1606, and a second heater bridge 1608. A first end of the second thermal radiator 124 is coupled to the first heater electrode 708, a second end of the second thermal radiator 124 is coupled to the first end of the heater bridge 1606, a first end of the thermal radiator 122 is coupled to the second end of the heater bridge 1606, a second end of the thermal radiator 122 is coupled to the first end of the heater bridge 1608, a first end of the thermal radiator 1610 is coupled to the second end of the heater bridge 1608, and a second end of the thermal radiator 1610 is coupled to the heater electrode 710. Two heater bridges 1606 and 1608 are included to prevent the thermal radiators 122, 124, and 1610 from landing on the second bus waveguide 1602. The performance of the heater can be adjusted by adjusting the lengths of the thermal radiators 122, 124, and 1610 and correspondingly adjusting the positions of the heater bridges 1606 and 1608.

[0046] FIG17 illustrates a cross-sectional view 1700 of some other embodiments of the integrated wafer of FIG1-FIG16.

[0047] In some embodiments, the first dielectric layer 116 extends over the top of the semiconductor waveguide layer 106 and is located directly between the second dielectric layer 118 and portions 110, 112, 114 of the semiconductor waveguide layer 106. In some embodiments, thermal radiators 122, 124 extend into the second dielectric layer 118.

[0048] Figures 18-34 show cross-sectional views 1800-3400 of some embodiments of a method for forming an integrated wafer including a heater over a waveguide. Although Figures 18-34 are described with respect to one method, it should be understood that the structures disclosed in Figures 18-34 are not limited to this method, but can exist independently of this method.

[0049] Figures 18-27 show cross-sectional views 1800-2700 of some embodiments of the method for forming waveguides.

[0050] As shown in the cross-sectional view 1800 of FIG18, a semiconductor waveguide layer 106 is provided. In some embodiments, the semiconductor waveguide layer 106 is formed on the base dielectric layer 104 and the base semiconductor layer 102 by epitaxial growth or other suitable processes to deposit a semiconductor on the base dielectric layer 104. In some other embodiments, the semiconductor waveguide layer 106, the base dielectric layer 104, and the base semiconductor layer 102 are provided as an SOI substrate.

[0051] In some embodiments, the semiconductor waveguide layer 106 comprises intrinsic silicon, lightly doped (e.g., p-) silicon, or some other suitable semiconductor. In some embodiments, the base dielectric layer 104 comprises silicon dioxide or some other suitable dielectric material. In some embodiments, the base semiconductor layer 102 comprises silicon or some other suitable semiconductor.

[0052] As shown in the cross-sectional view 1900 of FIG19, the semiconductor waveguide layer 106 is etched to define the core portion 114 and pickup portions 110, 112 above the base portion 108. This etching forms laterally spaced first trenches 1902 and second trenches 1904 in the semiconductor waveguide layer 106 to form the core portion 114 and the pickup portions 110, 112 spaced apart from the core portion 114. The etching extends into the semiconductor waveguide layer 106 but does not penetrate it, such that the base portion 108 remains between the core portion 114 and the pickup portions 110, 112, so that heat can be transferred from the pickup portions 110, 112 to the core portion 114 through the thermally conductive base portion 108.

[0053] In some embodiments, a mask layer 1906 is formed over a portion of the semiconductor waveguide layer 106, and etched according to the mask layer 1906. In some embodiments, the etching includes a dry etching process (e.g., a plasma etching process, a reactive ion etching process, an ion beam etching process, or a similar process), a wet etching process, or some other suitable process. In some embodiments, the mask layer includes a photoresist mask layer, a hard mask layer, or some other suitable mask layer.

[0054] As shown in the cross-sectional view 2000 of FIG20, the semiconductor waveguide layer 106 is doped to form doped regions 402, 404, 406, and 408 in the semiconductor waveguide layer 106. The first doped region 402 and the third doped region 406 are doped to have a first doping type (e.g., n-type). The second doped region 404 and the fourth doped region 408 are doped to have a second doping type (e.g., p-type). The third doped region 406 is doped to have a doping concentration substantially higher than that of the first doped region 402. The fourth doped region 408 is doped to have a doping concentration substantially higher than that of the second doped region 404. In some embodiments, regions 410 of the semiconductor waveguide layer 106 remain undoped (or retain any doping present when the semiconductor waveguide layer 106 was initially formed).

[0055] As shown in the cross-sectional view 2100 of FIG21, a first dielectric layer 116 is deposited on the semiconductor waveguide layer 106. The first dielectric layer 116 fills the first trench 1902 and the second trench 1904. In some embodiments, the first dielectric layer 116 comprises silicon dioxide or some other suitable material and is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or some other suitable process.

[0056] As shown in the cross-sectional view 2200 of FIG22, a first dielectric layer 116 is removed over the core portion 114 and pickup portions 110, 112 of the semiconductor waveguide layer 106. In some embodiments, removing the first dielectric layer 116 from the core portion 114 and pickup portions 110, 112 includes performing a planarization process (e.g., chemical mechanical planarization (CMP) or a similar process) on the first dielectric layer 116 and the semiconductor waveguide layer 106, such that the top of the semiconductor waveguide layer 106 and the top of the first dielectric layer 116 are substantially coplanar. In some other embodiments, removing the first dielectric layer 116 from the core portion 114 and pickup portions 110, 112 includes performing a blanket etch-back process on the first dielectric layer 116 until the top of the core portion 114 and pickup portions 110, 112 is exposed.

[0057] In some embodiments, the first dielectric layer 116 is not completely removed from the core portion and the pickup portions 110, 112, so as shown in FIG17, a portion of the first dielectric layer 116 remains on top of the core portion 114 and the pickup portions 110, 112.

[0058] As shown in the cross-sectional view 2300 of FIG23, a second dielectric layer 118 (e.g., a resist-protected dielectric layer) is deposited on the semiconductor waveguide layer 106 and the first dielectric layer 116. In some embodiments, the second dielectric layer 118 comprises silicon dioxide, silicon nitride, or some other suitable dielectric material and is deposited by a CVD process, PVD process, ALD process, or some other suitable process to have a substantially small thickness (e.g., less than about 500 nanometers, ranging from about 1 nanometer to 500 nanometers, or some other suitable thickness). For example, the thickness of the second dielectric layer 118 is less than the width of the first trench 1902 (less than the distance between the first pickup portion 110 and the core portion 114) and / or less than the width of the second trench 1904 (less than the distance between the second pickup portion 112 and the core portion 114).

[0059] As shown in the cross-sectional view 2400 of FIG24, a second dielectric layer 118 is etched to define the second dielectric layer 118. This etching removes the second dielectric layer 118 from the partial pick-up portions 110, 112. In some embodiments, a mask layer 2402 is formed over a portion of the second dielectric layer 118, and etching is performed based on the mask layer 2402. In some embodiments, the etching includes a dry etching process, a wet etching process, or some other suitable process.

[0060] As shown in the cross-sectional view 2500 of FIG25, a silicon layer 504 is formed along the exposed top of the first pickup portion 110, and a silicon layer 506 is formed along the exposed top of the second pickup portion 112. In some embodiments, the silicon layers 504, 506 are formed by depositing a conductive layer (e.g., a layer containing nickel, tungsten, titanium, or similar materials) on the exposed top of the pickup portions 110, 112, performing a first annealing process to form silicon layers 504, 506 from the conductive layer and the semiconductor waveguide layer 106 along the top of the pickup portions 110, 112, removing the remaining conductive layer from the silicon layers 504, 506 (e.g., by a selective etching process or some other suitable process), and performing a second annealing process to ensure that the remaining conductive layer is formed as silicon layers 504, 506.

[0061] As shown in the cross-sectional view 2600 of FIG26, an etch stop layer 502 is conformally deposited on the second dielectric layer 118 and silicon layers 504, 506. The etch stop layer 502 includes silicon dioxide, silicon nitride, silicon carbide, metal oxide (e.g., aluminum oxide or the like) or some other suitable material, and is deposited by CVD process, PVD process, ALD process or some other suitable process.

[0062] As shown in the cross-sectional view 2700 of FIG27, a third dielectric layer 120 (e.g., an interlayer dielectric layer) is deposited on the etch stop layer 502. The third dielectric layer 120 comprises silicon dioxide or some other suitable dielectric material and is deposited by a CVD process, a PVD process, an ALD process or some other suitable process.

[0063] Figures 28-31 show cross-sectional views 2800-3100 of some embodiments of a method for forming a heater on a semiconductor waveguide layer 106.

[0064] As shown in the cross-sectional view 2800 of FIG28, the third dielectric layer 120 is etched to form a first heater electrode opening 2802 and a second heater electrode opening (not shown) in the third dielectric layer 120. In some embodiments, a mask layer 2804 is formed over a portion of the third dielectric layer 120, and etching is performed based on the mask layer 2804. In some embodiments, etching includes a dry etching process, a wet etching process, or some other suitable process.

[0065] As shown in the cross-sectional view 2900 of FIG29, the third dielectric layer 120 and the etch stop layer 502 are etched to form a first heat radiator opening 2902 and a second heat radiator opening 2904 in the third dielectric layer 120 and the etch stop layer 502. This etching exposes a portion of the second dielectric layer 118. In some embodiments, the heat radiator openings 2902 and 2904 extend from the first heater electrode opening 2802 to the second heater electrode opening (not shown) along different paths. In some embodiments, the etching extends into the second dielectric layer 118, as shown by the dashed line 2908.

[0066] In some embodiments, a mask layer 2906 is formed over a portion of the third dielectric layer 120, and etching is performed based on the mask layer 2906. In some embodiments, the etching includes a first etching process for etching the third dielectric layer 120 and a second etching process for etching the etch stop layer 502 to expose the second dielectric layer 118. In some embodiments, these etching processes include a dry etching process or some other suitable process.

[0067] As shown in the cross-sectional view 3000 of FIG30, a first thermal radiator 122 is formed in a first thermal radiator opening 2902, a second thermal radiator 124 is formed in a second thermal radiator opening 2904, a first heater electrode 708 is formed in a first heater electrode opening 2802, and a second heating electrode (not shown) is formed in a second heater electrode opening (not shown). The thermal radiators 122, 124, the first heater electrode 708, and the second heating electrode (not shown) are formed by depositing a metal (e.g., tungsten, titanium, copper, or the like), silicon, silicate, or some other suitable material in their respective openings, by means of a CVD process, a PVD process, an ALD process, or some other suitable process, followed by a planarization process.

[0068] As shown in the cross-sectional view 3100 of FIG31, a first waveguide contact (not shown) and a second waveguide contact 604 are formed on the silicate layers 504 and 506 at the pickup portions 110 and 112, respectively. The waveguide contact is formed by etching a third dielectric layer 120 and an etch stop layer 502 to form an opening on the silicate layer, depositing a conductive material (e.g., tungsten, titanium, copper or the like) in the opening by a CVD process, a PVD process, an ALD process or some other suitable process, followed by a planarization process.

[0069] Figures 32-34 show cross-sectional views 3200-3400 of some embodiments of a method for forming a heater on a waveguide.

[0070] As shown in the cross-sectional view 3200 of FIG32, the third dielectric layer 120 is etched to form a heater bridge opening 3202 in the third dielectric layer 120. In some embodiments, a mask layer 3204 is formed over a portion of the third dielectric layer 120, and etching is performed on the mask layer 3204. In some embodiments, the etching forms a heater electrode opening (not shown).

[0071] As shown in the cross-sectional view 3300 of FIG33, a third dielectric layer 120 and an etch stop layer 502 are etched to form a first thermal radiator opening 3302 and a second thermal radiator opening 3304 in the third dielectric layer 120 and the etch stop layer 502. The etching exposes a portion of the second dielectric layer 118. In some embodiments, the etching extends into the second dielectric layer 118. In some embodiments, a mask layer 3306 is formed over a portion of the third dielectric layer 120, and etching is performed according to the mask layer 3306. In some embodiments, the first thermal radiator opening 3302 extends from a first heater electrode opening (not shown) to a heater bridge opening 3202, and the second thermal radiator opening 3304 extends from the heater bridge opening 3202 to a second heater electrode opening (not shown).

[0072] As shown in the cross-sectional view 3400 of FIG34, heat radiators 122 and 124 are formed in heat radiator openings 3302 and 3304, heater bridge 1202 is formed in bridge opening 3202, and heater electrode (not shown) is formed in heater electrode opening (not shown). The heat radiators 122 and 124 and heater bridge 1202 are formed by depositing metal (e.g., tungsten, titanium, copper, or the like), silicon, silicate, or some other suitable material in their respective openings through CVD, PVD, ALD, or some other suitable process, followed by a planarization process.

[0073] In some embodiments, waveguide contacts 602 and 604 are formed on the silicate layers 504 and 506 at the pickup portions 110 and 112, respectively.

[0074] Figure 35 shows a flowchart of some embodiments of a method 3500 for forming an integrated wafer including a heater over a waveguide. While method 3500 is shown and described as a series of actions or events, it should be understood that the order of these actions or events shown should not be construed as limiting. For example, some actions may occur in a different order than those shown and / or described herein and / or simultaneously with other actions or events. Furthermore, not all actions shown may require the implementation of one or more aspects or embodiments described herein. Moreover, one or more actions described herein may be performed in one or more individual actions and / or stages.

[0075] In block 3502, a core portion, a first pickup portion, and a second pickup portion are formed on the base portion of the semiconductor waveguide layer. Figure 19 shows a cross-sectional view 1900 corresponding to some embodiments of block 3502.

[0076] In block 3504, a dielectric layer is deposited over the core portion, the first pickup portion, and the second pickup portion of the semiconductor waveguide layer. Figure 23 shows a cross-sectional view 2300 corresponding to some embodiments of block 3504.

[0077] In block 3506, a first thermal radiator is formed on a first pickup portion of the dielectric layer and the semiconductor waveguide layer. Figure 30 shows a cross-sectional view 3000 corresponding to some embodiments of block 3506. Figure 34 shows a cross-sectional view 3400 corresponding to some other embodiments of block 3506.

[0078] In block 3508, a second thermal radiator is formed on the second pickup portion of the dielectric layer and the semiconductor waveguide layer. Figure 30 shows a cross-sectional view 3000 corresponding to some embodiments of block 3508. Figure 34 shows a cross-sectional view 3400 corresponding to some other embodiments of block 3508.

[0079] In block 3510, in some embodiments, a heater bridge is formed and coupled to the first and second thermal radiators. Figure 34 shows a cross-sectional view 3400 corresponding to some embodiments of block 3510.

[0080] Therefore, this disclosure relates to a heater on a waveguide, wherein the lateral distance between the heater and the core of the waveguide is increased, while the vertical distance between the heater and the waveguide is decreased, so as to improve the efficiency of the heater and the reliability of the integrated wafer, without increasing the optical loss of the core.

[0081] Therefore, in some embodiments, this disclosure relates to an integrated wafer including a semiconductor waveguide layer on a substrate. A core portion of the semiconductor waveguide layer projects upward from a base portion of the semiconductor waveguide layer. A first thermal radiator is spaced apart on the semiconductor waveguide layer and laterally spaced apart from the core portion in a first direction. A second thermal radiator is spaced apart on the semiconductor waveguide layer and laterally spaced apart from the core portion in a second direction different from the first direction. A first dielectric layer is located between the first thermal radiator and the semiconductor waveguide layer and between the second thermal radiator and the semiconductor waveguide layer. The distance between the first thermal radiator and the semiconductor waveguide layer is less than the distance between the first thermal radiator and the core portion. The distance between the second thermal radiator and the semiconductor waveguide layer is less than the distance between the second thermal radiator and the core portion.

[0082] In other embodiments, this disclosure relates to an integrated wafer including a semiconductor waveguide layer on a substrate. A first pickup portion of the semiconductor waveguide layer protrudes upward from a base portion of the semiconductor waveguide layer. A second pickup portion of the semiconductor waveguide layer protrudes upward from the base portion and is laterally spaced from the first pickup portion. A core portion of the semiconductor waveguide layer protrudes upward from the base portion and is laterally spaced between the first pickup portion and the second pickup portion. A protective dielectric layer is located over the first pickup portion, the second pickup portion, and the core portion. An interlayer dielectric (ILD) layer is located over the protective dielectric layer. A first thermal radiator and a second thermal radiator are located within the interlayer dielectric layer. The first thermal radiator is spaced apart from and separated from the first pickup portion by the protective dielectric layer over the first pickup portion. The second thermal radiator is spaced apart from and separated from the second pickup portion by the protective dielectric layer over the second pickup portion.

[0083] In yet another embodiment, this disclosure relates to a method of forming an integrated wafer. The method includes etching a semiconductor waveguide layer to define a first pickup portion, a second pickup portion, and a core portion of the semiconductor waveguide layer. The first pickup portion projects upward from a base portion of the semiconductor waveguide layer. The second pickup portion projects upward from the base portion and is laterally spaced from the first pickup portion. The core portion of the semiconductor waveguide layer projects upward from the base portion and is laterally spaced between the first and second pickup portions. The method includes depositing a first dielectric layer over the first pickup portion, the second pickup portion, and the core portion of the semiconductor waveguide layer. The method includes depositing a second dielectric layer over the first dielectric layer. The method includes etching the second dielectric layer to expose a first upper surface of the first dielectric layer over the first pickup portion and a second upper surface of the first dielectric layer over the second pickup portion. The method includes forming a first thermal radiator on the first upper surface of the first dielectric layer and forming a second thermal radiator on the second upper surface of the first dielectric layer.

[0084] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The nature of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 shows a cross-sectional view of some embodiments of an integrated wafer including a heater over a waveguide. Figures 2-3 show top views of some embodiments of the integrated wafer of Figure 1. Figures 4-6 show cross-sectional views of some other embodiments of the integrated wafer of Figure 1. Figure 7 shows a top view of some embodiments of an integrated wafer including a heater over a waveguide, wherein the waveguide forms a ring modulator. Figures 8-9 show cross-sectional views of some embodiments of the integrated wafer of Figure 7. Figures 10-11 show cross-sectional views of some other embodiments of the integrated wafer of Figures 7-9. Figure 12 shows a top view of some other embodiments of the integrated wafer of Figure 7. Figures 13-14 show cross-sectional views of some embodiments of the integrated wafer of Figure 12. Figures 15-16 show top views of some other embodiments of the integrated wafer of Figure 12. Figure 17 shows a cross-sectional view of some other embodiments of the integrated wafer of Figures 1-16. Figures 18-34 show cross-sectional views of some embodiments of a method for forming an integrated wafer including a heater over a waveguide. Figure 35 shows a flowchart of some embodiments of a method for forming an integrated wafer including a heater over a waveguide.

Claims

1. An integrated chip, comprising: A semiconductor waveguide layer is located on a substrate, with the core portion of the semiconductor waveguide layer protruding upward from the base portion of the semiconductor waveguide layer. A first thermal radiator is spaced apart on the semiconductor waveguide layer and laterally spaced apart from the core portion in a first direction; The second thermal radiator is spaced apart on the semiconductor waveguide layer and laterally spaced apart from the core portion in a second direction different from the first direction; And a first dielectric layer, located between the first thermal radiator and the semiconductor waveguide layer and between the second thermal radiator and the semiconductor waveguide layer, wherein the distance between the first thermal radiator and the semiconductor waveguide layer is less than the distance between the first thermal radiator and the core portion, wherein the distance between the second thermal radiator and the semiconductor waveguide layer is less than the distance between the second thermal radiator and the core portion.

2. The integrated wafer as claimed in claim 1, wherein a first pickup portion of the semiconductor waveguide layer protrudes upward from the base portion and is laterally spaced from the core portion in the first direction, wherein a second pickup portion of the semiconductor waveguide layer protrudes upward from the base portion and is laterally spaced from the core portion in the second direction, and wherein a first thermal radiator is located directly above the first pickup portion, and a second thermal radiator is located directly above the second pickup portion.

3. The integrated wafer as claimed in claim 2, wherein the distance between the first thermal radiator and the first pickup portion is less than the distance between the first thermal radiator and the core portion, and wherein the distance between the second thermal radiator and the second pickup portion is partially less than the distance between the second thermal radiator and the core portion.

4. The integrated wafer as claimed in claim 2, wherein the semiconductor waveguide layer includes a first doped region located in the core portion and a second doped region located in the core portion and adjacent to the first doped region, wherein the semiconductor waveguide layer includes a third doped region located in the first pickup portion and a fourth doped region located in the second pickup portion, the first doped region and the third doped region having a first doping type, and the second doped region and the fourth doped region having a second doping type different from the first doping type.

5. The integrated wafer of claim 2, wherein the core portion extends in a ring shape to form the core of a ring modulator, wherein the first pickup portion is surrounded by the core portion and the second pickup portion partially surrounds the core portion and the first pickup portion, wherein the first thermal radiator extends in an arc shape over the first pickup portion along the outer periphery of the first pickup portion, and wherein the second thermal radiator extends in an arc shape over the second pickup portion along the inner periphery of the second pickup portion.

6. The integrated wafer as claimed in claim 1, further comprising: The first heater electrode is spaced apart on the semiconductor waveguide layer and extends from the first thermal radiator to the second thermal radiator; And a second heater electrode, spaced apart on the semiconductor waveguide layer and extending from the first thermal radiator to the second thermal radiator, wherein the first heater electrode and the second heater electrode are coupled in parallel to the first thermal radiator and the second thermal radiator.

7. The integrated wafer as claimed in claim 1, further comprising: The first heater electrode is spaced apart on the semiconductor waveguide layer and coupled to the first thermal radiator; The second heater electrode is spaced apart on the semiconductor waveguide layer and coupled to the second thermal radiator; and a first heater bridge, spaced apart above the semiconductor waveguide layer and extending from the first thermal radiator to the second thermal radiator above the core portion, wherein the first thermal radiator is coupled in series between the first heater electrode and the first heater bridge, the first heater bridge is coupled in series between the first thermal radiator and the second thermal radiator, and the second thermal radiator is coupled in series between the first heater bridge and the second heater electrode.

8. The integrated wafer as claimed in claim 7, further comprising: A third thermal radiator is spaced apart above the semiconductor waveguide layer and laterally spaced apart from the core portion; And a second heater bridge, spaced apart above the semiconductor waveguide layer and extending from the second thermal radiator to the third thermal radiator above the core portion, wherein the second thermal radiator is coupled in series between the first heater bridge and the second heater bridge, the second heater bridge is coupled in series between the second thermal radiator and the third thermal radiator, and the third thermal radiator is coupled in series between the first heater bridge and the second heater electrode.

9. An integrated chip, comprising: A semiconductor waveguide layer is located on a substrate. A first pickup portion of the semiconductor waveguide layer protrudes upward from a base portion of the semiconductor waveguide layer. A second pickup portion of the semiconductor waveguide layer protrudes upward from the base portion and is laterally spaced from the first pickup portion. A core portion of the semiconductor waveguide layer protrudes upward from the base portion and is laterally spaced between the first pickup portion and the second pickup portion. A protective dielectric layer is located above the first pickup portion, the second pickup portion, and the core portion; an interlayer dielectric (ILD) layer is located above the protective dielectric layer. The first thermal radiator and the second thermal radiator are located within the interlayer dielectric layer. The first thermal radiator is spaced apart from and separated from the first pickup portion by the protective dielectric layer, and the second thermal radiator is spaced apart from and separated from the second pickup portion by the protective dielectric layer.

10. A method of forming an integrated wafer, comprising: A semiconductor waveguide layer is etched to define a first pickup portion, a second pickup portion, and a core portion of the semiconductor waveguide layer. The first pickup portion protrudes upward from a base portion of the semiconductor waveguide layer, the second pickup portion protrudes upward from the base portion and is laterally spaced from the first pickup portion, and the core portion of the semiconductor waveguide layer protrudes upward from the base portion and is laterally spaced between the first pickup portion and the second pickup portion. A first dielectric layer is deposited on the first pickup portion, the second pickup portion, and the core portion of the semiconductor waveguide layer; The second dielectric layer is deposited on top of the first dielectric layer; The second dielectric layer is etched to expose the first upper surface of the first dielectric layer over the first pickup portion and the second upper surface of the first dielectric layer over the second pickup portion; A first thermal radiator is formed on the first upper surface of the first dielectric layer, and a second thermal radiator is formed on the second upper surface of the first dielectric layer.

Images