Semiconductor structure and method for forming the same

Abstract

The method includes forming a dummy gate stack on a first protruding structure of a wafer, wherein the first protruding structure includes a first semiconductor layer; etching the dummy gate stack to form a trench in the dummy gate stack and expose the first semiconductor layer; removing the first semiconductor layer and a semiconductor strip below the first semiconductor layer to extend the trench downward; filling the trench with a dielectric material to form a dielectric isolation region; performing a back-side polishing process on the semiconductor substrate of the wafer to expose the dielectric isolation region from the back side of the wafer; and forming a back-side dielectric layer on the back side of the wafer, wherein the back-side dielectric layer contacts the dielectric isolation region.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor structures and methods of forming thereof. [Previous Technology]

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate. These material layers can also be patterned using lithography techniques to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest feature, enabling more components to be integrated into a given area. However, as the size of the smallest feature is reduced, additional problems arise that need to be addressed. [Summary of the Invention]

[0004] In some embodiments, a method for forming a semiconductor structure is provided, the method comprising forming a dummy gate stack on a first protruding structure of a wafer, wherein the first protruding structure includes a first semiconductor layer; etching the dummy gate stack to form a trench in the dummy gate stack and expose the first semiconductor layer; removing the first semiconductor layer and a semiconductor strip below the first semiconductor layer to extend the trench downward; filling the trench with a dielectric material to form a dielectric isolation region; performing a back-side polishing process on a semiconductor substrate of the wafer, wherein the dielectric isolation region is exposed from the back side of the wafer; and forming a back-side dielectric layer on the back side of the wafer, wherein the back-side dielectric layer contacts the dielectric isolation region.

[0005] In some embodiments, a method for forming a semiconductor structure is provided. This method includes a first plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the first plurality of semiconductor nanostructures overlaps with a lower semiconductor nanostructure of a corresponding first plurality of semiconductor nanostructures; a first gate stack located on the first plurality of semiconductor nanostructures; and a second plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the second plurality of semiconductor nanostructures overlaps with a lower semiconductor nanostructure of a corresponding second plurality of semiconductor nanostructures. The second gate stack is located on the second plurality of semiconductor nanostructures; the first shallow trench isolation region and the second shallow trench isolation region are located below the first plurality of semiconductor nanostructures and the second plurality of semiconductor nanostructures; the dielectric isolation region is located between and in contact with the first gate stack and the second gate stack, and is located between and in contact with the first shallow trench isolation region and the second shallow trench isolation region; and the back dielectric layer is located below the dielectric isolation region and in contact with the dielectric isolation region.

[0006] In some other embodiments, a semiconductor structure is provided, the semiconductor structure including a first transistor including a first gate stack; a second transistor including a second gate stack, wherein in a top view of the semiconductor structure, the longitudinal directions of the first gate stack and the second gate stack are aligned with the same straight line; a first shallow trench isolation region overlapping the first gate stack; a second shallow trench isolation region overlapping the second gate stack; a dielectric isolation region including: an upper portion separating the first gate stack and the second gate stack; and a lower portion separating the first shallow trench isolation region and the second shallow trench isolation region, wherein the entire dielectric isolation region is formed of a homogeneous dielectric material; and a back-side dielectric layer located below the lower portion of the dielectric isolation region and contacting the lower portion of the dielectric isolation region.

Implementation Method

[0008] It is important to understand that the following content provides many different embodiments or examples for implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the description. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment disclosed herein, but may depend on the processing conditions and / or required nature of the components. Furthermore, in the following description, embodiments in which the first component is formed above or on the second component include those where the first and second components are in direct contact, and embodiments in which additional components may be formed between the first and second components so that the first and second components are not in direct contact. In addition, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0009] Furthermore, to facilitate the description of the relationship between one element or component and another (plural) element or component in the diagram, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms may be used. In addition to the orientation shown in the diagram, spatially related terms also cover different orientations of the device during use or operation. The device may also be positioned elsewhere (e.g., rotated 90 degrees or located in other orientations), and the description of the spatially related terms used will be interpreted accordingly.

[0010] A continuous polysilicon (CPODE) isolation region (which may be a dielectric isolation region) on a diffusion edge is provided, and a method for forming the same. According to some embodiments of the invention, a single-layer continuous polysilicon isolation region on a diffusion edge is formed. The single-layer continuous polysilicon isolation region on a diffusion edge may be without an oxide pad. According to some embodiments, wherein the sacrificial layer between the Gate-All-Around (GAA) transistors is formed of oxide, if the continuous polysilicon isolation region on the diffusion edge includes an oxide pad, the oxide pad may be damaged when the sacrificial layer is removed, leading to leakage problems. According to some embodiments of the invention, the continuous polysilicon isolation region on the diffusion edge is formed by using a dielectric material different from the material of the sacrificial layer.

[0011] Although this document discusses fully wound gate transistors to explain the concepts of embodiments of the invention, embodiments of the invention are applicable to other types of transistors, including but not limited to planar transistors, FinFETs, Complementary Field-Effect Transistors (CFETs), and the like. The embodiments discussed herein provide examples of how the subject matter can be implemented or used, and modifications that can be made will be readily understood by those skilled in the art while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, similar reference numerals are used to label similar elements. Although method embodiments may be discussed in a particular order, other method embodiments may be performed in any logical order.

[0012] Figures 1 to 20A and 20B show schematic cross-sectional views of intermediate stages in forming a fully wound gate transistor and a continuous polysilicon isolation region on the diffusion edge, according to some embodiments. The corresponding process is also schematically reflected in the process flow shown in Figure 26.

[0013] Please refer to Figure 1, which shows a perspective view of the wafer. The wafer 10 includes a multilayer structure, which includes a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, or the like, but other substrates and / or structures may also be used, such as semiconductor-on-insulator (SOI), strained semiconductor-on-insulator, silicon-germanium on-insulator, or the like. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments, the substrate 20 may be doped as an n-type semiconductor.

[0014] According to some embodiments, the multilayer stack 22 is formed through a series of deposition processes involving alternating materials. The corresponding process is shown in process 202 in process flow 200. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0015] According to some embodiments, the first semiconductor material of the first layer 22A is formed from or includes semiconductors such as SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. According to some embodiments, the first layer 22A (e.g., SiGe) is deposited through epitaxial growth, and the corresponding deposition method may be vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), ultra-high vacuum chemical vapor deposition (UHVCVD), reduced-pressure chemical vapor deposition (RPCVD), or similar methods. According to some embodiments, the first layer 22A is formed to a first thickness in the range of about 30 Å to about 300 Å. However, any suitable thickness can be used while remaining within the range of the embodiments.

[0016] After the first layer 22A is deposited over the substrate 20, a second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, where the second semiconductor material differs from the first semiconductor material of the first layer 22A. For example, according to some embodiments, the first layer 22A is silicon-germanium, and the second layer 22B is formed of silicon, or vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0017] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a thickness different from that of the first layer 22A. According to some embodiments, for example, the first layer 22A has a thickness in the range of about 4 nm to about 7 nm, while the second layer 22B has a thickness in the range of about 8 nm to about 12 nm.

[0018] After the second layer 22B is formed over the first layer 22A, the deposition process is repeated to form the remaining layers of the multilayer stack 22 until the desired top layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thickness, and the second layers 22B have the same or similar thickness. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process, and in this description, the first layer 22A may alternatively be referred to as a sacrificial layer. According to some other embodiments, the second layer 22B is a sacrificial layer, and the second layer 22B is removed in a subsequent process.

[0019] According to some embodiments, some pad oxide layers and hard mask layers may be formed on the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0020] Referring to Figure 2, a portion of the multilayer stack 22 and the underlying substrate 20 is patterned during the etching process to form a trench 23. This corresponds to process 204 of process flow 200 shown in Figure 26. The trench 23 extends into the substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as the multilayer stack 22'. Below the multilayer stack 22', a portion of the substrate 20 is retained; these portions are hereinafter referred to as substrate strips 20'. The multilayer stack 22' comprises a first layer 22A and a second layer 22B. The first layer 22A is also alternatively referred to as a sacrificial layer, and the second layer is hereinafter also alternatively referred to as a nanostructure. These portions of the multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strips 24.

[0021] In the above embodiments, the fully wound gate transistor structure can be patterned by any suitable method. For example, these structures can be patterned using one or more photolithography processes (including dual patterning or multiple patterning processes). Generally, dual patterning or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fully wound gate transistor structure.

[0022] Figure 3 shows the formation of isolation region 26, which is also referred to herein as a shallow trench isolation (STI) region. This corresponds to process 206 of process flow 200 shown in Figure 26. Isolation region 26 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of substrate 20 or by deposition. The pad oxide may also be a deposited silicon oxide layer formed using atomic layer deposition, high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition, or similar methods. Isolation region 26 may also include a dielectric material above the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, high-density plasma chemical vapor deposition, or similar methods. Next, a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical polishing process) can be performed to make the top surface of the dielectric material flush with the remaining portion of the dielectric material in the isolation region 26.

[0023] Next, the isolation region 26 is recessed such that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the isolation region 26 to form a fin 28 (sometimes referred to as a protruding fin). The fin 28 comprises the top of the multilayer stack 22' and the substrate strip 20'. The recess of the isolation region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. Plasma can be generated during the etching process. Argon gas may also be included. In some other failures according to the invention, the recess of the isolation region 26 is performed by a wet etching process. The etching chemicals may include, for example, HF.

[0024] Referring to Figure 4, a dummy gate stack 30 and a gate spacer wall 38 are formed on the top surface and sidewalls of the fin 28. This corresponds to process 208 of process flow 200 shown in Figure 26. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by partially oxidizing the surface of the fin 28 to form an oxide layer, or by depositing a dielectric layer (e.g., a silicon oxide layer). The dummy gate electrode 34 may be formed, for example, using polycrystalline silicon or amorphous silicon, and may also use other materials, such as amorphous carbon.

[0025] Each dummy gate stack 30 may also include one (or a plurality of) hard masking layers 36 above the dummy gate electrode 34. The hard masking layer 36 may be formed of silicon nitride, silicon oxide, silicon carbide, silicon carbide oxide, or a multilayer thereof. The dummy gate stack 30 may span a single or a plurality of fins 28 and the isolation region 26 between the fins 28. The dummy gate stack 30 may have a longitudinal direction perpendicular to the longitudinal direction of the fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer above the dummy gate dielectric layer, depositing one or more hard masking layers, and then patterning these layers through a patterning process.

[0026] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of the present invention, the gate spacer 38 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon oxide (SiO2), silicon carbide nitride (SiCN), silicon oxynitride (SiON), silicon oxynitride carbon (SiOCN), or the like, and may have a single-layer structure or a multilayer structure comprising multiple dielectric layers. The formation process of the gate spacer 38 may include depositing one or more dielectric layers, followed by an anisotropic etching process on the dielectric layers. The remaining portion of the dielectric layers constitutes the gate spacer 38.

[0027] Figures 5A and 5B show cross-sectional schematic diagrams of the structure in Figure 4. Figure 5A shows a reference section AA of Figure 4, which cuts through the portion of fin 28 not covered by the dummy gate stack 30 and the gate gap wall 38, and is perpendicular to the gate length direction. The fin gap wall 39 on the sidewall of fin 28 is also shown. Figure 5B shows a reference section BB of Figure 4, which is parallel to the longitudinal direction of fin 28.

[0028] Please refer to Figures 6A and 6B to show the source / drain recess process. The corresponding process is shown in process 210 of process flow 200 in Figure 26. In the anisotropic etching process, the fins 28 not directly below the dummy gate stack 30 and the gate gap wall 38 are etched to form the source / drain recess 42.

[0029] Figures 7A, 7B, 8A, and 8B show the first layer 22A replaced by a disposable interposer layer 29. Referring to Figures 7A and 7B, first remove the first layer 22A, and then form an opening 27 between the second layers 22B. This corresponds to process 212 in process flow 200 shown in Figure 26.

[0030] Referring to Figures 8A and 8B, a disposable interposer 29 is formed between the second layers 22B. This corresponds to process 214 of process flow 200 shown in Figure 26. According to some embodiments, the disposable interposer 29 comprises an oxide, such as silicon oxide, and is therefore also referred to as a disposable oxide interposer (DOI). According to some other embodiments, the disposable interposer 29 may comprise other types of dielectric materials, such as AlO, SiON, SiC, SiCN, or the like.

[0031] The formation of the disposable interposer 29 may include depositing a dielectric layer using a conformal deposition process, such that the dielectric layer includes a portion filling the opening 27 and other portions outside the opening 27. Next, a trimming process (which may include an isotropic etching process or an isotropic etching process followed by an isotropic etching process) is performed to etch or remove portions of the dielectric layer outside the opening 27. The remaining portion of the dielectric layer forms the disposable interposer 29.

[0032] Referring to Figures 9A and 9B, a laterally recessed polishable interposer layer 29 is formed, and the recess is filled with a dielectric material to create an internal spacer wall 44 (Figure 9B). This corresponds to process 216 of process flow 200 shown in Figure 26. The lateral recess of the polishable interposer layer 29 can be achieved through a wet etching process or a dry etching process. The wet etching process can be performed using a dip-plating process, a spray plating process, a spin-coating process, or a similar method. The second layer 22B is not etched.

[0033] After the lateral recess, an internal spacer wall 44 is formed. According to some embodiments, the formation of the internal spacer wall 44 includes depositing a compliant dielectric layer that extends into the lateral recess. Next, an etching process (also known as a spacer wall trimming process) is performed to trim the portion of the dielectric layer outside the lateral recess, retaining the portion of the dielectric layer within the lateral recess. The remaining portion of the dielectric layer is referred to as the internal spacer wall 44.

[0034] Referring to Figures 10A and 10B, the epitaxial source / drain region 48 is formed in the source / drain recess 42 through selective epitaxy. This corresponds to process 218 of process flow 200 shown in Figure 26. Depending on whether the final transistor is a p-type or n-type transistor, p-type or n-type impurities can be doped in situ during epitaxy. For example, when the final transistor is a p-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), or similar materials can be grown. Conversely, when the final transistor is an n-type transistor, silicon phosphide (SiP), silicon carbon phosphide (SiCP), or similar materials can be grown.

[0035] Figures 11A and 11B show cross-sectional schematic diagrams of the structure after the formation of the Contact Etch Stop Layer (CESL) 50 and the Inter-Layer Dielectric (ILD) 52. The corresponding process is shown in process 220 of process flow 200 in Figure 26. The Contact Etch Stop Layer 50 may be formed of silicon oxide, silicon nitride, silicon carbide nitride, or the like, and may be formed using chemical vapor deposition, atomic layer deposition, or similar methods. The Inter-Layer Dielectric 52 may contain a dielectric material and may be formed using, for example, flowable chemical vapor deposition, spin coating, chemical vapor deposition, or any other suitable deposition method. The interlayer dielectric 52 may be formed of an oxygen-containing dielectric material, which may include silica, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like.

[0036] The contact etch stop layer 50 and the interlayer dielectric 52 are planarized through a planarization process (e.g., chemical mechanical polishing or mechanical polishing). According to some embodiments, the planarization process may remove the hard mask layer 36 to expose the dummy gate electrode 34, as shown in Figures 11A and 11B. According to some other embodiments, the planarization process may expose or stop at the hard mask layer 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask layer 36), the gate spacer wall 38, and the interlayer dielectric 52 are flush within the process variation range.

[0037] Figure 12 shows a top view of the structure shown in Figures 11A and 11B according to some embodiments. The multilayer stack 22', the substrate strip 20', and the fin 28 (refer to Figure 11A) have a longitudinal orientation in the X direction, and the corresponding cross-sectional view is referred to as the X-section view. The dummy gate stack 30 (including dummy gate electrodes 34 (e.g., polycrystalline silicon strips)) has a longitudinal orientation in the Y direction, and the corresponding cross-sectional view is referred to as the Y-section view. Epitaxial source / drain regions 48 are formed on some portions of the multilayer stack 22' (as shown in Figure 11B). The edges of the source / drain regions may contact or be spaced apart from the gate spacer wall 38. Although shown as epitaxial source / drain regions 48 formed on the fin 28, some adjacent epitaxial source / drain regions 48 may merge together.

[0038] Figures 13A and 13B respectively show a top view and a cross-sectional view of the hard mask 54 formed according to some embodiments. Figure 13B shows cross-sections 13B-13B of Figure 13A. As shown in Figure 13B, the hard mask 54 is formed above the dummy gate electrode 34. The hard mask 54 may include materials such as SiN, silicon (e.g., amorphous silicon), TiN, BN, or the like, or multiple layers thereof. A patterned etch mask 58 is formed above the hard mask 54. According to some embodiments, the etch mask 58 includes photoresist and may have a single-layer structure, a three-layer structure, or the like. The etch mask 58 is patterned.

[0039] The hard mask 54 is etched using an etch mask 58 to define a pattern and form an opening 56 that exposes the dummy gate electrode 34. As shown in the top view of Figure 13A, the opening 56 may be elongated and directly above a dummy gate electrode 34. Furthermore, the opening 56 is above and spans one or more multilayer stacks 22'. The opening 56 may have a longer edge aligned with the interface between the dummy gate stack 30 and the gate spacer 38, or it may overlap with the gate spacer 38, or it may overlap or not overlap with the contact etch stop layer 50 and the interlayer dielectric 52. After the hard mask 54 is patterned, the etch mask 58 may be removed (or not removed).

[0040] Next, the dummy gate electrode 34 below is etched using a hard mask 54 until the dummy gate dielectric 32 is exposed. Then, for example, the dummy gate dielectric 32 is removed by an isotropic etching process to expose the multilayer stack 22', resulting in the structure shown in Figure 14. This corresponds to process 222 of process flow 200 shown in Figure 26. Therefore, a trench 60 is formed in the dummy gate electrode 34. This etching can be anisotropic, such that the edge of the dummy gate electrode 34 facing the trench 60 is perpendicular and straight.

[0041] Subsequently, an etching process is performed to remove the exposed multilayer stack 22', followed by further etching of the underlying semiconductor material, such as the substrate strip 20'. This corresponds to process 224 of process flow 200 shown in Figure 26. Therefore, trench 62 is formed between adjacent isolation regions 26, as shown in Figure 15. According to some embodiments, trench 62 extends to a horizontal level below the bottom surface of the isolation region 26, as shown in Figure 15. According to some other embodiments, the bottom of trench 62 may also be flush with or above the bottom surface of the isolation region 26, as shown by dashed line 64.

[0042] It should be understood that the isolation region 26 may be worn out during the removal of the multilayer stack 22'. For example, etching of the polishable interposer layer 29 (sometimes referred to as the sacrificial layer) in the multilayer stack 22' can lead to the wear-out of the isolation region 26. Due to the similarity of the materials of the isolation region 26 and the multilayer stack 22', this results in low etch selectivity between the isolation region 26 and the multilayer stack 22'. Therefore, exposed portions of the isolation region 26 may be recessed. Dashed line 55 schematically shows the corresponding contour of the isolation region 26 caused by wear.

[0043] Figure 16 shows the filling of trenches 60 and 62 to form a continuous polysilicon (CPODE) isolation region 66 on the diffusion edge. This corresponds to process 226 of process flow 200 shown in Figure 26. According to some embodiments, the filling process may include depositing one or more dielectric materials to completely fill trenches 60 and 62. Subsequently, a planarization process (e.g., chemical mechanical polishing or mechanical polishing) may be performed to remove excess dielectric material above the dummy gate electrode 34, thereby forming the continuous polysilicon isolation region 66 on the diffusion edge.

[0044] According to some embodiments, the continuous polysilicon isolation region 66 on the diffusion edge may be selected from a dielectric material that has relatively high etch selectivity when the polishable interposer 29 is subsequently removed. For example, the continuous polysilicon isolation region 66 on the diffusion edge may be selected from SiN, SiON, SiOCN, SiCN, or the like or combinations thereof. According to some embodiments, the continuous polysilicon isolation region 66 on the diffusion edge has a monolayer structure, and the entire continuous polysilicon isolation region 66 on the diffusion edge is formed of a homogeneous dielectric material such as SiN.

[0045] According to some other embodiments, the continuous polysilicon isolation region 66 on the diffusion edge may have a multilayer structure, the multilayer structure including a dielectric pad 66A and a dielectric filling region 66B above the dielectric pad 66A. The dielectric filling region 66B and the dielectric pad 66A may also have high etch selectivity relative to the polishable interposer 29, such that when the polishable interposer 29 is etched, the continuous polysilicon isolation region 66 on the diffusion edge is not etched.

[0046] In subsequent processes, a back-side polishing process is performed from the back side of wafer 10. This corresponds to process 228 of process flow 200 shown in Figure 26. The substrate 20 is thinned. The back-side polishing process is performed until the continuous polysilicon isolation region 66 on the diffusion edge is exposed to the back side of wafer 10. According to some embodiments, as shown in Figure 17A, after the back-side polishing process, a portion of the substrate 20 (sometimes referred to as a bulk semiconductor substrate) may remain below the isolation region 26. When the continuous polysilicon isolation region 66 on the diffusion edge includes a dielectric pad 66A, the bottom of the dielectric pad 66A may be removed, exposing the dielectric fill region 66B to the back side of wafer 10.

[0047] Next, as shown in Figure 17A, the back-side dielectric layer 68 is formed through a deposition process. This corresponds to process 230 of process flow 200 shown in Figure 26. According to some embodiments, the back-side dielectric layer 68 is formed of oxides, nitrides, or the like, or includes the aforementioned materials. For example, the back-side dielectric layer 68 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon oxynitride, or the like.

[0048] According to some embodiments, when forming the structure shown in Figures 20A and 20B (or the structure shown in Figure 22), the back-side dielectric layer 68 may still be a blank layer that does not include other materials / components (e.g., conductive components). The back-side dielectric layer 68 may also be referred to as an insulating substrate.

[0049] It should be understood that when the continuous polysilicon isolation region 66 on the diffusion edge is formed of silicon nitride, the continuous polysilicon isolation region 66 on the diffusion edge may attract charges in the substrate 20 due to the high defect density in silicon nitride. This may result in a leakage path in region 73 (Figure 16). For example, Figure 25 shows two adjacent semiconductor fins formed above a p-type well region (used to form an n-type metal-oxide-semiconductor NMOS) and an N-type well region (used to form a p-type metal-oxide-semiconductor PMOS). Shallow trench isolation regions are formed in the p-type well region and the N-type well region. It should be understood that the shallow trench isolation region may include nitride pads contacting the p-type well region and the N-type well region. Silicon nitride has a high defect density and can trap charges, which can accumulate to form a leakage path. Furthermore, negative charges are attracted by the accumulated positive charges to form a leakage path.

[0050] By removing the portion of the semiconductor substrate that may form a leakage path, and by forming a back-side dielectric layer 68, a continuous polysilicon isolation region 66 on the diffusion edge is placed thereon, thus eliminating the leakage path.

[0051] Figure 17B shows a top view of the structure shown in Figure 17A, which shows a continuous polycrystalline silicon isolation region 66 on the diffusion edge.

[0052] Next, the dummy gate electrode 34 and dummy gate dielectric 32 (and any remaining hard masking layer 36) are removed in one or more etching processes to form a notch 70, as shown in Figure 18. This corresponds to process 232 of process flow 200 shown in Figure 26. According to some embodiments, the dummy gate electrode 34 and dummy gate dielectric 32 are removed via an anisotropic dry etching process. For example, the etching process may be performed using a reactive gas that selectively etches the dummy gate electrode 34 and dummy gate dielectric 32 at a rate faster than that of the interlayer dielectric 52. Each notch 70 exposes a portion of the multilayer stack 22' and / or over a portion of the multilayer stack 22', which contains future channel regions in the subsequently completed transistor.

[0053] The dummy gate electrode 34 and the dummy gate dielectric 32 can also have high etch selectivity relative to the continuous polysilicon isolation region 66 on the diffusion edge, so that the dummy gate electrode 34 and the dummy gate dielectric 32 are etched without etching the continuous polysilicon isolation region 66 on the diffusion edge.

[0054] Next, the polishable interposer 29 is removed to extend the notch 70 to the second layer 22B. This corresponds to process 234 of process flow 200 shown in Figure 26, to form the structure shown in Figure 19. The polishable interposer 29 can be removed by performing an isotropic etching process, such as a wet etching process using an etchant selective for the material of the polishable interposer 29, while the second layer 22B and the substrate 20 remain relatively unetched compared to the polishable interposer 29. The isolation regions 26 may be slightly recessed or not recessed. For example, (in the step shown in Figure 3) a silicon nitride capping layer may be formed on each isolation region 26 to protect the isolation region 26.

[0055] According to some embodiments, the polishable interlayer 29 is formed of silicon oxide (DOI), and when dry etching is performed, the etching gas may contain a mixture of NF3 and NH3, a mixture of HF and NH3, or the like. When wet etching is performed, diluted HF may be used.

[0056] When etching the polishable interposer 29, since the material of the continuous polysilicon isolation region 66 on the diffusion edge has a high etch selectivity relative to the polishable interposer 29, the continuous polysilicon isolation region 66 on the diffusion edge is not etched. For example, the etch selectivity ER29 / ER66 can be greater than about 5, greater than about 10, 10, 50 or greater, where ER29 is the etch rate of the polishable interposer 29 and ER66 is the etch rate of the continuous polysilicon isolation region 66 on the diffusion edge. Therefore, when etching the polishable interposer 29, lateral etching of the continuous polysilicon isolation region 66 on the diffusion edge, represented by arrow 75 in Figure 19, is avoided. For example, if the continuous polysilicon isolation region 66 on the diffusion edge comprises silicon nitride and the polishable interposer 29 comprises silicon oxide, the continuous polysilicon isolation region 66 on the diffusion edge will not be damaged.

[0057] According to some embodiments, the gap 67 is formed in a continuous polysilicon isolation region 66 on the diffusion edge. According to some other embodiments, no gap is formed.

[0058] Please refer to Figure 20B, marked region 72. Region 72 is the area on the diffusion edge where the continuous polysilicon isolation region 66 may be unfavorably removed if it contains a material (e.g., a silicon oxide pad) that has low etch selectivity relative to the material (e.g., silicon oxide) of the polishable interposer 29. When these portions of the silicon oxide pad are removed, the subsequently formed metal gate will be located closer to the corresponding source / drain plug, potentially causing problems such as electrical short circuits or leakage. Furthermore, the bottom of the silicon oxide pad may be eroded, making it difficult to form a compliant replacement gate dielectric, which may also lead to electrical short circuits or leakage.

[0059] According to some embodiments of the present invention, by increasing the etching selectivity ER29 / ER66, the region 72 shown in Figure 20 will be reduced or undamaged.

[0060] Referring to Figures 20A and 20B, a gate dielectric 74 and a gate electrode 76 are formed, thus forming a replacement gate stack 78. This corresponds to process 236 of process flow 200 shown in Figure 26. According to some embodiments, each gate dielectric 74 includes an interface layer and a high-dielectric-constant dielectric layer on the interface layer. The interface layer may be formed of or comprise silicon oxide, which may be deposited through a conformal deposition process (e.g., atomic layer deposition or chemical vapor deposition) or through an oxidation process. According to some embodiments, the high-dielectric-constant dielectric layer includes one or more dielectric layers. For example, the high-dielectric-constant dielectric layer may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof.

[0061] A gate electrode 76 is also formed. In the formation process, a conductive layer is first formed on a high-dielectric-constant dielectric layer and completely fills the remaining portion of the notch 70. The gate electrode 76 may contain a metallic material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, the gate electrode 76 may include any number of layers, any number of work function adjustment layers, and possible filler materials. The gate stack 78 also fills the space between adjacent second layers 22B and the space between the bottommost second layer 22B and the underlying substrate strip 20'.

[0062] After filling the notch 70, a planarization process (e.g., chemical mechanical polishing or mechanical polishing) is performed to remove excess portions of the gate dielectric 74 and gate electrode 76 above the top surface of the interlayer dielectric 52 (Figure 11B). The gate dielectric 74 and gate electrode 76 are collectively referred to as the replacement gate stack 78 of the final transistor.

[0063] Figure 20A further shows the formation of a dielectric layer 80 and a gate contact plug 82 according to some embodiments. The dielectric layer 80 may include an interlayer dielectric and may or may not include an etch stop layer between the interlayer dielectric and the substituted gate stack 78. The gate contact plug 82 is electrically connected to the gate electrode 76, thereby forming fully wound gate transistors 84A and 84B.

[0064] Although the structure of the fully wound gate transistors 84A and 84B in another cross section perpendicular to the cross section of Figure 20A is not shown, the structure in the other cross section can be understood from Figure 11B, except that the dummy gate stack 30 in Figure 11B is replaced by the gate stack 78.

[0065] Figures 21 and 22 show schematic diagrams of intermediate stages of structure formation according to alternative embodiments. These embodiments are essentially the same as the aforementioned embodiments, except that in the backside polishing process, the substrate 20 is removed and the isolation region 26 is exposed from the bottom. According to these embodiments, the backside dielectric layer 68 can still be a blank layer in the structure shown in Figure 22 without any other materials / components (e.g., conductive components), which corresponds to the structure after the replacement gate stack 78 is formed.

[0066] It should be understood that the isolation region 26 may include dielectric pads 26A and dielectric fill regions 26B that are distinguishable from each other. For example, dielectric pads 26A and dielectric fill regions 26B may be formed of the same material but have different properties, such as different densities. Dielectric pads 26A and dielectric fill regions 26B may also be formed of different materials. For example, dielectric pads 26A may be formed of silicon oxide, and dielectric fill regions 26B may be formed of silicon nitride.

[0067] According to some other embodiments, the dielectric pad 26A may be formed of silicon nitride, and the dielectric filling region 26B may be formed of silicon oxide. During the back-side polishing process, the bottom of the dielectric pad 26A is removed, thus the dielectric filling region 26B physically contacts the back-side dielectric layer 68. In contrast, in the structure shown in Figure 20A, the bottom of the dielectric pad 26A may still be present in the final structure.

[0068] Figures 23 and 24 show schematic diagrams of intermediate stages of structure formation according to alternative embodiments. These embodiments are essentially the same as the foregoing embodiments, except for the formation of a back-side wiring structure. For example, a dielectric layer 88 is formed, and a back-side metal line 86 is formed in the dielectric layer 88.

[0069] The back-side metal wire 86 is electrically connected to the front-side component through a conductive member 90, which can penetrate the isolation area 26. The conductive member 90 is schematically shown using dashed lines. The back-side metal wire 86 can be used to conduct electricity and / or signals. Therefore, the structure according to the embodiment of the present invention is also compatible with the formation of back-side wiring.

[0070] Embodiments of the present invention have several advantages. By using a dielectric material (e.g., silicon nitride) different from the sacrificial layer material in the multilayer stack for the continuous polysilicon isolation region on the diffusion edge, damage to the continuous polysilicon isolation region on the diffusion edge during etching of the sacrificial layer is eliminated. However, silicon nitride can cause leakage paths to occur below the continuous polysilicon isolation region on the diffusion edge and in contact with a portion of the semiconductor substrate of the continuous polysilicon isolation region on the diffusion edge. By removing the lower portion of the semiconductor substrate and replacing the lower portion of the semiconductor substrate with a dielectric layer, leakage paths are further removed.

[0071] According to some embodiments of the present invention, the method includes forming a dummy gate stack on a first protruding structure of a wafer, wherein the first protruding structure includes a first semiconductor layer; etching the dummy gate stack to form a trench in the dummy gate stack and expose the first semiconductor layer; removing the first semiconductor layer and a semiconductor strip below the first semiconductor layer to extend the trench downward; filling the trench with a dielectric material to form a dielectric isolation region; performing a back-side polishing process on the semiconductor substrate of the wafer, wherein the dielectric isolation region is exposed from the back side of the wafer; and forming a back-side dielectric layer on the back side of the wafer, wherein the back-side dielectric layer contacts the dielectric isolation region.

[0072] In one embodiment, the entire dielectric isolation region is formed of a homogeneous dielectric material. In one embodiment, a dummy gate stack is further located above a second protruding structure, the second protruding structure including: a second semiconductor layer; and a sacrificial layer located below and in contact with the second semiconductor layer, wherein the above method further includes, after forming the dielectric isolation region, etching the sacrificial layer with an etching chemical to create a space, wherein the dielectric isolation region is exposed to the etching chemical, and the sacrificial layer and the dielectric isolation region include different dielectric materials; and forming a replacement gate stack, the replacement gate stack being included as a portion of the space.

[0073] In one embodiment, the etching chemicals do not etch the dielectric isolation region. In one embodiment, the sacrificial layer comprises silicon oxide, and the dielectric isolation region comprises silicon nitride. In one embodiment, a replacement gate stack surrounds the second semiconductor layer. In one embodiment, when the sacrificial layer is etched, the sidewalls of the dielectric isolation region are exposed to the etching chemicals. In one embodiment, after a back-side polishing process, a portion of the semiconductor substrate is left to separate the shallow trench isolation region from the back-side dielectric layer. In one embodiment, the dielectric isolation region is between two shallow trench isolation regions, and wherein the two shallow trench isolation regions are polished during the back-side polishing process. In one embodiment, the above method further includes forming a metal line on the back side of the wafer, wherein the metal line contacts the back-side dielectric layer.

[0074] According to some embodiments of the present invention, the structure includes a first plurality of semiconductor nanostructures, wherein the upper semiconductor nanostructure of the first plurality of semiconductor nanostructures overlaps with the lower semiconductor nanostructure of the corresponding first plurality of semiconductor nanostructures; a first gate stack is located on the first plurality of semiconductor nanostructures; a second plurality of semiconductor nanostructures, wherein the upper semiconductor nanostructure of the second plurality of semiconductor nanostructures overlaps with the lower semiconductor nanostructure of the corresponding second plurality of semiconductor nanostructures; and a second gate. A stack is located on a second plurality of semiconductor nanostructures; a first shallow trench isolation region and a second shallow trench isolation region are located below the first plurality of semiconductor nanostructures and the second plurality of semiconductor nanostructures; a dielectric isolation region is located between and in contact with the first gate stack and the second gate stack, and is located between and in contact with the first shallow trench isolation region and the second shallow trench isolation region; and a back dielectric layer is located below the dielectric isolation region and in contact with the dielectric isolation region.

[0075] In one embodiment, the entire dielectric isolation region is formed of a homogeneous dielectric material. In one embodiment, the entire dielectric isolation region is formed of silicon nitride. In one embodiment, the structure further includes a semiconductor substrate located below the first shallow trench isolation region and the second shallow trench isolation region, wherein the semiconductor substrate is located above and contacts the back-side dielectric layer. In one embodiment, the structure further includes a back-side metal line located below and contacts the back-side dielectric layer. In one embodiment, the first gate stack includes a gate dielectric, and wherein a vertical portion of the gate dielectric contacts the dielectric isolation region to form a vertical interface.

[0076] According to some embodiments of the present invention, the structure includes a first transistor including a first gate stack; a second transistor including a second gate stack, wherein in a top view of the semiconductor structure, the longitudinal directions of the first gate stack and the second gate stack are aligned with the same straight line; a first shallow trench isolation region overlapping the first gate stack; a second shallow trench isolation region overlapping the second gate stack; a dielectric isolation region including: an upper portion separating the first gate stack and the second gate stack; and a lower portion separating the first shallow trench isolation region and the second shallow trench isolation region, wherein the entire dielectric isolation region is formed of a homogeneous dielectric material; and a back-side dielectric layer located below the lower portion of the dielectric isolation region and in contact with the lower portion of the dielectric isolation region.

[0077] In one embodiment, the entire dielectric isolation region comprises silicon nitride. In one embodiment, the back-side dielectric layer comprises silicon nitride. In one embodiment, the back-side dielectric layer comprises silicon oxide.

[0078] The foregoing outlines features of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments of the present invention. [Simplified Explanation of the Diagram]

[0007] Embodiments of the present invention can be better understood from the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Figures 1, 2, 3, 4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12, 13A, 13B, 14, 15, 16, 17A, 17B, 18, 19, 20A, and 20B show schematic diagrams of intermediate stages in forming a continuous polysilicon on diffusion edge (CPODE) isolation region on a transistor and diffusion edge, according to some embodiments. Figures 21 and 22 show schematic diagrams of intermediate stages in forming a continuous polysilicon on diffusion edge isolation region on a transistor and diffusion edge, according to alternative embodiments. Figures 23 and 24 show schematic diagrams of intermediate stages of the transistor and the continuous polysilicon isolation region on the diffusion edge, according to alternative embodiments. Figure 25 shows a leakage path that may be formed in a structure without a continuous polysilicon isolation region on the diffusion edge, according to some embodiments. Figure 26 shows a process flow for forming a nanostructured transistor, according to some embodiments.

Claims

1. A method of forming a semiconductor structure, comprising: forming a first shallow trench isolation region and a second shallow trench isolation region on both sides of a first protruding structure; forming a dummy gate stack on the first protruding structure of a wafer, wherein the first protruding structure includes a first semiconductor layer; etching the dummy gate stack to form a trench in the dummy gate stack and expose the first semiconductor layer; removing the first semiconductor layer and a semiconductor strip below the first semiconductor layer to extend the trench downward; filling the trench with a dielectric material to form a dielectric isolation region, wherein the dielectric isolation region extends along the top surface and sidewalls of the first shallow trench isolation region and the second shallow trench isolation region; performing a back-side polishing process on a semiconductor substrate of the wafer, wherein the dielectric isolation region is exposed from a back side of the wafer; and forming a back-side dielectric layer on the back side of the wafer, wherein the back-side dielectric layer contacts the dielectric isolation region.

2. The method of forming a semiconductor structure as claimed in claim 1, wherein the dummy gate stack is further located above a second protruding structure, the second protruding structure comprising: a second semiconductor layer; and a sacrificial layer located below and in contact with the second semiconductor layer, wherein the method of forming the semiconductor device further comprises, after forming the dielectric isolation region, etching the sacrificial layer with an etching chemical to create a space, wherein the dielectric isolation region is exposed to the etching chemical, and the sacrificial layer and the dielectric isolation region comprise different dielectric materials; and forming a replacement gate stack, the replacement gate stack being included in a portion of the space.

3. The method for forming a semiconductor structure as claimed in claim 2, wherein the etching chemical does not etch the dielectric isolation region.

4. The method of forming a semiconductor structure as claimed in claim 2, wherein the replacement gate stack surrounds the second semiconductor layer.

5. The method of forming a semiconductor structure as claimed in claim 2, wherein when the sacrificial layer is etched, one sidewall of the dielectric isolation region is exposed to the etching chemical.

6. A method of forming a semiconductor structure as claimed in any one of claims 1 to 5, wherein after the backside polishing process, a portion of the semiconductor substrate is left to separate the first shallow trench isolation region from the backside dielectric layer.

7. A method for forming a semiconductor structure as claimed in any one of claims 1 to 5, wherein the dielectric isolation region is between the first shallow trench isolation region and the second shallow trench isolation region, and wherein the first shallow trench isolation region and the second shallow trench isolation region are polished during the backside polishing process.

8. A semiconductor structure, comprising: a first plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the first plurality of semiconductor nanostructures overlaps with a lower semiconductor nanostructure of a corresponding first plurality of semiconductor nanostructures; a first gate stack located on the first plurality of semiconductor nanostructures; a second plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the second plurality of semiconductor nanostructures overlaps with a lower semiconductor nanostructure of a corresponding second plurality of semiconductor nanostructures; a second gate stack located on the second plurality of semiconductor nanostructures; a first shallow trench isolation region and a second shallow trench isolation region, lower than the first plurality of semiconductor nanostructures and the second plurality of semiconductor nanostructures; A dielectric isolation region is located between and in contact with the first gate stack and the second gate stack, and is located between and in contact with the first shallow trench isolation region and the second shallow trench isolation region, wherein the dielectric isolation region extends along the top surface and sidewall of the first shallow trench isolation region and the second shallow trench isolation region; and a back-side dielectric layer is located below the dielectric isolation region and in contact with the dielectric isolation region.

9. The semiconductor structure of claim 8 further includes: a semiconductor substrate located below the first shallow trench isolation region and the second shallow trench isolation region, wherein the semiconductor substrate is located above the back-side dielectric layer and contacts the back-side dielectric layer.

10. A semiconductor structure comprising: a first transistor including a first gate stack; a second transistor including a second gate stack, wherein, in a top view of the semiconductor structure, the longitudinal directions of the first gate stack and the second gate stack are aligned with the same straight line; a first shallow trench isolation region overlapping the first gate stack; a second shallow trench isolation region overlapping the second gate stack; a dielectric isolation region extending along the top surface and sidewalls of the first shallow trench isolation region and the second shallow trench isolation region, comprising: an upper portion separating the first gate stack and the second gate stack; and a lower portion separating the first shallow trench isolation region and the second shallow trench isolation region, wherein the dielectric isolation region is entirely formed of a homogeneous dielectric material; and a back-side dielectric layer located below the lower portion of the dielectric isolation region and in contact with the lower portion of the dielectric isolation region.

Images