Image sensor for stack chip air gap heat insulator

Abstract

An image sensor includes a pixel die stacked on a logic die. The logic die includes: at least one functional logic element disposed on a bonding side of the logic die; and a logic oxide array with raised logic oxide features, also disposed on the bonding side. The pixel die includes: a pixel array disposed on a light-receiving side of the pixel die; and a pixel oxide array with raised pixel oxide features disposed on a bonding side of the pixel die. A plurality of external bonding members are disposed between an external region of the logic die and an external region of the pixel die. A plurality of internal bonding members are formed in an internal region of the image sensor between the pixel oxide array and the logic oxide array, the internal bonding members being spaced apart by a plurality of fluid-connected air gaps extending between the logic die and the pixel die.

Description

Technical Field

[0001] The present invention relates generally to image sensors, and more specifically, but not exclusively, to image sensor stacked chipsets. Prior Technology

[0002] Image sensors have become ubiquitous. They are widely used in digital still cameras, cell phones, security cameras, and in medical, automotive, and other applications. The technology used to manufacture image sensors continues to advance by leaps and bounds. For example, the demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices.

[0003] CMOS image sensors (CIS) can utilize a stacked architecture with multiple chips placed on top of each other. This stacked architecture advantageously reduces the size of the CIS and shortens the length of certain circuit connections. For example, a CIS may include a pixel chip stacked together with a logic chip. The pixel chip can be configured to receive light on a pixel array, where the light generates electrical charges in the pixel. The logic chip may include a readout circuitry, an analog-to-digital converter circuitry, and additional logic circuitry.

[0004] In CIS with a stacked architecture, the functional components of the logic chip can generate significant thermal loads. The heat generated from the logic chip dissipates to adjacent stacked pixel chips, which can lead to increased dark current (DC) in a region and cause dark image inhomogeneity (DINU) – a common form of unwanted noise that occurs when pixels generate charge even though they do not receive significant light intensity. DINU is even more common in thermally operating environments (e.g., automotive applications). Simple Explanation of the Diagram

[0005] The following figures illustrate non-limiting and non-exhaustive embodiments of the invention, wherein, unless otherwise specified, similar element symbols refer to similar parts throughout the views.

[0006] [Figure 1] is a functional block diagram illustrating one embodiment of an image sensor (CIS) according to the teachings of the present invention.

[0007] [Figure 2A] illustrates an example image sensor with a stacked chip architecture according to the teachings of the present invention.

[0008] [Figure 2B] shows [picture] [2A] Partial exploded view of an example image sensor.

[0009] [Figure 2C] shows [picture] [2A] is a cross-sectional view of an example image sensor.

[0010] [Figure 3] A schematic perspective view showing an example of forming a plurality of fluid-connected air gaps according to the teachings of the present invention, including a pixel oxide array and a logic oxide array.

[0011] [Figure 4] shows a schematic cross-sectional view of an example image sensor having a stacked chip architecture according to the teachings of the present invention.

[0012] [Figure 5] shows a top view schematic diagram of an example image sensor having a stacked chip architecture according to the teachings of the present invention.

[0013] [Figure 6] shows a top view schematic diagram of another example image sensor with a stacked chip architecture according to the teachings of the present invention.

[0014] [Figure 7] shows a top view schematic diagram of another example image sensor with a stacked chip architecture according to the teachings of the present invention.

[0015] [Figure 8] illustrates an exemplary method for fabricating an image sensor with a stacked chip architecture according to the teachings of the present invention.

[0016] [Figure 9A] This illustration shows a thermal simulation of an example image sensor constructed without a plurality of fluid-connected air gaps.

[0017] [Figure 9B] illustrates a thermal simulation of an exemplary image sensor constructed according to the teachings of the present invention, having an air gap between a logic die and a pixel die.

[0018] The figure includes an appendix for preservation. [9A] to The details shown in [9B]. Implementation

[0019] This article illustrates examples of stacked chip architectures. Numerous specific details are presented in the following description to provide a thorough understanding of one of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the specific details or using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0020] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one example of the invention. Therefore, the appearance of the phrases "in an example" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same example. Furthermore, specific features, structures, or characteristics of embodiments can be combined in one or more examples in any suitable manner.

[0021] Several terms are used throughout this specification. These terms will be given their general meaning in the context of this art, unless otherwise specifically defined herein or clearly indicated in the context of their use. It should be noted that throughout this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, they have the same meaning.

[0022] For ease of understanding, this invention is set forth within the context of complementary metal-oxide-semiconductor ("CMOS") image sensors (CIS). However, it should be understood that this invention is not limited to CIS, but is applicable to non-CMOS image sensors with a stacked chip architecture and other semiconductor devices with a stacked chip architecture.

[0023] [Figure 1] is a functional block diagram illustrating one embodiment of a CIS 100 according to one embodiment of the present invention. CIS 100 may be an embodiment of a semiconductor device (such as an integrated circuit having a stacked device wafer as described below). CIS 100 includes a pixel array 104, a readout circuit system 108, functional logic 112, and a control circuit system 116.

[0024] The pixel array 104 is a two-dimensional ("2D") array of back-illuminated imaging sensors or pixels (e.g., pixels P1, P2, ..., Pn). In one embodiment, each pixel is an active pixel sensor ("APS"), such as a CMOS imaging pixel. As illustrated, each pixel is configured in a column (e.g., columns R1 to Ry) and a row (e.g., rows C1 to Cx) to acquire image data of an object (e.g., a person, place, or object), which can then be used to present a 2D image of the person, place, or object.

[0025] After each pixel has acquired its image data or image charge, the image data is read out by the readout circuitry 108 and transmitted to the functional logic 112. The readout circuitry 108 may include an amplifier circuitry, an analog-to-digital ("ADC") conversion circuitry, and / or other circuitry. The functional logic 112 may store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or other post-image effects). This functional logic 112 may be implemented by one or more logic elements (such as application-specific integrated circuits (ASICs)). The control circuitry 116 is coupled to the pixel array 104 to control the operating characteristics of the pixel array 104. In a non-limiting example, the control circuitry 116 may be coupled to generate a global shutter signal for controlling the image acquisition of each pixel (e.g., P1, P2, P3, ... Pn). In this example, the global shutter signal simultaneously enables all pixels within the pixel array 104 to transfer image charge from each individual photodetector during a single acquisition window. The control circuitry 116 controls other operational characteristics of the pixel array 104.

[0026] Semiconductor devices (such as, [Figure 1] The CIS 100 can be implemented as a stacked chip architecture, in which a first semiconductor die is stacked on top of and bonded to a second semiconductor die. For example, the first and second semiconductor dies can be bonded together using oxide surface-level micro-attachments in an active pixel array. The first and second semiconductor dies can be bonded by a hybrid bonding of metal-to-metal and dielectric-to-dielectric contacts simultaneously achieved in an external frame. The stacked chip architecture can advantageously reduce the form factor of the semiconductor device and can have additional features, such as allowing the use of a larger photodiode die area for the photodiode, and optimizing the processing and materials of the first die for the photodiode, while also optimizing the processing of the second die for supporting the circuit system.

[0027] [Figure 2A] [To Figure 2B] This diagram illustrates a CIS 200 having a stacked chip architecture according to the teachings of the present invention. The CIS 200 includes a pixel die 204 stacked on top of a logic die 208. In one example, the pixel die 204 includes... [picture] [1] The pixel array 104 is similar to a CIS pixel array and may also include other circuit systems. In one example, the logic die 208 includes: a readout circuit system, which is similar to... [picture] [1] Similar to the readout circuit system 108; and a plurality of logic elements having the same as... [picture] [1] Similar to the functional logic 112. In some embodiments, the logic die 208 may also include a control circuit system, such as [picture] [1] Control circuit system 116. To facilitate understanding of the unique characteristics of CIS 200, [picture] [2A] [To the image] [2B] Pixel arrays, readout circuitry, functional logic, and control circuitry are not shown to avoid obscuring the teachings of the invention. However, it should be understood that pixel die 204 and logic die 208 may contain such elements. In some embodiments, each of the pixel die and logic die may each contain additional circuitry.

[0028] [Figure 2B] shows [picture] [2A] is a partially exploded view of the CIS 200, in which pixel die 204 is separated from logic die 208 for clarity. Pixel die 204 has a light receiving side 212 that faces an object (e.g., a person, location, or object) to be captured by the pixel array when in use. Pixel die 204 also has a pixel bonding side 216 opposite to the light receiving side 212. Logic die 208 has a logic bonding side 220 facing the pixel bonding side 216 of pixel die 204. A plurality of external bonding members 224 (e.g., 224a) bond pixel dies 204 to logic dies 208 around an outer region 226 of the CIS 200, the outer region 226 of the CIS 200 including an outer region of the pixel die 204 and an outer region of the logic die 208, such that the external bonding members 224 surround an inner region 228 of the CIS 200, the inner region 228 of the CIS 200 including an inner region of the pixel die 204 and an inner region of the logic die 208. In one embodiment, the inner region 228 surrounds a pixel array on the pixel die 204. In the illustrated embodiment, each external bonding member 224 simultaneously achieves a hybrid bonding of metal-to-metal contact and dielectric-to-dielectric contact between the pixel die 204 and the logic die 208. In other embodiments, the external bonding members 224 may include one or more different bonding types. A CIS having a hybrid external connector 224 may be referred to as a hybrid-bonded image sensor or a hybrid-bonded CIS.

[0029] [Figure 2C] Display Diagram [2A] is a partial schematic cross-sectional view of the CIS 200 along a section line 2C passing through the external connector 224 containing the external connector 224a, to illustrate other configurations of the CIS 200. Each external connector 224 has a bonding height HB of at least about 1 µm (e.g., at least about 2 µm) or about 1 µm to about 3 µm. In one embodiment, the bonding height HB is about 1 µm. In another embodiment, the bonding height HB is about 2 µm. For clarity, the bonding height HB is the distance between the pixel die 204 and the logic die 208. As can be seen, adjacent external connectors 224 (e.g., 224b) are separated by an air channel 232. [picture] As shown in [4], air channels 232 (e.g., 232b and 232c) are fluidly connected to an air gap 248 between pixel die 204 and logic die 208. The air gap will be described in detail below. Return to [picture] [3] Each air passage 232 has a width of about 150 µm to about 2000 µm. In use, each air passage 232 achieves air (or other gas) exchange with the interior region 228 of the CIS 200, thereby removing heat energy from the interior region 228. In some embodiments, each air passage 232 is fluidly connected to an air gap.

[0030] Return to [picture] [2A] [Referring to Figure 2B], pixel die 204 includes a pixel oxide array 236 disposed on a pixel junction side 216 of pixel die 204. Similarly, logic die 208 includes a logic oxide array 240 disposed on a logic junction side 220 of logic die 208. Pixel oxide array 236 and logic oxide array 240 are configured to interface with each other at a plurality of internal bonding members 244 (e.g., 244a, 244b, 244c) between pixel die 204 and logic die 208. Simultaneously, the plurality of internal bonding members 244 support the pixel die 204 located on top of logic die 208 and fix the x, y, and z direction positions of pixel die 204 relative to logic die 208. Furthermore, the position and size of the internal bonding members 244 affect the thermal characteristics of pixel oxide array 236 and logic oxide array 240.

[0031] The pixel oxide array 236 and logic oxide array 240 facilitate the dissipation of heat from between the pixel die 204 and the logic die 208 by separating the pixel die 204 and the logic die 208. Specifically, the pixel oxide array 236 and logic oxide array 240 partially define a plurality of fluid-connected air gaps 248 between the pixel die 204 and the logic die 208 (e.g., [picture] [2A] shows 248a, 248b and 248c. Advantageously, these fluid-connected air gaps 248 restrict heat transfer from logic die 204 to pixel die 208, as described in detail below.

[0032] refer to [picture] [3] The pixel oxide array 236 is formed at least partially by a plurality of raised pixel oxide features 252 (e.g., 252a and 252b) extending away from the pixel grain 204. In the illustrated embodiment, the raised pixel oxide features 252 form a grid having one of a plurality of pixel oxide vertices, but in other embodiments, the raised pixel oxide features form non-grid shapes (e.g., "islands" or "strips", as described below respectively). [picture] [6] [To the image] [7] As described. In all embodiments, the raised pixel oxide feature 252 may be formed by an etching process, a deposition process or another process. An exemplary process for forming the raised pixel oxide feature 252 is described below.

[0033] Each raised pixel oxide feature extends away from the pixel die 204 by a height Hp of about 0.25 µm to about 1.75 µm. In one embodiment, each raised pixel oxide feature 252 has a height Hp of about 0.5 µm, which has been found to provide a favorable spacing level between the pixel die 204 and the oxide die 208 when the raised pixel oxide feature 252 is joined to one of the logic oxide dies described below. Each raised pixel oxide feature 252 has a width Wp of about 2.0 µm to about 5.0 µm. In one embodiment, each raised pixel oxide feature 252 has a width Wp of about 3.0 µm, which provides an effective mechanical strength and stress level without causing an excessively adverse effect on the insulation between the pixel die 204 and the logic die 208.

[0034] In some embodiments, different raised pixel oxide features 252 may have different heights Hp, widths Wp, and / or other dimensions across pixel die 204 and / or relative to the features of the logic oxide array 240 described below. Adjacent raised pixel oxide features 252 are spaced apart by a pitch Pp, which may range from about 10 µm to about 50 µm. In one embodiment, adjacent raised pixel oxide features 252 have a 33 µm pitch in both the x and y directions, which creates an effective air gap between the pixel die 204 and the logic die 208 (described below). In some embodiments, the x-direction pitch Pp may differ from the y-direction pitch Pp. In some embodiments, the pitch Pp may vary across pixel die 204.

[0035] Similar to the pixel oxide array 236, the logic oxide array 240 is formed by a plurality of raised logic oxide features 256 (e.g., 256a and 256b) of a height Hl extending away from the logic die 208 by about 0.25 µm to about 1.75 µm. [Not shown in Figure 3]. In the illustrated embodiment, the raised logic oxide feature 256 forms a grid with a plurality of logic oxide vertices, but in other embodiments, the raised logic oxide feature forms a non-grid shape. In the illustrated embodiment, the raised logic oxide feature 256 also forms an outer frame surrounding the grid and providing a base for the pixel oxide array (where 240 points are present in Figure 2A). Some embodiments may not include an outer frame. The raised logic oxide feature 256 may be formed by an etching process, a deposition process, or another process. An exemplary process for forming the raised logic oxide feature 256 is described below. In one embodiment, each raised logic oxide feature 256 has a height Hl of about 0.5 µm. Each raised logic oxide feature 256 has a width Wl of about 2.0 µm to about 5.0 µm. In one embodiment, each raised logic oxide feature 256 has a width Wl of about 3.0 µm. In some embodiments, different raised logic oxide features 256 may have different heights Hl, widths Wl, and / or other dimensions across logic die 208 and / or relative to the features of pixel oxide array 236. Adjacent raised logic oxide features 256 are spaced by a pitch Pl, which may range from about 10 µm to about 50 µm. In one embodiment, adjacent raised logic oxide features 256 have a 33 µm pitch in both the x and y directions. In some embodiments, the x-direction pitch Pl may differ from the y-direction pitch Pl. In some embodiments, the pitch Pl may vary across logic die 208. Any of the advantages described above regarding the specific dimensions of the raised pixel oxide features also apply to raised logic oxide features having those dimensions.

[0036] Still referencing [picture] [3] Pixel die 204, logic die 208, pixel oxide array 236, and logic oxide array 240 at least partially define a plurality of fluidly connected air gaps 248 (e.g., 248d and 248e). Each air gap 248 is a gap between pixel die 204 and logic die 208. Adjacent air gaps 248 are separated in the x and y directions by raised pixel oxide features 252 and raised logic oxide features 256. In one sense, each air gap 248 extends from pixel die 204 to logic die 208 in the z direction and thus has a depth G = Hp + Hl. In another sense, each air gap 248 can be considered as unique to pixel die 204 or logic die 208 and thus has a z-direction depth Hp or Hl. In one sense (i.e., G = Hp + HL), each air gap has a depth G of at least about 1 µm, about 1 µm, about 2 µm, at least about 2 µm, or about 1 µm to about 3 µm. In some embodiments, air gaps 248 do not have a uniform depth G. In some embodiments, the plurality of air gaps comprises two or more air gaps having a different depth G. For clarity, the invention refers to the plurality of air gaps 248 for ease of understanding. Since each air gap 248 is fluidly connected, the plurality of air gaps 248 can be considered as a single air gap having a plurality of distinct regions, at least partially divided by raised pixel oxide features 252 and raised logic oxide features 256.

[0037] Each air gap 248 serves as a thermal insulator between the pixel die 204 and the logic die 208. Specifically, due to the relatively low thermal conductivity of air compared to oxides, metals, and other solids (e.g., approximately 33.5 mW / mK at 400 K and atmospheric pressure), the space within each air gap 248 restricts the conduction of heat energy from the logic die 208 to the pixel die 204. Although the term "air gap" is used throughout this invention, the inventive structures described herein are not inherently limited to air gaps filled with air. In some embodiments, a vacuum may exist within one or more air gaps 248. In some embodiments, a non-air gas (e.g., an inert gas) may occupy one or more air gaps 248.

[0038] refer to [picture] [4] Since each air gap 248 is fluidly connected to an external heat sink S (e.g., ambient air) via one or more other fluidly connected air gaps 248 and / or air channels 232, each air gap 248 (e.g., 248f to 248j) allows convection to remove heat from the CIS 200. However, the air gaps 248 are located within the pixel oxide array 236 and the logic oxide array 240, and the air channels 232 are located between adjacent external connectors 224. In the illustrated embodiment, the air channels 232 are located in the outer region 226 of the CIS 200, while the air gaps 248 are located in the inner region 228 of the CIS 200. In the illustrated embodiment, the fluidly connected air gaps 248 are fluidly connected to the heat sink S via air channels 232b and 232c. Line F represents the fluid flow path through the air gap 248 to the heat sink S. In the illustrated embodiment, the fluid connection extends through the pixel oxide array 236 and through the logic oxide array 240 in at least two dimensions: across a page (i.e., the fluid flow path F) and into a page. Therefore, the stacked chip architecture of the present invention utilizes both conduction and convection to limit heat transfer from the logic chip 208 to the pixel chip 204.

[0039] [Figure 5] shows a top view of a CIS 200 with a stacked chip architecture according to the present invention. The CIS 200 has a pixel oxide array 236 and a logic oxide array 240, and a plurality of air gaps 248 (e.g., air gaps 248 k). In the illustrated embodiment, air gaps 248 k (formed within the pixel oxide array 236) are fluidly connected to at least four separate and adjacent air gaps 248 formed within the logic oxide array 240. As discussed above, the advantage of air gaps 248 is related to the lower thermal conductivity of air (or other gaseous material / vacuum between the pixel die 204 and the logic die 208) compared to oxides and other solids. Therefore, the ability of the structure of the present invention to limit heat transfer between the logic die 208 and the pixel die 204 is inversely related to the overlap area of ​​the internal bonding members (i.e., the sum of the areas of the internal bonding members 244). The overlapping area of ​​the internal bonding members is the area that allows heat energy to be conducted from the logic chip 208 to the pixel chip 204 via the solid internal bonding members 244.

[0040] To limit heat conduction from logic die 208 to pixel 204, the overlap area of ​​internal bonding members can be reduced. To reduce the overlap area, one or more of the following variables can be reduced: the width of the raised pixel oxide feature Wp and the width of the raised logic oxide feature Wl. Alternatively, to reduce the overlap area, one or more of the following variables can be reduced: the spacing between raised pixel oxide features Pp and the spacing between raised logic oxide features Pl. For example, increasing the spacing between raised pixel oxide features Pp reduces the number of raised pixel oxide features 252 in the pixel oxide array, thereby reducing the overlap area of ​​internal bonding members. Similarly, increasing the spacing between raised logic oxide features Pl reduces the number of raised logic oxide features 256 in the pixel oxide array. In one embodiment, Pp and Pl are each 33 µm, and each of Wp and Wl is approximately 3 µm.

[0041] The overlap area of ​​internal bonding members can also be reduced by offsetting the pixel oxide array 236 relative to the logic oxide array 240. Specifically, the pixel oxide array 236 can be offset relative to the logic oxide array 240 along an offset vector O, where the offset vector O has an offset length L and an offset angle α. The offset length L can be represented by an x-component (Vx) and a y-component (Vy). Therefore, L = Vx and Vy can each be in the range of approximately 0.1Pp (or 0.1P l) to approximately 0.9Pp (or 0.9P l). Similarly, the offset length L can be in the range of approximately 0.1Pp (or 0.1P l) to approximately 0.9Pp (or 0.9P l). For example, the offset length L can be in the range of approximately 0.25Pp (or 0.25P l) to approximately 0.75Pp (or 0.75P l), for example, approximately 0.5Pp (or 0.5P l). The offset angle α can be in the range of approximately 15° to approximately 75°. [picture] In a non-limiting embodiment of [5], the offset vector V has a shift of half the spacing, i.e., Vx = 0.5Pp and Vy = 0.5Pp. Therefore, the offset angle α = 45°. This configuration advantageously reduces the overlap area of ​​the inner joiners to the area where the pixel oxide array 236 intersects with the logic oxide array 240 (e.g., at the inner joiner 244). The foregoing examples are non-limiting, and other embodiments may have different properties, including different Vx, Vy, and / or α. In any embodiment having a given WP, Wl, Pp, and Pl, the pixel oxide array 236 may be offset relative to the join oxide array 240 to reduce or minimize the overlap area of ​​the inner joiners.

[0042] [Figure 6] shows a top view of another image sensor 600 with a stacked chip architecture according to the teachings of the present invention. The image sensor 600 has a pixel oxide array 604 and a logic oxide array 608, which are similar to the pixel oxide array 236 and logic oxide array 240 described above, respectively. The pixel oxide array 604 includes a plurality of raised pixel oxide features 612. The logic oxide array 608 includes a plurality of raised logic oxide features 616. As described above, the raised pixel oxide features and the raised logic oxide features can form a non-grid shape. In this embodiment, the raised pixel oxide features 612 form a plurality of vertical "strips". Similarly, the raised logic oxide features 616 form a plurality of horizontal "strips". This configuration reduces the number of internal bonding elements 620, which advantageously reduces the overlap area of ​​the internal bonding elements to improve the insulation between the pixel die and the logic die.

[0043] [Figure 7] shows a top view of another image sensor 700 with a stacked chip architecture according to the teachings of the present invention. The image sensor 700 has a pixel oxide array 704 similar to the pixel oxide array 236 described above. The image sensor 700 also has a logic oxide array located behind the pixel oxide array 704. As in other embodiments, the pixel oxide array 704 and the logic oxide array respectively include a plurality of raised pixel oxide features 712 and a plurality of raised logic oxide features. In this embodiment, the raised pixel oxide features 712 and the raised logic oxide features form a plurality of "islands" having a rounded shape to facilitate fluid flow. Each pixel oxide island (e.g., formed by a raised pixel oxide feature 712) forms an internal junction 720 with a logic oxide island. Each island has a diameter δ of about 2 µm to about 5 µm and is spaced from adjacent islands by a distance P of about 10 µm to about 50 µm. Because the pixel oxide array 704 and logic oxide array reduce obstruction to one of the fluid flows (e.g., as shown by arrow F), this configuration facilitates convective heat transfer from the image sensor 700. Therefore, air flows more easily through the air gap 724 and air channel 728. In some embodiments, the plurality of islands comprises islands having two or more different diameters δ. In some embodiments, the plurality of islands comprises islands having two or more different shapes (e.g., square, oval, circular, or other shapes). In some embodiments, the plurality of islands comprises islands spaced apart by two or more different distances P. Therefore, the size and position of the islands can be optimized based on the location of one or more heat sources in the image sensor 700.

[0044] [Figure 8] illustrates a non-limiting method for preparing a pixel die having one of the pixel oxide arrays as described above and a logic die having one of the logic oxide arrays as described above, wherein the pixel oxide array and the logic oxide array form a plurality of internal bonding elements between the pixel die and the logic die. The pixel die can be prepared before, simultaneously with, or after the preparation of the logic die.

[0045] To fabricate a pixel oxide array, a pixel die having an oxide layer on a bonding side is provided. At step 800, a mask is then applied to an internal region of the pixel die on the bonding side, the mask having a negative profile of the pixel oxide array to be formed. In other words, the mask covers the portion of the oxide that will form raised pixel oxide features. Therefore, the mask defines the characteristics of the raised pixel oxide features, including size, location, and spacing. In one embodiment, the mask defines Wp and Pp. In another embodiment, the mask defines δp and P Island. At step 804, a plurality of recesses are then etched in the oxide layer of the pixel die using one or more etchants and etching steps, the recesses corresponding to areas not covered by the mask. The recesses can be etched to a depth Hp. At step 808, after etching, the mask is removed from the pixel die.

[0046] Similarly, fabricating a logic oxide array requires a process similar to that of a pixel oxide array. A logic die is provided having an oxide layer on its bonding side. At step 812, a mask is then applied to an internal region of the logic die on the bonding side, the mask having a negative profile of the logic oxide array to be formed. Therefore, the mask defines the characteristics of the raised logic oxide features, including size, location, and spacing. In one embodiment, the mask defines Wl and Pl. In another embodiment, the mask defines δl. At step 816, a plurality of recesses are then etched in the oxide layer of the logic die using one or more etchants and etching steps, these recesses corresponding to areas not covered by the mask. The recesses can be etched to a depth Hl. At step 820, after etching, the mask is removed from the logic die.

[0047] At step 824, the pixel oxide array and the logic oxide array are then bonded together to form a plurality of internal bonding elements as described above, such that each recess in the oxide layer etched to the pixel die is fluidly connected to at least one recess in the oxide layer etched to the logic die, and vice versa. Thus, this method produces a semiconductor device having a stacked architecture, wherein a plurality of fluidly connected air gaps separate the logic die from the pixel die. In one embodiment, bonding the pixel oxide array to the logic oxide array establishes a fluid connection between a) an air channel between a plurality of adjacent external bonding elements and b) the plurality of air gaps. In one embodiment, the method includes masking using either a shield that shields the logic oxide array (or pixel oxide array) or an air channel between a plurality of adjacent external bonding elements.

[0048] The aforementioned process describes the steps required to fabricate the plurality of internal bonding elements between the pixel oxide array and the logic oxide array to form a plurality of fluid-connected air gaps. The aforementioned process is not intended to limit the semiconductor fabrication process to these steps alone. Rather, one or more additional and optional processing steps may be performed, or following any of the steps described above.

[0049] Compared to known stacked wafer architectures (including stacked wafer architectures with uniform oxide contacts between and across dies, and stacked wafer architectures containing a metal layer between dies), the innovative stacked wafer architecture of this invention significantly reduces heat transfer between logic dies (heat sources) and pixel dies. This reduction in heat transfer advantageously mitigates dark image inhomogeneity (DINU).

[0050] [Figure 9A] Schematic illustration of a thermal simulation of an image sensor constructed without the plurality of fluidly connected air gaps taught in this invention. Appendix A-1 shows in color. [picture] [9A] For reference. This simulation illustrates the temperature variation between (and across) a logic chip 900 and a pixel chip 904 bonded together by a uniform oxide layer 908. A heat source 912 is located on the logic chip 900 in the middle left of the simulation. Therefore, the temperature is highest at the heat source 912, i.e., ~380 K. Due to heat conduction from the heat source 912 to the pixel chip 904, the temperature of the pixel chip 904 varies from ~345 K (12 K higher than the ambient temperature of 333 K) closest to the heat source 912 to approximately ~343 K. The temperature at 100 μm from the heat source is 337.5 K; in other words, ΔT = 7.5 K.

[0051] [Figure 9B] Illustrate a thermal simulation of an image sensor configured with an air gap 916 as taught in this invention between a logic chip 900 and a pixel chip 904. Appendix A-2 shows in color [picture] [9B] For reference. In this embodiment, the oxide layer system across pixel grain 904 is non-uniform. Instead, the oxide layer comprises two raised oxide features 908a, 908b separated by an air gap 916. [picture] [9A] Compared to the darker color changes of pixel 904, it can be seen that the temperature across pixel 904 is significantly higher than that at [the point where the color changes are darker]. [picture] [9A] shows a low simulation. Specifically, except in an extremely isolated location near the heat source 912, the temperature of the pixel 904 generally does not exceed ~337 K (4 K higher than the ambient temperature of 333 K) – a 67% improvement. In other words, ΔT = 2.1 K – a 70% reduction.

[0052] Dark image inhomogeneity (DINU) varies with dark current (DC), and decreases non-linearly (exponentially) as temperature decreases. Therefore, a relatively small temperature decrease on the pixel die 904 causes an exponential decrease in both DC and DINU. Thus, compared to... [picture] Compared to the image sensor simulated in [9A], [picture] The image sensor simulated in [9B] reduces the DINU across the pixel chip 904 by approximately 70%. This significant reduction in DINU is due to the air gap 916 that insulates the pixel chip 904 from the heat source 912. Therefore, the image sensor of the present invention performs significantly better than known image sensors.

[0053] The above description of the examples illustrated in the present invention (including the content set forth in the abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the invention have been set forth herein for illustrative purposes, those skilled in the art will recognize that various modifications can be made within the scope of the invention.

[0054] These modifications may be made to the invention in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting the invention to the specific instances disclosed in this specification. Rather, the scope of the invention will be determined entirely by the appended claims, which will be interpreted in accordance with the established principles of claim interpretation.

[0055] 2C: Section line 100: Complementary Metal-Oxide-Semiconductor Image Sensor 104: pixel array 108: Readout Circuit System 112: Functional Logic 116: Control circuit system 200: Complementary Metal-Oxide-Semiconductor Image Sensor 204: Pixel chip / pixel wafer / pixel 208: Logic grain / oxide grain 212: Optical receiving side 216: Pixel merging side 220: Logical junction side 224: External joint / Mixed external joint / Adjacent external joint 224a: External connector 224b: Adjacent external joint 226: External Area 228: Internal Area 232: Air passage 232b: Air passage 232c: Air passage 236: Pixel Oxide Array 240: Logic Oxide Array 244: Internal joint / Solid internal joint 244a: Internal joint 244b: Internal joint 244c: Internal joint 248a - 248e: Air gaps connected by fluid 248f - 248k: Air gap 252: Raised pixel oxide features / Adjacent raised pixel oxide features 252a: Raised pixel oxide feature 252b: Raised pixel oxide feature 256: Features of raised logic oxides / Features of adjacent raised logic oxides 256a: Features of raised logic oxides 256b: Raised logic oxide characteristics 600: Image Sensor 604: Pixel Oxide Array 608: Logic Oxide Array 612: Raised pixel oxide feature 616: Features of raised logic oxides 620: Internal joint 700: Image Sensor 704: Pixel Oxide Array 712: Raised pixel oxide features 720: Internal joint 724: Air gap 728: Air passage 800: Steps 804: Steps 808: Steps 812: Steps 816: Steps 820: Steps 824: Steps 900: Logic die / logic chip 904: Pixel chip 908: Uniform oxide layer 908a: Characteristics of raised oxides 908b: Features of raised oxides 912: Heat source 916: Air gap C1 - Cx: lines F: Line / Fluid Flow Path / Arrow G: Depth H l: Height / Z-direction depth / Depth HB: Joining height Hp: Height / Z-axis Depth / Depth L: Offset length O: Offset vector P Island: Spacing between islands P1 - Pn: pixels Pp: Spacing / x-direction spacing / y-direction spacing / spacing of raised pixel oxide features P l: Spacing / x-direction spacing / y-direction spacing / raised logic oxide feature spacing R1 - Ry: Columns S: External heatsink / heat sink Vx:x component Vy:y component W l: Width / Width of raised logic oxide feature Wp: Width / Width of raised pixel oxide feature X: Direction Y: direction Z: Direction α: Offset angle δ: diameter

Claims

1. An image sensor comprising: A logic die, comprising a functional logic element disposed on one of the junction sides of the logic die; The pixel die is stacked on top of the logic die. The pixel die includes: a pixel array disposed on a light-receiving side of the pixel die; and a pixel oxide array of raised pixel oxide features disposed on a bonding side of the pixel die, wherein the raised pixel oxide features extend directly between the pixel die and the logic die to contact the logic die to form a plurality of internal bonds, thereby defining a plurality of fluidly connected air gaps between the logic die and the pixel die, wherein each air gap is a void between the pixel die and the logic die and is separated by the raised pixel oxide features in an x-direction and a y-direction, and wherein the plurality of air gaps are located in an internal region of the logic die and an internal region of the pixel die; and a plurality of external bonds disposed between an external region of the logic die and an external region of the pixel die.

2. The image sensor of claim 1, wherein the raised pixel oxide features form a plurality of pixel oxide islands in the shape of a square, an oval or a circle.

3. The image sensor of claim 2, wherein the pixel oxide islands include a first pixel oxide island and a second pixel oxide island, and wherein the first pixel oxide island and the second pixel oxide island have different shapes.

4. The image sensor of claim 2, wherein the pixel oxide islands have a rounded shape and wherein the pixel oxide islands have a diameter greater than about 2 µm and less than about 5 µm.

5. The image sensor of claim 4, wherein the pixel oxide islands have two or more different diameters.

6. The image sensor of claim 1, wherein adjacent pixel oxide islands are separated by a spacing P, wherein the spacing P is greater than about 10 µm and less than about 50 µm.

7. The image sensor of claim 1, wherein adjacent pixel oxide islands are separated by two or more different spacings P.

8. The image sensor of claim 1, wherein the plurality of fluidly connected air gaps have a depth G between the internal region of the logic die and the internal region of the pixel die, and wherein the depth G is between about 1 µm and about 3 µm.

9. An image sensor comprising: A logic die includes: a functional logic element disposed on a bonding side of the logic die; a logic oxide array of raised logic oxide features disposed on the bonding side of the logic die; and a pixel die stacked on top of the logic die, the pixel die including: a pixel array disposed on a light-receiving side of the pixel die, wherein the raised logic oxide features extend directly between the pixel die and the logic die to contact the pixel die to form a plurality of internal bonding members, thereby defining a plurality of fluidly connected air gaps between the logic die and the pixel die, wherein each air gap is a void between the pixel die and the logic die and is separated by the raised pixel oxide features in an x-direction and a y-direction, and wherein the plurality of air gaps are located in an internal region of the logic die and an internal region of the pixel die; and a plurality of external bonding members disposed between an external region of the logic die and an external region of the pixel die.

10. The image sensor of claim 9, wherein the raised logic oxide features are formed as a plurality of logic oxide islands in the shape of a square, an oval or a circle.

11. The image sensor of claim 10, wherein the plurality of logic oxide islands includes a first logic oxide island and a second logic oxide island, and wherein the first logic oxide island and the second logic oxide island have different shapes.

12. The image sensor of claim 10, wherein the logic oxide islands have a rounded shape and wherein the logic oxide islands have a diameter greater than about 2 µm and less than about 5 µm.

13. The image sensor of claim 12, wherein the logic oxide islands have two or more different diameters.

14. The image sensor of claim 9, wherein adjacent logic oxide islands are separated by a spacing P, wherein the spacing P is greater than about 10 µm and less than about 50 µm.

15. The image sensor of claim 9, wherein adjacent logic oxide islands are separated by two or more different spacings P.

16. The image sensor of claim 9, wherein the plurality of fluidly connected air gaps have a depth G between the internal region of the logic die and the internal region of the pixel die, and wherein the depth G is between about 1 µm and about 3 µm.

17. An image sensor comprising: A logic die includes: a functional logic element disposed on a junction side of the logic die; and a logic oxide array with raised logic oxide features disposed on the junction side of the logic die; and a pixel die stacked on top of the logic die, the pixel die including: a pixel array disposed on a light-receiving side of the pixel die; and a pixel oxide array with raised pixel oxide features disposed on a junction side of the pixel die; A plurality of external bonding members disposed between an external region of the logic die and an external region of the pixel die; wherein the raised logic oxide features are attached to the logic die at a plurality of internal bonding members in an internal region of the logic die, wherein the raised pixel oxide features are attached to the pixel die at a plurality of internal bonding members in an internal region of the pixel die, and wherein the internal bonding members are spaced apart from each other and are spaced apart in an x-direction and a y-direction by a plurality of fluid-connected air gaps forming a gap between the internal region of the logic die and the internal region of the pixel die.

18. The image sensor of claim 17, wherein individual raised logical oxide features are aligned with and in contact with individual raised pixel oxide features.

19. The image sensor of claim 18, wherein each raised logical oxide feature has a first height and each raised pixel oxide feature has a second height, wherein the sum of the first height and the second height is equal to a depth G, and wherein the depth G is between about 1 µm and about 3 µm.

20. The image sensor of claim 17, wherein the raised logic oxide features and the raised pixel oxide features form a plurality of logic oxide islands in the shape of a square, an oval or a circle.

21. The image sensor of claim 20, wherein the pixel oxide islands have a rounded shape and wherein the pixel oxide islands have two or more different diameters.

22. The image sensor of claim 21, wherein adjacent pixel oxide islands are separated by a spacing P, wherein the spacing P is greater than about 10 µm and less than about 50 µm.

23. The image sensor of claim 22, wherein adjacent pixel oxide islands are separated by two or more different spacings P.

Images