Packaging substrate and semiconductor package comprising the same

TWI934323BActive Publication Date: 2026-08-01ABSOLICS INC
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Patent Information

Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
ABSOLICS INC
Filing Date
2024-10-29
Publication Date
2026-08-01

AI Technical Summary

Technical Problem

Semiconductor packaging technologies lack sufficient support for high-performance, high-frequency semiconductor devices due to issues with substrate materials such as ceramic and resin, and glass substrates with through-holes are prone to damage during manufacturing and handling.

Method used

A package substrate featuring a glass core with through-holes and a crack prevention layer that provides mechanical and thermal shock resistance, composed of a crack prevention layer with specific properties to stabilize the glass core and enhance electrical connectivity.

Benefits of technology

The package substrate exhibits improved durability against thermal and mechanical shocks, maintaining electrical reliability and stability during manufacturing and operation.

✦ Generated by Eureka AI based on patent content.

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Patent Text Reader

Abstract

A packaging substrate and a semiconductor package including the thereof are provided. The packaging substrate according to this embodiment includes a glass core. The glass core includes a through-hole extending through the thickness direction of the glass core. The glass core has a surface. The packaging substrate includes a crack-resistant layer surrounding at least a portion of the surface of the glass core. In the packaging substrate, the ratio of the thickness of the crack-resistant layer to the thickness of the glass core is 0.0001 to 0.05. In this case, a packaging substrate with excellent durability against thermal and mechanical shocks can be provided.
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Description

Technical Field

[0001] This embodiment relates to a package substrate and a semiconductor package including the same. Prior Art

[0002] When manufacturing electronic components, realizing circuits on semiconductor wafers is called the front-end process (FE), and assembling the wafers in a state that can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid growth of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is advancing in various forms, such as line widths in the nanometer range below micrometers, cells exceeding 10 million, high-speed operation, and the generation of large amounts of heat. However, this advancement lacks the technical support of relatively complete semiconductor packaging. Therefore, the electrical performance of semiconductors sometimes depends on the packaging technology and the corresponding electrical connections, rather than on the performance of the semiconductor technology itself.

[0004] Ceramic or resin is used as the package base material. Ceramic substrates have difficulty mounting high-performance, high-frequency semiconductor devices due to their high resistance and dielectric constant. While resin substrates can mount relatively high-performance, high-frequency semiconductor devices, they have limitations in reducing wiring pitch.

[0005] Recently, research is underway to use silicon or glass as substrates for high-end packaging. By forming through-holes in silicon or glass substrates and applying conductive material to these through-holes, the wiring length between the device and the host board can be shortened, while also achieving excellent electrical characteristics.

[0006] Prior art literature Patent Literature Korean Patent No. 10-1067109 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] An object of the present embodiment is to provide a package substrate having excellent durability against thermal shock and mechanical shock, and a semiconductor package including the same.

[0009] Means used to solve problems

[0010] A package substrate according to an embodiment of the present disclosure includes a glass core.

[0011] The glass core includes a through hole penetrating along a thickness direction of the glass core.

[0012] The glass core has a surface.

[0013] The encapsulation substrate includes a crack prevention layer surrounding at least a portion of a surface of the glass core.

[0014] In the packaging substrate, a ratio of the thickness of the crack prevention layer to the thickness of the glass core is 0.0001 to 0.05.

[0015] The tensile strength of the anti-cracking layer may be 1 MPa to 20 MPa.

[0016] The linear thermal expansion coefficient of the crack prevention layer may be 100 ppm / °C to 800 ppm / °C.

[0017] At a frequency of 100 Hz, the dielectric constant of the anti-cracking layer can be less than 4.

[0018] The package substrate may include a first conductive layer disposed on the crack prevention layer.

[0019] The first conductive layer may have a peel strength of 300 gf or greater with respect to the surface of the crack prevention layer.

[0020] The package substrate may further include an adhesion enhancing layer disposed between the elastic layer and the first conductive layer.

[0021] The anti-cracking layer may be roughened.

[0022] At least a portion of the crack prevention layer may be disposed in contact with a surface of the glass core.

[0023] The crack prevention layer may have a peel strength of 400 gf or greater with respect to the surface of the glass core.

[0024] The anti-cracking layer may include an organic silicone elastomer.

[0025] The surface of the glass core may include: an upper surface; and a side surface connected to the upper surface and formed along the thickness direction of the glass core.

[0026] The crack prevention layer may surround a side surface of the glass core.

[0027] The through hole may include an inner space and a through hole inner diameter surface surrounding the inner space.

[0028] The crack prevention layer may be disposed between the inner space and the inner diameter surface of the through hole.

[0029] The minimum value of the diameter of the internal space may be greater than or equal to 50 μm.

[0030] A semiconductor package according to another embodiment of the present description includes the package substrate and a semiconductor device mounted on the package substrate.

[0031] Effects of the Invention

[0032] The package substrate of the present embodiment can exhibit excellent durability against thermal shock and mechanical shock. Simple diagram description

[0033] FIG. 1 a is a cross-sectional view illustrating a package substrate according to an example of the present embodiment. FIG. 1 b is a plan view illustrating a package substrate according to an example of the present embodiment. FIG2 is an enlarged view of portion A of FIG1a. FIG. 3 is a cross-sectional view illustrating a package substrate according to another example of the present embodiment. FIG. 4 is a cross-sectional view illustrating a package substrate according to still another example of the present embodiment. Implementation Method

[0034] The following describes several embodiments in detail with reference to the accompanying drawings to facilitate implementation by those skilled in the art. However, the present invention can be implemented in a variety of different ways and is not limited to the embodiments described herein. Throughout this specification, identical or similar components are denoted by the same reference numerals.

[0035] Throughout this specification, the term "combination of..." included in a Markush-type description refers to a mixture or combination of one or more components selected from the group consisting of the components described in the Markush-type description, thereby meaning that the present invention includes one or more components selected from the group consisting of the components.

[0036] Throughout this specification, unless otherwise specified, terms such as "first," "second," "A," and "B" are used to distinguish between similar terms. Furthermore, unless otherwise specified, terms referring to the singular should be understood to include the plural.

[0037] In the present specification, the “~” type may refer to a compound including a compound equivalent to “~” or a derivative of “~”.

[0038] In this specification, the meaning of B being located on A is that B is located on A in direct contact or with another layer in between, and should not be limited to the meaning that B is located on the surface of A in contact.

[0039] In this specification, the meaning of A being connected to B refers to A and B being directly connected or being connected through other constituent elements between A and B. Unless otherwise specified, the interpretation is not limited to A and B being directly connected.

[0040] Unless otherwise specified, expressions in the singular in this specification are interpreted as including the singular or plural meaning as explained in the context.

[0041] In this specification, the shape, relative size, angle, etc. of each component in the drawings are exemplary and may be exaggerated for the purpose of explanation, but the scope of rights is not interpreted as being limited to the drawings.

[0042] In this specification, "A and B are adjacent" means that A and B are in contact, or means that A and B are not in contact but are close to each other. In this specification, unless otherwise specified, the expression "A and B are adjacent" should not be interpreted as limited to A and B being in contact.

[0043] In this specification, unless otherwise specified, a fine line refers to a line with a width of 5 μm or less, and illustratively, may refer to a line with a width of 1 μm to 4 μm or less.

[0044] Unless otherwise specified in this specification, the physical properties of each structural element in the package substrate are interpreted as values ​​measured at room temperature, which is 20°C to 25°C.

[0045] To achieve high integration of the package substrate and optimize the signal transmission path, through-holes can be formed in the glass core. However, due to the high hardness of glass, the glass core with such a complex structure is easily damaged by various impacts during the manufacturing process.

[0046] Specifically, during the process of forming the redistribution layer on the glass core, the glass core may be repeatedly exposed to high and low temperatures. This can lead to increased internal stress in the glass core. Furthermore, substrates containing this glass core are susceptible to cracking during movement and handling, even when subjected to minor mechanical shock.

[0047] The inventors of this embodiment have experimentally confirmed that by applying a crack prevention layer to a packaging substrate, the packaging substrate can have stable durability against thermal shock and mechanical shock and can suppress the widespread propagation of cracks throughout the glass core, thereby completing this embodiment.

[0048] Hereinafter, this embodiment will be described in detail.

[0049] FIG1a is a cross-sectional view illustrating a package substrate according to an example of the present embodiment. FIG1b is a plan view illustrating a package substrate according to an example of the present embodiment. FIG2 is an enlarged view of portion A of FIG1a. This embodiment will be described with reference to FIG1a, FIG1b, and FIG2.

[0050] glass core

[0051] The package substrate 100 according to the present embodiment may include a glass core 10 .

[0052] Glass core 10 can be in the form of a glass substrate. Glass core 10 can be made of, for example, alkali borosilicate flat glass, non-alkali borosilicate flat glass, or non-alkali earth borosilicate flat glass. Any flat glass suitable for electronic components can be used. Glass core 10 can be a glass substrate for electronic devices. For example, products manufactured by Schott, AGC, Corning, and the like can be used, but are not limited thereto.

[0053] The thickness of the glass core 10 can be 50 μm or greater. The thickness can be 100 μm or greater. The thickness can be 250 μm or greater. The thickness can be 400 μm or greater. The thickness can be 500 μm or greater. The thickness can be 3000 μm or less. The thickness can be 2000 μm or less. The thickness can be 1000 μm or less. When a glass core 10 having these thicknesses is used, semiconductor devices can be stably fixed and protected.

[0054] The glass core 10 may include a through hole 101 penetrating along a thickness direction of the glass core 10 .

[0055] The through hole 101 is composed of an inner space 102 and a through hole inner diameter surface 103 surrounding the inner space 102. The inner space 102 refers to an empty space, and the through hole inner diameter surface 103 refers to the surface of the glass core 10 formed inside the through hole 101.

[0056] The through hole 101 may have a diameter that varies along the thickness direction of the glass core 10. The through hole 101 may have a substantially uniform diameter in the thickness direction of the glass core 10.

[0057] The cross section of the through hole 101 may have an hourglass shape. The cross section of the through hole 101 may have a rectangular, triangular, or trapezoidal shape other than the hourglass shape. The cross section of the through hole 101 refers to the cross section of the glass core 10 in the thickness direction.

[0058] The through hole 101 may include a first opening portion 104 connected to the upper surface of the glass core 10 and a second opening portion 105 connected to the lower surface of the glass core 10 .

[0059] Through-hole 101 connects first opening 104 and second opening 105 and may further include a minimum inner diameter portion 106, which is the portion with the smallest inner diameter. The diameter of through-hole 101 in minimum inner diameter portion 106 may be smaller than the diameter of through-hole 101 in first opening 104. The diameter of through-hole 101 in minimum inner diameter portion 106 may be smaller than the diameter of through-hole 101 in second opening 105.

[0060] When through-hole 101 includes minimum inner diameter portion 106, the cross-section of through-hole 101 can have an hourglass shape. When through-hole 101 has an hourglass-shaped cross-section, it is easier to form a thin film on through-hole inner diameter surface 103 by coating or sputtering. Thus, when a conductive layer and / or crack prevention layer 20 is formed within through-hole 101, the reliability of package substrate 100 can be further improved.

[0061] The diameter of the through hole 101 in the first opening 104 may be 40 μm to 200 μm. The diameter may be greater than 60 μm. The diameter may be greater than 80 μm. The diameter may be greater than 100 μm. The diameter may be less than 180 μm. The diameter may be less than 160 μm. The diameter may be less than 140 μm. The diameter may be less than 120 μm.

[0062] The diameter of the through hole 101 in the second opening 105 may be 40 μm to 200 μm. The diameter may be greater than 60 μm. The diameter may be greater than 80 μm. The diameter may be greater than 100 μm. The diameter may be less than 180 μm. The diameter may be less than 160 μm. The diameter may be less than 140 μm. The diameter may be less than 120 μm.

[0063] In this case, the electrical reliability of the package substrate 100 can be stably controlled while further improving the integration degree of the package substrate 100 .

[0064] The diameter of the through hole 101 in the minimum inner diameter portion 106 may be 50% to 99% of the smaller diameter value of the diameter of the through hole 101 in the first inner diameter portion or the diameter of the through hole 101 in the second inner diameter portion. The diameter of the through hole 101 in the minimum inner diameter portion 106 may be 60% or more of the smaller diameter value of the diameter of the through hole 101 in the first inner diameter portion or the diameter of the through hole 101 in the second inner diameter portion. The diameter of the through hole 101 in the minimum inner diameter portion 106 may be 70% or more of the smaller diameter value of the diameter of the through hole 101 in the first inner diameter portion or the diameter of the through hole 101 in the second inner diameter portion. The diameter of the through hole 101 in the minimum inner diameter portion 106 may be 90% or less of the smaller diameter value of the diameter of the through hole 101 in the first inner diameter portion or the diameter of the through hole 101 in the second inner diameter portion. The diameter of the through hole 101 in the minimum inner diameter portion 106 may be 80% or less of the smaller diameter between the diameter of the through hole 101 in the first inner diameter portion and the diameter of the through hole 101 in the second inner diameter portion. In this case, a uniform thickness of the crack prevention layer 20 and / or the conductive layer can be formed over the entire through hole inner diameter surface 103.

[0065] The surface of the glass core 10 may include an upper surface and a side surface connected to the upper surface and formed in a thickness direction of the glass core 10. The surface of the glass core 10 may include a lower surface opposite to the upper surface.

[0066] The side surface formed along the thickness direction of the glass core 10 not only means that the side surface is formed perpendicular to the upper surface of the glass core 10, but also means that at least a portion of the side surface forms an angle (inclination angle) other than 90 degrees with the upper surface.

[0067] The side surface may be a plane or a curved surface.

[0068] The glass core 10 may include a hollow space inside.

[0069] The cavity may be formed by partially recessing the upper surface or lower surface of the glass core 10 in the thickness direction of the glass core 10 , or may be formed by penetrating the glass core 10 in the thickness direction of the glass core 10 .

[0070] By mounting the device in the cavity, the package substrate 100 and the device are electrically connected. The device can be not only a semiconductor device such as a CPU, GPU, or memory chip, but also a capacitor device, a transistor device, an impedance device, and other modules. In other words, any semiconductor device mounted on a semiconductor device can be used as the device without restriction.

[0071] Structure of the anti-cracking layer

[0072] The glass core 10 may have a surface. The encapsulation substrate 100 may include a crack prevention layer 20 surrounding at least a portion of the surface of the glass core 10.

[0073] The crack prevention layer 20 stably supports the glass core 10 in high-temperature environments, preventing it from bending and being damaged by internal stress. It also effectively inhibits cracks that have already occurred within the glass core 10 from spreading further. Furthermore, the crack prevention layer 20 imparts controlled elasticity to predetermined areas of the package substrate 100, thereby stably protecting the package substrate 100 from mechanical shocks that may occur during handling.

[0074] In this embodiment, the ratio of the thickness of the glass core 10 to the thickness of the anti-crack layer 20 can be adjusted within a predetermined range. In this case, the durability of the encapsulation substrate 100 against external impacts can be improved by more firmly supporting and protecting the glass core 10. Furthermore, the heat treatment time required to form the anti-crack layer 20 can be adjusted to prevent excessive thermal deformation of the glass core 10.

[0075] The thickness of the crack prevention layer 20 is the thickness of the crack prevention layer 20 located on the upper surface, side surface, or lower surface of the glass core 10. That is, the thickness of the crack prevention layer 20 not formed in the through-hole 101 is considered the thickness of the crack prevention layer 20. When the thickness of the crack prevention layer 20 is uneven at different locations, the average thickness of the crack prevention layer 20 is the thickness of the crack prevention layer 20 according to this embodiment.

[0076] The ratio of the thickness of the crack prevention layer 20 to the thickness of the glass core 10 can be 0.0001 to 0.05. The ratio can be greater than 0.0005. The ratio can be greater than 0.001. The ratio can be greater than 0.003. The ratio can be greater than 0.005. The ratio can be less than 0.03. The ratio can be less than 0.02. In this case, a package substrate 100 having improved durability can be provided without excessively damaging the glass core 10.

[0077] The thickness of the crack prevention layer 20 can be 100 nm to 50 μm. The thickness can be greater than 500 nm. The thickness can be greater than 1 μm. The thickness can be greater than 3 μm. The thickness can be greater than 5 μm. The thickness can be less than 40 μm. The thickness can be less than 30 μm. The thickness can be less than 20 μm. In this case, the crack prevention layer 20 can firmly support the glass core 10 and effectively prevent cracks from forming and expanding within the glass core 10. In addition, the crack prevention layer 20 can be formed within a controlled curing time.

[0078] The crack prevention layer 20 may surround the side surface of the glass core 10 .

[0079] External force applied to the package substrate 100 during handling by an operator may act mainly in the direction of the side surface of the glass core 10. The crack prevention layer 20 formed with the above structure can more effectively protect the glass core 10 from mechanical impact.

[0080] The crack prevention layer 20 surrounding the side surface of the glass core 10 may surround not only the side surface of the glass core 10 but also at least a portion of the upper surface and / or lower surface of the glass core 10. In this case, the crack prevention layer 20 may cover the edges of the upper surface and / or lower surface.

[0081] The anti-crack layer 20 surrounding the glass core 10 not only means the situation that the anti-crack layer 20 surrounds the glass core 10 in a manner connected to the glass core 10, but is also interpreted as including the situation that the anti-crack layer 20 surrounds the side surface of the glass core 10 in a state where other components are arranged between the anti-crack layer 20 and the glass core 10.

[0082] FIG3 is a cross-sectional view illustrating a package substrate according to another example of the present embodiment.

[0083] The encapsulation substrate includes a glass core. The specific structure of the encapsulation substrate is described above in Figures 1a, 1b, and 2. The following description focuses on the differences.

[0084] The crack prevention layer 20 can be disposed between the interior space 102 and the through-hole inner diameter surface 103. Because the through-hole 101 has a delicate and complex structure, the area surrounding the through-hole 101 may correspond to a portion of the glass core 10 that is particularly susceptible to impact. When the crack prevention layer 20 has the aforementioned structure, it can more effectively prevent the formation and propagation of cracks within the glass core 10.

[0085] When the crack prevention layer 20 has the above-described structure, this embodiment can adjust the minimum diameter of the internal space 102 within a predetermined range. In this case, a conductive layer can be formed within the through hole 101 with relative ease without any gaps, thereby improving the electrical reliability of the package substrate 100 to a certain level.

[0086] The minimum diameter of the internal space 102 may be 50 μm or greater. The minimum diameter may be 65 μm or greater. The minimum diameter may be 80 μm or greater. The minimum diameter may be 200 μm or less. The minimum diameter may be 180 μm or less. The minimum diameter may be 120 μm or less. In this case, a conductive layer can be easily formed within the through hole 101.

[0087] The crack prevention layer 20 can have a structure that surrounds the entire surface of the glass core 10. In other words, the crack prevention layer 20 can be provided not only on the side of the through-hole 101, but also on the upper, lower, and side surfaces of the glass core 10. This protects the glass core 10 from external impacts and helps prevent cracks from spreading throughout the entire glass core 10.

[0088] Physical properties of anti-cracking layer

[0089] This embodiment allows for controlled tensile strength of the crack prevention layer 20. The crack prevention layer 20, with its controlled strength, can stably secure the glass core 10, which can deform due to thermal stress. This prevents defects caused by bending of the glass core 10 during the manufacturing process, particularly during the formation of the redistribution layer. Furthermore, the crack prevention layer 20 imparts appropriate elasticity to at least a portion of the package substrate 100, mitigating external impacts on the glass core 10.

[0090] The tensile strength of the crack prevention layer 20 can be measured using a universal testing machine (UTM).

[0091] The anti-crack layer 20 may have a tensile strength of 1 MPa to 20 MPa. The tensile strength may be greater than 2 MPa. The tensile strength may be greater than 4 MPa. The tensile strength may be less than 15 MPa. The tensile strength may be less than 10 MPa. In this case, even if the glass core 10 has a structure that is susceptible to impact, the encapsulation substrate 100 can still have stable durability.

[0092] The crack prevention layer 20 can have a linear thermal expansion coefficient within a predetermined range in this embodiment. Having these characteristics can prevent damage to the glass core 10 by modulating the external forces applied to the glass core 10 due to the thermal expansion of the crack prevention layer 20 itself during the formation of the rewiring layer. Furthermore, when a conductive layer is provided in contact with the crack prevention layer 20, damage to the electrical connection caused by the expansion of the crack prevention layer 20 can be suppressed.

[0093] The linear thermal expansion coefficient is a value measured using dynamic mechanical analysis (DMA).

[0094] The linear thermal expansion coefficient of the crack prevention layer 20 is 100 ppm / °C to 800 ppm / °C. The linear thermal expansion coefficient may be greater than 150 ppm / °C. The linear thermal expansion coefficient may be greater than 200 ppm / °C. The linear thermal expansion coefficient may be greater than 250 ppm / °C. The linear thermal expansion coefficient may be greater than 300 ppm / °C. The linear thermal expansion coefficient may be less than 700 ppm / °C. The linear thermal expansion coefficient may be less than 600 ppm / °C. The linear thermal expansion coefficient may be less than 500 ppm / °C. The linear thermal expansion coefficient may be less than 400 ppm / °C. In this case, the package substrate 100 can have stable durability and electrical reliability even after repeated heat treatments.

[0095] This embodiment can control the dielectric properties of the crack prevention layer 20. When a conductive layer is formed on the crack prevention layer 20, the crack prevention layer 20 can function as an insulator. By achieving a high density of fine patterns on the crack prevention layer 20 with controlled dielectric properties, signal aliasing between wirings can be suppressed, and power consumption of the package substrate 100 caused by the dielectric properties of the crack prevention layer 20 can also be reduced.

[0096] The dielectric constant of the crack prevention layer 20 is measured using a dielectric constant meter at room temperature.

[0097] At a frequency of 100 Hz, the dielectric constant of the crack prevention layer 20 may be 4 or less. The dielectric constant may be 3.5 or less. The dielectric constant may be 3 or less. The dielectric constant may be 2.8 or less. The dielectric constant may be 1.5 or greater.

[0098] At a frequency of 100 kHz, the dielectric constant of the crack prevention layer 20 may be 4 or less. The dielectric constant may be 3.5 or less. The dielectric constant may be 3 or less. The dielectric constant may be 2.8 or less. The dielectric constant may be 1.5 or greater.

[0099] In this case, the conductive layer pattern formed on the crack prevention layer 20 can effectively transmit signals.

[0100] The package substrate 100 may include a first conductive layer (not shown) disposed on the crack prevention layer 20. The peel strength of the first conductive layer relative to the crack prevention layer 20 may be greater than 300 gf.

[0101] The conductive layer is a conductor that transmits electrical signals. The conductive layer may include a first conductive layer. The first conductive layer is the conductive layer located closest to the anti-crack layer 20. At least a portion of the first conductive layer may be formed to contact the anti-crack layer 20. The conductive layer may include a conductive material. For example, the conductive layer may include at least one of copper, nickel, aluminum, gold, and silver. The conductive layer may be made of copper, for example.

[0102] When the first conductive layer is formed on the crack prevention layer 20, the crack prevention layer 20 can serve as a support and insulator for the first conductive layer. This embodiment can improve the bonding force between the crack prevention layer 20 and the first conductive layer, so that the crack prevention layer 20 can stably fix the first conductive layer.

[0103] The peel strength of the first conductive layer relative to the crack prevention layer 20 was measured using an adhesion tester using a 180° peel test. The measurement speed (peel speed) was set to 10 mm / s, the measurement distance (peel distance) was set to 70 mm, and the measurement area was set to the area on the upper and lower surfaces of the glass core where no through-holes were formed. For example, the above peel strength value can be measured using a Condor Sigma adhesion tester from XYZ TEC.

[0104] The average value of the measured peel strength values ​​is taken as the peel strength of the first conductive layer with respect to the crack prevention layer 20 .

[0105] The first conductive layer may have a peel strength relative to the crack prevention layer 20 of 300 gf or greater. The peel strength may be 350 gf or greater. The peel strength may be 400 gf or greater. The peel strength may be 450 gf or greater. The peel strength may be 500 gf or greater. The peel strength may be 1200 gf or less. In this case, the crack prevention layer 20 can help form fine micropatterns on the upper surface of the glass core 10, etc., by stably supporting and securing the first conductive layer.

[0106] In this embodiment, in order to further increase the bonding force between the anti-crack layer 20 and the first conductive layer, an adhesion enhancement layer (not shown in the figure) can be provided between the anti-crack layer 20 and the first conductive layer (or conductive layer).

[0107] The adhesion enhancement layer can further improve the bonding force between the organic anti-crack layer 20 and the first conductive layer (or conductive layer), thereby more stably maintaining the electrical reliability of the first conductive layer (or conductive layer).

[0108] The adhesion enhancing layer may be any one selected from the group consisting of azole compounds, silane compounds, silanized azole compounds, and combinations thereof. The adhesion enhancing layer having the above composition can effectively improve the bonding strength of the conductive layer without excessively etching the conductive layer.

[0109] To further improve the peel strength of the first conductive layer relative to the anti-crack layer 20, the anti-crack layer 20 can be roughened. Increasing the surface roughness of the anti-crack layer 20 increases the contact area between the anti-crack layer 20 and the first conductive layer, creating an anchoring effect at the interface between the anti-crack layer 20 and the first conductive layer, thereby further improving the peel strength.

[0110] At least a portion of the crack prevention layer 20 may be provided in contact with the surface of the glass core 10. The crack prevention layer 20 may have a peel strength of 400 gf or greater relative to the surface of the glass core 10.

[0111] The bonding force between the crack prevention layer 20 and the glass core 10 at the joint portion thereof can be controlled within the range of this embodiment. This prevents the crack prevention layer 20 from easily separating from the glass core 10 and allows the crack prevention layer 20 to stably support and protect the glass core 10. Furthermore, the electrical connection between the conductive layer pattern formed on the crack prevention layer 20 and the conductive layer pattern formed in another area of ​​the package substrate 100 can be less easily disconnected.

[0112] The peel strength of the crack preventing layer 20 with respect to the surface of the glass core 10 is measured under the same conditions as the method of measuring the peel strength of the first conductive layer with respect to the crack preventing layer 20 .

[0113] The peel strength of the crack prevention layer 20 relative to the surface of the glass core 10 can be 400 gf or greater. The peel strength can be 450 gf or greater. The peel strength can be 500 gf or greater. The peel strength can be 550 gf or greater. The peel strength can be 600 gf or greater. The peel strength can be 1200 gf or less. In this case, the crack prevention layer 20 is unlikely to fall off the surface of the glass core 10, thereby helping to stably maintain the durability and electrical reliability of the package substrate 100.

[0114] Composition of anti-cracking layer

[0115] The crack prevention layer 20 may include an organic silicone elastomer.

[0116] The silicone elastomer imparts the mechanical properties required in this embodiment to the crack prevention layer 20, thereby stably securing the glass core 10 in high-temperature atmospheres and operating environments. Furthermore, the silicone elastomer can be cured in a relatively short period of time through heat treatment after light treatment. This increases the crosslink density of the crack prevention layer 20, enhancing its hardness. The duration of high-temperature exposure of the glass core 10 during the formation of the crack prevention layer 20 is controlled, thereby suppressing deformation of the glass core 10 due to thermal stress.

[0117] The crack prevention layer 20 may comprise at least 70% by weight of an organosilicon elastomer. The crack prevention layer 20 may comprise at least 80% by weight of an organosilicon elastomer. The crack prevention layer 20 may comprise at least 90% by weight of an organosilicon elastomer. The crack prevention layer 20 may comprise at most 100% by weight of an organosilicon elastomer. The crack prevention layer 20 may be an organosilicon elastomer. In this case, the crack prevention layer 20 is imparted with increased hardness, thereby stably securing the glass core 10 and reducing the degree of bending of the glass core 10 to below a certain level during the substrate manufacturing process.

[0118] Silicone elastomers can be produced by cross-linking a base agent, which is a silicone resin, and a curing agent.

[0119] The main agent may contain an alkenyl group at one or more terminals. The main agent may have a structure of the following Chemical Formula 1. [Chemical Formula 1] In the chemical formula 1, n is an integer from 20 to 60.

[0120] The curing agent may have a structure of the following Chemical Formula 2. [Chemical Formula 2] In the Chemical Formula 2, x and y are each independently an integer of 2 to 10.

[0121] During the curing process, the alkenyl groups in the main agent can form crosslinks with the curing agent. This can increase the crosslink density within the blended resin and impart controlled hardness to the anti-cracking layer 20.

[0122] When forming the crack prevention layer 20, 3 to 20 parts by weight of curing agent can be used relative to 100 parts by weight of the main agent. When forming the crack prevention layer 20, 5 or more parts by weight of curing agent can be used relative to 100 parts by weight of the main agent. When forming the crack prevention layer 20, 8 or more parts by weight of curing agent can be used relative to 100 parts by weight of the main agent. When forming the crack prevention layer 20, 15 or less parts by weight of curing agent can be used relative to 100 parts by weight of the main agent. This helps impart the desired hardness and elasticity of this embodiment to the crack prevention layer 20.

[0123] The anti-crack layer 20 may further include a metal catalyst. The metal catalyst may cause the organosilicon elastomer to crosslink in a short period of time. For example, a platinum catalyst may be used as the metal catalyst.

[0124] The anti-cracking layer 20 may further include other additives in addition to the above-mentioned blended resin. The additives are not limited as long as they are commonly used in the film field.

[0125] Other components of the package substrate

[0126] FIG4 is a schematic diagram illustrating a package substrate according to yet another example of the present embodiment.

[0127] The encapsulation substrate includes a glass core. The specific structure of the encapsulation substrate is described above in Figures 1a, 1b, 2, and 3. The following description focuses on the differences.

[0128] The rewiring layer 30 may include an insulating layer 32 and a conductive layer 31 disposed within the insulating layer 32 .

[0129] The package substrate 100 may include a redistribution layer 30 disposed on the glass core 10. The package substrate 100 may include a redistribution layer 30 disposed below the glass core 10. The package substrate 100 may include a redistribution layer 30 disposed above and below the glass core 10.

[0130] The redistribution layer 30 may be disposed within the through-hole 101. The conductive layer 31 may be disposed within the through-hole 101. When only the conductive layer 31 is present within the through-hole 101, the conductive layer 31 may be formed by filling the interior space 102 of the through-hole 101. When both the conductive layer 31 and the insulating layer 32 are present within the through-hole 101, the conductive layer 31 may be disposed adjacent to the through-hole inner diameter surface 103, and the insulating layer 32 may be disposed within the region surrounded by the conductive layer 31.

[0131] The rewiring layer 30 may be provided in contact with the surface of the glass core 10. Other components may be provided between the rewiring layer 30 and the surface of the glass core 10. The crack prevention layer 20 may be provided between the rewiring layer 30 and the surface of the glass core 10.

[0132] In the redistribution layer 30, an insulating layer 32 and a conductive layer 31 may be provided in a mixed manner. The redistribution layer 30 may be formed by embedding a conductive layer 31 having a predetermined position and form within the insulating layer 32. The conductive layer 31 may be formed as a thin line on at least a portion of the redistribution layer 30. The redistribution layer 30 may be electrically connected to upper and / or lower terminals, devices, and the like of the package substrate 100.

[0133] The rewiring layer 30 may be formed by repeating the process of forming and removing the insulating layer 32 and the conductive layer 31 .

[0134] For example, the insulating layer 32 may be formed using a build-up layer material such as Ajinomoto Build-up Film (ABF) produced by Ajinomoto Co., Ltd. of Japan, a primer material, etc., but is not limited thereto.

[0135] The description of the material of the conductive layer 31 overlaps with the previous content, so it will be omitted.

[0136] The package substrate 100 may further include a redistribution layer 30 and / or bumps (not shown) disposed below the glass core 10 .

[0137] The bumps may be provided in a predetermined form below the glass core 10. For example, the bumps may be provided on a portion of the lower surface of the package substrate 100 to be connected to a host board or the like.

[0138] semiconductor packaging

[0139] A semiconductor package according to still another example of the present embodiment includes a package substrate and a device electrically connected to the package substrate.

[0140] The package substrate may be mounted on a mainboard and electrically connected to the mainboard.

[0141] The description of the packaging substrate and devices overlaps with the previous content and will therefore be omitted.

[0142] Method for manufacturing package substrate

[0143] According to another example of the present embodiment, a method for manufacturing a package substrate includes: a through-hole forming step of forming a glass core by forming a through-hole in a glass substrate that penetrates the glass substrate in a thickness direction; and a crack prevention layer manufacturing step of forming a crack prevention layer around at least a portion of a surface of the glass core to manufacture the package substrate.

[0144] In the through-hole forming step, the glass substrate can be, for example, alkali borosilicate flat glass, non-alkali borosilicate flat glass, or non-alkali earth borosilicate flat glass. Any flat glass suitable for electronic components can be used. As the glass core, a glass substrate used in electronic devices can be used. Examples include, but are not limited to, products manufactured by Schott, AGC, and Corning.

[0145] In the through-hole forming step, the glass core can be formed by etching the glass substrate. Specifically, a defect can be formed at a predetermined position within the surface of the glass substrate. Methods for forming the defect can include mechanical etching and laser irradiation.

[0146] After the defects are formed, through-holes can be formed by physical or chemical etching. When chemical etching is used, wet etching can be performed using an etching solution. The etching solution is not limited, as long as it is an etching solution commonly used for etching glass substrates. For example, the etching solution can be a sulfuric acid solution, a nitric acid solution, or a hydrofluoric acid solution.

[0147] During the etching process, the remaining surface of the glass substrate except for the area where the defect is formed may be masked, or etching may be performed without masking.

[0148] A defect may be formed at one point on the upper surface of the glass substrate, and a defect may be formed at another point in the lower surface of the glass substrate opposite to the one point, and etching is performed to form a through hole having an hourglass-shaped cross section.

[0149] The opening on the upper surface side of the formed through hole is called the first opening, the opening on the lower surface side is called the second opening, and the part with the smallest diameter in the through hole is called the minimum inner diameter part.

[0150] The description of the first opening, the second opening and the minimum inner diameter portion is repeated in the previous description and will therefore be omitted.

[0151] In the crack prevention layer manufacturing step, the crack prevention layer can be formed at a predetermined position on the glass core. The description of the setting position of the crack prevention layer overlaps with the previous content, so the description will be omitted.

[0152] The anti-cracking layer can be formed by lamination or wet coating.

[0153] During the lamination process, the encapsulation substrate can be manufactured by stacking a film-like anti-crack layer at a predetermined position on the glass core.

[0154] In the wet coating method, the composition for manufacturing the crack preventing layer may be applied to a predetermined position of the glass core, and the applied composition for manufacturing the crack preventing layer may be cured to form the crack preventing layer.

[0155] The composition used to make the crack prevention layer can include a base agent of an organosilicon elastomer and a curing agent. The description of the composition of the base agent and curing agent of the organosilicon elastomer overlaps with the previous description and will be omitted.

[0156] The composition for producing the anti-crack layer may include 3 to 20 parts by weight of a curing agent relative to 100 parts by weight of the main agent. The composition for producing the anti-crack layer may include 5 or more parts by weight of a curing agent relative to 100 parts by weight of the main agent. The composition for producing the anti-crack layer may include 8 or more parts by weight of a curing agent relative to 100 parts by weight of the main agent. The composition for producing the anti-crack layer may include 15 or less parts by weight of a curing agent relative to 100 parts by weight of the main agent. This helps impart the desired mechanical properties of this embodiment to the anti-crack layer.

[0157] The composition for manufacturing the anti-cracking layer can be coated by methods such as spin coating or slit coating, but is not limited thereto.

[0158] The crack preventing layer may be formed by thermally curing the applied composition for manufacturing the crack preventing layer.

[0159] The composition for making the anti-cracking layer can be cured at a relatively low heat treatment temperature. The relatively low heat treatment temperature can be 70°C to 120°C. The temperature can be above 80°C. The temperature can be above 90°C. The temperature can be below 110°C.

[0160] When the composition for making the crack prevention layer is cured at a relatively low heat treatment temperature, the heat treatment can be performed for a relatively long time. In this case, the heat treatment time for the composition for making the crack prevention layer can be 30 to 90 minutes. The heat treatment time can be 40 minutes or longer. The heat treatment time can be 50 minutes or longer. The heat treatment time can be 80 minutes or less.

[0161] In this case, it is possible to suppress excessive thermal stress from being generated in the glass core during the formation of the crack preventing layer.

[0162] The composition used to manufacture the anti-cracking layer can be cured at a relatively high heat treatment temperature. The relatively high heat treatment temperature can be 120°C to 180°C. The temperature can be above 130°C, above 140°C, or below 170°C.

[0163] When the composition for making the crack prevention layer is cured at a relatively high heat treatment temperature, the heat treatment can be performed for a relatively short time. In this case, the heat treatment time for the composition for making the crack prevention layer can be 5 to 30 minutes. The heat treatment time can be 10 minutes or longer. The heat treatment time can be 15 minutes or longer. The heat treatment time can be 25 minutes or less.

[0164] In this case, thermal deformation of the glass core can be suppressed by reducing the time the glass core is exposed to high temperature.

[0165] The description about the thickness of the formed anti-crack layer overlaps with the previous content, so the description will be omitted.

[0166] In order to improve the bonding strength of the conductive layer to the anti-crack layer, the surface of the anti-crack layer can be roughened. During the formation of the anti-crack layer, the bonding strength between the conductive layer and the anti-crack layer can be adjusted by adjusting the heat treatment time and heat treatment temperature.

[0167] As another method to improve the bonding strength of the conductive layer to the crack prevention layer, an adhesion enhancement layer can be formed on the surface of the crack prevention layer. The description of the adhesion enhancement layer overlaps with the previous content and will be omitted.

[0168] A rewiring layer may be formed on the package substrate on which the crack prevention layer is formed. After a conductive layer is formed on the glass core or the crack prevention layer, an insulating layer may be formed around the conductive layer to form the rewiring layer.

[0169] The conductive layer can be formed by a dry process or a wet process.

[0170] The dry process forms a seed layer by sputtering the area where the conductive layer is to be placed, and then electroplating the area where the seed layer has been formed to form the conductive layer. When forming the seed layer, metals such as titanium, chromium, and nickel can be sputtered, or these metals can be sputtered together with copper. Sputtering creates an anchoring effect between the surface of the glass core, crack prevention layer, or insulating layer and the metal particles, thereby improving the adhesion of the conductive layer.

[0171] The wet process involves applying a primer to the area where the conductive layer is to be formed, followed by metal plating. The primer can include a compound with functional groups such as amines. Depending on the desired adhesion, the primer can include both a compound with functional groups such as amines and a silane coupling agent. When using a silane coupling agent, the primer layer can be formed by pre-treating the primer-treated surface with the silane coupling agent and then applying the compound with amines to the pre-treated area.

[0172] After forming the seed layer or primer layer, a conductive layer can be formed by metal electroplating. Copper plating can be used for forming the conductive layer, but is not limited thereto. Prior to metal electroplating, the portions of the seed layer or primer layer where the conductive layer is not required are passivated, or the portions where the conductive layer is required are activated, and then electroplating can be performed. Activation or passivation methods can include irradiation with laser light of a specific wavelength, chemical treatment, and the like. However, metal electroplating can also be performed without activation or passivation, and then the conductive layer can be etched and patterned according to a pre-designed shape.

[0173] After forming the conductive layer, an insulating layer can be formed surrounding the conductive layer. The insulating layer can be a film-shaped insulating layer. Specifically, the insulating layer can be formed by laminating the film-shaped insulating layer under reduced pressure. In this case, the insulating layer is formed to surround the conductive layer without gaps, enabling the package substrate to have excellent electrical reliability.

[0174] The description of the setting position of the rewiring layer overlaps with the previous content, so it will be omitted.

[0175] As needed, a process of forming connection terminals, bumps, a covering layer, etc. on the upper surface and / or lower surface of the package substrate or mounting a device on the substrate can be further performed.

[0176] The following examples are provided to illustrate the present embodiment in more detail. The following examples are merely examples for explaining and understanding the present embodiment, and the scope of the present embodiment is not limited thereto.

[0177] Manufacturing Example: Manufacturing of Package Substrate

[0178] Example 1: After laser irradiation was used to create defects on the surface of a glass plate SG7.8 (thickness 0.7 mm) from Corning, wet etching was performed to form multiple through-holes, thereby manufacturing a glass core. The diameter of the core through-holes was adjusted to 100 μm.

[0179] Dow's Sylgard 184 composition, used to create the crack prevention layer, was applied to the upper surface of the glass core. The base and curing agent of Sylgard 184 were mixed in a ratio of 10:1 (by weight) and then applied to the glass plate. The applied composition was heat-treated at 100°C for 60 minutes and cured, forming an 8μm thick crack prevention layer. A nickel target was used to sputter the crack prevention layer to form a nickel layer, and a copper target was used to sputter the nickel layer to form a copper layer, completing the seed layer. Copper was plated on the seed layer to form a first conductive layer with a total thickness of 1μm, thus preparing the package substrate.

[0180] Example 2: A package substrate was manufactured under the same conditions as in Example 1 except that the thickness of the anti-crack layer was set to 7 μm.

[0181] Example 3: A package substrate was manufactured under the same conditions as in Example 1 except that the thickness of the anti-crack layer was set to 10 μm.

[0182] Example 4: A package substrate was manufactured under the same conditions as in Example 1 except that the thickness of the anti-crack layer was set to 11 μm.

[0183] Comparative Example 1: A package substrate was manufactured under the same conditions as in Example 1, except that 3M's Scotchgard Film Protector FX-1000 was used as the composition for manufacturing the anti-crack layer to form the anti-crack layer without performing a heat treatment.

[0184] Evaluation Example: Measurement of the Peel Strength of the Conductive Layer to the Anti-Crack Layer

[0185] On the package substrates of each example, the peel strength of the first conductive layer relative to the crack prevention layer was measured using a Condor Sigma adhesion tester from XYZ TEC, using a 180° peel test. The measurement speed (peel speed) was set to 10 mm / s, the measurement distance (peel distance) was set to 70 mm, and the measurement area was set to an area without through-holes. The average peel strength measured during the crack prevention layer peeling process for each manufacturing example was used as the peel strength for each manufacturing example.

[0186] The measured values ​​for each example are reported in Table 1 below.

[0187] Evaluation Example: Heat Resistance Evaluation

[0188] The package substrates of each Example and Manufacturing Example were exposed to 100°C for 10 minutes. The package substrates of each Example and Manufacturing Example were then visually inspected. If the package substrate warped or the crack prevention layer deformed, the substrate was evaluated as unacceptable. If neither warping nor deformation occurred, the substrate was evaluated as acceptable.

[0189] The evaluation results of each example and comparative example are shown in Table 1 below.

[0190] Evaluation Example: Evaluation of Physical Properties of Crack-Preventing Layer

[0191] The tensile strength of the crack prevention layer in the package substrate of Example 1 was measured at room temperature using a universal testing machine (UTM).

[0192] The linear thermal expansion coefficient of the crack prevention layer was measured using dynamic mechanical analysis (DMA).

[0193] The dielectric constant of the crack prevention layer at a frequency of 100 Hz and the dielectric constant at a frequency of 100 kHz were measured using a dielectric constant meter.

[0194] The measured values ​​of Example 1 are shown in Table 2 below.

[0195] Table 1 Anti-cracking layer thickness (μm) Ratio of crack-proof layer thickness to glass core thickness Maximum peel strength (gf) Average peel strength (gf) Heat resistance evaluation Example 1 8 0.011 751.8 691.5 qualified Example 2 7 0.010 871.6 683.4 qualified Example 3 10 0.014 795.2 687.4 qualified Example 4 11 0.016 837.9 776.9 qualified Comparative Example 1 8 0.011 - - Unqualified

[0196] Table 2 Tensile strength (MPa) Linear thermal expansion coefficient (ppm / ℃) Dielectric constant at a frequency of 100 Hz Dielectric constant at a frequency of 100 kHz Example 1 6.7 340 2.72 2.68

[0197] In Table 1, the average peel strength of each manufacturing example is 600 gf or more. This means that the conductive layer has excellent bonding strength with the crack prevention layer in all manufacturing examples.

[0198] In the heat resistance evaluation, all Examples 1 to 4 were evaluated as acceptable, whereas Comparative Example 1 was evaluated as unacceptable.

[0199] The preferred embodiments of the present invention are described in detail above, but the scope of the present invention is not limited thereto. Various modifications and improvements made by ordinary technicians in the technical field of the present invention using the basic concepts of the present invention defined in the appended claims also fall within the scope of the present invention.

[0200] 10: Glass core 100: packaging substrate 101:Through hole 102: Interior Space 103: Through hole inner diameter surface 104: First opening 105: Second opening 106:Minimum inner diameter part 20: Anti-cracking layer 30: Rewiring layer 31: conductive layer 32: Insulation layer

Claims

1. An encapsulation substrate comprising a glass core, the glass core including a through-hole extending along the thickness direction of the glass core, the glass core having a surface, the encapsulation substrate including a crack-resistant layer surrounding at least a portion of the surface of the glass core, the encapsulation substrate including a first conductive layer disposed on the crack-resistant layer, the ratio of the thickness of the crack-resistant layer to the thickness of the glass core being 0.0001 to 0.05, wherein the through-hole includes an internal space and an inner diameter surface surrounding the internal space, the crack-resistant layer being disposed between the internal space and the inner diameter surface of the through-hole, the minimum diameter of the internal space being 50 μm or more, and wherein the peel strength of the first conductive layer relative to the crack-resistant layer is 300 gf or more.

2. The encapsulation substrate as claimed in claim 1, wherein the tensile strength of the crack-resistant layer is from 1 MPa to 20 MPa.

3. The encapsulation substrate as claimed in claim 1, wherein the linear coefficient of thermal expansion of the crack-resistant layer is from 100 ppm / ℃ to 800 ppm / ℃.

4. The packaging substrate as claimed in claim 1, wherein the dielectric constant of the anti-crack layer is 4 or less at a frequency of 100 Hz.

5. The encapsulation substrate as claimed in claim 1, further comprising an adhesion enhancement layer disposed between the crack-resistant layer and the first conductive layer.

6. The encapsulation substrate as claimed in claim 1, wherein the crack-resistant layer is roughened.

7. The encapsulation substrate as claimed in claim 1, wherein at least a portion of the crack-resistant layer is configured to be in contact with the surface of the glass core, and the peel strength of the crack-resistant layer relative to the surface of the glass core is 400 gf or more.

8. The encapsulation substrate as claimed in claim 1, wherein the crack-resistant layer comprises an organosilicon elastomer.

9. The encapsulation substrate as claimed in claim 1, wherein the surface of the glass core comprises: upper surface; The anti-crack layer surrounds the side surface of the glass core, and is connected to the upper surface and formed along the thickness direction of the glass core.

10. A semiconductor package comprising a package substrate as described in claim 1 and a semiconductor device mounted on the package substrate.