Method of manufacturing structure having electrode and anodized part

Abstract

A method of manufacturing a structure having electrodes and anodized portions includes: forming a top metal layer on a substrate; forming a top patterned photoresist on the top metal layer to expose a portion of the top surface of the top metal layer, wherein the top patterned photoresist has a first masking portion and a second masking portion thicker than the first masking portion; anodizing the top metal layer through the top patterned photoresist to form an anodized segment; removing the first masking portion after anodizing; and after removing the first masking portion, etching the top metal layer through the top patterned photoresist to form a top metal pattern.

Description

Technical Field

[0001] The present disclosure relates to a method of manufacturing a structure having an electrode and an anodized portion. Prior Art

[0002] The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

[0003] Traditional display manufacturing is a standardized process. In recent years, new types of displays such as micro LED displays, mini LED displays, quantum dot LED displays, etc. have emerged and are expected to dominate the display field, so new display manufacturing processes are waiting to be established. A set of processes for making a display includes many steps, and reducing one of the steps can reduce costs and improve efficiency. Summary of the invention

[0004] According to some embodiments of the present disclosure, a method for manufacturing a structure having an electrode and an anodized portion includes: forming a top metal layer on a substrate; forming a top patterned photoresist on the top metal layer to expose a portion of a top surface of the top metal layer, wherein the top patterned photoresist has a first mask portion and a second mask portion that is thicker than the first mask portion; anodizing the top metal layer through the top patterned photoresist to form an anodized segment; removing the first mask portion after anodizing; and after removing the first mask portion, etching the top metal layer through the top patterned photoresist to form a top metal pattern.

[0005] The above description is only used to illustrate the problem to be solved by the present disclosure, the technical means to solve the problem, and the effects produced, etc. The specific details of the present disclosure will be introduced in detail in the following implementation methods and related drawings. Simple diagram description

[0006] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows: FIG. 1 is a flow chart illustrating a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. 2A, 2B, 2C, 2D and 2E are schematic cross-sectional views illustrating intermediate stages of a method for fabricating a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. FIG. 2F is a schematic top view of the structure in FIG. 2E , wherein the cross section in FIG. 2E is taken along line segment 2E-2E in FIG. 2F . FIG. 2G is a schematic cross-sectional view illustrating an intermediate stage of a method for fabricating a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. FIG. 3A is a schematic cross-sectional view of a patterned photoresist according to some embodiments of the present disclosure. FIG. 3B is a schematic cross-sectional view of a patterned photoresist according to some embodiments of the present disclosure. 4A , 4B and 4C are schematic cross-sectional views illustrating a process of forming an opening in a photoresist to expose a metal layer under the photoresist according to some embodiments of the present disclosure. FIG. 4D is a schematic cross-sectional view illustrating a process of forming an opening in a photoresist to expose a metal layer under the photoresist according to some embodiments of the present disclosure. Figures 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J and 5K are cross-sectional schematic diagrams illustrating intermediate stages of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. FIG. 6 is a partial top view illustrating the structure in FIG. 5K according to some embodiments of the present disclosure. FIG. 7A is another partial top view illustrating the structure in FIG. 5K according to some embodiments of the present disclosure. FIG. 7B is another partial top view illustrating the structure in FIG. 5K according to some embodiments of the present disclosure. FIG. 7C is another partial top view illustrating the structure in FIG. 5K according to some embodiments of the present disclosure. 8A, 8B, 8C, 8D, 8E and 8F are schematic cross-sectional views illustrating intermediate stages of a method for fabricating a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. 9A, 9B, 9C, 9D, 9E and 9F are schematic cross-sectional views illustrating intermediate stages of a method for fabricating a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. 10A , 10B and 10C are schematic cross-sectional views illustrating intermediate stages of a method for fabricating a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. Implementation

[0007] The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and components will be depicted in a simple schematic manner in the drawings.

[0008] In various embodiments, the description is made with reference to the drawings. However, certain embodiments may be implemented without one or more of these specific details, or in combination with other known methods and configurations. In the following description, many specific details, such as specific configurations, dimensions, and processes, are set forth in order to provide a thorough understanding of the present disclosure. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail so as not to unnecessarily obscure the present disclosure. References throughout this specification to "one embodiment", "some embodiments", etc. mean that the specific features, structures, configurations, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment", "according to some embodiments", etc., which appear throughout this specification, do not necessarily refer to the same embodiment of the present disclosure. In addition, specific features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0009] Please refer to FIG. 1. FIG. 1 is a flow chart illustrating a method of manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The method begins at step S101, wherein a top metal layer is formed on a substrate. The method continues at step S102, wherein a top patterned photoresist is formed on the top metal layer to expose a portion of a top surface of the top metal layer, wherein the top patterned photoresist has a first mask portion and a second mask portion that is thicker than the first mask portion. The method continues at step S102, wherein the top metal layer is anodized through the top patterned photoresist to form an anodized segment. The method continues at step S104, wherein the first mask portion is removed. The method continues at step S105, wherein the top metal layer is etched through the top patterned photoresist to form a top metal pattern. Although the method is shown and described below as a series of steps or events, it should be understood that the order in which these steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or occur simultaneously with other steps or events other than those shown and / or described in the present disclosure. In addition, not all steps shown are necessary to implement one or more aspects or embodiments described in this embodiment. In addition, one or more steps described in this disclosure can be performed in one or more separate steps and / or stages.

[0010] Please refer to FIG. 2A. FIG. 2A is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. As shown in FIG. 2A, a top metal layer TM is formed (e.g., by deposition) on a substrate SUB, and a photoresist PR is formed on the top metal layer TM. The material of the photoresist PR is a positive photoresist. A first area of the photoresist PR is exposed to light of a first exposure dose E1. A second area of the photoresist PR is exposed to light of a second exposure dose E2 less than the first exposure dose E1. A third area of the photoresist PR is not exposed. In some embodiments, UV light may be used to expose the photoresist PR, but the present disclosure is not limited thereto. In some embodiments, a grayscale mask (or a halftone mask) may be used to expose the photoresist PR. For example, a halftone mask may include a fully exposed portion that transmits the full intensity of light (i.e., a first exposure dose E1), a halftone portion that transmits a portion of the light (e.g., a second exposure dose E2, which may be 20% to 60% of the first exposure dose E1), and a full-tone portion that completely blocks the light.

[0011] In some embodiments, the top metal layer TM contains a metal that can be anodized. In some embodiments, the top metal layer TM may include at least one element of aluminum, zirconium, hafnium, and tantalum. In some embodiments, the top metal layer TM may include at least one rare earth metal element. For example, the aluminum atomic ratio in the top metal layer TM is greater than 80% to have better conductivity, but the present disclosure is not limited thereto.

[0012] Please refer to FIG. 2B. FIG. 2B is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2A may be followed by the intermediate stage shown in FIG. 2B in sequence. As shown in FIG. 2B, the exposed photoresist PR is developed to form a patterned photoresist PR'. The patterned photoresist PR' has a first mask portion PR11 and a second mask portion PR12. The second mask portion PR12 is thicker than the first mask portion PR11. The patterned photoresist PR' has a hollow portion that exposes a portion S of the top surface of the top metal layer TM. It can be seen that the area where the photoresist PR is exposed with the first exposure dose E1 will be completely removed, the area where the photoresist PR is exposed with the second exposure dose E2 will be partially removed to form the first mask portion PR11, and the area where the photoresist PR is not exposed will be retained as it is to form the second mask portion PR12.

[0013] Please refer to FIG. 2C. FIG. 2C is a schematic cross-sectional view illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2B may be sequentially followed by the intermediate stage shown in FIG. 2C. As shown in FIG. 2C, the top metal layer TM is anodized through the patterned photoresist PR' to form an anodized segment AS (i.e., an anodic oxide). As previously described, the top metal layer TM contains a metal that can be anodized (e.g., aluminum), and thus the top metal layer TM can be anodized so that the anodized segment AS extends to a side of the top metal layer TM away from the patterned photoresist PR'.

[0014] Please refer to FIG. 2D. FIG. 2D is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2C may be followed by the intermediate stage shown in FIG. 2D. As shown in FIG. 2D, the first mask portion PR11 is removed after the anodization is completed. In some embodiments, an ashing process is performed on the first mask portion PR11 and the second mask portion PR12 until the first mask portion PR11 is completely removed and the remaining second mask portion PR12 still covers the top surface of the top metal layer TM. Specifically, the first mask portion PR11 is removed to expose other portions of the top surface of the top metal layer TM. In some embodiments, oxygen plasma is used in the ashing process to perform etching of the first mask portion PR11 and the second mask portion PR12.

[0015] Please refer to FIG. 2E and FIG. 2F. FIG. 2E is a schematic cross-sectional view illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. FIG. 2F is a schematic top view illustrating the structure in FIG. 2E, wherein the cross section in FIG. 2E is taken along the line segment 2E-2E in FIG. 2F. The intermediate stage shown in FIG. 2D may be followed by the intermediate stages shown in FIG. 2E and FIG. 2F in sequence. As shown in FIG. 2E and FIG. 2F, the top metal layer TM is etched through the remaining second mask portion PR12 to form a top metal pattern TP that can be used as an electrode.

[0016] In some embodiments, the top metal layer TM and the anodized section AS have an etching selectivity ratio higher than 2.0 in the step of etching the top metal layer TM (as shown in FIGS. 2E and 2F ). Thus, the anodized section AS can resist the step of etching the top metal layer TM.

[0017] Please refer to FIG. 2G. FIG. 2G is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stages shown in FIG. 2E and FIG. 2F may be followed by the intermediate stage shown in FIG. 2G. As shown in FIG. 2G, the remaining second mask portion PR12 is removed to expose the top surface of the top metal pattern TP.

[0018] Please refer to FIG. 3A and FIG. 3B. FIG. 3A is a schematic cross-sectional view of a patterned photoresist PR' according to some embodiments of the present disclosure. FIG. 3B is a schematic cross-sectional view of a patterned photoresist PR' according to some embodiments of the present disclosure. As shown in FIG. 3A and FIG. 3B, the length D1 represents the thickness of the patterned photoresist PR', and the length D2 represents the distance that the lower surface of the patterned photoresist PR' extends laterally outward relative to the upper surface of the patterned photoresist PR'. In some embodiments, the over cut ratio of the patterned photoresist PR' can be defined by the value of the length D2 divided by the length D1. For example, since the lower surface of the patterned photoresist PR' extends laterally outward relative to the upper surface of the patterned photoresist PR', the length D1 is a positive number, and the value of the length D2 divided by the length D1 is also a positive number. On the contrary, since the lower surface of the patterned photoresist PR' extends laterally inward relative to the upper surface of the patterned photoresist PR', the length D1 is a negative number, and the value of the length D2 divided by the length D1 is also a negative number.

[0019] In some embodiments, the overcut ratio of the patterned photoresist PR' is less than 0.3. Thus, after the patterned photoresist PR' is subjected to an ashing process to completely remove the first mask portion PR11 as shown in FIG. 2D, the interface between the anodized segment AS and the non-anodized portion of the top metal layer TM will still be covered by the remaining second mask portion PR12 and will not be exposed. Therefore, in the step of etching the top metal layer TM (as shown in FIG. 2E and FIG. 2F), the non-anodized portion of the top metal layer TM will not be etched at the aforementioned interface.

[0020] Please refer to FIG. 4A, FIG. 4B and FIG. 4C. FIG. 4A, FIG. 4B and FIG. 4C are cross-sectional schematic diagrams illustrating a process of forming an opening O in a photoresist PR to expose a metal layer ML below the photoresist PR according to some embodiments of the present disclosure. As shown in FIG. 4A, the photoresist PR is exposed by using a grayscale mask (or a halftone mask) and then developed to form a recess R on its top surface. As shown in FIG. 4B, the photoresist PR having the recess R is subjected to an ashing process to form an opening O having a width Wa. As shown in FIG. 4C, the photoresist PR continues to be subjected to an ashing process to expand the opening O from the width Wa to the width Wb.

[0021] Therefore, by comparing FIGS. 2A to 2C with FIGS. 4A to 4C, it can be seen that the space between two patterns of the patterned photoresist PR' can be better controlled by development rather than an ashing process, especially when the size of the opened space (e.g., the width W shown in FIG. 2C) is less than 20 μm.

[0022] In some embodiments, the disclosed method of manufacturing a structure having an electrode and an anodized portion may be used to manufacture a thin film transistor, as illustrated in FIGS. 5A to 5K .

[0023] Please refer to FIG. 4D. FIG. 4D is a cross-sectional schematic diagram illustrating a process of forming an opening O in a photoresist PR to expose a metal layer ML below the photoresist PR according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 4A may be followed by the intermediate stage shown in FIG. 4D. As shown in FIG. 4D, the photoresist PR having a recess R is subjected to a plasma ashing process to form an opening O. Specifically, the gas used in the plasma ashing process contains CO2. It should be noted that CO2 ions have directionality due to the acceleration of the plasma sheath. Thus, compared with the opening O in FIG. 4B, the inner wall of the opening O in FIG. 4D is relatively steep, and the width of the opening O can be better controlled.

[0024] Please refer to FIG. 5A. FIG. 5A is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. As shown in FIG. 5A, a bottom metal layer BM is formed on a substrate SUB, and a photoresist PR is formed on the bottom metal layer BM. The aluminum atomic ratio of the bottom metal layer BM is greater than 60%. The material of the photoresist PR is a positive photoresist. A first area of the photoresist PR is exposed to light of a first exposure dose E1. A second area of the photoresist PR is exposed to light of a second exposure dose E2 less than the first exposure dose E1. A third area of the photoresist PR is not exposed. In some embodiments, UV light may be used to expose the photoresist PR, but the present disclosure is not limited thereto. In some embodiments, a grayscale mask (or a halftone mask) may be used to expose the photoresist PR. For example, a halftone mask may include a fully exposed portion that transmits the full intensity of light (i.e., a first exposure dose E1), a halftone portion that transmits a portion of the light (e.g., a second exposure dose E2, which may be 20% to 60% of the first exposure dose E1), and a full-tone portion that completely blocks the light.

[0025] Please refer to FIG. 5B. FIG. 5B is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 5A may be followed by the intermediate stage shown in FIG. 5B in sequence. As shown in FIG. 5B, the exposed photoresist PR is developed to form a first patterned photoresist PR1. The first patterned photoresist PR1 has a first mask portion PR11 and a second mask portion PR12. The second mask portion PR12 is thicker than the first mask portion PR11. It can be seen that the area of the photoresist PR exposed with the first exposure dose E1 will be completely removed, the area of the photoresist PR exposed with the second exposure dose E2 will be partially removed to form the first mask portion PR11, and the area of the photoresist PR not exposed will be retained as it is to form the second mask portion PR12.

[0026] Please refer to FIG. 5C. FIG. 5C is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 5B may be followed by the intermediate stage shown in FIG. 5C. As shown in FIG. 5C, the bottom metal layer BM is etched through the first patterned photoresist PR1 to form a first lower metal pattern LP1 and a second lower metal pattern LP2 covered by a first mask portion PR11 and a second mask portion PR12, respectively.

[0027] In some embodiments, a wet etching process may be performed to etch the bottom metal layer BM. In some embodiments, a PAN etchant (a mixture of phosphoric acid, acetic acid, nitric acid, and water) may be used in the wet etching process. For example, the mixing ratio of phosphoric acid, acetic acid, nitric acid, and water may be 16:1:1:2, but the present disclosure is not limited thereto. In some embodiments, hydrogen peroxide and sulfuric acid may be used in the wet etching process.

[0028] In some embodiments, a dry etching process may be performed to etch the bottom metal layer BM. For example, the dry etching process may be an enhanced capacitance coupled plasma (ECCP) process using, for example, Cl 2 and BCl 3, but the present disclosure is not limited thereto.

[0029] Please refer to FIG. 5D. FIG. 5D is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 5C may be followed by the intermediate stage shown in FIG. 5D. As shown in FIG. 5D, the first mask portion PR11 is removed to expose the top surface of the first lower metal pattern LP1. In some embodiments, an ashing process is performed on the first mask portion PR11 and the second mask portion PR12 until the first mask portion PR11 is completely removed and the second mask portion PR12 still covers the top surface of the second lower metal pattern LP2. In some embodiments, an oxygen plasma is used in the ashing process to perform etching of the first mask portion PR11 and the second mask portion PR12.

[0030] Please refer to FIG. 5E. FIG. 5E is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 5D may be followed by the intermediate stage shown in FIG. 5E. As shown in FIG. 5E, the etched bottom metal layer BM' is anodized. The first lower metal pattern LP1 and the second lower metal pattern LP2 are partially anodized after anodization, and thus have an anodized portion AD (i.e., an anodized oxide). The anodized second lower metal pattern LP2 has a surface portion S1 that is not anodized and contacts the second mask portion PR12.

[0031] In some embodiments, the etched bottom metal layer BM' is anodized to reach a termination voltage. The first lower metal pattern LP1 and the second lower metal pattern LP2 each have a thickness T1 (e.g., the vertical length of the first lower metal pattern LP1 in FIG. 5D) and a width W1 (e.g., the lateral length of the first lower metal pattern LP1 in FIG. 5D) before being anodized, and the termination voltage is less than the smallest of the thickness T1 and the width W1 in nm divided by 0.9 nm-V -1. In this way, the etched bottom metal layer BM' will not be completely anodized and a conductive portion will remain.

[0032] In some embodiments, the width W1 of the first lower metal pattern LP1 is greater than the thickness T1 of the first lower metal pattern LP1 , but the present disclosure is not limited thereto.

[0033] In some embodiments, the etched bottom metal layer BM' is anodized to a termination voltage greater than 10 V and less than 500 V. It should be noted that if the etched bottom metal layer BM' is anodized to a termination voltage greater than 500 V, the anodized portion AD of the etched bottom metal layer BM' (e.g., the anodized portion AD of the first lower metal pattern LP1) may be too thick, resulting in a high operating voltage of the thin film transistor.

[0034] In some embodiments, the etched bottom metal layer BM' is anodized by applying a constant current greater than 0.5 mA / cm2. In some embodiments, the constant current is between 0.05 mA / cm2 and 5 mA / cm2.

[0035] In some embodiments, the etched bottom metal layer BM' is anodized until the termination voltage is reached and maintained for at least 300 seconds. This makes the thickness of the anodized portion AD of the etched bottom metal layer BM' more uniform.

[0036] In some embodiments, an annealing process may be performed on the anodized bottom metal layer BM'. In this way, the resistance of the anodized bottom metal layer BM' (e.g., the anodized portion AD of the anodized first lower metal pattern LP1) to the second wet etching process (if any) may be increased. In some embodiments, the annealing temperature used in the annealing process is greater than 200°C, but the present disclosure is not limited thereto.

[0037] In some embodiments, the etched bottom metal layer BM' is anodized using an electrolyte having a pH value between pH 5 and pH 8. It should be noted that if the pH value is less than pH 5 or greater than pH 8, more pores will appear in the anodized portion AD of the etched bottom metal layer BM'.

[0038] In some embodiments, the etched bottom metal layer BM' is anodized using an electrolyte containing less than 45 wt% of water. Thus, the hydrogen content in the anodized portion AD of the etched bottom metal layer BM' can be very small. The hydrogen content can reduce the breakdown voltage of the gate insulator. Hydrogen sometimes affects the semiconductor layer A and reduces its stability.

[0039] In some embodiments, the etched bottom metal layer BM' is anodized using an electrolyte containing water, ethylene glycol, and ammonium tartrate. For example, the electrolyte may contain about 68.5 wt% of ethylene glycol, about 30 wt% of water, and about 1.5 wt% of ammonium tartrate, but the present disclosure is not limited thereto.

[0040] In some embodiments, the etched bottom metal layer BM' is anodized at a temperature below 15° C. In this way, the anodized portion AD of the etched bottom metal layer BM' is more dense, thereby improving the quality.

[0041] Please refer to FIG. 5F. FIG. 5F is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 5E may be followed by the intermediate stage shown in FIG. 5F. As shown in FIG. 5F, the second mask portion PR12 is removed to expose the unanodized surface portion S1 of the second lower metal pattern LP2.

[0042] Please refer to FIG. 5G. FIG. 5G is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. To further manufacture a thin film transistor, the intermediate stage shown in FIG. 5F may be followed by the intermediate stage shown in FIG. 5G. As shown in FIG. 5G, a semiconductor layer A is deposited on the anodized bottom metal layer BM' to cover the first lower metal pattern LP1 and the second lower metal pattern LP2, so that the first lower metal pattern LP1 and the second lower metal pattern LP2 contact the semiconductor layer A. The first lower metal pattern LP1 is used as a gate electrode, and the anodized portion AD of the anodized first lower metal pattern LP1 is used as a gate insulator.

[0043] In some embodiments, the semiconductor layer A is an oxide semiconductor layer. In addition, the semiconductor layer A includes at least one element selected from aluminum, gallium, indium, zinc, tin, and zirconium, but the present disclosure is not limited thereto. In some embodiments, the semiconductor layer A includes MoS 2.

[0044] In some embodiments, the semiconductor layer A may be deposited by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process.

[0045] In some embodiments, the semiconductor layer A may be a multilayer structure including different components. For example, the semiconductor layer A may be a double-layer structure including indium gallium zinc oxide (IZO) and indium gallium zinc tin oxide (IGZTO), but the present disclosure is not limited thereto. In this way, the channel mobility may be improved.

[0046] As shown in FIG. 5G , a top metal layer TM is deposited on the semiconductor layer A. It should be noted that the surface of the top metal layer TM in contact with the semiconductor layer A contains a metal (e.g., aluminum) that can be anodized. The combination of the semiconductor layer A and the top metal layer TM serves as a conductive layer. A second patterned photoresist PR2 is formed on the top metal layer TM. The method for forming the second patterned photoresist PR2 may be the same as or similar to the method for forming the first patterned photoresist PR1, and thus the formation of the second patterned photoresist PR2 may refer to the description of FIG. 5A and FIG. 5B , which will not be repeated here. The second patterned photoresist PR2 has a first hollow portion H1 that exposes a surface portion S2 of the top metal layer TM.

[0047] In some embodiments, the step of depositing the semiconductor layer A and the step of depositing the top metal layer TM are performed continuously in a vacuum. That is, before depositing the top metal layer TM, the semiconductor layer A is not in contact with the atmosphere. In some embodiments, the step of depositing the semiconductor layer A and the step of depositing the top metal layer TM are performed in a chamber and transferred in a vacuum. In this way, the oxidized semiconductor layer A can be prevented from contacting the air.

[0048] Please refer to FIG. 5H. FIG. 5H is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 5G may be followed by the intermediate stage shown in FIG. 5H in sequence. As shown in FIG. 5H, and in conjunction with FIG. 5G, the surface portion S2 of the top metal layer TM is anodized through the second patterned photoresist PR2 until the top metal layer TM has an anodized section AS (i.e., an anodic oxide) extending from the surface portion S2 of the top metal layer TM to the side of the top metal layer TM facing the semiconductor layer A. As described above, the surface of the top metal layer TM in contact with the semiconductor layer A contains an anodized metal (e.g., aluminum), so the top metal layer TM can be anodized to extend the anodized section AS to the side of the top metal layer TM facing the semiconductor layer A. In some embodiments, when the top metal layer TM is anodized by applying a voltage V1 thereto, a voltage V2 is also applied to the first lower metal pattern LP1, and the voltage V2 is greater than the voltage V1 minus 10 volts. In this way, the semiconductor layer A can provide more carriers, thereby forming an alternative conductive path to assist the anodization at the bottom of the anodized segment AS.

[0049] In some embodiments, a surface portion S2 of the top metal layer TM is anodized to reach a termination voltage. The top metal layer TM has a thickness T2 before being anodized. The termination voltage is greater than the thickness T2 in nm divided by 1.0 nm-V -1. In this way, it is ensured that the anodized segment AS can reach the side of the top metal layer TM facing the semiconductor layer A.

[0050] In some embodiments, the thickness of the top metal layer TM (eg, thickness T2 as shown in FIG. 5G ) is less than 1.0 μm. In this way, the voltage required for anodization is not too high and is easy to control.

[0051] In some embodiments, as shown in FIG. 5H , the semiconductor layer A has a channel region Aa and a conductive region Ab. The channel region Aa is covered and contacted by the anodized segment AS. The channel region Aa can be defined by the vertical projection of the anodized segment AS onto the semiconductor layer A. The conductive region Ab is covered and contacted by other conductive segments of the top metal layer TM. In order to reduce the contact resistance of the conductive region Ab relative to the top metal layer TM, an annealing process can be performed to react the conductive region Ab with aluminum in the top metal layer TM. Aluminum increases oxygen vacancies in the conductive region Ab of the semiconductor layer A. The annealing process also improves the stability of the channel region Aa of the semiconductor layer A.

[0052] In some embodiments, the top metal layer TM is anodized at a temperature below 15° C. In this way, the anodized section AS of the top metal layer TM is more dense, thereby improving the quality.

[0053] Please refer to FIG. 5I. FIG. 5I is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 5H may be followed by the intermediate stage shown in FIG. 5I. As shown in FIG. 5I, a second hollow portion H2 is formed in the second patterned photoresist PR2. In some embodiments, an ashing process is performed on the second patterned photoresist PR2 until the second hollow portion H2 is formed to expose a portion of the top metal layer TM. In some embodiments, an oxygen plasma is used in the ashing process to perform etching of the second patterned photoresist PR2.

[0054] Please refer to FIG. 5J. FIG. 5J is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 5I may be followed by the intermediate stage shown in FIG. 5J in sequence. As shown in FIG. 5J, the top metal layer TM is etched through the second hollow portion H2 to form a first upper metal pattern UP1 and a second upper metal pattern UP2. The first upper metal pattern UP1 is above the anodized first lower metal pattern LP1 and has a drain DE and a source SE. The drain DE and the source SE are connected to the anodized section AS and are electrically isolated from each other by the anodized section AS. The anodized section AS is used as a channel protection structure. The second upper metal pattern UP2 is above the second lower metal pattern LP2. The second upper metal pattern UP2 forms a contact structure with the second lower metal pattern LP2.

[0055] In some embodiments, the etching selectivity ratio between the top metal layer TM and the anodized segment AS in the step of etching the top metal layer TM (as shown in FIG. 5J ) is higher than 2.0.

[0056] Please refer to FIG. 5K. FIG. 5K is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 5J may be followed by the intermediate stage shown in FIG. 5K. As shown in FIG. 5K, the second patterned photoresist PR2 is removed to expose the first upper metal pattern UP1 and the second upper metal pattern UP2.

[0057] In some embodiments, the thickness of the semiconductor layer A is less than 100 nm. In this way, back channel leakage can be reduced in some cases. In addition, the problem of excessive contact resistance between the semiconductor layer A and other layers in contact with the semiconductor layer A (i.e., the second lower metal pattern LP2, the second upper metal pattern UP2, the drain DE and the source SE) can be avoided.

[0058] Please refer to FIG. 6 and FIG. 7A. FIG. 6 and FIG. 7A are partial top views of the structure shown in FIG. 5K according to some embodiments of the present disclosure. In detail, FIG. 6 presents a partial schematic diagram of the first lower metal pattern LP1 (covered by the anodized portion AD) and the first upper metal pattern UP1 after anodization. FIG. 7A presents a partial schematic diagram of the second lower metal pattern LP2 (covered by the anodized portion AD and exposing the surface portion S1) and the second upper metal pattern UP2 after anodization forming the aforementioned contact structure.

[0059] Please refer to FIG. 7B. FIG. 7B is another partial top view of the structure shown in FIG. 5K according to some embodiments of the present disclosure. As shown in FIG. 7B, the surface portion S1 of the second lower metal pattern LP2 exposed by the anodized portion AD has a smaller area than that shown in FIG. 7A.

[0060] Please refer to FIG. 7C. FIG. 7C is another partial top view of the structure shown in FIG. 5K according to some embodiments of the present disclosure. As shown in FIG. 7C, the surface portion S1 of the second lower metal pattern LP2 exposed by the anodized portion AD and the second upper metal pattern UP2 covering the second lower metal pattern LP2 both extend along the second lower metal pattern LP2.

[0061] According to this, it can be seen that the method of manufacturing a structure having an electrode and an anodized portion according to the embodiment shown in FIG. 5A to FIG. 5K can manufacture a thin film transistor using only two sets of PEP (Photo Engraving Process). Therefore, the manufacturing cost of the thin film transistor can be significantly reduced and the manufacturing efficiency can be effectively improved.

[0062] Please refer to FIGS. 8A to 8F. FIGS. 8A to 8F are schematic cross-sectional views illustrating intermediate stages of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. As shown in FIG. 8A, a gate electrode GE is formed on a substrate SUB by a set of PEPs. As shown in FIG. 8B, a gate insulator layer GI is formed on the substrate SUB (e.g., by deposition) to cover the gate electrode GE. In some embodiments, the gate insulator layer GI is formed by using at least one of SiO 2, Al 2O 3, and SiN x. As shown in FIG. 8C, a semiconductor layer A is formed (e.g., by deposition) to cover the gate insulator layer GI. As shown in FIG. 8D, a top metal layer TM is formed (e.g., by deposition) to cover the semiconductor layer A. As shown in FIG. 8E, the top metal layer TM is anodized, for example, by using a second patterned photoresist PR2 (omitted in FIG. 8E) as shown in FIG. 5G to form an anodized segment AS. As shown in FIG. 8F , the top metal layer TM is etched, for example, by using the second patterned photoresist PR2 (which is subjected to an ashing process) shown in FIG. 5I to form a drain DE and a source SE.

[0063] Please refer to FIG. 9A. FIG. 9A is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. In some embodiments, the intermediate stage shown in FIG. 5A may be directly followed by the intermediate stage shown in FIG. 9A. In other words, the bottom metal layer BM in FIG. 5A is replaced by the bottom metal layer BM-1 in FIG. 9A. As shown in FIG. 9A, the bottom metal layer BM-1 is a multilayer structure. Specifically, the bottom metal layer BM-1 includes a first sublayer SL1, a second sublayer SL2, and a third sublayer SL3. The first sublayer SL1 contains aluminum. The second sublayer SL2 is stacked on the first sublayer SL1. The third sublayer SL3 is stacked on the second sublayer SL2.

[0064] In some embodiments, the second sub-layer SL2 contains molybdenum, but the present disclosure is not limited thereto. The second sub-layer SL2 containing molybdenum can prevent the first sub-layer SL1 containing aluminum from hillocking during subsequent high-temperature processes. Molybdenum has a poor anodizing effect, but can be used as a barrier metal.

[0065] In some embodiments, the third sub-layer SL3 contains copper, but the present disclosure is not limited thereto. The third sub-layer SL3 containing copper can increase the conductivity of the entire bottom metal layer BM-1. In some embodiments, the second sub-layer SL2 containing molybdenum can be used as a barrier layer to prevent copper diffusion from the third sub-layer SL3 containing copper.

[0066] In some embodiments, the third sub-layer SL3 may include a barrier metal, such as tantalum, titanium, or tungsten, but the present disclosure is not limited thereto.

[0067] In some embodiments, one of the second sub-layer SL2 and the third sub-layer SL3 may be omitted. For example, in some embodiments, the bottom metal layer BM-1 may be a double-layer structure including only the first sub-layer SL1 and the second sub-layer SL2 containing molybdenum. In some embodiments, the bottom metal layer BM-1 may be a double-layer structure including only the first sub-layer SL1 and the third sub-layer SL3 containing copper.

[0068] Please refer to FIG. 9B. FIG. 9B is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 9A may be followed by the intermediate stage shown in FIG. 9B. As shown in FIG. 9B, the bottom metal layer BM-1 is etched through the first patterned photoresist PR1 to form a first lower metal pattern LP1 and a second lower metal pattern LP2. In addition, the first lower metal pattern LP1 and the second lower metal pattern LP2 are covered by a first mask portion PR11 and a second mask portion PR12, respectively.

[0069] In some embodiments, the third sub-layer SL3 including copper may be selectively etched by using an H 2 O 2 based etchant.

[0070] Please refer to FIG. 9C. FIG. 9C is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 9B may be followed by the intermediate stage shown in FIG. 9C. As shown in FIG. 9C, the first mask portion PR11 is removed to expose the top surface of the third sub-layer SL3 above the first lower metal pattern LP1. The step of removing the first mask portion PR11 as shown in FIG. 9C is the same as or similar to the step shown in FIG. 5D, so the description of FIG. 5D may be referred to and will not be repeated here.

[0071] Please refer to FIG. 9D. FIG. 9D is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 9C may be followed by the intermediate stage shown in FIG. 9D. As shown in FIG. 9D, the second sublayer SL2 and the third sublayer SL3 of the first lower metal pattern LP1 are selectively etched (relative to the first sublayer SL1) to expose the top surface of the first sublayer SL1. The remaining first sublayer SL1 of the first lower metal pattern LP1 is used as the first lower metal pattern LP1'.

[0072] In some embodiments, the second sub-layer SL2 including molybdenum may be etched by using a solution including hydrogen peroxide and citric acid.

[0073] In some embodiments, an etching selectivity ratio of the second sub-layer SL2 to the first sub-layer SL1 in the selective etching is higher than 2.0.

[0074] In some embodiments, the second sub-layer SL2 may be omitted. That is, the bottom metal layer BM-1 may only include the first sub-layer SL1 containing aluminum and the third sub-layer SL3 containing copper.

[0075] Please refer to FIG. 9E. FIG. 9E is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 9D may be followed by the intermediate stage shown in FIG. 9E. As shown in FIG. 9E, the first lower metal pattern LP1' is anodized, and the second lower metal pattern LP2 is anodized to form a second lower metal pattern LP2'. The steps of anodizing the first lower metal pattern LP1' and the second lower metal pattern LP2 as shown in FIG. 9E are the same or similar to the steps shown in FIG. 5E, so the description of FIG. 5E may be referred to and will not be repeated here.

[0076] Please refer to FIG. 9F. FIG. 9F is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 9E may be followed by the intermediate stage shown in FIG. 9F. As shown in FIG. 9F, the second mask portion PR12 is removed to expose the top surface of the third sublayer SL3 of the second lower metal pattern LP2'. The step of removing the second mask portion PR12 as shown in FIG. 9F is the same as or similar to the step shown in FIG. 5F, so the description of FIG. 5F may be referred to and will not be repeated here. In some embodiments, the intermediate stage shown in FIG. 9F may be followed by the intermediate stages shown in FIGS. 5G to 5K.

[0077] Please refer to FIG. 10A. FIG. 10A is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. In some embodiments, the intermediate stage shown in FIG. 5F may be directly followed by the intermediate stage shown in FIG. 10A. As shown in FIG. 10A, a semiconductor layer A is deposited on an anodized bottom metal layer BM'. A top metal layer TM is deposited on the semiconductor layer A. A second patterned photoresist PR2 is formed on the top metal layer TM. In other words, the top metal layer TM in FIG. 5G is replaced by the top metal layer TM in FIG. 10A. As shown in FIG. 10A, the top metal layer TM is a multilayer structure. Specifically, the top metal layer TM includes a first sublayer SL1, a second sublayer SL2, and a third sublayer SL3. The first sublayer SL1 contains aluminum. The second sublayer SL2 is stacked on the first sublayer SL1. The third sublayer SL3 is stacked on the second sublayer SL2. In addition, the second patterned photoresist PR2 has a first hollow portion H1 that exposes a surface portion S4 of the top metal layer TM. The surface portion S4 is a portion where the top surface of the third sub-layer SL3 is located directly above the first lower metal pattern LP1.

[0078] In some embodiments, the second sub-layer SL2 contains molybdenum, but the present disclosure is not limited thereto. The second sub-layer SL2 containing molybdenum can prevent the first sub-layer SL1 containing aluminum from bulging during a subsequent high-temperature process.

[0079] In some embodiments, the third sub-layer SL3 contains copper, but the present disclosure is not limited thereto.

[0080] In some embodiments, one of the second sub-layer SL2 and the third sub-layer SL3 may be omitted.

[0081] In some embodiments, the step of depositing the semiconductor layer A as shown in FIG. 10A is the same as or similar to the step shown in FIG. 5G, so the description of FIG. 5G can be referred to and will not be repeated here. In some embodiments, the step of forming the second patterned photoresist PR2 as shown in FIG. 10A is the same as or similar to the step shown in FIG. 5G, so the description of FIG. 5G can be referred to and will not be repeated here.

[0082] Please refer to FIG. 10B. FIG. 10B is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 10A may be followed by the intermediate stage shown in FIG. 10B. As shown in FIG. 10B, the third sub-layer SL3 and the second sub-layer SL2 in the first hollow portion H1 are selectively etched relative to the first sub-layer SL1 to expose the surface portion S2 of the first sub-layer SL1 in the first hollow portion H1.

[0083] In some embodiments, the second sub-layer SL2 including molybdenum may be etched by using a solution including hydrogen peroxide and citric acid.

[0084] In some embodiments, an etching selectivity ratio of the second sub-layer SL2 to the first sub-layer SL1 in the selective etching is higher than 2.0.

[0085] In some embodiments, the second sub-layer SL2 may be omitted. That is, the top metal layer TM may only include the first sub-layer SL1 containing aluminum and the third sub-layer SL3 containing copper.

[0086] Please refer to FIG. 10C. FIG. 10C is a cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing a structure having an electrode and an anodized portion according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 10B may be followed by the intermediate stage shown in FIG. 10C. As shown in FIG. 10C, and in conjunction with FIG. 10B, the surface portion S2 of the first sub-layer SL1 exposed by the first hollow portion H1 is anodized through the second patterned photoresist PR2 until the top metal layer TM has an anodized segment AS extending from the surface portion of the first sub-layer SL1 exposed by the first hollow portion H1 to the side of the first sub-layer SL1 facing the semiconductor layer A. In some embodiments, the step of anodizing the first sub-layer SL1 of the top metal layer TM as shown in FIG. 10C is the same as or similar to the step shown in FIG. 5H, and therefore, the description of FIG. 5H may be referred to, and will not be repeated here.

[0087] From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that the method of the present disclosure can be used to manufacture a structure having an electrode and an anodized portion. In addition, the method of the present disclosure can also use only two sets of PEP processes to manufacture thin film transistors. Therefore, the manufacturing cost can be significantly reduced and the manufacturing efficiency can be effectively improved. In addition, in some embodiments of the method of the present disclosure where the top metal layer is first anodized and then etched, the lateral length of the anodized section used as a channel protection structure can be more accurately controlled. Moreover, compared with the process of etching first and then anodizing, the process of anodizing first and then etching does not anodize the edge of the top metal layer, so the degree of anodization of the top metal layer can be better controlled (because the amount of charge used for anodization is easy to calculate).

[0088] Although the present disclosure has been disclosed as above in the implementation mode, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application.

[0089] A: Semiconductor layer Aa: Channel area Ab: conduction area AD: Anodized part AS: Anodizing Section BM, BM', BM-1: bottom metal layer D1,D2: length DE: drain E1: First exposure dose E2: Second exposure dose GE: Gate Electrode GI: Gate Insulator Layer H1: The first hollow part H2: The second hollow part LP1, LP1': First lower metal pattern LP2, LP2': Second lower metal pattern ML:Metal Layer O: Open PR: Photoresist PR': Patterned Photoresist PR1: First patterned photoresist PR11: First mask area PR12: Second mask area PR2: Second patterned photoresist R: Depression S: Part S1, S2, S4: surface area S101, S102, S103, S104, S105: Steps SE: Source SL1: First sublayer SL2: Second sublayer SL3: The third sublayer SUB: Substrate T1, T2: thickness TM: Top Metal Layer TP: Top Metal Pattern UP1: First upper metal pattern UP2: Second upper metal pattern V1, V2: voltage W,W1,Wa,Wb: Width

[0090] Domestic storage information (please note the order of storage institution, date and number) none Overseas deposit information (please note the order of deposit country, institution, date and number) none

Claims

1. A method of manufacturing a structure having electrodes and anodized portions, comprising: forming a top metal layer on a substrate; forming a top patterned photoresist on the top metal layer to expose a portion of a top surface of the top metal layer, wherein the top patterned photoresist has a first masking portion and a second masking portion thicker than the first masking portion; anodizing the top metal layer through the top patterned photoresist to form an anodized segment; removing the first masking portion after the anodizing; and after removing the first masking portion, etching the top metal layer through the top patterned photoresist to form a top metal pattern.

2. The method as described in claim 1, wherein the thickness of the top metal layer is less than 1.0 µm.

3. The method as described in claim 1, wherein the removal of the first masking portion is performed by a plasma ashing process.

4. The method as described in claim 1, wherein the top patterned photoresist is a positive photoresist layer.

5. The method as described in claim 4, wherein the overcut ratio of the top patterned photoresist is less than 0.

3.

6. The method as described in claim 1, further comprising: forming a semiconductor layer on the substrate prior to forming the top metal layer, such that the semiconductor layer is covered by the top metal layer.

7. The method of claim 6, further comprising a step performed prior to forming the semiconductor layer, comprising: forming a bottom metal layer on the substrate; forming a bottom patterned photoresist on the bottom metal layer, wherein the bottom patterned photoresist has a first masking portion and a second masking portion thicker than the first masking portion; etching the bottom metal layer through the bottom patterned photoresist to form a bottom metal pattern; removing the first masking portion of the bottom patterned photoresist; after removing the first masking portion of the bottom patterned photoresist, anodizing the bottom metal layer through the bottom patterned photoresist, such that the bottom metal pattern has an anodized portion and an unanodized portion covering the anodized portion; and completely removing the bottom patterned photoresist, wherein the semiconductor layer is formed over the anodized bottom metal pattern.

8. The method as described in claim 7, wherein the bottom metal layer contains aluminum.

9. The method as described in claim 7, wherein the aluminum atom ratio in the bottom metal layer is greater than 80%.

10. The method of claim 7, wherein the bottom metal layer comprises a first sublayer containing aluminum and at least one second sublayer stacked on the first sublayer, and wherein the method further comprises: selectively etching the at least one second sublayer relative to the first sublayer through the bottom patterned photoresist after removing the first mask portion of the bottom patterned photoresist and before anodizing the bottom metal pattern to expose the first sublayer.

11. The method as described in claim 7, wherein the removal of the first mask portion of the bottom patterned photoresist is performed by a plasma ashing process.

12. The method as described in claim 11, wherein the gas used in the plasma ashing process contains CO2.

13. The method as described in claim 12, wherein the gas further contains Ar.

14. The method of claim 6, further comprising a step performed prior to forming the semiconductor layer, comprising: forming a gate electrode on the substrate from a bottom metal layer; and forming a gate insulator layer on the substrate to cover the gate electrode, wherein forming the semiconductor layer covers the semiconductor layer on the gate insulator layer.

15. The method as described in claim 14, wherein the formation of the gate insulator layer is performed by using at least one of SiO2, Al2O3 and SiNx.

16. The method as described in claim 6, wherein the thickness of the semiconductor layer is less than 100 nm.

17. The method as described in claim 1, wherein the etch selectivity ratio of the top metal layer to the anodized section is greater than 2.

0.

18. The method of claim 1, wherein the top metal layer comprises a first sublayer containing aluminum and at least one second sublayer stacked on the first sublayer, and wherein the method further comprises: selectively etching the at least one second sublayer relative to the first sublayer through the top patterned photoresist before anodizing the top metal pattern to expose the first sublayer.

19. The method as described in claim 18, wherein the at least one second sublayer contains copper.

20. The method as claimed in claim 1, wherein the anodizing is performed until the anodized section reaches the side of the top metal layer away from the top patterned photoresist.

21. The method as described in claim 1, wherein the aluminum atom ratio in the top metal layer is greater than 80%.

22. The method as described in claim 1, wherein the width of the anodized section is less than 20 µm.

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