Semiconductor device and fabrication method thereof

Abstract

A method for fabricating a semiconductor device includes forming a dielectric layer over a portion of a substrate, forming a first P-type work function layer over the dielectric layer, wherein the first P-type work function layer includes titanium nitride, forming a second P-type work function layer over the first P-type work function layer, wherein the second P-type work function layer includes doped titanium nitride, forming an aluminum-containing N-type work function layer over the second P-type work function layer, wherein the dopant in the second P-type work function layer reduces aluminum diffusion from the aluminum-containing N-type work function layer to the second P-type work function layer, and forming a metal layer over the aluminum-containing N-type work function layer. This disclosure also provides a semiconductor device.

Description

[Technical Field]

[0001] This disclosure relates to the field of semiconductors, and in particular to semiconductor devices and methods of fabrication thereof. [Previous Technology]

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Several generations of integrated circuits have been produced through technological advancements in IC materials and design, each generation being smaller and more complex than the previous one. Throughout the development of ICs, functional density (i.e., the number of interconnected components per wafer area) has generally increased, while geometric dimensions (i.e., the smallest components (or lines) that can be created using manufacturing processes) have decreased. This miniaturization process generally brings benefits such as increased production efficiency and reduced associated costs.

[0003] Such miniaturization also increases the complexity of processing and fabricating integrated circuits. Integrated circuits contain various circuit device elements, such as transistors. One characteristic of transistors is their threshold voltage. As transistor dimensions become smaller, it is desirable to find methods to extend the tuning range of the threshold voltage without adversely affecting other aspects of the transistor. [Summary of the Invention]

[0004] This disclosure provides a method for fabricating a semiconductor device, comprising forming a dielectric layer above a portion of a substrate, forming a first P-type work function layer above the dielectric layer, wherein the first P-type work function layer comprises titanium nitride, forming a second P-type work function layer above the first P-type work function layer, wherein the second P-type work function layer comprises doped titanium nitride, forming an aluminum-containing N-type work function layer above the second P-type work function layer, wherein the dopant in the second P-type work function layer reduces aluminum diffusion from the aluminum-containing N-type work function layer to the second P-type work function layer, and forming a metal layer above the aluminum-containing N-type work function layer.

[0005] This disclosure provides a method for fabricating a semiconductor device, comprising receiving a semiconductor structure, the semiconductor structure including a complex nanostructure above a substrate and source / drain components coupled to the complex nanostructure, forming a gate dielectric layer above and surrounding the nanostructure, and performing an atomic layer deposition process to form a P-type work function layer above the gate dielectric layer, wherein one cycle of the atomic layer deposition process includes a first half-cycle and a subsequent second half-cycle, and the first half-cycle includes sequentially pulsed a first metal precursor and a first non-metal precursor in a chamber, and the second half-cycle includes sequentially pulsed a second metal precursor and a second non-metal precursor in a chamber, wherein the first metal precursor and the second metal precursor contain different metal elements.

[0006] This disclosure provides a semiconductor device comprising a substrate, a gate dielectric layer above a portion of the substrate, a first titanium and nitrogen work function layer above the gate dielectric layer, a second titanium and nitrogen work function layer above the first titanium and nitrogen work function layer, wherein the composition of the second titanium and nitrogen work function layer is different from that of the first titanium and nitrogen work function layer, an aluminum work function layer above the second titanium and nitrogen work function layer, wherein the second titanium and nitrogen work function layer includes an element for reducing aluminum diffusion from the aluminum work function layer to the second titanium and nitrogen work function layer, and a conductive layer disposed above the aluminum work function layer.

Implementation Method

[0008] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0009] This document may use spatially relative terms, such as "below," "under," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagrams and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagrams. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after the turn.

[0010] Furthermore, when using terms such as "approximately" or "around" to describe a number or range of numbers, this terminology is intended to cover a reasonable range of numbers that takes into account the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing parts with the characteristics associated with that number, the number or range of numbers covers a reasonable range including, for example, within + / - 10% of the number. For example, those skilled in the art know that the manufacturing tolerance associated with a deposited material layer is + / - 15%, and a material layer with a thickness of "approximately 5 nanometers" can cover a size range of 4.25 nanometers to 5.75 nanometers. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed. To avoid ambiguity, the X, Y, and Z directions are perpendicular to each other and used consistently in the drawings. Throughout this disclosure, similar reference numerals denote similar features.

[0011] The functional gate stack of a transistor includes a gate electrode above the gate dielectric layer. The gate electrode may include one or more work function layers with a suitable work function, thereby enhancing the device performance of the corresponding transistor (e.g., reducing the threshold voltage). As mentioned above, it is desirable to find a method to extend the tuning range of the threshold voltage without adversely affecting other aspects of the transistor. One way to adjust the threshold voltage is to adjust the thickness of the work function layer, which is part of the gate stack of the transistor. However, increasing the thickness of the work function metal layer becomes more difficult when manufacturing smaller circuits.

[0012] This disclosure relates to expanding the critical voltage adjustment range of a P-type transistor. The first mechanism of this disclosure involves introducing a type-1 dopant into the work function layer of the P-type transistor to reduce aluminum diffusion, thereby increasing the work function and decreasing the critical voltage of the P-type transistor. The second mechanism of this disclosure involves introducing a type-2 dopant into the work function layer of the P-type transistor to reduce the work function, thereby increasing the critical voltage of the P-type transistor. Therefore, the critical voltage adjustment range can be expanded without adjusting the thickness of the work function layer. These two mechanisms will be explained in more detail with reference to Figures 1 to 22.

[0013] Referring to Figures 1 and 2-3, method 100 includes step 102, which is receiving a semiconductor structure 200. Figure 3 depicts a partial cross-sectional view of the semiconductor structure 200 taken along line segment A-A' shown in Figure 2. A partial cross-sectional view of the semiconductor structure 200 taken along line segment C-C' shown in Figure 2 is similar to Figure 3 and is omitted for simplicity. In the embodiment illustrated here, the semiconductor structure 200 includes a first element region 200A for forming an N-type element (e.g., an N-type gate-all-around (GAA) gate) and a second element region 200B for forming a P-type element (e.g., a P-type GAA transistor). The semiconductor structure 200 includes a substrate 202 (as shown in Figure 3). In one embodiment, the substrate 202 is a bulk silicon substrate (i.e., comprising bulk single-crystal silicon). In various embodiments, substrate 202 may comprise other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some alternative embodiments, substrate 202 may be a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SOI) substrate, or a germanium-on-insulator (SOI) substrate, and may include a carrier, with the insulator on the carrier and the semiconductor layer on the insulator. Substrate 202 may comprise various doped regions configured according to the design requirements of semiconductor structure 200. P-type doped regions may comprise P-type dopants, such as boron, indium, other P-type dopants, or combinations thereof. N-type doped regions may contain N-type dopants, such as phosphorus, arsenic, other N-type dopants, or combinations thereof. In some embodiments, substrate 202 includes doped regions formed by a combination of P-type and N-type dopants. For example, p-well structures, n-well structures, dual-well structures, raised structures, or combinations thereof are provided. Various doped regions can be formed by performing ion implantation processes, diffusion processes, and / or other suitable doping processes.

[0014] The semiconductor structure 200 also includes a plurality of fin-shaped active regions (e.g., fin-shaped active regions 205a, 205b) disposed above the substrate 202. In this embodiment, each fin-shaped active region 205a is formed in a first element region 200A of the semiconductor structure 200 (as shown in FIG. 2), and each fin-shaped active region 205b is formed in a second element region 200B of the semiconductor structure 200. The fin-shaped active regions 205a, 205b may individually or collectively represent a single fin-shaped active region 205 or a plurality of fin-shaped active regions 205. Each fin-shaped active region 205 extends longitudinally along the X direction and is divided into a channel region 205C and a source / drain region 205SD. The source / drain region may individually or collectively represent a source region or a drain region, depending on the context.

[0015] The fin-shaped active region 205 can be formed from the top of the substrate 202 and an alternating vertical stack 207 of semiconductor layers (as shown in FIG. 3) using a combination of photolithography and etching steps. In the depicted embodiment, the alternating vertical stack 207 of semiconductor layers includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206. Each channel layer 208 may contain a semiconductor material, such as silicon, germanium, silicon carbide, silicon germanium, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while each sacrificial layer 206 has a different composition than the channel layers 208. In one embodiment, the channel layer 208 contains silicon and the sacrificial layer 206 contains silicon germanium. The channel layer 208 and the sacrificial layer 206 can be epitaxially deposited on the substrate 202 using molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), and / or other suitable epitaxial growth processes. In some embodiments, each fin-shaped active region 205 may include a total of three to ten pairs of alternating sacrificial layers 206 and channel layers 208; of course, other configurations may be adopted depending on specific design requirements.

[0016] The semiconductor structure 200 further includes an isolation member 204 (as shown in FIG. 11) formed above the substrate 202 to isolate two adjacent fin-shaped active regions. The isolation member 204 may also represent a shallow trench isolation (STI) member. In some embodiments, the isolation member 204 may comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials. In some embodiments, the top surface of the isolation member 204 is lower than the top surface of the top of the substrate. The top surface of the isolation member 204 may be a curved (e.g., concave) surface with a lowest point near its center.

[0017] Referring again to Figures 2-3, the semiconductor structure 200 also includes a dummy gate structure 216 formed above the channel region 205C of the fin-shaped active region 205. The channel region 205C and the dummy gate structure 216 also define source / drain regions 205SD that do not vertically overlap with the dummy gate structure 216. Each channel region 205C is disposed between two source / drain regions 205SD along the X direction. Although two dummy gate structures 216 are shown in Figure 2, the semiconductor structure 200 may include other numbers of dummy gate structures. In this embodiment, a gate replacement process (or gate-last process) is used, in which the dummy gate structure 216 is used as a placeholder for a functional gate stack (e.g., the functional gate stacks 255, 260 shown in Figures 21A and 21B). Other processes for forming the functional gate stack are also possible. In this embodiment, although not shown separately, each dummy gate structure 216 includes a dummy gate dielectric layer (e.g., silicon oxide) and a dummy gate electrode (e.g., polysilicon) disposed above the dummy gate dielectric layer. The semiconductor structure 200 also includes gate spacers 218 extending along the sidewalls of the dummy gate structures 216. In some embodiments, the gate spacers 218 may comprise silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. The gate spacers 218 may be a single-layer or multi-layer structure.

[0018] Referring to Figures 1 and 4, method 100 includes step 104, which involves etching the source / drain region 205SD of the fin-shaped active region 205 to form a source / drain opening 220. In some embodiments, the source / drain region 205SD of the fin-shaped active region 205 not covered by the dummy gate structure 216 and gate spacer 218 isotropically etched by dry etching or a suitable etching process to form the source / drain opening 220. In an exemplary dry etching process, oxygen-containing gas, hydrogen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof may be applied. The source / drain opening 220 extends through the stack 207 of the channel layer 208 and the sacrificial layer 206 and extends into the substrate 202. As shown in FIG4, the source / drain opening 220 exposes the sidewalls of the channel layer 208 and the sacrificial layer 206.

[0019] Referring to Figures 1 and 5-6, method 100 includes step 106, which is replacing the sacrificial layer 206 with a dummy layer 224. Referring to Figure 5, after the source / drain opening 220 is formed, the sacrificial layer 206, which intersects with the channel layer 208 in the channel region 205C, is selectively removed. The selective removal of the sacrificial layer 206 releases the channel layer 208 to form a channel member. Depending on the design, the channel layer 208 may take the form of nanowires, nanosheets, or other nanostructures. The selective removal of the sacrificial layer 206 forms spaces 222 between and around adjacent channel layers 208. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include etching with an ammonia hydroxide-hydrogen peroxide-water mixture (APM) (e.g., an ammonia hydroxide-hydrogen peroxide-water mixture, etc.).

[0020] Referring to FIG6, in an exemplary process, after selectively removing the sacrificial layer 206, a dielectric material layer is deposited around the channel layer 208 and over the source / drain openings 220. The dielectric material layer fills the space 222 between the channel layers 208 and covers the end sidewalls of the channel layers 208. After the dielectric material layer is deposited, an etching process is performed to selectively etch the dielectric material layer, thereby forming dummy layers 224 interleaved with the channel layers 208. The dielectric material layer may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, high-k dielectric materials (e.g., alumina, hafnium oxide, etc.), other suitable materials, or combinations thereof, and may be used using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods. In one embodiment, the dielectric material layer comprises silicon oxide.

[0021] Referring to Figures 1 and 7, method 100 includes step 108, which is forming an inner spacer component 226. After the dummy layer 224 is formed, an etching process is performed to selectively etch the dummy layer 224 to form an inner spacer recess (currently filled by the inner spacer component 226). The etching process selectively and partially etches the dummy layer 224 to form the inner spacer recess, while the exposed channel layer 208 is not significantly etched. In embodiments where the channel layer 208 is substantially composed of silicon and the dummy layer 224 is formed of silicon oxide, a selective wet etching process or a selective dry etching process can be used to perform the selective etching of the dummy layer 224. The extent of etching of the dummy layer 224 is controlled by the duration of the etching process. In an alternative embodiment, the back etching of the dielectric material layer and the selective partial etching of the dummy layer 224 are performed by performing the same etching process. The inner spacer component 226 is then formed in the inner spacer recess. In an exemplary process, after the inner spacer recess is formed, an inner spacer material layer (not shown) is deposited over the semiconductor structure 200, contained within the inner spacer recess. The deposited inner spacer material layer is then etched back to remove excess inner spacer material, thereby forming an inner spacer component 226. The etch-back process in step 108 can be a dry etching process, similar to the dry etching process used in the formation of the source / drain openings 220. The inner spacer component 226 conforms to the shape of the corresponding inner spacer recess. The inner spacer material layer can comprise silicon oxide, silicon nitride, silicon oxide carbon, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material.

[0022] Referring to Figures 1 and 8, method 100 includes step 110, which is to form a source / drain component adjacent to a channel region 205C. The source / drain component is formed in and / or above the source / drain region 205SD and coupled to a channel layer 208 in the channel region 205C. In this embodiment, an N-type source / drain component 220N is formed in a first element region 200A, and a P-type source / drain component (not shown) is formed in a second element region 200B. The exemplary N-type source / drain component may contain silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped by introducing N-type dopants, such as phosphorus, arsenic, or antimony, during the epitaxial process, or ex-situ doped using a junction implant process. Exemplary P-type source / drain components may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be in-situ doped during the epitaxial process by introducing P-type dopants, such as boron or gallium, or ex-situ doped using a junction implantation process.

[0023] Referring to Figures 1 and 9-10, method 100 includes step 112, which is to selectively remove the dummy gate structure 216 to form a gate trench 234. Referring to Figure 9, after the source / drain components are formed, a contact etch stop layer (CESL) 230 and an interlayer dielectric layer (ILD layer) 232 are formed over the semiconductor structure 200. CESL 230 is used to protect various underlying components during subsequent manufacturing processes and may contain silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, and / or other suitable deposition or oxidation processes. As shown in Figure 9, CESL 230 may be formed on the top surface of the source / drain component (e.g., N-type source / drain component 228N) and the sidewalls of the gate spacer 218. Following CESL 230 deposition, an ILD layer 232 is deposited over the semiconductor structure 200 using CVD, PECVD, or other suitable deposition techniques. The ILD layer 232 may comprise silicon oxide, a low-k dielectric material, tetraethyl orthosilicate (TES), doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof. The top surface of the semiconductor structure 200 may be planarized using one or more chemical mechanical planarization (CMP) processes to expose the dummy gate electrode of the dummy gate structure 216. Referring to FIG10, the dummy gate structure 216 is selectively removed to form a gate trench 234 over the channel region 205C. The dummy gate structure 216 is selectively removed using an etching process. The etching process used to remove the dummy gate structure 216 may include any suitable process, such as a dry etching process, a wet etching process, or a combination thereof, and is used to selectively remove the dummy gate structure 216.

[0024] Referring to Figures 1 and 10-11, method 100 includes step 114, which is to selectively remove the dummy layer 224 to form a gate opening 236. Figure 11 depicts a cross-sectional view of the semiconductor structure 200 taken along line segment B-B' shown in Figures 2 and 10. After the dummy gate structure 216 is removed, the dummy layer 224 is selectively removed to form the gate opening 236. The selective removal of the dummy layer 224 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective wet etching process may include using diluted hydrofluoric acid (DHF), or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). An exemplary selective dry etching process may include the use of anhydrous hydrogen fluoride (anhydrous HF) vapor, trifluoromethane, nitrogen trifluoride, hydrogen, ammonia, carbon tetrafluoride, sulfur hexafluoride, or combinations thereof. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture, etc.).

[0025] Referring to Figures 1 and 12, method 100 includes step 116, which is to form a gate dielectric layer 238 over the semiconductor structure 200. In some embodiments, the gate dielectric layer 238 is a multilayer structure, including an interface layer 238a and a high-k dielectric layer 238b above the interface layer 238a. In some other embodiments, the interface layer 238a can be formed by thermal oxidation and may include silicon oxide. In other words, the interface layer 238a is formed only along the exposed surfaces of the semiconductor components (e.g., the top of the substrate 202 and the channel layer 208). In some embodiments, the interface layer 238a may be conformally deposited over the substrate 202, including in the gate trench 234 and the gate opening 236, and on the isolation component 204. Then, a high-k dielectric layer 238b is conformally deposited over the semiconductor structure 200 by performing a deposition process (e.g., CVD, ALD, etc.) to achieve a generally uniform thickness over the top surface of the semiconductor structure 200, thereby partially filling the gate trench 234 and the gate opening 236. The term "conformally" is used herein to describe a layer having a substantially uniform thickness across different regions. The high-k dielectric layer 238b may comprise a dielectric material having a high dielectric constant, such as greater than that of silicon oxide. Exemplary high-k dielectric materials include hafnium, zirconium, tantalum, titanium, oxygen, nitrogen, other suitable components, or combinations thereof. In some embodiments, the high-k dielectric layer 238b may comprise a high-k dielectric material, including, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, TiO2, Ta2O5, other suitable high-k dielectric materials, or combinations thereof.

[0026] In the illustrated embodiment, in order to effectively adjust the work function of the gate stack of the P-type transistor without significantly affecting other physical or electrical properties of the gate stack (e.g., gate resistance Rg, channel resistance Rch), the gate stack of the P-type transistor comprises a multilayer P-type work function structure 241 with a thickness of T, instead of forming a single P-type work function layer with a thickness of T (as shown in FIG. 14). For example, in one embodiment, the multilayer P-type work function structure 241 has a first P-type work function layer 240 and a second P-type work function layer 242 above the first P-type work function layer 240. The second P-type work function layer 242 may be a single-layer work function layer (described with reference to FIG. 14) or may contain two sub-layers (described with reference to FIG. 17).

[0027] In this embodiment, two different mechanisms can be implemented to expand the critical voltage regulation range of the P-type transistor without changing the total thickness T of its P-type work function structure 241. The first mechanism involves introducing a first type dopant into the first P-type work function layer 240 and / or the second P-type work function layer 242. The first type dopant can reduce or prevent aluminum diffusion from the aluminum-containing N-type work function layer above the second P-type work function layer 242 to the first P-type work function layer 240 and / or the second P-type work function layer 242. The degree of reduction in aluminum diffusion can cause an increase in the work function of the gate stack of the P-type transistor, thereby reducing the critical voltage of the P-type transistor. The first type dopant can contain tungsten, oxygen, fluorine, or other suitable components. The first type dopant can be introduced through atomic layer deposition processes, plasma doping, parameter control during the deposition of the first P-type work function layer 240 and / or the second P-type work function layer 242, or other suitable processes. The following will describe in detail, with reference to FIG16, an exemplary example of forming a P-type work function layer containing a type I dopant.

[0028] The second mechanism of the two mechanisms involves introducing a second type dopant into the first P-type work function layer 240. The intrinsic work function position of the second type dopant can be smaller than that of the material of the first P-type work function layer 240. Therefore, introducing the second type dopant into the first P-type work function layer 240 can reduce the work function position of the first P-type work function layer 240, resulting in an increase in the critical voltage of the P-type transistor. The second type dopant can contain silicon, aluminum, tantalum, or other suitable compositions. An exemplary example of forming a P-type work function layer containing a second type dopant will be described in detail below with reference to FIG16.

[0029] Referring to Figures 1 and 13-15, method 100 includes step 118, which is to deposit a first P-type work function layer 240 over a semiconductor structure 200. Figure 14 depicts a magnified portion of the semiconductor structure 200. Figure 15 depicts a simplified diagram of an exemplary cycle of an atomic layer deposition process 300 for forming the first P-type work function layer 240 of the P-type work function structure 241.

[0030] Referring to Figures 13, 14, and 15, a first P-type work function layer 240 is conformally deposited over a substrate 202, encompassing a high-k dielectric layer 238b over a channel layer 208. The first P-type work function layer 240 can be deposited using ALD, CVD, PVD, or other suitable processes. The first P-type work function layer 240 contains a P-type work function material for a P-type transistor, such as TiN, TaN, TiSiN, TaSiN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other P-type work function materials, or combinations thereof. In some embodiments, the first P-type work function layer 240 completely fills the remaining portion of the gate opening 236 between adjacent channel layers 208. In the illustrated embodiment, the first P-type work function layer 240 does not completely fill the remaining portion of the gate opening 236 between adjacent channel layers 208. In some embodiments, the first P-type work function layer 240 has a thickness T1 of about 6 Å to about 18 Å.

[0031] The first P-type work function layer 240 can be formed by implementing the ALD process 300 shown in FIG. 15. In the initial process, a semiconductor structure 200 as shown in FIG. 12 is loaded into a process cavity, wherein the process cavity is prepared for performing the ALD process 300 to form a work function layer, such as the first P-type work function layer 240, above the gate dielectric layer 238 and the substrate 202. After being loaded into the process cavity, the semiconductor structure 200 is exposed to a metal-containing precursor (which may be referred to as a pulse process 310 or a metal-containing pulse process). Then, a discharge process 320 is performed to remove any remaining metal-containing precursor and any byproducts from the process cavity. Then, the semiconductor structure 200 is exposed to a non-metal-containing precursor (which may be referred to as a non-metal-containing pulse process or a pulse process 330). Then, a discharge process 340 is performed to remove any remaining non-metal-containing precursor and any byproducts from the process cavity. A pulse process 310, a discharge process 320, a pulse process 330, and a discharge process 340 constitute an ALD cycle, which includes two deposition stages (pulse processes 310 and 330) and two discharge stages (discharge processes 320 and 340). Each ALD cycle is a self-limiting process, in which less than or equal to approximately one monolayer is deposited during each ALD cycle. The ALD cycle is repeated until the first P-type work function layer 240 reaches the desired (target) thickness T1. In embodiments where the first P-type work function layer 240 comprises titanium nitride, the metal-containing precursor may comprise titanium tetrachloride (TiCl4), tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or other suitable materials, and the non-metal-containing precursor may comprise NH3, nitrogen, N2H4, or other suitable materials. In one embodiment, the metal-containing precursor comprises TiCl4, and the non-metal-containing precursor comprises NH3. A carrier gas may be used to transport the precursor to the process chamber. In some embodiments, the carrier gas may be an inert gas, such as argon, helium, other suitable inert gases, or combinations thereof. In some embodiments, each exhaust process 320 and exhaust process 340 applies an inert gas, such as argon, helium, other suitable inert gases, or combinations thereof.

[0032] Referring now to Figures 1, 13, 14, and 16, method 100 includes step 120, which is to deposit a second P-type work function layer 242 over a first P-type work function layer 240. Figure 14 depicts a magnified portion of the semiconductor structure 200. Figure 16 depicts a simplified diagram of an exemplary cycle of an atomic layer deposition process 350 for forming the second P-type work function layer 242 of the P-type work function structure 241. After forming the first P-type work function layer 240, the second P-type work function layer 242 is conformally deposited over the substrate 202, encompassing the first P-type work function layer 240. The second P-type work function layer 242 can be deposited using ALD, CVD, PVD, or other suitable processes. In the illustrated embodiment, the second P-type work function layer 242 completely fills the remainder of the gate opening 236 between adjacent channel layers 208. In some other embodiments, the second P-type work function layer 242 does not completely fill the remaining portion of the gate opening 236 between adjacent channel layers 208. The second P-type work function layer 242 comprises a P-type work function metal for a P-type transistor, such as doped TiN (e.g., TiWN, TiSiN), other P-type work function materials (e.g., doped TaN, or other doped P-type work function materials), or combinations thereof. In some embodiments, the second P-type work function layer 242 has a thickness T2 of about 7 Å to about 19 Å.

[0033] According to the first mechanism described above, a first type of dopant (e.g., tungsten, oxygen, fluorine) can be introduced into the first P-type work function layer 240 and / or the second P-type work function layer 242 to reduce or avoid aluminum diffusion from the aluminum-containing N-type work function layer to the first P-type work function layer 240 and / or the second P-type work function layer 242, thereby reducing the critical voltage of the P-type transistor. In the embodiment illustrated in FIG14A, tungsten is introduced into the second P-type work function layer 242. For example, the second P-type work function layer 242 comprises tungsten-doped titanium nitride (titanium tungsten nitride (TiWN)).

[0034] An ALD process 350, as shown in FIG16, is implemented to form a TiWN-based second P-type work function layer 242. The ALD process 350 includes a first half-cycle 350A for forming a tungsten nitride monolayer and a subsequent second half-cycle 350B for forming a titanium nitride monolayer. In other words, once the ALD process 350 is completed, the second P-type work function layer 242 will contain a stacked structure comprising alternating WN monolayers and TiN monolayers. Elemental interdiffusion between the monolayers forms the second P-type work function layer 242 comprising tungsten-doped titanium nitride (titanium tungsten nitride (TiWN)).

[0035] In the initial process, after the first P-type work function layer 240 is formed, the semiconductor structure 200 is loaded into the process cavity, wherein the process cavity is prepared for performing the ALD process 350 to form the second P-type work function layer 242 above the first P-type work function layer 240 and the substrate 202.

[0036] After being loaded into the process cavity, the semiconductor structure 200 is exposed to a first metal-containing precursor (which may represent a pulse process 360 or a first metal-containing pulse process). Then, a discharge process 365 is performed to remove any remaining first metal-containing precursor and any byproducts from the process cavity. The semiconductor structure 200 is then exposed to a first non-metal-containing precursor (which may represent a first non-metal-containing pulse process or a pulse process 370). Then, a discharge process 375 is performed to remove any remaining first non-metal-containing precursor and any byproducts from the process cavity. Pulse process 360, discharge process 365, pulse process 370, and discharge process 375 constitute the first half-cycle 350A of the ALD cycle of the ALD process 350. Each first half-cycle 350A of the ALD cycle is a self-limiting process, wherein less than or equal to about one monolayer is deposited during each first half-cycle 350A. The first half-cycle 350A is repeated until the tungsten nitride monolayer reaches the desired (target) thickness. For example, within one cycle of the ALD process 350, the first half-cycle 350A can be executed A times before proceeding to the second half-cycle 350B, where A is a positive integer. In other words, a cycle of the ALD process 350 can contain multiple executions of the first half-cycle 350A.

[0037] After executing the first half-cycle 350A, the cycle of the ALD process 350 continues to the second half-cycle 350B. A semiconductor structure 200 having a tungsten nitride monolayer is exposed to a second metal-containing precursor (which may represent a second metal-containing pulse process or pulse process 380). Then, a discharge process 385 is performed to remove any remaining second metal-containing precursor and any byproducts from the process cavity. Then, the semiconductor structure 200 is exposed to a second non-metal-containing precursor (which may represent a second non-metal-containing pulse process or pulse process 390). Then, a discharge process 395 is performed to remove any remaining second non-metal-containing precursor and any byproducts from the process cavity. Pulse process 380, discharge process 385, pulse process 390, and discharge process 395 constitute the second half-cycle 350B of the ALD cycle of the ALD process 350. Each second half-cycle 350B of the ALD process is a self-limiting process, wherein less than or equal to about one monolayer is deposited during each second half-cycle 350B. The second half-cycle 350B is repeated until the titanium nitride monolayer reaches the desired (target) thickness. For example, the second half-cycle 350B may be performed B times before entering the next cycle of the ALD process 350, where B is a positive integer. The entire cycle of the ALD process 350 (including the first half-cycle 350A and the second half-cycle 350B) may be repeated multiple times until the second P-type work function layer 242 reaches the desired (target) thickness T2. In some embodiments, a carrier gas is used to transport the precursor to the process chamber. In some embodiments, the carrier gas is an inert gas, such as argon-containing gas, helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, each exhaust process 365, 375, 385, 395 applies an inert gas, such as argon-containing gas, helium-containing gas, other suitable inert gases, or combinations thereof.

[0038] In embodiments where the second P-type work function layer 242 comprises titanium tungsten nitride, the first metal-containing precursor may comprise tungsten hexafluoride (WF6), tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), carbonyl tungsten (e.g., W(CO)₆), tris(3-hexyne)carbonyl tungsten (W(CO)(CH3CH2C≡CCH2CH3)3), bis(tert-butylimino)bis(dimethylamino)tungsten (VI) (((CH3)3CN)2W(N(CH3)2)2), or other suitable tungsten-containing precursors. The second metal-containing precursor may comprise titanium tetrachloride (TiCl4), tetra(dimethylamino)titanium, tetra(diethylamino)titanium, or other suitable titanium-containing precursors. The non-metal-containing precursor may comprise NH3, nitrogen, N2H4, or other suitable materials. In this embodiment, both the first half-cycle 350A and the second half-cycle 350B use the same non-metallic precursor. However, in some other embodiments, different non-metallic precursors may be applied to the first half-cycle 350A and the second half-cycle 350B. In one embodiment, the percentage of tungsten atoms in the TiWN-based second P-type work function layer 242 is in the range of about 5% to about 27%. If the percentage of tungsten atoms in the TiWN-based second P-type work function layer 242 is less than 5%, the work function of the gate stack 260 and the resulting critical voltage may not be effectively regulated; and if the percentage of atoms in the TiWN-based second P-type work function layer 242 is greater than 27%, the adhesion between the second P-type work function layer 242 and the photoresist to be formed on the TiWN-based second P-type work function layer 242 in the subsequent patterning process may be insufficient, resulting in poor patterning results. In one embodiment, to obtain a satisfactory tungsten concentration, the ratio of quantity B to quantity A is in the range of about 3 to 10. In other words, one cycle of the ALD process 350 may include performing one first half-cycle 350A and performing 3 to 10 second half-cycles 350B. In the illustrated embodiment, the first half-cycle 350A is performed before the second half-cycle 350B. In some alternative embodiments, the second half-cycle 350B is performed before the first half-cycle 350A. Additional steps may be provided before, during, and after the ALD process 350, and some of these steps may be moved, replaced, or deleted in additional embodiments of the ALD process 350.

[0039] Various parameters of the ALD process 350 can be adjusted to achieve desired growth characteristics, such as the flow rate of the deposition gas (containing titanium-containing precursor gas, tungsten-containing precursor gas, nitrogen-containing precursor gas, and / or carrier gas), the concentration (or dose) of the titanium-containing precursor gas, the concentration (or dose) of the tungsten-containing precursor gas, the concentration (or dose) of the nitrogen-containing precursor gas, the carrier gas concentration (or dose), the ratio of the titanium-containing precursor gas concentration to the tungsten-containing precursor gas concentration, the ratio of the metal-containing precursor gas concentration to the non-metal-containing precursor gas concentration, the power of the radio frequency (RF) source (e.g., used during the deposition process to generate plasma), the bias voltage (e.g., applied during the deposition process to excite plasma)), the pressure of the process chamber, the duration of the deposition process, other suitable deposition parameters, or combinations thereof. In some embodiments, the ratio of the duration of the pulsed process 370 to the duration of the pulsed process 360 is less than 2.5. In one embodiment, the duration of the pulsed process 360 in the first half-cycle 350A is between about 0.5 seconds and about 10 seconds. In some embodiments, the temperature maintained in the process cavity during pulse process 380 is from about 300°C to about 400°C. In some embodiments, the various cycles of ALD process 350 have the same quantity B to quantity A ratio, and the tungsten concentration in the second P-type work function layer 242 is uniform throughout the second P-type work function layer 242. In some other embodiments, one or more cycles of ALD process 350 have different quantity B to quantity A ratios, and the tungsten concentration in the second P-type work function layer 242 is non-uniform throughout the second P-type work function layer 242. For example, referring to FIG14A, the tungsten concentration in the second P-type work function layer 242 may have a graded profile that gradually decreases from bottom to top, or a stepwise profile that decreases from bottom to top. As described above, the tungsten concentration in the second P-type work function layer 242 is in the range of from about 5% to about 27%. In one embodiment, the bottom surface of the second P-type work function layer 242 has a tungsten concentration of about 27%, and the top surface of the second P-type work function layer 242 has a tungsten concentration of about 5%.

[0040] In the above embodiments, tungsten is introduced as a dopant into the titanium nitride-containing P-type work function structure 241. In another embodiment shown in FIG14B, oxygen can be introduced as a dopant into the titanium nitride-containing P-type work function structure 241. Oxygen-containing dopants can be introduced by oxygen plasma doping of the first P-type work function layer 240 and / or the second P-type work function layer 242. For example, once oxygen is introduced as a dopant, both the first P-type work function layer 240 and the second P-type work function layer 242 can contain oxygen-containing titanium nitride. In some other embodiments, a baking process can be used on the titanium nitride-based first P-type work function layer 240 and / or the second P-type work function layer 242 to increase their corresponding oxygen concentration. In some other embodiments, the first P-type work function layer 240 comprises titanium nitride formed by the ALD process 300, and the temperature maintained in the corresponding process cavity during the pulse process 310 is from about 300°C to about 400°C; the second P-type work function layer 242 comprises titanium nitride formed by the ALD process 300, and the temperature maintained in the corresponding process cavity during the pulse process 310 is from about 300°C to about 400°C. For embodiments where the first P-type work function layer 240 and the second P-type work function layer 242 comprise titanium nitride formed by the ALD process 300, and the temperature maintained in the corresponding process cavity during the pulse process 310 is from about 300°C to about 400°C, the oxygen concentration of the titanium nitride-based first P-type work function layer 240 and the second P-type work function layer 242 is in the range of from about 15% to about 50%. If the temperature is below approximately 300°C, the oxygen concentration in the first P-type work function layer 240 and the second P-type work function layer 242 may be too high, leading to an increase in gate resistance Rg. If the temperature is above approximately 400°C, the titanium-containing precursor (TiCl4) may be completely consumed, resulting in an oxygen concentration in the first P-type work function layer 240 and the second P-type work function layer 242 that is too low to affect the work function of titanium nitride. In one embodiment, the temperature associated with the ALD process 300 for forming the second P-type work function layer 242 may be different from (e.g., less than) the temperature associated with the ALD process 300 for forming the first P-type work function layer 240. Therefore, the first P-type work function layer 240 and the second P-type work function layer 242 may have different oxygen concentrations. For example, in one embodiment, the oxygen concentration in the second P-type work function layer 242 is higher than the oxygen concentration in the first P-type work function layer 240.

[0041] The above embodiments include various combinations of different compositions of the first P-type work function layer 240 and the second P-type work function layer 242. For example, in one embodiment shown in FIG14A, the first P-type work function layer 240 comprises oxygen-containing titanium nitride formed at a temperature ranging from about 300°C to about 400°C, and the second P-type work function layer 242 comprises titanium tungsten nitride or tungsten-containing titanium nitride. In another embodiment shown in FIG14B, the first P-type work function layer 240 comprises oxygen-containing titanium nitride formed at a first temperature ranging from about 300°C to about 400°C, and the second P-type work function layer 242 comprises oxygen-containing titanium nitride formed at a second temperature ranging from about 300°C to about 400°C. The first temperature may be different from (e.g., lower than, greater than) or equal to the second temperature, and the oxygen concentration in the second P-type work function layer 242 may be higher than, equal to, or lower than the oxygen concentration in the first P-type work function layer 240.

[0042] In the embodiments described above with reference to Figures 14-16, the second P-type work function layer 242 is a single-layer work function layer. In some alternative embodiments, the second P-type work function layer 242 may be a multi-layer work function layer. Referring to Figure 17, the second P-type work function layer 242 includes a first layer 242a and a second layer 242b above the first layer 242a. The first layer 242a and the second layer 242b are P-type work function layers with different compositions. In one embodiment, the first P-type work function layer 240 includes oxygen-containing titanium nitride formed at a first temperature in the range of about 300°C to about 400°C, the first layer 242a includes tungsten nitride, and the second layer 242b includes titanium tungsten nitride. It should be noted that in order to provide good adhesion between the second P-type work function layer 242 and the photoresist layer formed in subsequent processes to achieve satisfactory patterning, a TiWN-based second layer 242b is formed above the WN-based first layer 242a. The thickness T3 of the first layer 242a may be equal to or different from (e.g., greater than or less than) the thickness T4 of the second layer 242b, and the total thickness of the first layer 242a (i.e., T3 + T4) and the thickness of the second layer 242b are equal to T2. In one embodiment, the ratio of thickness T3 to thickness T2 is equal to 0.5. In another embodiment, the ratio of thickness T3 to thickness T2 is equal to 2. In some embodiments, depending on the choice of the tungsten-containing precursor, the first layer 242a may contain tungsten carbonitride (WN) ("WN:C" or "WCN"), and the second layer 242b may contain titanium carbonitride.

[0043] In the above embodiments, an exemplary example of the first mechanism has been described. An exemplary example of the second mechanism includes introducing a second type dopant (e.g., silicon, aluminum, tantalum) into the P-type work function structure 241 to reduce the work function positions of the P-type work function structure 241. For example, referring to FIG14C, according to the second mechanism, in order to reduce the work function positions of the P-type work function structure 241, the first P-type work function layer 240 may contain silicon-containing titanium nitride (e.g., TiSiN). The second type dopant (e.g., silicon) can be introduced in a manner similar to that used for the first type dopant (e.g., tungsten) as described with reference to FIG16. For example, in order to form the silicon-doped TiN-based first P-type work function layer 240 (e.g., TiSiN), an ALD process similar to that of an ALD process 350 including a first half-cycle 350A and a second half-cycle 350B can be performed. One difference between these two ALD processes may involve introducing type II dopant by using a precursor containing type II dopant (e.g., a silicon-containing precursor) to dope the TiN-based first p-type work function layer 240, instead of using a tungsten-containing metal precursor to introduce type I dopant. The silicon concentration in the silicon-doped TiN-based first p-type work function layer 240 is less than about 20%. If the silicon concentration is greater than 20%, the gate resistance Rg of the resulting gate stack may be too high, adversely affecting the transistor performance. The silicon concentration in the first p-type work function layer 240 can be uniform or non-uniform, somewhat similar to the tungsten concentration described above with reference to FIG16. In an embodiment according to the second mechanism, the second P-type work function layer 242 formed above the first P-type work function layer 240 on a silicon-doped TiN-based substrate may contain titanium nitride formed at a third temperature above 400°C, and the oxygen concentration may be less than the oxygen concentration of a titanium- and nitrogen-containing P-type work function layer (e.g., the first P-type work function layer 240 formed according to the first mechanism) formed at a first temperature in the range of about 300°C to 400°C. In some other embodiments, as shown in FIG14D, a second type dopant (e.g., silicon, aluminum, tantalum) may be introduced into the second P-type work function layer 242 of the P-type work function structure 241. For example, the first P-type work function layer 240 may contain titanium nitride formed at a third temperature above 400°C, and the oxygen concentration is less than that of a titanium and nitrogen-containing P-type work function layer (e.g., the P-type work function layer 240 formed according to the first mechanism) formed at a first temperature in the range of about 300°C to 400°C; the second P-type work function 242 may contain silicon-containing titanium nitride (e.g., TiSiN) and may be formed by the ALD process described with reference to FIG14C.

[0044] In some embodiments, the semiconductor structure 200 includes a first P-type transistor having a critical VT0, and includes a first P-type work function layer and a second P-type work function layer, wherein the first P-type work function layer includes titanium nitride formed at a third temperature above 400°C, the second P-type work function layer includes titanium nitride formed at a third temperature above 400°C, and the second P-type work function layer is located above the first P-type work function layer. The semiconductor structure 200 also includes a second P-type transistor having a critical VT1, and includes a P-type work function structure 241 (e.g., an oxygen-containing TiN-based first P-type work function layer 240 and a TiWN-based second P-type work function layer 242) formed according to the first mechanism described above with reference to FIG14. The semiconductor structure 200 also includes a third P-type transistor having a critical VT2, and includes a P-type work function structure (e.g., a TiSiN-based first P-type work function layer 240 and a TiN-based second P-type work function layer 242) formed according to the second mechanism. Aside from the different configurations of the P-type work function structure, the gate stacking configurations of the three P-type transistors are essentially the same. Compared to the first P-type transistor, by introducing dopant into the P-type work function structure, different critical voltages can be achieved without changing the thickness of the P-type work function structure. In one embodiment, critical voltage VT1 is less than critical voltage VT0, and critical voltage VT2 is greater than critical voltage VT0. Therefore, the critical voltage adjustment range of the P-type transistor can be advantageously expanded to meet various design requirements.

[0045] Referring to Figures 1 and 18, method 100 includes step 122, which is to pattern the P-type work function structure 241 to remove a portion of the P-type work function structure 241 in the first element region 200A. The P-type work function structure 241 is patterned after its formation. The operation in step 122 can be performed using a photolithography process, including forming an impedance (or photoresist) layer over the P-type work function structure 241 by spin coating, performing a pre-exposure baking process, performing an exposure process, performing a post-exposure baking process, and developing the exposed impedance layer in a developer solution. After development, the impedance layer becomes an impedance pattern. An etching process is performed when the impedance pattern is used as an etching mask to remove a portion of the P-type work function structure 241 formed in the first element region 200A.

[0046] Referring to Figures 1 and 19, method 100 includes step 124, which is to form an N-type work function layer 246 over the semiconductor structure 200. After the P-type work function structure 241 is patterned, the N-type work function layer 246 is deposited over the gate dielectric layer 238 using a suitable process such as atomic layer deposition. In one embodiment, the N-type work function layer 246 is conformally deposited over the semiconductor structure 200 to have a generally uniform thickness over the top surface of the semiconductor structure 200, thereby partially filling the gate trench 234 and the gate opening 236 in the first element region 200A. In some embodiments, the N-type work function layer 246 may comprise a metal having a sufficiently low effective work function, such as Ti, Al, TaC, TaCN, TaSiN, or combinations thereof. For example, the N-type work function layer 246 may comprise an aluminum-containing N-type work function layer formed of titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), or titanium aluminum nitride (TiAlN), or other suitable materials. In some other embodiments, the aluminum-containing N-type work function layer 246 (e.g., TiAlC) may be formed using an ALD process similar to ALD process 350, selecting suitable precursors (titanium-containing precursors, carbon-containing precursors, aluminum-containing precursors), and the aluminum concentration of the aluminum-containing N-type work function layer 246 may be adjusted by adjusting the ratio of its corresponding quantity B to quantity A, thereby adjusting the work function of the aluminum-containing N-type work function layer 246 to obtain a wider critical voltage regulation range for the N-type transistor.

[0047] Referring to Figures 1, 20, and 21A-21B, method 100 includes step 126, which involves forming one or more conductive layers over the substrate 202 to complete the fabrication of functional gate stacks 255 and 260. Figure 21A depicts an enlarged portion of the gate stack 255 formed in the gate trench 234 in the first element region 200A, and Figure 21B depicts an enlarged portion of the gate stack 260 formed in the gate trench 234 in the second element region 200B. In some embodiments disclosed herein, the one or more conductive layers include a first protective layer 248 and a second protective layer 250 conformally formed over the N-type work function layer 246, and a metal electrode layer 252 formed over the second protective layer 250. In one embodiment, the first protective layer 248 comprises titanium nitride, and the deposition thickness of the first protective layer 248 may be less than the thickness T1 of the first P-type work function layer 240. In one embodiment, both the first protective layer 248 and the first P-type work function layer 240 comprise oxygen-containing titanium nitride, and the oxygen concentration of the first protective layer 248 is higher than that of the first P-type work function layer 240. The second protective layer 250 may comprise silicon. The metal electrode layer 252 may comprise a conductive material, such as Al, W, and / or Cu, and may be deposited using ALD, CVD, PVD, plating, or other suitable processes to fill any remaining portion of the gate trench 234. In various embodiments, a planarization process (e.g., chemical mechanical polishing (CMP)) may be performed to remove excess material above the ILD layer 232, thereby ultimately completing the structure of the gate stack 255 in the first element region 200A and the structure of the gate stack 260 in the second element region 200B. In the illustrated embodiment, the gate stack 255 formed in the gate trench 234 of the first element region 200A includes a metal electrode layer 252, and the gate stack 260 formed in the gate trench 234 of the second element region 200B does not include a metal electrode layer 252.

[0048] In the above embodiments, an N-type work function layer 246 is formed in the first element region 200A and the second element region 200B. In some alternative embodiments, as shown in FIG22, a portion of the N-type work function layer 246 formed in the second element region 200B is removed. In another alternative embodiment, a portion of the first protective layer 248 and the second protective layer 250 formed in the second element region 200B may also be removed. The above-described second mechanism (e.g., introducing a second type of dopant to reduce the work function) can be used to adjust the critical voltage of the P-type transistor formed in the second element region 200B as shown in FIG22.

[0049] After forming the gate stacks 255 and 260, further processes are performed. These further processes may include forming a silicon layer (not shown) over the source / drain components and a multi-layer interconnect (MLI) structure (not shown) over the semiconductor structure 200. The MLI may include various interconnect components disposed in a dielectric layer, such as an etch stop layer and an ILD layer (e.g., ILD layer 232), and the interconnect components such as vias and conductive lines, source / drain contacts, and gate contacts. In some embodiments, vias are vertical interconnect components for interconnecting element-level contacts, such as source / drain contacts formed over the source / drain components and gate contacts (not shown) formed over the gate stacks 255 and 260.

[0050] Although not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and their fabrication. In some embodiments, this disclosure provides a method for extending the critical voltage regulation range of a P-type transistor without adjusting the total thickness of the P-type work function layer.

[0051] This disclosure provides many different embodiments. This document discloses semiconductor structures and methods for fabricating them. In one exemplary embodiment, this disclosure relates to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes forming a dielectric layer over a portion of a substrate, forming a first P-type work function layer over the dielectric layer, wherein the first P-type work function layer comprises titanium nitride, forming a second P-type work function layer over the first P-type work function layer, wherein the second P-type work function layer comprises doped titanium nitride, forming an aluminum-containing N-type work function layer over the second P-type work function layer, wherein the dopant in the second P-type work function layer reduces aluminum diffusion from the aluminum-containing N-type work function layer to the second P-type work function layer, and forming a metal layer over the aluminum-containing N-type work function layer.

[0052] In some embodiments, the percentage of titanium atoms in the second P-type work function layer is less than the percentage of titanium atoms in the first P-type work function layer. In some embodiments, the work function of the second P-type work function layer is less than the work function of the first P-type work function layer. In some embodiments, the dopant in the second P-type work function layer comprises oxygen, tungsten, or fluorine. In some embodiments, the dopant in the second P-type work function layer comprises tungsten, and the formation of the second P-type work function layer comprises performing an atomic layer deposition process, and one cycle of the atomic layer deposition process comprises performing multiple first cycles to form multiple first monolayers of titanium nitride, and after performing the first cycles, performing multiple second cycles to form multiple second monolayers of tungsten nitride over the first monolayers. In some embodiments, the method of fabricating a semiconductor device further comprises adjusting the ratio of the second cycle to the first cycle to adjust the tungsten concentration in the second P-type work function layer. In some embodiments, the precursor for forming the first monolayer of titanium nitride comprises ammonia and a titanium-containing precursor, and the precursor for forming the second monolayer of titanium nitride comprises ammonia and a tungsten-containing precursor. In some embodiments, the method of fabricating a semiconductor device further includes adjusting the ratio of the pulse duration of ammonia to the pulse duration of the tungsten-containing precursor to adjust the tungsten concentration in the second P-type work function layer. In some embodiments, the method of fabricating a semiconductor device further includes forming a third P-type work function layer above the first P-type work function layer before the formation of the second P-type work function layer, wherein the first P-type work function layer comprises titanium nitride, the second P-type work function layer comprises tungsten-containing titanium nitride, and the third P-type work function layer comprises tungsten nitride. In some embodiments, the first P-type work function layer comprises oxygen-containing titanium nitride.

[0053] In another exemplary embodiment, this disclosure relates to a method for fabricating a semiconductor device, comprising receiving a semiconductor structure, the semiconductor structure including a complex nanostructure above a substrate and source / drain components coupled to the complex nanostructure, forming a gate dielectric layer above and surrounding the nanostructure, and performing an atomic layer deposition process to form a P-type work function layer above the gate dielectric layer, wherein one cycle of the atomic layer deposition process includes a first half-cycle and a subsequent second half-cycle, and the first half-cycle includes sequentially pulsed a first metal precursor and a first non-metal precursor in a chamber, and the second half-cycle includes sequentially pulsed a second metal precursor and a second non-metal precursor in a chamber, wherein the first metal precursor and the second metal precursor contain different metal elements.

[0054] In some embodiments, the P-type work function layer comprises TiWN, the first metal precursor comprises titanium, and the second metal precursor comprises tungsten. In some embodiments, the first non-metallic precursor and the second non-metallic precursor have the same composition. In some embodiments, the second half-cycle of the atomic layer deposition process comprises repeatedly performing the step of sequentially pulsed second metal precursor and second non-metallic precursor. In some embodiments, the method of fabricating a semiconductor device further comprises, before performing the atomic layer deposition process, depositing another work function layer on the gate dielectric layer, wherein the other work function layer and the second metal precursor comprise the same metal element. In some embodiments, the method of fabricating a semiconductor device further comprises, after performing the atomic layer deposition process, depositing an N-type work function layer over the P-type work function layer, and forming a metal layer over the N-type work function layer.

[0055] In another embodiment, this disclosure relates to a semiconductor device. The semiconductor device includes a substrate, a gate dielectric layer above a portion of the substrate, a first titanium and nitrogen work function layer above the gate dielectric layer, a second titanium and nitrogen work function layer above the first titanium and nitrogen work function layer, wherein the composition of the second titanium and nitrogen work function layer is different from that of the first titanium and nitrogen work function layer, an aluminum work function layer above the second titanium and nitrogen work function layer, wherein the second titanium and nitrogen work function layer includes elements for reducing aluminum diffusion from the aluminum work function layer to the second titanium and nitrogen work function layer, and a conductive layer disposed above the aluminum work function layer.

[0056] In some embodiments, the semiconductor device further includes a complex nanostructure on top of a substrate, wherein a gate dielectric layer, a first titanium- and nitrogen-containing work function layer, and a second titanium- and nitrogen-containing work function layer are all disposed on top of and surround the complex nanostructure. In some embodiments, the second titanium- and nitrogen-containing work function layer comprises oxygen, tungsten, or fluorine. In some embodiments, the second titanium- and nitrogen-containing work function layer comprises TiWN.

[0057] The components of several embodiments have been summarized above to facilitate a better understanding of the various aspects disclosed herein by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. For example, different resistances of the conductors can be achieved by implementing different thicknesses for the bit-line conductor and the word line conductor. However, other techniques can also be used to change the resistance of the metal conductor. [Simplified Explanation of the Diagram]

[0007] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. It should also be noted that the accompanying drawings only illustrate typical embodiments of the present invention and should not be considered as limiting the scope, as the present invention can also be applied to other embodiments. FIG1 is a flowchart illustrating a method for forming a semiconductor structure according to various embodiments of the present disclosure. FIG2 is a partial top view illustrating an exemplary semiconductor structure undergoing various operating stages in the method of FIG1 according to various aspects of the present disclosure. FIG3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 18, 19, 20, 21A, 21B, and FIG22 are partial cross-sectional views illustrating a semiconductor structure during various manufacturing stages in the method of FIG1 according to various aspects of the present disclosure. Figures 14A, 14B, 14C, and 14D are partial cross-sectional views illustrating various semiconductor structures according to the various states disclosed herein. Figure 15 is a simplified timing diagram illustrating one cycle of an atomic layer deposition process according to the various states disclosed herein. Figure 16 is a simplified timing diagram illustrating one cycle of another atomic layer deposition process according to the various states disclosed herein.

Claims

1. A method for fabricating a semiconductor device, comprising: A dielectric layer is formed on top of a portion of a substrate; The process includes: forming a first P-type work function layer above the dielectric layer, wherein the first P-type work function layer comprises titanium nitride; forming a second P-type work function layer above the first P-type work function layer, wherein the second P-type work function layer comprises doped titanium nitride; forming an aluminum-containing N-type work function layer above the second P-type work function layer, wherein the dopant in the second P-type work function layer reduces aluminum diffusion from the aluminum-containing N-type work function layer to the second P-type work function layer; and forming a metal layer above the aluminum-containing N-type work function layer, wherein the dopant in the second P-type work function layer comprises tungsten, and the formation of the second P-type work function layer includes performing an atomic layer deposition process, wherein one cycle of the atomic layer deposition process includes: performing multiple first cycles to form multiple first monolayers of titanium nitride; And after executing the first cycle, a second cycle is executed multiple times to form a plurality of second monolayers of tungsten nitride on top of the first monolayer.

2. The method for fabricating a semiconductor device as claimed in claim 1, wherein the percentage of titanium atoms in the second P-type work function layer is less than the percentage of titanium atoms in the first P-type work function layer.

3. The method for fabricating a semiconductor device as described in claim 1, wherein the work function of the second P-type work function layer is less than the work function of the first P-type work function layer.

4. The method for fabricating a semiconductor device as claimed in claim 1, wherein the precursor for forming the first monolayer of titanium nitride includes ammonia and a titanium-containing precursor, and the precursor for forming the second monolayer of tungsten nitride includes ammonia and a tungsten-containing precursor.

5. The method for fabricating the semiconductor device as described in claim 1, further comprising: Before the second P-type work function layer is formed, a third P-type work function layer is formed above the first P-type work function layer, wherein the first P-type work function layer includes titanium nitride, the second P-type work function layer includes tungsten-containing titanium nitride, and the third P-type work function layer includes tungsten nitride.

6. A method for fabricating a semiconductor device as claimed in claim 1, wherein the first P-type work function layer comprises titanium oxynitride.

7. A method for fabricating a semiconductor device, comprising: A semiconductor structure is received, the semiconductor structure comprising: a complex nanostructure above a substrate; and a source / drain component coupled to the nanostructure; forming a gate dielectric layer above and surrounding the nanostructure; and performing an atomic layer deposition process to form a P-type work function layer above the gate dielectric layer, wherein one cycle of the atomic layer deposition process includes a first half-cycle and a subsequent second half-cycle, and the first half-cycle includes sequentially pulsed a first metal precursor and a first non-metal precursor in a chamber, and the second half-cycle includes sequentially pulsed a second metal precursor and a second non-metal precursor in the chamber, wherein the first metal precursor and the second metal precursor comprise different metal elements, wherein the first half-cycle of the atomic layer deposition process includes repeatedly performing the step of sequentially pulsed the first metal precursor and the first non-metal precursor to form multiple first monolayers of titanium nitride. The second half-cycle of the atomic layer deposition process includes repeatedly performing the step of sequentially pulsed second metal precursor and second non-metal precursor, thereby forming a plurality of second monolayers of tungsten nitride above the first monolayer, wherein the second metal precursor comprises tungsten.

8. A method for fabricating a semiconductor device as claimed in claim 7, wherein the P-type work function layer comprises TiWN and the first metal precursor comprises titanium.

9. A method for fabricating a semiconductor device as claimed in claim 7, wherein the first non-metallic precursor and the second non-metallic precursor have the same composition.

10. The method for manufacturing the semiconductor device as described in any one of claims 7 to 9, further comprising: Prior to performing the atomic layer deposition process, another work function layer is deposited on the gate dielectric layer, wherein the other work function layer and the second metal precursor contain the same metal element.

11. The method for fabricating a semiconductor device as described in any one of claims 7 to 9, further comprising: After performing the atomic layer deposition process, an N-type work function layer is deposited on top of the P-type work function layer; And to form a metal layer above the N-type work function layer.

12. A semiconductor device, comprising: One substrate; A gate dielectric layer is disposed above a portion of the substrate; a first titanium and nitrogen work function layer is disposed above the gate dielectric layer; a second titanium and nitrogen work function layer is disposed above the first titanium and nitrogen work function layer, wherein the composition of the second titanium and nitrogen work function layer is different from that of the first titanium and nitrogen work function layer; an aluminum work function layer is disposed above the second titanium and nitrogen work function layer, wherein the second titanium and nitrogen work function layer contains elements for reducing aluminum diffusion from the aluminum work function layer to the second titanium and nitrogen work function layer; and a conductive layer is disposed above the aluminum work function layer, wherein the second titanium and nitrogen work function layer comprises a stacked structure comprising a plurality of first monolayers of titanium nitride and a plurality of second monolayers of tungsten nitride above the first monolayers.

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