Method for making semiconductor device and the product made therefrom

Abstract

A semiconductor device includes a semiconductor substrate unit, a two-dimensional material layer formed on the semiconductor substrate unit and composed of a transition metal dichalcogenide, two single crystals, and two metal electrode layers. The single crystals are spaced apart on the two-dimensional material layer. Each single crystal is composed of a first metal material or a mesometallic compound composed of the first metal material and a second metal material. The metal electrode layers are composed of the second metal material, and each metal electrode layer contacts its corresponding single crystal. In this invention, the first metal material has a first melting point, and the second metal material has a second melting point, the first melting point being lower than the second melting point. This invention also provides a method for manufacturing the aforementioned semiconductor device.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a method for manufacturing a semiconductor device and the product thereof. Prior Technology

[0002] Transition metal dichalcogenides (TMDs), with their two-dimensional layered structure consisting of only molecular layers, can transition from an indirect bandgap in three-dimensional structures to a direct bandgap. When fabricated as field-effect transistors, they exhibit excellent on / off current ratios, thus attracting significant attention in recent years. Common TMDs include two-dimensional semiconductor materials such as molybdenum disulfide (MoS₂), tungsten disulfide (WS₂), molybdenum diselenide (MoSe₂), and tungsten diselenide (WSe₂).

[0003] Referring to Figure 1, the early publication of the Republic of China Patent No. TW202109882 (hereinafter referred to as Case 1) discloses a conventional semiconductor device 1, which includes a substrate 11, a semiconductor two-dimensional material (e.g., MoS2) layer 12 disposed on the substrate 11, a source film structure 13S and a drain film structure 13D respectively disposed on a source region 12S and a drain region 12D of the semiconductor two-dimensional material layer 12, a gate dielectric layer 14 extending along a channel region 12C of the semiconductor two-dimensional material layer 12 and partially exposing the source film structure 13S and the drain film structure 13D, and a gate electrode 15 disposed on the gate dielectric layer 14. The source film structure 13S and the drain film structure 13D each have a sequentially stacked conductive two-dimensional material layer 131S and 131D containing group IV elements, a separate metal layer 132S and 132D, and an electrode metal layer 133S and 133D. Each conductive two-dimensional material layer 131S and 131D is made of germanene or stanene. Each separate metal layer 132S and 132D can be made of a metallic material such as aluminum (Al), bismuth (Bi), cadmium (Cd), chromium (Cr), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), or tungsten (W) that does not form an alloy with the conductive two-dimensional material layers 131S and 131D. Each electrode metal layer 133S and 133D can be made of metal materials such as indium (In), lead (Pb), copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (Pt), cobalt (Co), rhodium (Rh), iron (Fe), ruthenium (Ru), manganese (Mn), molybdenum (Mo), vanadium (V), titanium (Ti), zirconium (Zr), hafnium (Hf), or magnesium (Mg), which can form alloys with each conductive two-dimensional material layer 131S and 131D.

[0004] However, the current density of TMDs transistors is often limited by contact resistance (Rc). This is because during the fabrication of TMDs transistors, the two-dimensional semiconductor material is easily damaged and defects are generated by the high energy during the fabrication of the contact electrode metal layer, which triggers the pinning effect at the Fermi level, ultimately making it impossible to effectively reduce the Schottky barrier.

[0005] As explained above, improving the manufacturing process and structure of semiconductor devices to effectively reduce contact resistance and increase current density is a problem that needs to be solved by relevant industry players in this field. Summary of the Invention

[0006] Therefore, the first objective of the present invention is to provide a method for manufacturing a semiconductor device that can effectively reduce contact resistance and increase current density.

[0007] Therefore, the method for manufacturing the semiconductor device of the present invention includes the following steps: a step (a), a step (b), a step (c), and a step (d).

[0008] Step (a) involves forming a two-dimensional material layer composed of a transition metal dichalcogenide on a semiconductor substrate unit.

[0009] Step (b) involves forming two spaced-apart lower metal layers, each composed of a first metal material, on the two-dimensional material layer.

[0010] Step (c) involves forming an upper metal layer made of a second metal material on each of the lower metal layers, so that each upper metal layer and the lower metal layer form a double-layer structure.

[0011] Step (d) involves subjecting the bilayer structure to selective annealing and then cooling it to room temperature.

[0012] In this invention, the first metallic material has a first melting point, and the second metallic material has a second melting point, wherein the first melting point is lower than the second melting point.

[0013] In each bilayer structure, the first and second metal materials are alloyed during selective annealing, and after cooling to room temperature, a single crystal of the first metal material and a metal electrode layer of the second metal material are precipitated. The single crystals of the first metal material are spaced apart on the two-dimensional material layer, and the metal electrode layers of each second metal material are in contact with the single crystal of the first metal material corresponding to them. Alternatively, a portion of the second metal material and a portion of the first metal material in each bilayer structure generate an intermetallic compound during selective annealing, and a remaining portion of the second metal material and the intermetallic compound in each bilayer structure, after cooling to room temperature, respectively form a metal electrode layer of the second metal material and a single crystal of the intermetallic compound. The single crystals of the intermetallic compound are spaced apart on the two-dimensional material layer, and the metal electrode layers of each second metal material are in contact with the single crystal of the intermetallic compound corresponding to them.

[0014] The second objective of this invention is to provide a semiconductor device obtained by the aforementioned manufacturing method.

[0015] The semiconductor device of the present invention includes a semiconductor substrate unit, a two-dimensional material layer formed on the semiconductor substrate unit and composed of a transition metal dichalcogenide, two single crystals, and two metal electrode layers. The single crystals are spaced apart on the two-dimensional material layer. Each single crystal is composed of a first metal material or a mesometallic compound composed of the first metal material and a second metal material. The metal electrode layers are composed of the second metal material, and each metal electrode layer contacts its corresponding single crystal. In this invention, the first metal material has a first melting point, and the second metal material has a second melting point, the first melting point being lower than the second melting point.

[0016] The advantage of this invention is that the single crystals of each first metal material or each monometallic compound located on the two-dimensional material layer help to reduce contact resistance and increase current density. Simple Explanation of the Diagram

[0017] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: Figure 1 is a schematic diagram illustrating a conventional semiconductor device disclosed in the early publication number of Republic of China Patent No. TW202109882; Figures 2A to 2D are schematic diagrams illustrating steps (a), (b), (c), and (d) of a first embodiment of the manufacturing method of the semiconductor device of the present invention, respectively. Figures 3A to 3F are schematic diagrams illustrating the detailed process of step (a) of the manufacturing method of the first embodiment of the present invention; Figure 4 is a schematic diagram illustrating the process of implementing step (d) in the manufacturing method of the first embodiment of the present invention and the resulting semiconductor device; Figure 5 is a schematic diagram illustrating a second embodiment of the method for manufacturing a semiconductor device according to the present invention, during the implementation of step (d) and the resulting semiconductor device; Figure 6 is a schematic diagram illustrating a third embodiment of the method for manufacturing a semiconductor device according to the present invention, the process of carrying out step (d), and the resulting semiconductor device; Figure 7 is a Raman spectrum; Figures 8A and 8B are cross-sectional images obtained by transmission electron microscopy (TEM), illustrating the microscopic images of a semiconductor device obtained in a specific example 1 (E1) of the manufacturing method of the present invention; Figure 9 is a cross-sectional image obtained by a high-resolution transmission electron microscope (HRTEM), illustrating a Bi single crystal of the semiconductor device of this specific example (E1) of the present invention; Figure 10A is a current density versus gate voltage (Vg) curve, illustrating a comparison of the transfer characteristics of the semiconductor device of Example 1 (E1) and the semiconductor device of Comparative Example 1 (CE1). Figure 10B is a graph showing the relationship between total resistance (R total) and channel length (L), illustrating a comparison of the electrical characteristics of the semiconductor device of this specific example 1 (E1) and the semiconductor device of this comparative example 1 (CE1), with its y-intercept being twice the contact resistance (2Rc). Figure 11 is a grazing-incidence x-ray diffraction (GIXRD) diagram illustrating the crystal structure of the semiconductor device obtained by the method of the present invention in Example 3 (E3), and the semiconductor devices obtained by the methods of Comparative Example 2 (CE2) and Comparative Example 3 (CE3). Figure 12A is a TEM cross-sectional image illustrating the microscopic image of the semiconductor device obtained by the method of Comparative Example 2 (CE2); Figure 12B is a TEM cross-sectional image illustrating a microscopic image of a semiconductor device obtained by the method of Comparative Example 4 (CE4); Figure 13A is a TEM cross-sectional image with a partially magnified TEM cross-sectional image inserted in the lower right corner, illustrating a microscopic image of a semiconductor device obtained according to a specific example 2 (E2) of the manufacturing method of the present invention; Figure 13B is a magnified cross-sectional image of Figure 13A, illustrating a Bi3Ni single crystal of the semiconductor device of this specific example 2 (E2) of the present invention; Figure 14 is a TEM cross-sectional image illustrating the contact between a Bi contact layer and a MoS2 two-dimensional material layer in the semiconductor device of this specific example 3 (E3) of the present invention; Figure 15A is a graph of drain current versus gate voltage (hereinafter referred to as Id-Vg), illustrating the comparison of the transfer characteristics of the semiconductor device of Comparative Example 2 (CE2) and the semiconductor device of Comparative Example 4 (CE4); Figure 15B is an Id-Vg curve diagram illustrating the comparison of the transmission characteristics of the semiconductor device of Comparative Example 2 (CE2) and the semiconductor device of Specific Example 2 (E2) of the present invention; Figure 15C is an Id-Vg curve, illustrating a comparison of the transmission characteristics of the semiconductor device of Comparative Example 2 (CE2) and the semiconductor device of Specific Example 3 (E3) of the present invention; Figure 16A is a graph showing the relationship between total resistance and channel length, illustrating the contact resistance of the semiconductor device in Comparative Example 2 (CE2); Figure 16B is a graph showing the relationship between total resistance and channel length, illustrating the contact resistance of the semiconductor device in this specific example (E3) of the present invention; Figures 17A and 17B are graphs of drain current density versus gate voltage (Vg), illustrating the comparison of the transfer characteristics of the semiconductor device of Comparative Example 2 (CE2) after undergoing different annealing temperatures; Figures 18A and 18B are graphs of drain current density versus gate voltage (Vg), illustrating the comparison of the transfer characteristics of the semiconductor device of this specific example 3 (E3) after undergoing different annealing temperatures; Figures 19A and 19B are graphs of drain current density versus gate voltage (Vg), illustrating the comparison of the transfer characteristics of the semiconductor device of this specific example 1 (E1) after undergoing different annealing temperatures; Figure 20 is a graph showing the relationship between conduction current density and annealing temperature, obtained from Figures 17, 18, and 19. Figure 21A is a graph of drain current density versus gate voltage (Vg), illustrating a comparison of the transfer characteristics of the semiconductor device in Comparative Example 2 (CE2) and Specific Example 3 (E3) of the present invention; and Figure 21B is a graph of drain current density versus drain voltage (Vd), illustrating the output characteristics of the semiconductor device of this specific example 3 (E3) of the present invention. Implementation

[0018] Before the invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.

[0019] Referring to Figures 2, 3, and 4, a first embodiment of the method for manufacturing the semiconductor device and the product thereof according to the present invention is shown. The method for manufacturing the first embodiment of the present invention includes the following steps: step (a), step (b), step (c), and step (d).

[0020] As shown in Figure 2A, step (a) involves forming a two-dimensional material layer 3 composed of a transition metal dichalcogenide (TMD) on a semiconductor substrate unit 2. The semiconductor substrate unit 2 includes a doped semiconductor substrate 21 and a dielectric layer 22 formed on the doped semiconductor substrate 21. In this first embodiment of the invention, the doped semiconductor substrate 21 and the dielectric layer 22 are illustrated using a heavily phosphorus (P)-doped N-type silicon substrate and a silicon dioxide (SiO2) layer as examples, but are not limited thereto. The TMDs applicable to this first embodiment of the invention can be selected from MoS2, WS2, MoSe2, or WSe2. In this first embodiment of the invention, the TMDs are illustrated using MoS2, an N-type semiconductor material, but are not limited thereto. In detail, the N-type silicon substrate and the silicon dioxide layer are used as a bottom gate and a gate dielectric layer, respectively, of the semiconductor device finally completed by the manufacturing method in the first embodiment of the present invention, while the two-dimensional material layer 3 is used as a channel layer of the semiconductor device.

[0021] In step (a) of the first embodiment of the present invention, the two-dimensional material layer 3 is formed on the semiconductor substrate unit 2 via a wet transfer method as shown in Figures 3A to 3F. Specifically, the two-dimensional material layer 3 is first formed on a sapphire substrate 301 by chemical vapor deposition (CVD) (as shown in Figure 3A). Then, as shown in Figure 3B, a polymethyl methacrylate (PMMA) layer 302 is coated onto the sapphire substrate 301 on which the two-dimensional material layer 3 is formed by spin coating. Subsequently, the sapphire substrate 301 covered with the PMMA layer 302 is immersed in a 1M potassium hydroxide (KOH) aqueous solution 303, allowing the KOH aqueous solution 303 to etch from the periphery of the PMMA layer 302 toward the two-dimensional material layer 3. After the periphery of the PMMA layer 302 detaches from the sapphire substrate 301, the two-dimensional material layer 3 gradually detaches from the sapphire substrate 301 due to surface tension and the buoyancy contributed by the KOH aqueous solution 303 (see Figure 3D). Next, the two-dimensional material layer 3 covered with the PMMA layer 302 is placed in deionized water 304 (see Figure 3E), and then the semiconductor substrate unit 2 is placed in the deionized water 304 to retrieve the two-dimensional material layer 3 covered with the PMMA layer 302 (see Figure 3F). Subsequently, the PMMA layer 302, the two-dimensional material layer 3, and the semiconductor substrate unit 2 are placed on a heating plate (not shown) and dried at 100°C (as shown in Figure 3G). Next, the PMMA layer 302, the two-dimensional material layer 3, and the semiconductor substrate unit 2 are sequentially immersed in acetone at 60°C for 10 minutes to remove the PMMA layer 302 (see Figure 3H), and then immersed in isopropanol (IPA) to remove the acetone, and finally dried with nitrogen (N2) to complete step (a).

[0022] As shown in Figure 2B, step (b) involves forming two spaced-apart lower metal layers 61 on the two-dimensional material layer 3, each composed of a first metal material.

[0023] As shown in Figure 2C, step (c) involves forming an upper metal layer 62 made of a second metal material on each lower metal layer 61, so that each upper metal layer 62 and the lower metal layer 61 form a double-layer structure 6.

[0024] As shown in Figure 2D, step (d) involves selectively annealing the bilayer structures 6 and then cooling them to room temperature. This selective annealing is performed from above the bilayer structures 6 using a laser annealing technique. The laser light used in this technique has a predetermined wavelength range between 800 nm and 1 mm. It should be noted that selective annealing means that the thermal energy of the laser light within the predetermined wavelength range is absorbed by the lower metal layer 61 and the upper metal layer 62 of each bilayer structure 6, but not by the two-dimensional material layer 3. Therefore, during selective annealing, each bilayer structure 6 undergoes a phase transformation due to the thermal energy of the laser light, while the two-dimensional material layer 3, partially covered by each bilayer structure 6, is not damaged by the thermal energy of the laser light.

[0025] In this invention, the first metallic material has a first melting point, and the second metallic material has a second melting point, wherein the first melting point is lower than the second melting point. The first metallic material applicable to this invention is selected from Bi, Sb, In, Sn, or Pb, and the second metallic material is selected from Au, Ni, Pt, Pd, Ti, or Al. However, conditionally, when the first metallic material is Bi or Sn, Al is excluded from the second metallic material; when the first metallic material is Pb, Ni, Ti, and Al are excluded from the second metallic material.

[0026] In some embodiments, the lower metal layer 61 of each double-layer structure 6 has a first thickness between 1 nm and 20 nm, and the upper metal layer 62 of each double-layer structure 6 has a second thickness between 10 nm and 100 nm. In some embodiments, the first thickness of each lower metal layer 61 is between 2 nm and 12 nm, and the second thickness of each upper metal layer 62 is between 35 nm and 75 nm. In this first embodiment of the invention, the first metal material is Bi, and the second metal material is Au.

[0027] Referring to Figure 4, in detail, the first metal material and the second metal material in each double-layer structure 6 are alloyed during the selective annealing process, and after cooling to room temperature, a single crystal 41 of the first metal material (Bi) and a metal electrode layer 5 of the second metal material (Au) are precipitated respectively, thereby obtaining the semiconductor device of the first embodiment of the present invention. The single crystals 41 of the first metal material are spaced apart on the two-dimensional material layer 3, and the metal electrode layers 5 of each second metal material are in contact with their respective single crystals 41 of the first metal material. Thus, it can be seen that each single crystal 41 of the first metal material (Bi) is composed of the first metal material, and each metal electrode layer 5 is composed of the second metal material (Au).

[0028] It should be further explained here that the thickness of the lower metal layer (Bi) 61 in each of the bilayer structures 6 in the first embodiment determines the position of the single crystal precipitated after selective annealing and cooling to room temperature. Specifically, when the first thickness of each lower metal layer 61 is relatively thick, after selective annealing and cooling to room temperature, the single crystal 41 of the first metal material (Bi) tends to precipitate on a periphery and an upper surface of the metal electrode layer 5 of the corresponding second metal material (Au) (as shown in Figure 4). When the first thickness of each lower metal layer 61 is relatively thin, after selective annealing and cooling to room temperature, the single crystal 41 of the first metal material (Bi) tends to precipitate on a lower surface of the metal electrode layer 5 of the corresponding second metal material (Au) to directly contact the two-dimensional material layer 3.

[0029] Referring to Figure 5, a second embodiment of the method for manufacturing the semiconductor device and its product of the present invention is generally the same as the first embodiment, except that the second metal material is Ni. Specifically, a portion of the second metal material and a portion of the first metal material in each double-layer structure 6 are used to form a dielectric metal compound during the selective annealing process. After cooling to room temperature, a remaining portion of the second metal material and the dielectric metal compound respectively form a metal electrode layer 5 of the second metal material and a single crystal 42 of the dielectric metal compound. The single crystals 42 of the dielectric metal compound are spaced apart on the two-dimensional material layer 3, and the metal electrode layer 5 of each second metal material is in contact with its corresponding single crystal 42 of the dielectric metal compound. Thus, each single crystal 42 of the dielectric metal compound is a dielectric metal compound composed of the portion of the first metal material and the portion of the second metal material.

[0030] In detail, each single crystal 42 of the intermetallic compound is Bi 3Ni. Each single crystal 42 of the intermetallic compound has a plurality of Bi 3Ni layers (not shown) stacked along a thickness direction of the two-dimensional material layer 3, and each metal electrode layer 5 of the second metal material is correspondingly formed on an upper surface of each single crystal (Bi 3Ni) 42 of the intermetallic compound.

[0031] Referring to Figure 6, a third embodiment of the method for manufacturing the semiconductor device and its product is generally the same as the second embodiment, except that in step (d), a remaining portion of the first metal material in each double-layer structure 6 forms a Bi contact layer 43 after cooling to room temperature. Each Bi contact layer 43 is sandwiched between the Bi 3Ni layer of the corresponding monometallic compound single crystal 42 and the two-dimensional material layer 3.

[0032] The present invention provides the following comparative and specific examples of the manufacturing methods of these embodiments, and the microstructure and electrical properties of the semiconductor devices obtained by the manufacturing methods thereon.

[0033] <Concrete example 1 (E1)>

[0034] A specific example 1 (E1) of the method for manufacturing the semiconductor device of the present invention is implemented according to the first embodiment. First, a two-dimensional MoS2 material layer of this specific example 1 (E1) is formed on a phosphorus-doped N-type silicon substrate by a wet transfer method. Next, a patterned photoresist layer is formed on the MoS2 two-dimensional material layer on the phosphorus-doped N-type silicon substrate by a photolithography process to partially expose two spaced regions of the MoS2 two-dimensional material layer. Then, a 10 nm Bi layer and a 50 nm Au layer are sequentially deposited on the two regions of the MoS2 two-dimensional material layer exposed outside the patterned photoresist layer by an electron beam evaporation apparatus at an operating pressure of 5 x 10⁻⁶ to 1.2 x 10⁻⁵ torr. Then, the patterned photoresist layer is removed to obtain the two-layer structure of this specific example 1 (E1). Finally, each bilayer structure was selectively annealed using a Coherent® Diamond E-1000 CO2 laser annealing system purchased from Pennsylvania, USA. The selective annealing parameters for this Example 1 (E1) are summarized in Table 1 below. In this Example 1 (E1) of the present invention, the MoS2 two-dimensional material layer is used as a channel layer of the semiconductor device, and the length of the channel layer is 17.0 μm, 3 μm, 6 μm, 9 μm, and 12 μm.

[0035] Table 1 wavelength 10.6μm Scan type Line scan Scan speed 7 cm / sec Laser beam size 12 mm in length 150μm width repetition frequency 10000 Hz Pulse width 10μs Duty cycle 10% Output power 90W

[0036] <Comparative Example 1 (CE1)>

[0037] A comparative example 1 (CE1) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of specific example 1 (E1), except that the selective laser is not performed in comparative example 1 (CE1).

[0038] <Concrete example 2 (E2)>

[0039] A specific example 2 (E2) of the method for manufacturing the semiconductor device of the present invention is implemented according to the second embodiment. In this specific example 2 (E2), before depositing a Bi layer with a double-layer structure, a shutter of the electron beam evaporation apparatus is used to shield the underside of a MoS2 two-dimensional material layer. Specifically, after the shutter shields the underside of the MoS2 two-dimensional material layer, the power supply of an electron gun in the electron beam evaporation apparatus is turned on to generate an electron beam that bombards a Bi bulk material in a crucible, causing a bismuth oxide (BiOx) film formed on a surface of the Bi bulk material to deposit on the shutter. After the bismuth oxide film on the surface of the Bi bulk material is completely ejected, the shutter is removed, allowing the Bi bulk material to continue being bombarded by the electron beam, thereby depositing a 10 nm Bi layer on the MoS2 two-dimensional material layer. This avoids the deposition of a BiOx layer on the MoS2 two-dimensional material layer in this specific example 2 (E2) that would affect electrical performance. Next, a 30 nm Ni layer was deposited on the Bi layer in Example 2 (E2). Finally, selective annealing of Example 2 (E2) was performed with selective annealing parameters that were substantially the same as those in Example 1 (E1). The output power and scan speed of Example 2 (E2) during selective annealing were 80 W and 5 cm / sec, respectively. In Example 2 (E2) of the present invention, the MoS2 two-dimensional material layer is used as a channel layer of the semiconductor device, and the length of the channel layer is 3.0 μm, 150 nm, 200 nm, 300 nm, and 500 nm.

[0040] <Concrete example 3 (E3)>

[0041] A specific example 3 (E3) of the method for manufacturing the semiconductor device of the present invention is implemented according to the third embodiment and is substantially the same as that of specific example 2 (E2), except that the scan speed during selective annealing in specific example 3 (E3) is 7 cm / sec.

[0042] <Comparative Example 2 (CE2)>

[0043] A comparative example 2 (CE2) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of specific example 2 (E2), except that the selective annealing is not performed in comparative example 2 (CE2).

[0044] Comparative Example 3 (CE3)

[0045] Comparative Example 3 (CE3) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of Specific Example 2 (E2), except that Comparative Example 3 (CE3) uses a rapid thermal annealing (RTA) technique instead of selective annealing. In Comparative Example 3 (CE3), the RTA technique involves heating to 400°C at a heating rate of 10°C / sec for 60 seconds.

[0046] <Comparative Example 4 (CE4)>

[0047] A comparative example 4 (CE4) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of comparative example 3 (CE3), except that comparative example 4 (CE) is heated to 300°C for 30 seconds when performing an RTA technique.

[0048] <Concrete example 4 (E4)>

[0049] A specific example 4 (E4) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of specific example 2 (E2), except that a 50 nm Au layer is deposited on a Bi layer.

[0050] As shown in Figure 7, the Raman spectra reveal that the signal peak positions of the MoS2 two-dimensional material layer in Comparative Example 1 (CE1) are similar to those in Specific Example 1 (E1). This indicates that the MoS2 two-dimensional material layer in Specific Example (E1) was not damaged by CO2 laser after selective annealing, hence the similarity in signal peak positions between the two-dimensional MoS2 material layers in Specific Example (E1) and Comparative Example 1 (CE1).

[0051] As shown in the TEM cross-sectional image in Figure 8 and the HRTEM cross-sectional image in Figure 9, after selective annealing, the Bi in the bilayer structure of Example 1 (E1) is precipitated on the side (see Figure 8A) and top surface (see Figure 8B) of Au, and the precipitated Bi is a single crystal (see Figure 9). It should be noted that the Bi and Au shown in the TEM cross-sectional images (Figure 8A, Figure 8B) were obtained by analysis using an energy dispersive spectrometer (EDS) configured in a TEM apparatus.

[0052] Furthermore, as shown by the electrical data in Figure 10A, the current density of this specific example 1 (E1) is approximately 42% higher than that of the comparative example 1 (CE1).

[0053] The Id-Vg curves (not shown in the figure, only the Id-Vg curve of the semiconductor device with a channel length of 17 μm is shown in Figure 10A) and Id-Vd curves (not shown in the figure) of the semiconductor devices of Specific Example 1 (E1) and Comparative Example 1 (CE1) are shown in Figure 10B. The contact resistance (Rc) obtained by the transfer length method (TLM) is shown in Figure 10B. The carrier concentration required for TLM is 8.64 x 10 12 / cm 2. As can be seen from Figure 10B, the contact resistance (Rc) of Comparative Example 1 (CE1) is as high as 46.5 kΩ·μm, while the contact resistance (Rc) of Specific Example 1 (E1) is only 35 kΩ·μm.

[0054] Figure 11 shows the GIXRD diagrams of the present invention, the comparative example 3 (E3), the comparative example 2 (CE2), and the comparative example 3 (CE3); wherein, the incident angle of an X-ray incident on the present invention, the comparative example 2 (E2), the comparative example 2 (CE2), and the comparative example 3 (CE3) is set to 0.5 degrees. As shown in Figure 11, Comparative Example 2 (CE2), which did not undergo selective annealing, only showed diffraction peaks of Ni, indicating that Comparative Example 2 (CE2) only contained Ni crystalline phase. Comparative Example 3 (CE3), which underwent RTA at 400°C for 60 seconds, showed diffraction peaks of both Ni and BiNi, indicating that Comparative Example 3 (CE3) contained both Ni and BiNi crystalline phases. In contrast, Specific Example 3 (E3), which underwent selective annealing at a scan speed of 7 cm / min and an output power of 80 W, only showed diffraction peaks of Bi3Ni, indicating that the bilayer structure of Specific Example 3 (E3) underwent phase transformation into Bi3Ni crystalline phase after CO2 laser annealing.

[0055] As shown in the TEM cross-sectional image in Figure 12A, Comparative Example 2 (CE2) has Bi and Ni sequentially stacked on SiO2. As shown in the TEM cross-sectional image in Figure 12B, Comparative Example 4 (CE4) has BiNi and Ni sequentially stacked on a MoS2 two-dimensional material layer on SiO2. It should be noted that when the inventors took the TEM cross-sectional image of the semiconductor device of Comparative Example 2 (CE2), they did not capture the area showing the MoS2 two-dimensional material layer. Therefore, the MoS2 two-dimensional material layer of the semiconductor device of Comparative Example 2 (CE2) is not shown in Figure 12A, and this will be explained here as well.

[0056] Further, as shown in the TEM cross-sectional images in Figures 13A and 13B, in Example 2 (E2), selective annealing was performed at a scan speed of 5 cm / min and an output power of 80 W, a Bi3Ni single crystal composed of multiple Bi3Ni layers was sequentially stacked on a MoS2 two-dimensional material layer. Calculations show that the spacing between two adjacent Bi3Ni layers in the Bi3Ni single crystal of Example 2 (E2) is approximately 0.242 nm. Furthermore, as shown in the TEM cross-sectional image in Figure 14, in Example 3 (E3), selective annealing was performed at a scan speed of 7 cm / min and an output power of 80 W, Bi and a Bi3Ni single crystal composed of multiple Bi3Ni layers were sequentially stacked on a MoS2 two-dimensional material layer. Figures 13A, 13B, and 14 show that in Example 2 (E2), where selective annealing was performed at a slower scan rate (5 cm / min), the Bi in the bilayer structure completely formed the Bi 3Ni single crystal with Ni. In contrast, in Example 3 (E3), where selective annealing was performed at a faster scan rate (7 cm / min), the Bi in the bilayer structure only partially formed the Bi 3Ni single crystal with Ni, leaving residual Bi in contact with the MoS 2 two-dimensional material layer. It is worth noting that the melting point of the Bi 3Ni single crystals formed after CO 2 laser annealing in Examples 2 (E2) and 3 (E3) is higher than that of Bi in Comparative Example 2 (CE2). Therefore, it can be inferred that the semiconductor devices of Examples 2 (E2) and 3 (E3) have higher thermal stability than Comparative Example 2 (CE2). The results of the thermal stability and electrical performance tests of the semiconductor devices of the present invention will be described later. Similarly, Ni, Bi, BiNi, Bi3Ni and MoS2 shown in the TEM cross-sectional images (Fig. 12A, Fig. 12B, Fig. 13A and Fig. 14) were obtained through TEM-EDS analysis.

[0057] The carrier mobility (µFE) of the semiconductor device (BiNi contact) in Comparative Example 4 (CE4) decreased from 12.8 cm² / V·s to 8.3 cm² / V·s (see Figure 15A) as shown in the electrical analysis results of Figures 15A, 15B, and 15C. Similarly, in the semiconductor device (Bi₃Ni contact) of Specific Example 2 (E2), a decrease in µFE from 14.3 to 10.1 cm² / V·s was observed (see Figure 15B). In contrast, the semiconductor device (Bi₃Ni / Bi contact) of Specific Example 3 (E3) exhibited a stable mobility, maintaining a similar value between 19.5 and 20.3 cm² / V·s (see Figure 15C).

[0058] The contact resistance (Rc) obtained by TLM calculation for the Id-Vg curves (not shown in the figures, only the Id-Vg curve for the 500 nm channel length is shown in Figure 15C) and Id-Vd curves (not shown in the figures) corresponding to each channel length of the semiconductor devices of Specific Example 3 (E3) and Comparative Example 2 (CE2) is shown in Figures 16A and 16B, respectively; wherein the carrier concentration required for TLM is 1.43 x 10 13 / cm 2. As can be seen from Figures 16A and 16B, the contact resistance (Rc) of Comparative Example 2 (CE2) and Specific Example 3 (E3) is similar, at 177 Ω·μm and 174 Ω·μm, respectively.

[0059] The thermal stability and electrical properties test results of the semiconductor devices of Comparative Example 2 (CE2), Specific Example 3 (E3), and Specific Example 1 (E1) are shown in Figures 17, 18, and 19, respectively. Specifically, the semiconductor devices of Comparative Example 2 (CE2), Specific Example 3 (E3), and Specific Example 1 (E1) were each subjected to a 5-minute RTA at different temperatures within a temperature range of 200°C to 500°C in a nitrogen atmosphere, and then an IV measurement was performed after each heating cycle.

[0060] As shown in Figures 17A and 17B, the slope of the linear region of the Id-Vg curve of the semiconductor device of Comparative Example 2 (CE2) at a source voltage (hereinafter referred to as VDS) of 1V decreases as the RTA temperature increases. This indicates that the contact resistance (Rc) of the semiconductor device of Comparative Example 2 (CE2) increases with the RTA temperature. Furthermore, Figure 17A also shows that after one RTA at 400°C, the on / off ratio of the semiconductor device of Comparative Example 2 (CE2) drops to below one order of magnitude, indicating that the electrical properties of Comparative Example 2 (CE2) have significantly decreased after the RTA at 400°C.

[0061] As shown in Figures 18A and 18B, although the slope of the linear region of the Id-Vg curve of the semiconductor device of Example 3 (E3) decreases with increasing RTA temperature, the slope of the linear region of the Id-Vg curve remains stable when the RTA temperature reaches 300°C. Even after a single RTA at 500°C, the semiconductor device of Example 3 (E3) maintains an on / off ratio of four orders of magnitude (see Figure 18A). This confirms that the Bi3Ni single crystal in the semiconductor device of Example 3 (E3) of the present invention provides excellent thermal stability for its electrical performance.

[0062] As shown in Figures 19A and 19B, the slope of the linear region of the Id-Vg curve obtained by the semiconductor device of Example 1 (E1) under the condition of VDS being 1V decreases significantly with the increase of RTA temperature. Figure 19A also shows that after one RTA at 350°C, the on / off ratio of the semiconductor device of Example 1 (E1) is less than an order of magnitude.

[0063] As shown in Figure 20, the semiconductor device of Example 3 (E3) of the present invention, after undergoing RTA at 200°C, 250°C and 300°C in sequence, still maintains a conduction current density of about 2.5 μA / μm without showing a decreasing trend. In contrast, the semiconductor devices of Comparative Example 2 (CE2) and Example 1 (E1), after undergoing RTA at 200°C, 250°C and 300°C in sequence, retain only about 50% and 21% of the conduction current density, respectively.

[0064] As shown in Figure 21A, the carrier mobility and conduction current density of Comparative Example 2 (CE2) without selective annealing and Specific Example 3 (E3) with selective annealing performed at a scan speed of 7 cm / min and an output power of 80 W are similar. It is noteworthy that the critical voltage (Vth) and sub-threshold swing (SS) of Comparative Example 2 (CE2) without selective annealing are -4.7 V and 1680 mV / dec, respectively. After selective annealing at a scan speed of 7 cm / min and an output power of 80 W (i.e., Specific Example 3 (E3)), the critical voltage (Vth) and SS shift positively to -0.7 V and decrease to 1020 mV / dec, respectively. This can be attributed to the selective annealing of Specific Example 3 (E3). Furthermore, as shown in Figure 21B, the output characteristics of the semiconductor device of Specific Example 3 (E3) of the present invention exhibit clear ohmic contact behavior at gate voltages between 0 V and 35 V.

[0065] In summary, the method for manufacturing the semiconductor device and its products of the present invention, by means of the single crystals 41 of each first metal material (Bi) located on the two-dimensional material layer 3, can help reduce the contact resistance (Rc) and increase the current density, and the single crystals (Bi 3Ni) 42 of each dielectric metal compound can also help improve the thermal stability of the semiconductor device, thus achieving the purpose of the present invention.

[0066] However, the above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification of the present invention shall still fall within the scope of the patent of the present invention.

[0067] 1: Traditional semiconductor devices 11:Substrate 12: Semiconductor two-dimensional material layer 12C: Passage Area 12D: Drain Zone 12S: Source Region 13D: Drain film structure 131D: Conductive two-dimensional material layer 132D: Separated metal layer 133D: Electrode metal layer 13S: Source film structure 131S: Conductive two-dimensional material layer 132S: Separated Metal Layer 133S: Electrode metal layer 2: Semiconductor substrate unit 21: Doped semiconductor substrate 21 22: Dielectric layer 3: Two-dimensional material layer 301: Sapphire substrate 302: PMMA layer 303: KOH aqueous solution 304: Deionized water 41: Single crystal of the first metallic material 42: Single crystals of mesometallic compounds 43:Bi contact layer 5: Metal electrode layer 6: Double-layer structure 61: Lower metal layer 62: Upper metal layer

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: a step (a) forming a two-dimensional material layer composed of a transition metal dichalcogenide on a semiconductor substrate unit; a step (b) forming two lower metal layers spaced apart from each other and composed of a first metal material on the two-dimensional material layer; a step (c) forming an upper metal layer composed of a second metal material on each of the lower metal layers, so as to form a bilayer structure with each of the lower metal layers; and a step (d) subjecting the bilayer structure to selective annealing and then cooling it to room temperature; wherein, The first metallic material has a first melting point, and the second metallic material has a second melting point, the first melting point being lower than the second melting point; wherein, in each bilayer structure, the first metallic material and the second metallic material are alloyed during the selective annealing process, and after cooling to room temperature, a single crystal of the first metallic material and a metal electrode layer of the second metallic material are precipitated respectively, the single crystals of the first metallic material being spaced apart on the two-dimensional material layer, and the metal electrode layer of each second metallic material being in contact with the single crystal of the corresponding first metallic material; or wherein, a portion of the second metallic material and a portion of the first metallic material in each bilayer structure generate a dielectric metal compound during the selective annealing process, and a remaining portion of the second metallic material and the dielectric metal compound in each bilayer structure, after cooling to room temperature, respectively form a metal electrode layer of the second metallic material and a single crystal of the dielectric metal compound, the single crystals of the dielectric metal compound being spaced apart on the two-dimensional material layer, and the metal electrode layer of each second metallic material being in contact with the single crystal of the corresponding dielectric metal compound.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein, The first metallic material is selected from Bi, Sb, In, Sn, or Pb, and the second metallic material is selected from Au, Ni, Pt, Pd, Ti, or Al. However, under certain conditions, when the first metallic material is Bi or Sn, the second metallic material excludes Al; when the first metallic material is Pb, the second metallic material excludes Ni, Ti, and Al.

3. The method of manufacturing a semiconductor device as described in claim 2, wherein, The first metallic material is Bi, and the second metallic material is Au or Ni.

4. A method for manufacturing a semiconductor device as described in claim 2, wherein, The first metallic material is Bi, the second metallic material is Ni, each single crystal of the intermetallic compound is Bi 3Ni, each single crystal of the intermetallic compound has a plurality of Bi 3Ni layers stacked along a thickness direction of the two-dimensional material layer, and each metal electrode layer of the second metallic material is respectively formed on an upper surface of each single crystal of the intermetallic compound.

5. A method for manufacturing a semiconductor device as described in claim 4, wherein, In step (d), a remaining portion of the first metallic material in each bilayer structure forms a Bi contact layer after cooling to room temperature. Each Bi contact layer is sandwiched between the Bi 3Ni layer of the corresponding monometallic compound single crystal and the two-dimensional material layer.

6. A method for manufacturing a semiconductor device as claimed in claim 1, wherein, Each double-layer structure has a lower metal layer with a first thickness between 1 nm and 20 nm.

7. A method for manufacturing a semiconductor device as claimed in claim 1, wherein, Each double-layer structure has an upper metal layer with a second thickness between 10 nm and 100 nm.

8. A method for manufacturing a semiconductor device as claimed in claim 1, wherein, The selective annealing is a laser annealing technique performed from above one of the bilayer structures, wherein the laser light of the laser annealing technique has a predetermined wavelength range between 800 nm and 1 mm.

9. A method for manufacturing a semiconductor device as claimed in claim 1, wherein, The semiconductor substrate unit includes a doped semiconductor substrate and a dielectric layer formed on the doped semiconductor substrate.

10. A semiconductor device comprising: a semiconductor substrate unit; a two-dimensional material layer formed on the semiconductor substrate unit and composed of a transition metal dichalcogenide; two single crystals spaced apart on the two-dimensional material layer, each single crystal being composed of a first metal material or a mesometallic compound composed of the first metal material and a second metal material; and two metal electrode layers composed of the second metal material, each metal electrode layer contacting its corresponding single crystal; wherein... The first metallic material has a first melting point, and the second metallic material has a second melting point, wherein the first melting point is lower than the second melting point.

11. The semiconductor device as claimed in claim 10, wherein, The first metallic material is selected from Bi, Sb, In, Sn, or Pb, and the second metallic material is selected from Au, Ni, Pt, Pd, Ti, or Al. However, under certain conditions, when the first metallic material is Bi or Sn, the second metallic material excludes Al; when the first metallic material is Pb, the second metallic material excludes Ni, Ti, and Al.

12. The semiconductor device as claimed in claim 11, wherein, The first metallic material is Bi, and the second metallic material is Au or Ni.

13. The semiconductor device as claimed in claim 11, wherein, The first metallic material is Bi, the second metallic material is Ni, each single crystal of the intermetallic compound is Bi 3Ni, each single crystal has a plurality of Bi 3Ni layers stacked along a thickness direction of the two-dimensional material layer, and each metal electrode layer of the second metallic material is respectively formed on an upper surface of each single crystal of the intermetallic compound.

14. The semiconductor device of claim 13 further comprises two Bi contact layers, each Bi contact layer being sandwiched between a Bi3Ni layer of a corresponding monometallic compound single crystal and the two-dimensional material layer.

15. The semiconductor device as claimed in claim 10, wherein, The semiconductor substrate unit includes a doped semiconductor substrate and a dielectric layer formed on the doped semiconductor substrate.

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