Flattening resistor and manufacture method thereof

Abstract

This invention provides a planarized resistive element and its manufacturing method, which includes a substrate, a resistive layer and an electrode layer. This invention solves the problems of increased impedance and abnormal product characteristics caused by improper bonding at the interface between the electrode layer and the resistive layer. It includes eliminating the height difference at the interface and handling the discontinuous structure of the electrode layer contour by using laser or grinding after the electrode layer manufacturing process is completed.

Description

Technical Field

[0001] This invention relates to a resistive element and its manufacturing method, particularly a flattened resistive element and its manufacturing method that maintains a stable impedance under long-term energization. Prior Technology

[0002] Sputtering is a physical vapor deposition technique. In the manufacturing process of thin film resistors, sputtering uses electricity to deposit sputtered target material atoms or molecules onto semiconductor wafers, glass, or ceramics through a metal mask to form a thin film of a specific shape.

[0003] The sputtering process generates a large amount of heat, causing the mask to expand due to heat exposure. This expansion causes the pattern on the mask to deviate from its relative position on the substrate. This pattern misalignment can lead to overspraying of the target material during sputtering, affecting dimensional stability.

[0004] Due to the characteristics of traditional printing technology, uneven thickness and excessive height differences occur in the contact area between the electrode layer and the resistive layer, which hinders electron migration and further increases impedance.

[0005] In addition, the printing technology can also cause excess material to be splashed at the edges of the printed layer, resulting in discontinuities in the electrode layer contour structure, uneven current distribution, and complex current paths.

[0006] The three situations described above can cause the performance of the resistor to become unstable, thereby affecting the consistency and reliability of the product. Furthermore, they can cause localized overheating, further impacting the reliability of the component and potentially leading to a decrease in the thermal stability of the resistor. Summary of the Invention

[0007] To address the aforementioned problems, this invention provides a planarized resistive element and its manufacturing method, thereby resolving the issue of uneven height differences in the contact area between the electrode layer and the resistive layer of conventional resistors. This unevenness hinders electron migration and further increases current impedance. In such cases, the performance of the resistive element becomes unstable, affecting product consistency and reliability. Furthermore, it can cause localized overheating, further impacting element reliability and potentially leading to a decrease in the resistor's thermal stability.

[0008] This invention provides a method for manufacturing a planarized resistive element, comprising:

[0009] Form a substrate;

[0010] An electrode layer is formed at both ends of the substrate;

[0011] A truncated concave platform is formed on one surface of the electrode layer by laser or grinding;

[0012] A resistive layer is formed, covering the chamfered platform of the electrode layer; and

[0013] A protective layer is formed on the resistive layer.

[0014] Preferably, the length of the chamfered recess of the electrode layer is less than or equal to half the length of the electrode layer.

[0015] Preferably, the chamfered concave platform has a chamfer angle of 40° to 120°.

[0016] Preferably, the average roughness of a centerline of a surface of the chamfered concave platform is 0.1 nm to 10 μm.

[0017] Furthermore, the present invention provides a flattened resistive element comprising:

[0018] One substrate;

[0019] An electrode layer is disposed at both ends of the substrate, and the electrode layer has a truncated corner recess.

[0020] A resistive layer is disposed on the surface of the substrate, and the resistive layer is connected to the electrode layer; and

[0021] A protective layer is disposed on the resistive layer, exposing the electrode layer.

[0022] Preferably, the length of the chamfered recess of the electrode layer is less than or equal to half the length of the electrode layer.

[0023] Preferably, the chamfered concave platform has a chamfer angle of 40° to 120°.

[0024] Preferably, the average roughness of a centerline of a surface of the chamfered recess of the electrode layer is 0.1 nm to 10 μm.

[0025] The electrode layer of the present invention is provided with a chamfered recess, which improves the flatness, thickness consistency and bonding stability of the contact surface between the electrode layer and the resistor layer. It solves the technical problems of uneven current distribution, complex current path, local overheating, and easy deformation and poor contact under long-term energization caused by the height difference of the junction surface and discontinuous electrode layer contour structure in conventional resistors. This reduces the impedance change rate of the resistor element under long-term energization and improves the consistency, reliability and thermal stability of the product. Simple Explanation of the Diagram

[0026] Figure 1 is a top view of the planarized resistive element of the present invention. Figures 2 to 5 are schematic diagrams illustrating the manufacturing process of the planarized resistive element of the present invention. Figure 6 is a magnified view of area A in Figure 1. Figure 7 is a flowchart of the manufacturing method of the planarized resistive element of the present invention. Implementation

[0027] The following detailed description of various embodiments of the present invention, accompanied by accompanying drawings, will facilitate a better understanding by the reader. In addition to these detailed descriptions, the present invention can be widely implemented in other embodiments. Any easy substitutions, modifications, or equivalent changes to the described embodiments should be understood to be included within the scope of the present invention, and the patent scope should be defined by the scope of the patent application. It should be noted that the drawings are for illustrative purposes only and do not represent the actual size or quantity of the components; some details may not be fully depicted for the sake of simplicity.

[0028] For the sake of simplicity, a rectangular resistor is used as an example, but it should be understood that it is used as an example and not to limit the invention. The flattened resistor element of the present invention can be implemented in any shape.

[0029] Please refer to Figures 1 to 6. Figure 1 is a top view of the planarized resistor element of the present invention, Figures 2 to 5 are schematic diagrams of the manufacturing process of the planarized resistor element of the present invention, and Figure 6 is a partial enlarged view of area A in Figure 1.

[0030] The planarized resistive element 1 of the present invention comprises a substrate 10, an electrode layer 20, a resistive layer 30 and a protective layer 40.

[0031] Step S01, as shown in Figure 2, involves setting a substrate 10 and printing electrode layers 20 on both ends of the substrate 10 to form two electrodes.

[0032] Step S02, as shown in Figure 3, involves laser or grinding to prepare the surface of the electrode layer 20, forming a chamfered recess 50. The length of the chamfered recess 50 is less than or equal to half the length of the electrode layer, ensuring that the highest point of the electrode layer remains unchanged, thus preventing overspray. The surface roughness Ra of the prepared electrode layer is less than 1 μm. The electrode layer is made of an alloy, which may consist of metals such as titanium, copper, aluminum, nickel, gold, carbon, and silicon.

[0033] The chamfered recess 50 has a chamfer angle θ of 40°~120°, the distance between the chamfered recess 50 and the surface of the electrode layer 20 has a first step difference D1 of 0.1μm~20μm, the distance between the chamfered recess 50 and the surface of the substrate 10 has a second step difference D2 of 0.1μm~10μm, and the average roughness (Ra) of the centerline of the surface of the chamfered recess 50 is 0.1nm~10μm.

[0034] Step S03, as shown in Figure 4, involves sputtering a resistive layer 30 onto the substrate 10 and the electrode layer 20. The resistive layer 30 covers the substrate 10 and the chamfered recess 50 of the electrode layer 20. The thickness of the resistive layer 30 is less than or equal to the first step difference D1 of the chamfered recess 50, and the first step difference D1 is greater than the second step difference D2 of the chamfered recess 50. The resistive layer 30 contacts the side and top surfaces of the chamfered recess 50 to increase the contact surface area between the resistive layer 30 and the electrode layer 20, preventing oversputtering of the resistive layer 30 and ensuring a consistent thickness in the contact area between the resistive layer 30 and the electrode layer 20. This avoids uneven thickness, which can lead to thermal deformation and warping of the resistive layer 30 during energization, resulting in excessive height differences in the contact area, hindering electron migration and increasing impedance. The resistive layer is made of a sputtered alloy, which may be composed of metals such as titanium, copper, aluminum, nickel, gold, carbon, and silicon.

[0035] In step S04, as shown in Figure 5, a protective layer 40 is printed onto the resistive layer 30 and then cured. The total thickness of the protective layer 40 and the resistive layer 30 is greater than or equal to the first segment difference D1 of the chamfered recess 50. The material of the protective layer 40 can be epoxy resin or a mixture of epoxy resins.

[0036] Please refer to Figure 7, which is a flowchart of the manufacturing method of the planarized resistive element of the present invention.

[0037] In Figure 7, region A is the boundary area between the resistive layer 30 and the electrode layer 20. The resistive protrusion 70 on region A is a protrusion formed due to the obstruction of the chamfered recess 50 during the sputtering process, so that the resistive layer 30 and the electrode layer 20 are completely attached, maintaining the consistency of the contours of the electrode layer 20 and the resistive layer 30.

[0038] The printing, laser, grinding, sputtering and curing processes used in this invention can be performed using conventional techniques to achieve the same effect. For the sake of brevity, this invention will not be described in detail.

[0039] [Example 1]: Impedance value detection

[0040] To test the effect of the flattened resistor element of the present invention, a conventional resistor lacking the technical features of the present invention was used as the control group, and the flattened resistor element of the present invention was used as the experimental group. The change in impedance value was tested at the initial energization (i.e., without changing any conditions). The experimental results are shown in Table 1. The flattened resistor element of the present invention can suppress the impedance change rate to 0.01%~1%. [Table 1] Impedance detection Minimum impedance (KΩ) Maximum impedance (KΩ) Impedance change rate Initial power-on (No conditions changed) Known resistance 100 198 98% Flattening resistor 100 101 1%

[0041] [Example 2]: Resistance measurement during prolonged power supply

[0042] To test the effect of the flattened resistor element of the present invention, the present invention was used as the experimental group, and a conventional resistor lacking the flattened resistor of the present invention was used as the control group. The change in resistance value was tested under a 1000-hour power-on life test. The experimental results are shown in Table 2. The flattened resistor element of the present invention can suppress the resistance change rate to 0.05%. [Table 2] Life test Minimum resistance (KΩ) Maximum resistance (KΩ) Resistance change rate 1000 hours of power supply Known resistance 100 110 10% Flattening resistor 100 100.05 0.05%

[0043] As can be seen from the above experimental results, the flattened resistor element of the present invention can effectively reduce the instability of the resistance value. Its impedance change rate and resistance value change rate after 1000 hours of energization are 0.01%~1% and 0.05%, respectively. Compared with the conventional resistors which are 98% and 10%, the resistance value stability is significantly improved. Therefore, it is proven that the present invention can prevent the resistance value from being unstable and maintain high resistance value accuracy and reliability under high temperature and long-term operation.

[0044] The electrode layer of the present invention is provided with a chamfered recess, which improves the flatness, thickness consistency and bonding stability of the contact surface between the electrode layer and the resistor layer. It solves the technical problems of uneven current distribution, complex current path, local overheating, and easy deformation and poor contact under long-term energization caused by the height difference of the junction surface and discontinuous electrode layer contour structure in conventional resistors. This reduces the impedance change rate of the resistor element under long-term energization and improves the consistency, reliability and thermal stability of the product.

[0045] 1: Flattened resistor element 10:Substrate 20: Electrode layer 30: Resistive layer 40: Protective layer 50: Chamfered concave platform 60: Boundary area 70: Resistance protrusion A: Border area D1: First segment difference D2: Second segment difference S01~S06: Steps θ: tangent

Claims

1. A method for manufacturing a planarized resistive element, comprising: forming a substrate; forming an electrode layer at both ends of the substrate; forming a chamfered recess on a surface of the electrode layer by laser or grinding, wherein the average roughness of a center line of a surface of the chamfered recess is 0.1 nm to 10 μm; forming a resistive layer covering the chamfered recess of the electrode layer; and forming a protective layer on the resistive layer.

2. The manufacturing method as described in claim 1, wherein the length of the chamfered recess of the electrode layer is less than or equal to half the length of the electrode layer.

3. The manufacturing method as described in claim 1, wherein the chamfered recess has a chamfer angle of 40° to 120°.

4. A planarized resistive element, comprising: a substrate; an electrode layer disposed at both ends of the substrate, the electrode layer having a chamfered recess, the average roughness of a center line of a surface of the chamfered recess being 0.1 nm to 10 μm; a resistive layer disposed on the surface of the substrate, the resistive layer being connected to the electrode layer; and a protective layer disposed on the resistive layer and exposing the electrode layer.

5. The planarized resistive element as claimed in claim 4, wherein the length of the chamfered recess of the electrode layer is less than or equal to half the length of the electrode layer.

6. The flattened resistive element as claimed in claim 4, wherein the chamfered recess has a chamfer angle of 40° to 120°.

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