Inductors for an integrated circuit

Abstract

An inductor for an integrated circuit may include a conductive trace and one or more magnetic films surrounding a top, a bottom, and a side of the conductive trace. The one or more magnetic films may include one or more trenches along a first path and one or more trenches along a second path to form a plurality of segments of the magnetic films, the first path being directly above a length of the conductive trace and the second path being directly above a width of the conductive trace. In some embodiments, one or more multilayer stacks may surround a top, a bottom, and a side of the conductive trace. Other embodiments are also described and claimed in this invention.

Description

Technical Field

[0001] The present disclosure relates generally to inductors for integrated circuits, and more particularly to inductors including conductive traces and magnetic films for use in radio frequency integrated circuits. Prior Art

[0002] An inductor is a passive component that stores energy in a magnetic field based on the flow of current. An inductor can consist of a conductive trace with two terminals and can have a shape that forms an open loop or a coil. Inductors are used in radio frequency (RF) integrated circuits (ICs) to implement filters, impedance matching networks, resonators, couplers, and other circuitry components. For example, some ICs utilize inductors in circuitry to implement mobile networking technologies.

[0003] One measure of inductor efficiency is the inductor's quality factor (or Q factor). An inductor's Q factor typically refers to the ratio of inductive reactance to resistance at a given frequency. The Q factor can be a measure of efficiency, with a higher Q factor behaving more like an ideal inductor. Summary of the Invention

[0004] Embodiments of the present disclosure include wrapping a conductive trace of an inductor with one or more magnetic films having grooves (e.g., dielectric spacers) in multiple directions. The grooves may form segments (e.g., islands or blocks) of the magnetic film that surround the conductive trace in three dimensions. Some embodiments may include an inductor for an RF IC. The inductor may include a conductive trace and one or more magnetic films, comprising one or more layers of magnetic film alternating with one or more layers of dielectric. The conductive trace may have two terminals and form an open loop or coil. The one or more magnetic films may wrap around the top, bottom, and sides of the conductive trace. The one or more magnetic films may include one or more grooves along a first path directly over a length of the conductive trace and one or more grooves along a second path to form the segments, the first path directly over a width of the conductive trace. The grooves of the one or more magnetic films may completely pass through the one or more magnetic films between the segments. In some embodiments, one or more multilayer stacks comprising the one or more magnetic films may wrap around a top, a bottom, and a side of the conductive trace. The one or more multilayer stacks may be formed into a laminate in a lamination process. The one or more multilayer stacks may include magnetic film layers separated from each other by dielectric layers. The multilayer stacks may also include one or more grooves along a path directly over a length or a width of the conductive trace to form multiple sections of the one or more multilayer stacks. Other aspects are also described and claimed.

[0005] The above summary does not constitute an exhaustive list of all aspects of the present disclosure. It is contemplated that the present disclosure includes all systems and methods that can be implemented from all suitable combinations of the various aspects summarized above, as well as those disclosed in the detailed description below and specifically noted in the claims section. Such combinations may have particular advantages not specifically listed in the above summary. Simple diagram description

[0006] Several aspects of the present disclosure are illustrated herein by way of example and not limitation in the accompanying figures, where like reference numbers indicate like elements. It should be noted that references to "an" or "one" aspect in this disclosure do not necessarily refer to the same aspect, and such references mean at least one. Furthermore, for the sake of brevity and to reduce the total number of figures, a given figure may be used to illustrate features of more than one aspect of the present disclosure, and not all elements shown in a figure may be required for a given aspect. [ FIG. 1 ] An example of an inductor including conductive traces and one or more magnetic films having grooves according to an embodiment. FIG2 is an example of a top view of the inductor of FIG1 . FIG3 is an example of a side view of the inductor of FIG1 . FIG4 is an example of a close-up top view of the inductor of FIG1 . FIG5 is an example of a close-up side view of the inductor of FIG1. [FIGS. 6A] to [FIGS. 6F] are examples of inductors including one or more conductive traces and one or more multilayer stacks according to embodiments. 7A to 7E are examples of top view and side view patterns of conductive traces of an inductor including a magnetic film having grooves according to an embodiment, and FIG. 7F is an example of top view and side view patterns of conductive traces of a reference inductor without a magnetic film. FIG. 8 shows an example of an inductor formed in a back-end-of-the-line build-up structure according to an embodiment. [ FIG. 9 ] An example of an inductor formed in a grain-level redistribution layer according to an embodiment. [Fig. 10] An example of thin film production according to an embodiment. [ Fig. 11 ] An example of dual damascene manufacturing according to an embodiment. [ FIG. 12 ] An example of an inductor formed in a package-level redistribution layer according to an embodiment. [ FIG. 13 ] An example of an inductor including discrete integrated passive devices coupled to discrete dies according to an embodiment. Implementation Method

[0007] To improve radio frequency (RF) integrated circuits (ICs), for example, to implement fifth-generation (5G) mobile network technology, inductors with higher inductance density and a higher quality factor (or Q factor) occupying a smaller area are desired. However, many IC inductors suffer from low inductance per unit area and high losses (quantified by a low Q factor). To overcome these limitations, monolithic integration of IC-compatible metallic ferromagnetic films can be utilized. These films comprise thin layers of magnetic material with high magnetic permeability. Designing the shape, size, and thickness of the magnetic film can enhance the performance of the inductor, and consequently, the circuit.

[0008] However, high energy dissipation caused by parasitic eddy currents in the metallic ferromagnetic layer and a limited operating frequency range due to ferromagnetic resonance can limit inductor performance. For example, while using thicker magnetic films can increase inductance, increasing the thickness of the magnetic film can also reduce the inductor's Q factor due to increased eddy current losses. This can make the use of thicker magnetic films impractical. Therefore, it is desirable to improve the performance of inductors in ICs (e.g., to achieve higher inductance per unit area and a higher Q factor) while reducing the high energy dissipation caused by eddy currents.

[0009] Embodiments of the present disclosure include wrapping a conductive trace of an inductor with one or more magnetic films having grooves (e.g., dielectric spacers) in multiple directions. The grooves may form segments (e.g., islands or blocks) of the magnetic film that surround the conductive trace in three dimensions. Some embodiments may include an inductor for an RF IC. The inductor may include a conductive trace and one or more magnetic films, comprising one or more layers of magnetic film alternating with one or more layers of dielectric. The conductive trace may have two terminals and form an open loop or coil. The one or more magnetic films may wrap around the top, bottom, and sides of the conductive trace. The one or more magnetic films may include one or more grooves along a first path directly over a length of the conductive trace and one or more grooves along a second path to form the segments, the first path directly over a width of the conductive trace. The grooves of the one or more magnetic films may completely pass through the one or more magnetic films between the segments. In some embodiments, one or more multilayer stacks comprising the one or more magnetic films may wrap around a top, a bottom, and a side of the conductive trace. The one or more multilayer stacks may be formed as a laminate in a lamination process (e.g., a deposition or electroplating lamination process). The one or more multilayer stacks may include magnetic film layers separated from each other by dielectric layers. The multilayer stacks may also include one or more grooves along a path directly over a length or a width of the conductive trace to form multiple sections of the one or more multilayer stacks. As a result, the inductor can operate with improved performance (e.g., higher inductance per unit area and higher Q factor) while reducing high energy dissipation caused by eddy currents.

[0010] In some embodiments, a three-dimensional magnetic film can be patterned to maximize the quality factor of an inductor. Due to its high magnetic permeability, the magnetic film can increase the magnetic flux density around the inductor. The magnetic film can be patterned to mitigate eddy currents, which in turn reduces power consumption in the system due to the magnetic film's high conductivity. For example, even though the high magnetic permeability of the magnetic film increases the Q factor, losses due to eddy currents can still degrade the inductor's Q factor. To reduce eddy currents, one or more magnetic films can be formed by filling trenches with a dielectric, such as polyimide or air (e.g., a dielectric spacer). This confines eddy currents circulating in the structure and reduces overall losses. However, forming a magnetic film with trenches can reduce the spatial density of the magnetic film around the inductor. This can result in lower magnetic flux density and a lower Q factor. Therefore, in the embodiments described herein, the pattern of the formed magnetic film can be optimized to achieve an optimal balance between inductance density per unit length and total losses due to eddy currents, thereby achieving the highest Q factor.

[0011] In some implementations, the optimized pattern may include forming a magnetic film with one or more grooves in the X direction (e.g., across the width of the conductive trace), the Y direction (e.g., across the length of the conductive trace), and / or the Z direction (e.g., across the thickness of the conductive trace). For example, the magnetic film may be uniformly formed with grooves to include numerous segments in both the Y and Z directions. The optimized pattern of the magnetic film may also include more than two grooves in the X direction. The spacing between magnetic film layers and the spacing between grooves in the X direction may be optimized to achieve the highest Q factor.

[0012] Several aspects of the present disclosure will now be explained with reference to the accompanying drawings. Whenever the shapes, relative positions, and other aspects of components described are not clearly defined, the scope of the present disclosure is not limited to the components shown, and this is meant for illustrative purposes only. Furthermore, while many details are described, it should be understood that some aspects of the present disclosure may be practiced without these details. In other instances, well-known circuits, structures, and technologies have not been shown in detail to avoid obscuring the understanding of this description. As used herein, the terms "above," "below," "over," "under," "top," "bottom," "side," "to," "between," "spanning," and "on" may refer to the relative position of one layer relative to another layer. A layer that is said to be "on," "below," "above," "under," "on top," "bottom," "to the side of," "between," "across," or "on" another layer, or that is "joined to" or "in contact with" another layer, may be directly in contact with the other layer or may have one or more intervening layers (e.g., dielectric layers). A layer that is "between" layer(s) may be directly in contact with those layers or may have one or more intervening layers (e.g., dielectric layers).

[0013] Figures 1 through 5 will now be described to explain possible embodiments, including those shown in Figures 6A through 6D. Figure 1 illustrates an example of an inductor 110 including a conductive trace 112 and one or more layers of magnetic film 114 having grooves, according to an embodiment. The one or more layers of magnetic film 114 having grooves can be implemented as a multilayer stack as shown in any of Figures 6A through 6D. Conductive trace 112 (e.g., copper) can include two terminals 116 and 118 for connecting to the circuitry of an IC or IC package. Conductive trace 112 can be formed as an open loop. Inductor 110 can be used, for example, in filters, impedance matching networks, resonators, couplers, or other circuitry components. For example, inductor 110 can be used in the circuitry of an IC implementing 5G mobile network technology. The layers of the magnetic film can include an IC-compatible metallic ferromagnetic material with high magnetic permeability. The one or more layers of magnetic film 114 can be monolithically integrated with the IC. The one or more layers of magnetic film 114 may include a plurality of magnetic films surrounding the conductive trace 112. For example, the plurality of magnetic films may include a multilayer stack of magnetic film layers separated by dielectric layers, including as shown in Figures 6A to 6D.

[0014] With additional reference to FIG2 and FIG3 , a top view and a side view of inductor 110 are shown, respectively, by way of example. The one or more layers of magnetic film 114 may be patterned to surround the top, bottom, and sides (e.g., opposing sides, such as a first side and a second side) of the conductive trace 112. The one or more layers of magnetic film 114 may include one or more trenches 120 disposed along a first path 122 directly over the length of the conductive trace 112. For example, the first path 122 may be located in the Y direction over the conductive trace 112 and along the length of the conductive trace 112 (e.g., more than thirty trenches as shown in FIG2 ). The one or more layers of magnetic film 114 may also include one or more trenches 120 disposed along a second path 124 directly over the width of the conductive trace 112. For example, the second path 124 may be located in the X direction over the conductive trace 112 and across the width of the conductive trace 112 (e.g., three trenches as shown in FIG2 ). The one or more layers of magnetic film 114 may also include one or more grooves 120 disposed along a third path 126 directly beneath the width of the conductive trace 112. For example, the third path 126 may lie in the X-direction beneath the conductive trace 112 and across the width of the conductive trace 112 (e.g., three grooves in a path parallel to the second path 124). The one or more layers of magnetic film 114 may also include one or more grooves 120 disposed along a fourth path directly beneath the length of the conductive trace 112. For example, the fourth path may lie in the Y-direction beneath the conductive trace 112 and along the length of the conductive trace 112 (e.g., more than thirty grooves in a path parallel to the first path 122).

[0015] In some implementations, the one or more layers of magnetic film 114 may also include one or more grooves 120 e (indicated by phantom lines in FIG. 3 ) disposed along a fifth path 130 across the thickness of the conductive trace 112 on the first side, and / or one or more grooves 120 f (indicated by phantom lines in FIG. 3 ) disposed along a sixth path 132 across the thickness of the conductive trace 112 on the second side (see FIG. 3 ). For example, the grooves 120 may be disposed vertically and horizontally relative to the conductive trace 112. The fifth path 130 and the sixth path 132 may each be on opposite sides of the conductive trace 112 and located in the Z direction across the thickness of the conductive trace 112 (e.g., in paths parallel to each other).

[0016] Trenches 120 may form a plurality of segments (e.g., islands or blocks) of the magnetic film, such as segment 140. Furthermore, trenches 120 may extend completely through one or more layers of magnetic film 114 (including through multiple layers and between segments 140) and may be filled with a dielectric, such as polyimide or air (e.g., forming dielectric spacers between segments 140). For example, as shown in the side view of FIG. 3 , trenches 120a, 120b, 120c, and 120d may extend completely through multiple layers of one or more layers of magnetic film 114, with dielectric therebetween to form segments 140a, 140b, 140c, and 140d (e.g., electrically separated multi-layer segments). Consequently, inductor 110 may operate with improved performance, such as higher inductance per unit area and a higher Q factor, while reducing high energy dissipation caused by eddy currents.

[0017] In some implementations, one or more grooves 120 along one path can be aligned with one or more grooves 120 along another path. For example, as shown in the side view of FIG3 , grooves 120a and 120b along second path 124 are axially aligned (e.g., in the Z direction) with grooves 120c and 120d along third path 126. In another example, grooves 120 along first path 122 can be aligned (e.g., in the Z direction) with grooves 120 along fourth path directly below the length of conductive trace 112. In yet another example, grooves 120 along fifth path 130 can be aligned (e.g., in the X direction) with grooves 120 along sixth path 132. Thus, the patterning of grooves 120 above conductive trace 12 can be identical to the patterning of grooves 120 below conductive trace 12. Furthermore, the patterning of grooves 120 on opposite sides of conductive trace 12 can be identical.

[0018] In some implementations, one or more grooves 120 along one path can be offset relative to one or more grooves 120 along another path (e.g., a parallel path in another plane). For example, in some implementations, grooves 120a and 120b along second path 124 can be axially offset (e.g., in the Z direction) relative to grooves 120c and 120d along third path 126. Thus, the patterning of grooves 120 above conductive trace 12 can be different from the patterning of grooves 120 below conductive trace 12. Furthermore, the pattern of grooves 120 can be different on opposite sides of conductive trace 12.

[0019] Therefore, the one or more layers of magnetic film 114 can be patterned through the grooves 120 to optimize the inductor 110, such as to increase or maximize the Q factor. The layers of magnetic film can increase the magnetic flux density around the inductor 110 due to their high magnetic permeability. The one or more layers of magnetic film 114 can be patterned through the grooves 120 to reduce eddy currents and, in turn, reduce power loss in the system due to the high conductivity of the magnetic film. The patterning of the one or more layers of magnetic film 114 (such as by laser etching, dry reactive etching, or plasma etching) can be optimized to achieve an optimal balance between inductance density per unit length and total losses due to eddy currents, thereby achieving the highest Q factor.

[0020] Referring also to FIG4 and FIG5 , a close-up top view 142 and a close-up side view 144 of inductor 110 are shown, respectively, by way of example. Segments 140 (e.g., segments 140a, 140b, and 140c) of the one or more layers of magnetic film 114 may have a width A1, a length A2, and a thickness C. For example, for a 142 picohenry (pH) inductor optimized at 7 GHz, segments 140 may have a width A1 of 1.9 micrometers (µm), a length A2 of 1.9 µm, and a thickness C of 1125 nanometers (nm). Segments 140 may also be spaced apart by a distance B1 in the X direction and a distance B2 in the Y direction. Distances B1 and B2 may correspond to the dimensions of trench 120. For example, for a 142 pH inductor, segments 140 may be spaced apart by a distance B1 of 0.95 µm in the X direction and by a distance B2 of 0.95 µm in the Y direction. Segments 140 may also be spaced apart by a distance D in the Z direction (e.g., the distance between magnetic film layers). For example, for a 142 pH inductor, segments 140 may be spaced apart by a distance D of 50 nm in the Z direction. Segments 140 may also be spaced apart from conductive trace 112 by at least a distance E. For example, for a 142 pH inductor, segments 140 may be spaced apart from conductive trace 112 by at least 2 µm. Therefore, in three-dimensional patterning, the distance between magnetic film layers (e.g., distance D) may be smaller than the distance between any magnetic film layer and conductive trace 112 (e.g., distance E). Furthermore, in some implementations, the number of layers can be increased while reducing the layer thickness (e.g., distance C). This can achieve an even higher Q factor. For example, although three layers of magnetic film are shown by way of example, some embodiments may include four, five, or more layers of magnetic film.

[0021] In some embodiments, conductive trace 112 may include multiple regions. One or more layers of magnetic film 114 including grooves 120 may surround each of the regions. For example, referring again to FIG. 1 , conductive trace 112 may include terminal 116, followed by a first region 141a, followed by a turn, followed by a second region 141b, followed by another turn, followed by a third region 141c, followed by terminal 118 (e.g., forming an open loop of inductor 110). First region 141a, second region 141b, and third region 141c may each include a magnetic film including grooves 120 surrounding the region.

[0022] Figures 6A through 6D illustrate examples of inductors including one or more conductive traces and one or more multilayer stacks according to embodiments. For example, one or more multilayer stacks of any of Figures 6A through 6D may implement the one or more layers of magnetic film 114 with grooves shown in Figures 1 through 5 . Referring first to Figure 6A , an example side view of an inductor 110a according to embodiments is shown. For example, inductor 110a may be a single-turn inductor. Inductor 110a may include one or more multilayer stacks, each including one or more layers of magnetic film (e.g., magnetic film layers 114a, 114b, and 114c) separated by dielectric layers (e.g., dielectric layers 115a, 115b, 115c, and 115d). For example, the one or more multilayer stacks may be coupled to conductive trace 112a via an electroplating lamination process.

[0023] One or more multilayer stacks may surround the top, bottom, and sides of conductive trace 112a. For example, one or more multilayer stacks may include a first multilayer stack 183 below the bottom of conductive trace 112a. First multilayer stack 183 may include multiple layers of magnetic films (e.g., three layers in the example shown) alternating with dielectric layers. First multilayer stack 183 may also include etching of trenches 120 (e.g., trenches 120c and 120d). For example, the etching may be performed via laser etching, dry reactive etching, or plasma etching, and then filled with a dielectric (such as polyimide or air) to create a pattern that results in a higher Q factor for inductor 110a. One or more multilayer stacks may also include a second multilayer stack 185 surrounding the top and opposite sides of conductive trace 112a. Second multilayer stack 185 may also include multiple layers of magnetic films (e.g., three layers in the example shown) alternating with dielectric layers (e.g., like first multilayer stack 183). The second multilayer stack 185 may also include etching of the trenches 120 (e.g., trenches 120a and 120b). For example, trenches 120a and 120b may be aligned with trenches 120c and 120d, respectively (e.g., in the Z direction). For example, the etching may be performed via a further step of laser etching, dry reactive etching, or plasma etching, and filled with a dielectric (such as polyimide or air) to produce a pattern that results in a higher Q factor.

[0024] Referring to FIG6B , an example side view of an inductor 110b according to an embodiment is shown. For example, inductor 110b may be a multi-turn inductor. Inductor 110b may include one or more multilayer stacks, each comprising one or more layers of magnetic film (e.g., magnetic film layers 114a, 114b, and 114c) separated by dielectric layers (e.g., dielectric layers 115a, 115b, 115c, and 115d). The one or more multilayer stacks may be coupled to multiple conductive traces (e.g., different turns of inductor 110b), such as the group of conductive traces 112a through 112c, of inductor 110b via an electroplating lamination process. The one or more multilayer stacks may surround the top, bottom, and sides of the group of conductive traces 112a through 112c. For example, first multilayer stack 183 may be located below the bottom of the group, and second multilayer stack 185 may surround the top and opposite sides of the group. The first multilayer stack 183 may also include etching trenches above the group (e.g., trenches 120a to 120c above conductive traces 112a to 112c, respectively). The second multilayer stack 185 may also include etching trenches below the group (e.g., trenches 120d to 120f below conductive traces 112a to 112c, respectively). For example, the etching may be performed via laser etching, dry reactive etching, or plasma etching, and filled with a dielectric (such as polyimide or air) to produce a pattern that results in a higher Q factor for the inductor 110b.

[0025] Referring to FIG6C , an example side view of an inductor 110c according to an embodiment is shown. For example, inductor 110c may be another multi-turn inductor. Inductor 110c may include one or more multilayer stacks, each comprising one or more layers of magnetic film (e.g., magnetic film layers 114a, 114b, and 114c) separated by dielectric layers (e.g., dielectric layers 115a, 115b, 115c, and 115d). The one or more multilayer stacks may be coupled to multiple conductive traces (e.g., different turns of inductor 110c) on multiple metal layers, such as the group of conductive traces 112a through 112f, via an electroplating lamination process. For example, conductive traces 112a through 112c may be in an upper metal layer above conductive traces 112d through 112f in a lower metal layer. The one or more multilayer stacks may surround the top, bottom, and sides of the group of conductive traces 112a through 112f. For example, the first multilayer stack 183 may be below the bottom of the group, and the second multilayer stack 185 may surround the top and opposite sides of the group. The first multilayer stack 183 may also include etching trenches above the group (e.g., trenches 120a-120c above conductive traces 112a-112c, respectively, in the upper metal layer). The second multilayer stack 185 may also include etching trenches below the group (e.g., trenches 120d-120f below conductive traces 112a-112c, respectively, in the lower metal layer). For example, the etching may be formed by laser etching, dry reactive etching, or plasma etching and filled with a dielectric (such as polyimide or air) to produce a pattern that results in a higher Q factor for the inductor 110c.

[0026] Referring to FIG6D , an example side view of an inductor 110d according to an embodiment is shown. For example, inductor 110d may be another single-turn inductor. Inductor 110d may include one or more multilayer stacks, each comprising one or more layers of magnetic film (e.g., magnetic film layers 114a, 114b, and 114c) separated by dielectric layers (e.g., dielectric layers 115a, 115b, 115c, and 115d). The one or more multilayer stacks may be coupled to conductive trace 112a at one or more angles, for example, via a deposition lamination process. The one or more multilayer stacks may wrap around the top, bottom, and sides of conductive trace 112a at one or more angles. For example, first multilayer stack 183 may wrap around the sides of conductive trace 112a below the bottom of conductive trace 112a at an angle (e.g., a 45-degree slope for the upper portion of the sidewalls). Thus, each sidewall may be angled relative to the top and / or bottom. Second multilayer stack 185 may wrap around the top of conductive trace 112a and downward along the sides of conductive trace 112a at an angle (e.g., a 45-degree slope for each portion of the lower sidewall). First multilayer stack 183 may also include etching a trench above conductive trace 112a, and second multilayer stack 185 may include etching a trench below conductive trace 112a. For example, the etching may be formed via laser etching, dry reactive etching, or plasma etching, and filled with a dielectric (such as polyimide or air) to create a pattern that results in a higher Q factor for inductor 110d.

[0027] Referring to FIG6E , an example side view of an inductor 110e according to an embodiment is shown. For example, inductor 110e may be a multi-turn inductor. Inductor 110e may include one or more multilayer stacks, each including one or more layers of magnetic film (e.g., magnetic film layers 114a, 114b, and 114c) separated by dielectric layers (e.g., dielectric layers 115a, 115b, 115c, and 115d). The one or more multilayer stacks may be coupled to multiple conductive traces (e.g., different turns of inductor 110e), such as a group of conductive traces 112a through 112c, of inductor 110e. The one or more multilayer stacks may be coupled to the group at one or more angles, for example, via a deposition lamination process. The one or more multilayer stacks may wrap around the top, bottom, and sides of the group at one or more angles. For example, the first multilayer stack 183 may be below the bottom of the group, and the second multilayer stack 185 may be formed around the top and opposite sides of the group at an angle (e.g., a 30-degree slope for the sidewalls). Thus, the sidewalls may be angled relative to the top and / or bottom. The first multilayer stack 183 may also include etching trenches above the group (e.g., trenches 120a-120c above conductive traces 112a-112c, respectively). The second multilayer stack 185 may also include etching trenches below the group (e.g., trenches 120d-120f below conductive traces 112a-112c, respectively). For example, the etching may be performed via laser etching, dry reactive etching, or plasma etching and filled with a dielectric (e.g., polyimide or air) to create a pattern that results in a higher Q factor for the inductor 110e.

[0028] Referring to FIG6F , an example side view of an inductor 110f according to an embodiment is shown. For example, inductor 110f may be a multi-turn inductor. Inductor 110f may include one or more multilayer stacks, each including one or more layers of magnetic film (e.g., magnetic film layers 114a, 114b, and 114c) separated by dielectric layers (e.g., dielectric layers 115a, 115b, 115c, and 115d). The one or more multilayer stacks may be coupled to multiple conductive traces (e.g., different turns of inductor 110f) of multiple metal layers, such as the group of conductive traces 112a through 112f. The one or more multilayer stacks may be coupled to the group at one or more angles, for example, via a deposition lamination process. The one or more multilayer stacks may wrap around the top, bottom, and sides of the group at one or more angles. For example, a first multilayer stack 183 may be formed below the bottom of the group, and a second multilayer stack 185 may be formed around the top and opposite sides of the group at an angle (e.g., a 30-degree slope for the sidewalls). The first multilayer stack 183 may also include etching trenches above the group (e.g., trenches 120a-120c above conductive traces 112a-112c, respectively). The second multilayer stack 185 may also include etching trenches below the group (e.g., trenches 120d-120f below conductive traces 112d-112f, respectively). For example, the etching may be formed by laser etching, dry reactive etching, or plasma etching and filled with a dielectric (e.g., polyimide or air) to produce a pattern that results in a higher Q factor for inductor 110e.

[0029] Figures 7A through 7E illustrate examples of top-view patterns (shown above) and side-view patterns (shown in the middle) of conductive traces for inductors including a magnetic film with grooves (shown below), according to embodiments. For example, Figures 7A through 7E illustrate inductors 150, 152, 154, 156, and 158, respectively. Each of these examples may include one or more of the multilayer stacks shown in Figures 6A through 6D. Additionally, Figure 7F illustrates an example of top-view patterns (shown above) and side-view patterns (shown in the middle) of conductive traces for reference inductor 148 without a magnetic film (shown below). Inductors 148 through 158 can be designed and optimized to achieve an inductance at a target frequency (e.g., 7 GHz). Inductors 148 through 158 can have varying lengths, widths, inductances, Q factors, and resistances.

[0030] ( FIG7A ) Inductor 150, which adds three layers of magnetic film and trenches in the Y direction (compared to inductor 148), can have a shorter length, shorter width, approximately the same inductance, a lower Q factor, and a higher resistance than inductor 148. Inductor 152, which further adds trenches in the X direction above the conductive trace ( FIG7B ), can have a shorter length, shorter width, approximately the same inductance, a lower Q factor, and a lower resistance than inductor 148. Inductor 154, which further adds trenches in the X direction below the conductive trace ( FIG7C ), can have a shorter length, shorter width, approximately the same inductance, a higher Q factor, and a lower resistance than inductor 148. Inductor 156, which adds yet another trench in the X direction above and below the conductive trace ( FIG7D ), can have a shorter length, shorter width, approximately the same inductance, a higher Q factor, and a lower resistance than inductor 148. Finally, inductor 158 ( FIG. 7E ), which adds more trenches (e.g., four trenches) in the X direction above and below the conductive trace, can have a longer length, a shorter width, approximately the same inductance, a higher Q factor, and a lower resistance than inductor 148. Thus, inductors 150 , 152 , 154 , 156 , and 158 represent improvements over inductor 148 in various ways, including a smaller form factor (e.g., length and width) and / or a higher Q factor.

[0031] Additionally, in some implementations, the number of layers can be increased while reducing the thickness of each layer (e.g., distance C) to achieve a higher Q factor. For example, inductors 150, 152, 154, 156, and 158 can be designed with four or five layers of magnetic film (e.g., instead of three layers as shown) while reducing the thickness of each layer.

[0032] FIG8 illustrates an example of an inductor 110 formed in a back-end-of-the-line (BEOL) build-up structure 162 according to an embodiment. For example, inductor 110 may be an on-chip inductor utilized by circuitry of an IC 160 or die. Build-up structure 162 may include conductive traces 112 and one or more layers of magnetic film (e.g., one or more multilayer stacks as shown in FIG6A-6D ). The bottom side of build-up structure 162 may be formed on the top side of a semiconductor substrate 164. Semiconductor substrate 164 may include a plurality of semiconductor devices 166. The build-up structure and semiconductor substrate 164 together may form IC 160 or die. A plurality of landing pads 168 may be exposed on the top side of build-up structure 162 to enable attachment of IC 160 or die to a system (e.g., to an IC-level package).

[0033] FIG9 illustrates an example of an inductor 110 formed in a die-level redistribution layer (RDL) 171 according to an embodiment. For example, inductor 110 may be an on-die inductor utilized by circuitry of an IC 170 or die. Die-level RDL 171 may include conductive traces 112 and one or more layers of magnetic film (e.g., one or more multilayer stacks as shown in FIG6A through FIG6D ). A plurality of landing pads 172 may be exposed on the top side of die-level RDL 171. The plurality of landing pads 172 may enable IC 170 or die to be attached to a system (e.g., to an IC-level package). A plurality of test pads 174 (e.g., aluminum) may be exposed on the bottom side of die-level RDL 171. The bottom side of a die-level RDL 171 can be formed on the top side of a BEOL build-up structure 176, with a passivation layer 178 (e.g., SiNix) formed between the die-level RDL 171 and the build-up structure 176. The build-up structure 176 can include a metal seal ring 180 that prevents moisture and impurities from invading the layers of the build-up structure 176. The bottom side of the build-up structure 176 can be formed on the top side of a semiconductor substrate 184. The semiconductor substrate 184 can include a plurality of semiconductor devices 186. The die-level RDL 171, the build-up structure 176, and the semiconductor substrate 184 together can form an IC 170 or a die.

[0034] In some embodiments, the die-level RDL 171, including the inductor 110, can be fabricated via thin-film fabrication. For example, based on the utilization of the passivation layer 178 and the metal seal ring 180, the die-level RDL 171 can be formed via lamination, spin coating, spray coating, or other cost-effective techniques without adversely affecting the build-up structure 176. For example, with further reference to FIG10, the die-level RDL 171 can include dielectric layers 202 and 204 of different types and / or thicknesses, with metallization lines 206 forming vias 208 thereon. Conversely, the build-up structure 176 can continue to utilize more precise techniques, such as chemical vapor deposition (CVD), in its formation. With further reference to FIG11, the build-up structure 176 can be fabricated via dual damascene fabrication. For example, with additional reference to FIG. 11 , the build-up structure 176 may include a dielectric layer 212 of the same type and / or thickness, with metallization lines 214 forming vias 216 (eg, metal-filled openings) therein.

[0035] FIG12 illustrates an example of an inductor 110 formed in a package-level RDL 232 according to an embodiment. For example, inductor 110 may be a package-level inductor formed in package 230. Package-level RDL 232 may include conductive traces 112 and one or more layers of magnetic film (e.g., one or more multilayer stacks in FIG6A-6D ). Package 230 may include an IC 234 or die, which includes a build-up structure and a semiconductor substrate (e.g., build-up structure 162 and semiconductor substrate 164 shown by way of example). IC 234 or die may be encapsulated in a molding compound 235 (e.g., epoxy). Package 230 may also include a package-level RDL 232 coupled to IC 234 or die (e.g., attached to a surface of the die). For example, IC 234 or die may be flip-chip, and package-level RDL 232 may fan out connections associated with IC 234 or die. A plurality of landing pads 236 may be exposed on the bottom surface of the package-level RDL 232. Additionally, a plurality of bumps 238 may be attached to the plurality of landing pads 236 for attaching the package 230 to a system.

[0036] FIG13 illustrates an example of an inductor 110 including a discrete integrated passive device (IPD) 252, according to an embodiment. For example, IPD 252 may include a dielet coupled to a package 250. IPD 252 may include conductive traces 112 and one or more layers of magnetic film (e.g., one or more multilayer stacks as shown in FIG6A-6D). Package 250 may include an IC 254 or die, which includes a build-up structure and a semiconductor substrate (e.g., build-up structure 162 and semiconductor substrate 164 shown by way of example). IC 254 or die may be encapsulated in a molding compound 235 (e.g., epoxy). Package 250 may also include a package-level RDL 256 coupled to (attached to) the surface of IC 254 or die. For example, IC 254 or die may be flip-chip, and package-level RDL 256 may fan out the connections of IC 254 or die. A plurality of landing pads 258 can be exposed on the bottom surface of package-level RDL 256. Additionally, a plurality of bumps 260 can be attached to the plurality of landing pads 258 for coupling IPD 252 to package 250 and / or for attaching package 250 to a system. In some implementations, a plurality of microbumps 262 (e.g., smaller than the plurality of bumps 260) can be attached to some of the plurality of landing pads 258 for coupling IPD 252 to package 250.

[0037] In utilizing various aspects of the embodiments, those skilled in the art will appreciate that combinations or variations of the above embodiments are possible for an inductor comprising an inductor trace and a magnetic film having grooves for use in a radio frequency integrated circuit. Although the embodiments have been described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Instead, the specific features or acts disclosed should be understood as examples that can be used to illustrate the claims.

[0038] 110, 110a, 110b, 110c, 110d, 110e, 110f: Inductors 112, 112a, 112b, 112c, 112d, 112e, 112f: Conductive traces 114: Magnetic film 114a, 114b, 114c: magnetic film layer 115a, 115b, 115c, 115d: dielectric layer 116,118:Terminal 120,120a,120b,120c,120d,120e,120f: Grooves 122: First Path 124: Second Path 126: The Third Path 130: The Fifth Path 132: Sixth Path 140,140a,140b,140c,140d: Section 141a: First Area 141b: Second Area 141c: Third Area 142: Close-up top view 144: Close-up side view 148,150,152,154,156,158: Inductors 160:IC 162: Back-end process build-up structure; BEOL build-up structure 164:Semiconductor substrate 166:Semiconductor device 168: Landing Pad 170:IC 171: Grain-level redistribution layer; Grain-level RDL 172: Landing Pad 174:Test Pad 176:BEOL build-up structure 178: passivation layer 180:Metal sealing ring 183: First multi-layer stack 184:Semiconductor substrate 185: Second multi-layer stack 186:Semiconductor device 202,204: Dielectric layer 206:Metalized wire 208: Wire through hole 212: dielectric layer 214:Metalized wire 216:Through hole 230: Encapsulation 232: Package-level RDL 234:IC 235: Molding compound 236: Landing Pad 238: Bump 250: Encapsulation 252: Discrete Integrated Passive Device; IPD 254:IC 256: Package-level RDL 258: Landing Pad 260: Bump 262: Micro bump A1: Width A2: Length B1, B2: distance C:Thickness D, E: distance

Claims

1. An inductor for an integrated circuit (IC) comprising: a conductive trace; and one or more magnetic films surrounding a top, a bottom, and a side of the conductive trace, the one or more magnetic films including one or more trenches along a first path and one or more trenches along a second path to form a plurality of segments, the first path being directly above a length of the conductive trace and the second path being directly above a width of the conductive trace.

2. The inductor of claim 1, wherein the trenches of the one or more magnetic films completely pass through the one or more magnetic films between the segments of the plurality of segments.

3. The inductor of claim 1, wherein the one or more magnetic films include one or more trenches along a third path and one or more trenches along a fourth path, the third path being directly below the width of the conductive trace and the fourth path being directly below the length of the conductive trace.

4. The inductor of claim 3, wherein the one or more trenches along the first path are aligned with the one or more trenches along the third path, and wherein the one or more trenches along the second path are aligned with the one or more trenches along the fourth path.

5. The inductor of claim 3, wherein the one or more magnetic films include one or more trenches along a fifth path that directly crosses a thickness of the conductive trace.

6. The inductor of claim 1, wherein a plurality of magnetic films surround the conductive trace.

7. The inductor of claim 6, wherein the plurality of magnetic films comprises at least three layers of magnetic films.

8. The inductor of claim 6, wherein a first distance between the layers of the plurality of magnetic films is less than a second distance between the plurality of magnetic films and the conductive trace.

9. The inductor of claim 6, wherein the trenches of the plurality of magnetic films completely pass through the plurality of magnetic films between the segments of the plurality of segments.

10. The inductor of claim 6, wherein the plurality of magnetic films are located below the bottom of the conductive trace, and further comprises: a second plurality of magnetic films, which surround one side and the top of the conductive trace.

11. The inductor of claim 1, wherein the conductive trace and the one or more magnetic films are formed on a semiconductor substrate in a back-end process (BEOL) add-on structure.

12. The inductor of claim 1, wherein the conductive trace and the one or more magnetic films are formed in a grain-level redistribution layer (RDL).

13. The inductor of claim 1, wherein the conductive trace and the one or more magnetic films are formed in a package-level RDL coupled to a die.

14. The inductor of claim 1, wherein the conductive trace and the one or more magnetic films comprise a discrete integrated passive device (IPD) coupled to a discrete die.

15. The inductor of claim 1, further comprising: a second region of the conductive trace, wherein the one or more magnetic films further include one or more trenches to form a second plurality of segments surrounding the second region.

16. An inductor for an integrated circuit (IC) comprising: a conductive trace; and one or more multilayer stacks surrounding a top, a bottom, and a side of the conductive trace, the one or more multilayer stacks including magnetic film layers separated from each other by dielectric layers, the one or more multilayer stacks further including one or more trenches along a path to form a plurality of segments, the path being directly above at least one of a length or a width of the conductive trace.

17. The inductor of claim 16, wherein the trench of the one or more multilayer stacks completely passes through the one or more multilayer stacks between the segments of the plurality of segments.

18. The inductor of claim 16, wherein the one or more multilayer stacks include one or more trenches along a path directly below at least one of the length or the width of the conductive trace.

19. The inductor of claim 18, wherein the one or more trenches along the path directly above the conductive trace are aligned with the one or more trenches along the path directly below the conductive trace.

20. The inductor of claim 18, wherein the one or more multilayer stacks include one or more trenches along a fifth path that directly crosses a thickness of the conductive trace.

Images