Memory cell manufacturing process

Abstract

This invention discloses various three-dimensional memory cells, array structures, and fabrication processes. In one embodiment, a memory cell structure is provided, which is formed by alternating deposition of multiple semiconductor layers and sacrificial layers to form a stack, using a deep trench process to form vertical bit line holes in the stack, using an isotropic doping process to form floats in the semiconductor layers through the bit line holes, depositing a conductor material to fill the bit line holes, removing the sacrificial layer, depositing a gate dielectric layer between the semiconductor layers, and depositing a gate material onto the gate dielectric layer.

Description

Technical Field

[0001] [Asserting priority] The corresponding U.S. application is U.S. Patent Application No. 18 / 311,212, filed on May 2, 2023, entitled "3D Memory Cell and Array Structure and Process".

[0002] Pursuant to 35 USC 119(e) of the United States Patent and Trademark Office, the corresponding U.S. patent application of this invention claims priority based on the following patent applications: U.S. Provisional Patent Application No. 63 / 544,018, filed October 13, 2023, entitled "3D Cell and Array Structure and Process"; U.S. Provisional Patent Application No. 63 / 544,326, filed October 16, 2023, entitled "3D Cell and Array Structure and Process"; and U.S. Provisional Patent Application No. 63 / 609,879, filed December 14, 2023, entitled "3D Cell and Array Structure and Process", all of which are hereby incorporated herein by reference in their entirety.

[0003] Application 18 / 311,212 is a continuation-in-part (CIP) of U.S. Patent Application No. 17 / 937,432, filed on September 30, 2022, entitled "3D Memory Cells and Array Structures".

[0004] Application 18 / 311,212 claims priority under 35 USC 119(e) of the U.S. Patent Act, based on the following U.S. patent applications: U.S. Provisional Patent Application No. 63 / 398,807, filed August 17, 2022, entitled "Memory Cell and Array Structure and Operating Conditions"; U.S. Provisional Patent Application No. 63 / 406,255, filed September 14, 2022, entitled "3D Cell and Array Structure"; U.S. Provisional Patent Application No. 63 / 413,493, filed October 5, 2022, entitled "3D Cell and Array Structure"; U.S. Provisional Patent Application No. 63 / 418,698, filed October 24, 2022, entitled "3D Cell and Array Structure"; and U.S. Provisional Patent Application No. 63 / 445,670, filed February 14, 2023. U.S. Provisional Patent Application No. 63 / 445,672, filed February 14, 2023, entitled "3D Cell and Array Structure"; U.S. Provisional Patent Application No. 63 / 449,938, filed March 3, 2023, entitled "Novel 3D DRAM Cell, Array and Technology"; U.S. Provisional Patent Application No. 63 / 458,059, filed April 7, 2023, entitled "3D Cell and Array Structure and Process"; and U.S. Provisional Patent Application No. 63 / 460,289, filed April 18, 2023, entitled "3D Cell and Array Structure and Process," are all of which are hereby incorporated herein by reference in their entirety.

[0005] Application 17 / 937,432 claims priority under 35 USC 119(e) of the U.S. Patent Act, based on the following patent applications: U.S. Provisional Patent Application No. 63 / 398,807, filed August 17, 2022, entitled "Memory Cell and Array Structure and Operating Conditions"; U.S. Provisional Patent Application No. 63 / 295,874, filed January 1, 2022, entitled "Alpha-RAM (a-RAM) or Alpha-DRAM (a-DRAM) Technology"; U.S. Provisional Patent Application No. 63 / 291,380, filed December 18, 2021, entitled "3D DRAM Alternative Technology"; U.S. Provisional Patent Application No. 63 / 254,841, filed October 12, 2021, entitled "3D DRAM Alternative Technology"; and U.S. Provisional Patent Application No. 63 / 254,841, filed October 12, 2021, entitled "3D DRAM Alternative Technology"; and U.S. Provisional Patent Application No. 63 / 298,807, filed August 17, 2022, entitled "Memory Cell and Array Structure and Operating Conditions"; and U.S. Provisional Patent Application No. 63 / 295,874, filed January 1, 2022, entitled "Alpha-RAM (a-RAM) or Alpha-DRAM (a-DRAM) Technology ...54,841, filed October 12, 2021, entitled "3D DRAM Alternative Technology"; and U.S. Provisional Patent Application No. U.S. Provisional Patent Application No. 63 / 251,583, entitled "3D DRAM Alternative Technology," filed on [date missing]. All of the above applications are hereby incorporated herein by reference in their entirety. [Cross-reference to related applications]

[0006] This invention application relates to the following concurrently examined application, whose agent number is SIONS-PT9-CIP1, filed on May 2, 2023, and entitled "3D Memory Cell and Array Structure". [Field of Invention]

[0007] Exemplary embodiments of the present invention relate generally to the field of memory, and particularly to memory cells and array structures and related manufacturing processes. [Background of the Invention] Prior Technology

[0008] As the complexity and density of electronic circuits increase, memory size, complexity, and cost become important considerations. One way to increase memory capacity is to use three-dimensional (3D) array structures. 3D array structures have been successfully used in NAND flash memory. However, for dynamic random access memory (DRAM), due to its unique transistor-capacitor (1T1C) cell structure, a cost-effective 3D array structure has not yet been realized. Summary of the Invention

[0009] In various exemplary embodiments, three-dimensional (3D) memory cells, array structures, and related processes are disclosed. In one embodiment, a novel 3D array structure for implementing DRAM using floating-body cells is disclosed. The array structure is formed using a deep trench process similar to that of 3D NAND flash memory. Therefore, ultra-high density DRAM can be realized. In one embodiment, a 3D NOR-type memory cell and array structure are provided. The disclosed memory cells and array structures are applicable to many technologies. For example, the innovative memory cells and array structures are applicable to dynamic random-access memory (DRAM), floating-body cell (FBC) memory, NOR-type flash memory, and thyristors.

[0010] In an exemplary embodiment, a memory cell structure is provided, comprising a first semiconductor material, a floating semiconductor material having an inner surface surrounding and connected to the first semiconductor material, and a second semiconductor material having an inner surface surrounding and connected to the floating semiconductor material. The memory cell structure further includes a first dielectric layer connected to a top surface of the floating material, a second dielectric layer connected to a bottom surface of the floating material, a front gate connected to the first dielectric layer, and a rear gate connected to the second dielectric layer.

[0011] In an exemplary embodiment, a three-dimensional (3D) memory array is provided, comprising a plurality of memory cells separated by a dielectric layer to form a stack of memory cells. Each memory cell in the stack includes a bit line formed of one of a first semiconductor material and a first conductor material, a floating semiconductor material having a surrounding and connected inner surface of the bit line, a source line formed of one of a second semiconductor material and a second conductor material having a surrounding and connected inner surface of the floating semiconductor material, and a word line formed of a third conductor material, which is coupled to the floating semiconductor through the dielectric layer to form a gate of the memory cell. Furthermore, the bit lines connecting the stack of memory cells form vertical bit lines.

[0012] In an exemplary embodiment, a memory cell structure is provided, which is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers to form a stack. A deep trench process is used to form holes for vertical bit lines in the stack. An isotropic doping process is used to form floats in the semiconductor layers through the holes for the bit lines. A conductor material is deposited to fill the holes for the bit lines. The sacrificial layer is removed. A gate dielectric layer is deposited between the semiconductor layers. A gate material is deposited on the gate dielectric layer.

[0013] Additional features and advantages of exemplary embodiments of the present invention will become apparent from the detailed description, drawings and claims listed below. Simple Explanation of the Diagram

[0014] Exemplary embodiments of the invention will be more fully understood from the detailed description provided below and the drawings of various embodiments of the invention. However, this should not be construed as limiting the invention to the specific embodiments, but is for explanation and understanding purposes only.

[0015] Figure 1A shows an embodiment of the cell structure of a three-dimensional (3D) NOR array constructed according to the present invention.

[0016] Figure 1B shows an embodiment of the internal unit structure of the unit shown in Figure 1A.

[0017] Figure 1C shows another embodiment of the unit structure constructed according to the present invention.

[0018] Figure 1D shows the unit structure of Figure 1C, with some parts of the unit removed.

[0019] Figure 1E shows another embodiment of the unit structure constructed according to the present invention.

[0020] Figure 1F shows the internal element structure of the element shown in Figure 1E, with some parts of the element removed.

[0021] Figure 1G shows another embodiment of the unit structure constructed according to the present invention.

[0022] Figure 1H shows the internal element structure of the element shown in Figure 1G, with some parts of the element removed.

[0023] Figure 1I shows another embodiment of the unit structure constructed according to the present invention.

[0024] Figure 1J shows the internal element structure of the element shown in Figure 1I, with some parts of the element removed.

[0025] Figure 1K shows another embodiment of a unit structure constructed using a junctionless thin-film transistor according to the present invention.

[0026] Figure 1L shows an embodiment of a cross-sectional view of the unit structure shown in Figure 1K, taken along the cross-section marked AA'.

[0027] Figure 1M shows another embodiment of the unit structure using a junctionless thin-film transistor according to the present invention.

[0028] Figure 1N shows a cross-sectional view of the unit structure shown in Figure 1M, taken along the cross-section marked AA'.

[0029] Figure 10 shows another embodiment of the unit structure using a junctionless thin-film transistor according to the present invention.

[0030] Figure 1P shows a cross-sectional view of the unit structure shown in Figure 1O, taken along the cross-section marked AA'.

[0031] Figure 1Q shows an exemplary embodiment of a three-dimensional (3D) NOR type memory cell structure using a floating body cell (FBC) configuration according to the present invention.

[0032] Figure 1R shows the cell structure shown in Figure 1Q, with the front gate and gate dielectric layer removed.

[0033] Figure 1S shows a cell formed using a PMOS transistor.

[0034] Figure 1T shows an embodiment of an array structure based on the cell structure shown in Figure 1Q.

[0035] Figure 1U shows another embodiment of the array structure according to the present invention.

[0036] Figure 1V shows the equivalent circuit diagram of the array structure shown in Figure 1T.

[0037] Figure 1W shows another embodiment of the equivalent circuit diagram of the array structure shown in Figure 1T.

[0038] Figure 2A shows another embodiment of the cell structure for 3D NOR type flash memory constructed according to the present invention.

[0039] Figure 2B shows the internal cell structure of the cell shown in Figure 2A, with a portion of the cell removed.

[0040] Figure 2C shows another embodiment of the cell structure for 3D non-volatile random access memory constructed according to the present invention.

[0041] Figure 2D shows the internal unit structure of the embodiment shown in Figure 2C, with a portion of the unit removed.

[0042] Figures 3A to 3C show embodiments of the 3D array structure constructed according to the present invention.

[0043] Figures 4A to 4I illustrate an embodiment of the general process steps according to the present invention to form a 3D array comprising the cell structure shown in Figure 1A.

[0044] Figure 4J shows the summary process conditions and materials used in conjunction with the process steps described and shown in Figures 4A to 4I.

[0045] Figures 5A to 5C show embodiments of the general process steps for forming an array using the cell structure shown in Figure 1E according to the present invention.

[0046] Figures 6A to 6F show embodiments of the general process steps for forming an array using the cell structure shown in Figure 1I according to the present invention.

[0047] Figures 7A to 7D show embodiments of the general process steps for forming an array comprising the cell structure shown in Figure 1I according to the present invention.

[0048] Figures 8A to 8E show another embodiment of the outline process steps for forming an array comprising the cell structure shown in Figure 1G according to the present invention.

[0049] Figures 9A to 9C show another embodiment of the general process steps for forming the unit structure shown in Figures 1E to 1F according to the present invention.

[0050] Figures 10A to 10E show another embodiment of the outline process steps performed to form an array comprising the cell structure shown in Figure 1K according to the invention.

[0051] Figures 11A to 11D show another embodiment of a general process step configured to form an array comprising the cell structure shown in Figure 1M according to the invention.

[0052] Figures 12A to 12E show another embodiment of a general process step configured to form an array comprising the cell structure shown in Figure 10 according to the invention. Implementation

[0053] Those skilled in the art will understand that the following detailed description is illustrative only and is not intended to be limiting in any way. Other embodiments of the invention will readily be suggested to those skilled in the art who will benefit from this disclosure. Implementations of exemplary embodiments of the invention will now be described in detail with reference to the figures. The same element symbols or numbers will be used throughout the figures and in the following detailed description to denote the same or similar components.

[0054] In various exemplary embodiments, three-dimensional (3D) memory cells, array structures, and related processes are disclosed. For example, 3D NOR cell and array structures and processes are disclosed. Various embodiments of the present invention can be applied to many technologies. For example, various embodiments of the present invention can be applied to dynamic random-access memory (DRAM), NOR flash memory, ferroelectric random-access memory (FRAM), resistive random-access memory (RRAM), phase-change memory (PCM), magnetoresistive random-access memory (MRAM), and memory elements called "synapses" in neural network arrays used for computation or artificial intelligence (AI) applications in memory. Furthermore, embodiments of the present invention are applicable to other memory applications not listed.

[0055] Figure 1A illustrates an embodiment of a cell structure for a three-dimensional (3D) NOR array constructed according to the present invention. The cell structure shown in Figure 1A includes a semiconductor layer forming a vertical bit line (BL) 101 comprising silicon or polysilicon, a float 102 formed of silicon or polysilicon, and a horizontal source line (SL) 103 formed of silicon or polysilicon. The cell also includes a front gate 104a, a rear gate 104b, a first gate dielectric layer 105a, and a second gate dielectric layer 105b. In one embodiment, gates 104a and 104b are formed of a conductive material, such as metal or heavily doped polysilicon. The front gate 104a and rear gate 104b may be connected to a horizontal word line (WL).

[0056] This unit can be formed as an NMOS or PMOS transistor. In an NMOS unit embodiment, bit line 101 and source line 103 are N+ type doped, and the float 102 is P- type doped. In a PMOS unit embodiment, bit line 101 and source line 103 are P+ type doped, and the float 102 is N- type doped.

[0057] Figure 1B shows an embodiment of the internal unit structure of the cell shown in Figure 1A, wherein a portion of the front gate 104a, gate dielectric layer 105a, and BL 101 are removed. While this embodiment shows the bit line 101 and float 102 as circular, in other embodiments, the bit line 101 and float 102 can have any suitable shape, such as square, rectangular, triangular, hexagonal, etc. These variations are all within the scope of the embodiments.

[0058] Depending on the cell type and technology, the gate dielectric layers 105a and 105b can be formed from various different materials and structures. For example, in one embodiment, the cell can be formed as a floating cell for DRAM applications. In this embodiment, the gate dielectric layers 105a and 105b are thin gate oxide layers or high-k material layers, such as hafnium oxide (HfO2). In another embodiment, the gate dielectric layers 105a and 105b are formed from other suitable materials to form NOR flash memory, ferroelectric random-access memory (FRAM), resistive random-access memory (RRAM), phase-change memory (PCM), magnetoresistive random-access memory (MRAM), etc., as shown in Figures 2A to 2D.

[0059] Figure 1C shows another embodiment of the cell structure constructed according to the present invention. This embodiment is similar to the embodiment in Figure 1A, except that the metal core at the center of the semiconductor layer 109 forms a vertical bit line 101 of the metal to reduce the bit line resistance.

[0060] Figure 1D shows the cell structure of Figure 1C, in which the front gate 104a, gate dielectric layer 105a, a portion of the metal BL 101, and semiconductor layer 109 are removed.

[0061] Figure 1E shows another embodiment of the cell structure constructed according to the present invention. This embodiment is similar to the embodiments shown in Figures 1C to 1D, except that, as shown, a drain region 107 is formed around the side of the metal bit line 101. In one embodiment, the drain region 107 is formed of silicon or polycrystalline silicon and heavy doping of the opposite type to that of the float 102. For example, "opposite type of doping" means that P-type (positive) doping is opposite to N-type (negative) doping. For example, if the float 102 includes P-type doping, then the drain region 107 includes N-type doping, which is the opposite type of doping. If the float 102 includes N-type doping, then the drain region 107 includes P-type doping, which is also the opposite type of doping. The terms "heavily doped" and "lightly doped" are relative terms describing the amount of doping. When a semiconductor is doped with too many electrons or holes, it is called a heavily doped semiconductor, denoted by N+ or P+, respectively. When a semiconductor is doped with a small number of electrons or holes, it is called a lightly doped semiconductor, denoted by N- or P-, respectively. As shown in Figure 1E, the holes in the vertical bit lines are filled with metal to form metal bit lines 101, thereby reducing the bit line resistance.

[0062] Figure 1F shows the internal cell structure of the cell shown in Figure 1E, in which a portion of the front gate 104a, gate dielectric layer 105a, and metal bit line 101 are removed.

[0063] Figure 1G shows another embodiment of the cell structure constructed according to the present invention. This embodiment is similar to the embodiments shown in Figures 1C to 1D, except that the source line 103 is formed of a conductive material (such as metal) to reduce the source line resistance. A source region 108 comprising a semiconductor material (e.g., silicon or polycrystalline silicon) is formed between the metal source line 103 and the float 102. The source region 108 has a heavy doping of the opposite type to that of the float 102.

[0064] Figure 1H shows the internal cell structure of the cell shown in Figure 1G, in which the front gate 104a and gate dielectric layer 105a, a portion of the metal BL 101 and semiconductor layer 109 are removed.

[0065] Figure 1I shows another embodiment of the cell structure constructed according to the present invention. This embodiment is similar to Figures 1A and 1B, except that bit lines 101 and source lines 103 are made of metal. The float 102 is formed of a semiconductor material (e.g., silicon or polycrystalline silicon). In one embodiment, the float 102 is heavily doped with N+ or P+ type. This forms a junctionless cell transistor. In another embodiment, the float 102 is lightly doped with N- or P- type. This forms a Schottky junction cell transistor.

[0066] Figure 1J shows the internal cell structure of the cell shown in Figure 1I, with the front gate 104a, gate dielectric layer 105a and a portion of BL 101 removed.

[0067] Figure 1K shows another embodiment of a unit cell structure constructed using a junctionless thin-film transistor according to the present invention. This embodiment is similar to the embodiments shown in Figures 1A and 1B, except that the semiconductor layer 115 comprises silicon, polycrystalline silicon, germanium (Ge), indium gallium zinc oxide (IGZO), tungsten-doped indium oxide semiconductor, or any other suitable semiconductor material, surrounding BL 101 and an insulator 116 comprising oxides or nitrides. In one embodiment, the semiconductor layer 115 has N-type or P-type heavy doping to form channels for the unit cell transistor. In one embodiment, the bit line 101 and source line 103 are formed of a conductive material, such as a metal or heavily doped polycrystalline silicon. Figure 1K also shows cross-sections labeled A-A'.

[0068] Figure 1L shows an embodiment of the unit structure shown in Figure 1K, drawn along the cross section labeled AA' shown in Figure 1K.

[0069] Figure 1M shows another embodiment of a cell structure using a junctionless thin-film transistor according to the present invention. This embodiment is similar to the embodiments shown in Figures 1A and 1B, except for the semiconductor region 109. The semiconductor region 109 is formed of a different material than the float 102. For example, if the float 102 is formed of silicon or polycrystalline silicon, then the semiconductor region 109 is formed of silicon germanium (SiGe), silicon carbide (SiC), or any other suitable semiconductor material. This configuration forms a heterostructure interface between the two materials and forms quantum wells within the semiconductor region 109 to store charges, such as holes. This increases the data retention time of the cell.

[0070] Figure 1N shows a cross-sectional view of the unit structure shown in Figure 1M along the cross section labeled AA' shown in Figure 1M.

[0071] Figure 10 shows another embodiment of the cell structure using a junctionless thin-film transistor according to the present invention. This embodiment is similar to the embodiments shown in Figures 1M to 1N, except that the semiconductor region 109 is formed in a different shape. The semiconductor region 109 is formed of a different material than the float 102. For example, if the float 102 is formed of silicon or polycrystalline silicon, then the semiconductor region 109 is formed of silicon germanium (SiGe), silicon carbide (SiC), or any other suitable semiconductor material. This forms a heterostructure interface between the two materials and forms quantum wells within the semiconductor region 109 to store charges, such as holes. This increases the data retention time of the cell.

[0072] Figure 1P shows a cross-sectional view of the unit structure shown in Figure 1O, drawn along the cross-section labeled AA' shown in Figure 1O.

[0073] Figure 1Q illustrates an exemplary embodiment of a three-dimensional (3D) NOR-type memory cell structure configured using floating body cells (FBCs) according to the present invention. For example, a 3D NOR-type array may comprise a multi-layered floating body cell array to increase memory capacity. A floating body cell is essentially a transistor with a float. The float stores charge (e.g., electrons or holes) to represent data. The cell structure includes a control gate, a drain, a source, and a float. In a 3D memory array, the control gate, drain, and source of the cell are connected to the word line (WL), bit line (BL), and source line (SL), respectively.

[0074] In the cell structure shown in Figure 1Q, N+ silicon or polycrystalline silicon forms bit lines (BL) 101, and P- floats 102 are used for charge storage. N+ silicon or polycrystalline silicon forms source lines (SL) 103. This cell can form a dual-gate transistor as shown in Figure 1Q or a single-gate transistor as shown in Figure 1R. For the dual-gate transistor shown in Figure 1Q, the cell structure includes two control gates, referred to as the front gate 104a and the rear gate 104b, respectively. The front gate 104a and the rear gate 104b are coupled to the float 102 via gate dielectric layers 105a and 105b, respectively. The gate dielectric layer is an insulating layer between the gate and the transistor body. When an appropriate voltage is applied to the front gate 104a or the back gate 104b, a front gate channel (FGC) 1014 or a back gate channel (BGC) 1012 will be formed on the surface of the float 102 under the gate dielectric layers 105a and 105b to conduct current between the bit line 101 and the source line 103. In one embodiment, the front gate 104a and the back gate 104b are connected to different word lines (WL).

[0075] In one embodiment, the P-float 102 includes a plurality of surfaces as shown in FIG1Q. An inner surface 1002 surrounds and is connected to BL 101. An outer surface 1004 is connected to the source line 103. A top surface 1008 is connected to dielectric layer 105a, and a bottom surface 1006 is connected to dielectric layer 105b. Therefore, in one embodiment, a memory cell structure is provided, comprising a first semiconductor material BL 101, a semiconductor material float 102 having an inner surface 1002 surrounding and connected to the first semiconductor material BL 101, and a second semiconductor material SL 103 having an inner surface 1010 surrounding and connected to the semiconductor material float 102. The memory cell structure further includes a first dielectric layer 105a connected to the top surface 1008 of the float material 102, a second dielectric layer 105b connected to the bottom surface 1006 of the float material 102, a front gate 104a connected to the first dielectric layer 105a, and a rear gate 104b connected to the second dielectric layer 105b. In various embodiments, minor modifications can be made to the disclosed structure, such as adding a lightly doped drain (LDD), halo implantation, pocket implantation, or channel implantation, all of which are included within the scope of this invention.

[0076] Figure 1R shows the cell structure shown in Figure 1Q, where the front gate 104a, gate dielectric layer 105a, and a portion of the bit line 101 are removed. The P-buoy 102 is formed into a donut shape as shown. Although this embodiment shows the bit line 101 and the float 102 as circular, it is clear that they can have any desired shape, such as square, rectangle, triangle, hexagon, etc. These variations should remain within the scope of the invention.

[0077] In one embodiment, the unit structure contains only one gate, as shown in FIG1R. As shown, the float 102 is coupled to only one gate 104b. An embodiment of the 3D array structure using this unit structure embodiment is shown in FIG1T.

[0078] The embodiment shown in Figure 1Q uses an NMOS transistor as the cell. In another embodiment, as shown in Figure 1S, the cell is formed using a PMOS transistor. The bit line 101, the float 102, and the source line 103 are formed of P+, N-, and P+ materials, respectively.

[0079] Figure 1T shows an embodiment of an array structure based on the cell structure shown in Figure 1Q. The array structure includes vertical bit lines 101a to 101c and floats 102a to 102e. The array structure also includes source lines 103a to 103e and word lines 104a to 104d. The array structure also includes a dielectric layer 105, which comprises a gate oxide or a high-k material, such as HfOx.

[0080] In one embodiment, a three-dimensional (3D) memory array includes a plurality of memory cells separated by dielectric layers to form a stack of memory cells. For example, Figure 1T shows a 3D array with a stack of three memory cells and identifies a specific "memory cell". Each memory cell in the stack of memory cells includes a bit line 101 formed of one of a first semiconductor material and a first conductor material, a semiconductor material float 102 having an inner surface surrounding and connected to the bit line, a source line 103 formed of one of a second semiconductor material and a second conductor material and having an inner surface surrounding and connected to the semiconductor material float 102, and a word line 104 formed of a third conductor material coupled to the semiconductor float 102 via a dielectric layer 105 to form a gate of the memory cell. In addition, the bit lines connecting the stack of memory cells form vertical bit lines (e.g., bit line 101a).

[0081] Figure 1U shows another embodiment of the array structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 1T, except that its unit is a single-gate transistor. Insulating layers 106a and 106b formed of materials such as oxides are also shown in Figure 1U.

[0082] Figure 1V shows the equivalent circuit diagram of the array structure shown in Figure 1T. For example, the equivalent circuit shows transistors 301a to 301h, which are formed by the array structure shown in Figure 1T. Referring again to the array structure in Figure 1T, word line structures 104a to 104d are connected to word lines WL0 to WL3. Float structures 102a to 102e are floats FB0 to FB4. Source line structures 103a to 103e are connected to source lines SL0 to SL4, and bit line structure 101a is a vertical bit line (BL). In this embodiment, each float (e.g., floats FB0 to FB4) is coupled to two word lines. This array requires special bias conditions for read and write operations to avoid selecting two cells simultaneously.

[0083] Figure 1W shows another embodiment of the equivalent circuit diagram of the array structure shown in Figure 1T. This embodiment is similar to the embodiment shown in Figure 1V, except that the odd-number lines WL1, WL3, etc., are grounded. This will shut down transistors 301c, 301d, 301g, and 301h. In this embodiment, each float is coupled to only one word line. However, compared to the embodiment shown in Figure 1V, the storage capacity of this embodiment is reduced by half.

[0084] Figure 2A shows another embodiment of a cell structure for a 3D NOR flash memory constructed according to the present invention. This embodiment is similar to the embodiments shown in Figures 1A and 1B, except that the gate dielectric layers 105a and 105b are replaced by charge trapping layers 160a and 160b comprising oxide-nitride-oxide (ONO) layers. In one embodiment, the charge trapping layer 160b includes a tunneling oxide layer 161a, which is thin enough to allow electrons to tunnel through when a high electric field is applied. This changes the threshold voltage of the cell to represent the stored data. The nitride layer 161b traps electrons for data storage. The barrier oxide 161c is thick enough to prevent electrons from tunneling to the gates 104a and 104b. In another embodiment, the barrier oxide 161c includes a tunneling oxide layer, and the tunneling oxide layer 161a includes a barrier oxide layer. In this embodiment, during programming, electrons are injected into the nitride layer 161b from one of the gates 104a or 104b.

[0085] Figure 2B shows the internal cell structure of the cell shown in Figure 2A, in which the front gate 104a, charge trapping layer 160a and a portion of BL 101 are removed.

[0086] Although the ONO layers 161a to 161c shown in Figure 2B are used as examples of charge trapping layers 160a and 160b, in other embodiments, charge trapping layers 160a and 160b comprise any suitable number of oxide and nitride layers. For example, in another embodiment, charge trapping layers 160a and 160b comprise an oxide-nitride-oxide-nitride-oxide (ONONO) layer. In another embodiment, charge trapping layers 160a and 160b comprise only one oxide layer and one oxide-nitride (ON) layer. These variations are all within the scope of the embodiments.

[0087] In various embodiments, charge trapping layers 160a and 160b are also used in other cell embodiments shown in Figures 1A to 1L to replace gate dielectric layers 105a and 105b to form different types of NOR flash memory cells.

[0088] Figure 2C shows another embodiment of the cell structure for 3D non-volatile random access memory constructed according to the present invention. This embodiment is similar to the embodiments shown in Figures 1A and 1B, except that gate dielectric layers 105a and 105b are replaced by non-volatile memory gate dielectric layers 170a and 170b. In one embodiment, non-volatile memory gate dielectric layers 170a and 170b comprise multiple layers, such as layers 171a and 171b.

[0089] Figure 2D shows the internal unit structure of the embodiment shown in Figure 2C, wherein the front gate 104a, the non-volatile memory gate dielectric layer 170a, and a portion of BL 101 are removed.

[0090] In one embodiment of forming ferroelectric random-access memory (FRAM), the non-volatile memory gate dielectric layer 170b includes a ferroelectric layer 171a, such as lead zirconate titanate (PZT) or hafnium oxide (HfO2) or hafnium dioxide (HfZrO2) in an oblique crystal phase. Layer 171b includes a dielectric layer, such as hafnium oxide (HfO2). When a high voltage is applied to the gates 104a and 104b, the resulting electric field changes the magnetic poles of the ferroelectric material in the ferroelectric layer 171a, thereby changing the threshold voltage of the cell to represent the stored data.

[0091] In another embodiment of forming resistive random-access memory (RRAM), the non-volatile memory gate dielectric layers 170a and 170b include an adjustable resistance layer 171a, such as hafnium oxide (HfOx), titanium oxide (TiOx), or tantalum oxide (TaOx), and a dielectric layer 171b, such as silicon oxide (SiO2). In another embodiment of forming phase-change memory (PCM), the non-volatile memory gate dielectric layers 170a and 170b consist of multiple layers including at least one phase change layer 171a, such as germanium-antimony-tellurium alloy or chalcogenide glass, Ge2Sb2Te5 (GST), and a heating layer 171b, such as tungsten (W), titanium (Ti), or polycrystalline silicon.

[0092] In another embodiment, a magnetoresistive random-access memory (MRAM) is formed, wherein the non-volatile memory gate dielectric layers 170a and 170 comprise multiple layers containing ferromagnetic materials 171a and 171b, such as an iron-nickel (NiFe) or iron-cobalt (CoFe) alloy, and a tunnel barrier layer, such as hafnium oxide (HfO2), formed between layers 171a and 171b. The materials of the aforementioned non-volatile memory gate dielectric layers 170a and 170b are merely examples; any other suitable material may be used within the scope of this embodiment for the non-volatile memory gate dielectric layers 170a and 170b.

[0093] The non-volatile memory gate dielectric layers 170a and 170b shown in this embodiment can also be used with all other cell embodiments shown in Figures 1A to 1L to replace gate dielectric layers 105a and 105b to form various types of non-volatile random access memory cells.

[0094] Figures 3A to 3C illustrate embodiments of a 3D array structure constructed according to the present invention. Figure 3A shows a 3D array formed using the cell structures shown in Figures 1C to 1D. However, in other embodiments, the 3D array structure is formed using any other cell structures shown in Figures 1A to 2D. The 3D array comprises multiple layers of vertically stacked cells. These cells are connected to vertical bit lines, such as vertical bit lines 101a to 101d. The 3D array includes multiple word line layers 104a to 104h, which are connected to the gates of the cells. The 3D array also includes multiple source line layers 103a to 103h. The intersection of one of the vertical bit lines 101a to 101d and one of the source lines 103a to 103h forms a cell, such as cell 120.

[0095] Figure 3B illustrates an embodiment of the bit lines constructed according to the present invention connected to the 3D array structure shown in Figure 3A. Vertical bit lines 101a to 101d are connected to horizontal bit lines 130a to 130d via a selection gate (e.g., selection gate 135a) and a contact (e.g., contact 137a). Horizontal bit lines 130a to 130d are formed of a conductive material, such as metal or heavily doped polysilicon. For example, the selection gate of selection gate 135a is formed of a vertical channel transistor. Selection gate lines 136a to 136d are connected to the control gate of the vertical channel selection gate of, for example, selection gate 135a.

[0096] The word line layers 104a to 104h and the source line layers 103a to 103h are connected to the word line decoder (not shown) and the source line voltage generator (not shown) respectively by forming a stepped structure for the word line and the source line at the edge of the array, as is the structure in a conventional 3D NAND flash memory.

[0097] Figure 3C shows another embodiment of the 3D array structure according to the present invention. The array is divided into multiple stacks by vertical slits 112a and 112b. Since each stack is connected to different word lines (such as 104 to 104h), vertical bit lines (such as 101a to 101c) can be connected to horizontal bit lines 130a to 130d without the need for a vertical selection gate (selection gate 135a as shown in Figure 3B).

[0098] 3D array structures can be used in various 3D NOR memory applications, such as dynamic random-access memory (DRAM), NOR flash memory, ferroelectric random-access memory (FRAM), resistive random-access memory (RRAM), phase-change memory (PCM), and magnetoresistive random-access memory (MRAM) using floating-body cells (FBC).

[0099] Furthermore, the 3D array structure can be applied to in-memory computing and 3D neural network arrays for artificial intelligence (AI) applications. For these applications, vertical bit lines 101a to 101d, word line layers 104a to 104h, and source line layers 103a to 103h are connected to the input neuron circuits and the output neuron circuits. Besides these applications, the novel 3D cell and array structure constructed according to this invention is also suitable for any other application.

[0100] Figures 4A to 4I illustrate an embodiment of the general process steps according to the present invention to form a 3D array comprising the cell structure shown in Figure 1A.

[0101] Figure 4A illustrates how multiple semiconductor layers 103a to 103g and multiple sacrificial layers 110a to 110f are deposited alternately to form a stack. In one embodiment, semiconductor layers 103a to 103g comprise silicon layers or polycrystalline silicon layers. Sacrificial layers 110a to 110f comprise oxide layers or nitride layers.

[0102] In one embodiment, semiconductor layers 103a to 103g are formed from amorphous silicon using processes such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process.

[0103] In one embodiment, after deposition, an annealing process is applied to transform amorphous silicon into polycrystalline silicon. In one embodiment, the annealing process utilizes low-temperature rapid thermal annealing, such as at 700 degrees Celsius for 4 minutes, or any other suitable annealing process.

[0104] Semiconductor layers 103a to 103g are doped during the deposition process using an in-situ doping process. For NMOS cells, N-type dopants, such as phosphine (PH3) or arsine (AsH3), are added during the deposition process. For PMOS cells, P-type dopants, such as diborane (B2H6), are added during the deposition process.

[0105] In another embodiment, semiconductor layers 103a to 103g are formed using a polycrystalline silicon deposition process, such as the high-temperature decomposition of silane (SiH4) at 580 to 650 degrees Celsius. This process forms a polycrystalline silicon layer on the surface of sacrificial layers 110a to 110f and releases hydrogen gas (H2).

[0106] In another embodiment, semiconductor layers 103a to 103g are formed using a silicon epitaxial growth process to form mono-silicon on the surface of sacrificial layers 110a to 110f. Because the silicon layers are grown layer by layer, this process may require a longer processing time.

[0107] The sacrificial layers 110a to 110f are formed using a deposition process, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process.

[0108] Figure 4B shows how a pattern is defined using a photolithography step, and then an anisotropic etching process, such as a deep trench process or a dry etching process, is used to etch through multiple semiconductor layers 103a to 103g and sacrificial layers 110a to 110f to form holes 111a to 111c for vertical bit lines, thereby forming multiple holes (or openings) for vertical bit lines, such as bit line holes 111a to 111c.

[0109] Figure 4C illustrates how floats (e.g., floats 102a to 102c) are formed using plasma doping (PLAD) or plasma immersion ion implantation (PIII), vapor phase doping, or any other suitable doping process. For NMOS cells, boron ions are implanted into N-type semiconductor layers 103a to 103g through holes 111a to 111c in the vertical bit lines using diborane / hydrogen (B2H6 / H2) plasma to form P-type floats 102a to 102c by inversion doping. For PMOS cells, phosphorus or arsenic ions are implanted into P-type semiconductor layers 103a to 103g using phosphine (PH3) or arsine (AsH3) plasma to form N-type floats 102a to 102c by inversion doping.

[0110] In one embodiment, the formation of the float requires special sidewall doping to create a P-type junction within an N-type polysilicon layer. This poses a significant challenge to conventional ion implantation or plasma doping because it requires directional properties of the applied electric bias on the wafer substrate. The next section reveals four innovative methods for forming P-type junctions via polysilicon sidewalls. [Spin-coating with organic or inorganic dopant materials]

[0111] The advantages of this method include lower costs for materials and capital equipment. Spin coating equipment is mature and readily available. The method includes the following process steps.

[0112] Coating: Referring to Figure 4C, the boron-containing material is coated using a spin-coating track after forming holes (e.g., holes 111a to 111c) in the vertical bit lines. The dopant material will fill the holes 111a to 111c in the vertical bit lines.

[0113] Curing: The wafer is processed in an atmospheric pressure furnace at a medium temperature (300 to 450 degrees Celsius) in an environment containing O2 (organic) or N2 (inorganic) to cure the material and form a thin capping film of oxidation or nitridation to prevent boron from diffusing from the holes 111a to 111c of the filled bit lines.

[0114] Drive-in: Increase the furnace temperature (950 to 1100 degrees Celsius) to drive the boron dopant into the required interface depth to form a float, such as float 102a to 102c, while converting the N-type amorphous silicon layer 103a to 103g into polycrystalline silicon.

[0115] Organic dopant layer stripping: Most of the carbon polymer material should have been oxidized and evaporated during the boron high-temperature drive-in process. However, plasma stripping is still required, followed by solvent / sulfuric acid cleaning to ensure the removal of all polymer residues. Figure 4D shows the array structure after this process step.

[0116] Inorganic dopant layer stripping: Silicon-containing spin-coated inorganic materials transform into silicon dioxide (SiO2) after high-temperature curing and driving processes. However, compared to conventional thermal oxidation and chemical vapor deposition (CVD) films, SiO2 films remain porous. Porous SiO2 can be etched away using specific concentrations of hydrogen fluoride (HF) or buffered oxide etchant (BOE). Figure 4D shows the array structure after this process step. Chemical vapor deposition (CVD) or atomic layer deposition (ALD)

[0117] The advantages of this method include ease of removing conformal dopant layer deposition. The method includes the following process steps.

[0118] Coating: Boron-containing SiO2 material is deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to conformally cover the entire sidewall of the holes 111a to 111c of the bit line.

[0119] Capping: During the drive-in step, a thin nitro oxide capping layer is formed by nitriding a top layer of SiO2 using (i) an undoped CVD / ALD thin oxide layer, (ii) a CVD / ALD thin nitride layer, or (iii) a nitrogen (N2) atmosphere. The exact type and thickness of the doped capping deposition need to be evaluated according to design rules to prevent boron dopant diffusion from affecting the required junction depth. However, even with a capping layer, the final deposition should not close / seal the bitline openings throughout the bitline channel and should leave sufficient gaps / openings extending to the bottom of the bitline to facilitate subsequent etching of the dopant layer. The exact type and thickness of the doped capping deposition can be evaluated according to design rules.

[0120] Drive-in: The wafer is loaded into an atmospheric pressure furnace and the furnace temperature is increased (950 to 1100 degrees Celsius) in an environment containing N2 to drive the boron dopant into the desired junction depth to form the floats 102a to 102c, while the N-type amorphous silicon layers 103a to 103g are converted into polycrystalline silicon.

[0121] Nitride cap removal: First, the wafer is immersed in diluted HF, and then immersed in standard phosphoric acid to remove the nitride cap and the sacrificial nitride layer.

[0122] Oxide stripping: SiO2 can be stripped using a specific concentration of HF or BOE. Figure 4D shows the array structure after this process step.

[0123] According to the present invention, the unconventional formation of the buoyancy body and the consistent control of the memory cell structure spanning extremely wide and high dimensions are key driving factors for this cell structure. The formation process has been described in the preceding paragraphs.

[0124] Consistency in the distribution and depth of dopant concentration across a wide horizontal plane and multiple vertical layers is crucial for ensuring cell performance and reliability.

[0125] Grain boundary diffusion is a first-order pathway for dopant inclusion in silicon. Conventional semiconductor methods for dopant inclusion and distribution are widely used through the following two approaches. [Ion Implantation]

[0126] In one embodiment, a bias electric field is applied to an ionized dopant material to bombard silicon in single-crystal or polycrystalline silicon. Due to the directional bombardment by the energized dopant, the silicon crystal structure is disrupted and becomes amorphous. Simultaneously, the dopant material penetrates into the silicon and is encapsulated within grain boundaries at the damaged depth. The doped silicon then repairs its crystal structure through a subsequent designed high-temperature heat treatment cycle, while simultaneously distributing the dopant gradient throughout the crystal structure up to the target depth. This method is widely used for device junction formation. [In-situ doping]

[0127] In one embodiment, the vapor-phase dopant is added during the thermal reaction of silane (SiH4) at approximately 400 to 600 degrees Celsius during low-pressure chemical vapor deposition (LPCVD). The resulting silicon will be amorphous at small grain sizes, with the initial dopant concentration confined within small grain boundaries. The doped amorphous silicon is then subjected to a subsequently designed high-temperature thermal treatment cycle, allowing the silicon grains to grow to the target stable grain size while redistributing the dopant within the polycrystalline structure. This method is widely used for polycrystalline silicon gate formation.

[0128] However, the formation of the float requires dopant diffusion through the sidewalls after polycrystalline silicon deposition, and does not require a bias electric field. This invention covers process steps and control parameters for achieving optimal float distribution, including (1) stable polycrystalline silicon grain size, and (2) dopant diffusion distribution and depth.

[0129] After the dopant source material is deposited in the bitline channel, sufficient thermal energy is applied to drive and diffuse the optimal dopant order into the silicon layer, while simultaneously promoting grain growth. As mentioned earlier, the dopant source is preferably SiO2 or an organic form deposited in the bitline channel via low-temperature CVD, ALD, or spin-coating. The dopant concentration and thermal cycling of the source material will determine the optimal float distribution.

[0130] To promote and achieve optimal float distribution, a low-temperature CVD or ALD deposition process, preferably using an amorphous silicon layer with a small grain size, is employed to allow dopants to begin initial diffusion across grain boundaries during the initial thermal cycling.

[0131] Optimal thermal cycling control parameters include inert gas environment (e.g., nitrogen (N2) or argon (Ar)), heating rate, target temperature (900 to 1100 degrees Celsius), duration, and duration of target temperature.

[0132] Figure 4D illustrates how holes in vertical bit lines (e.g., holes 111a to 111c in Figure 4C) are filled with semiconductor material (e.g., heavily doped polysilicon) to form vertical bit lines, such as vertical bit lines 101a to 101c. Semiconductors are deposited using any suitable deposition process, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process. The semiconductors of the bit lines (e.g., bit lines 101a to 101c) are heavily doped with the same type of doping as semiconductor layers 103a to 103g using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the bit line deposition process. For PMOS cells, a P-type dopant, such as diborane (B2H6), is added during the bit line deposition process.

[0133] Figures 4E to 4F illustrate embodiments of the fabrication steps for forming the cell structure shown in Figure 1C. After performing the fabrication steps shown in Figure 4C, the fabrication steps shown in Figure 4E are performed, wherein semiconductor layers 107a to 107c, such as polycrystalline silicon or silicon, are formed on the sidewalls of the holes 111a to 111c of the vertical bit lines using a deposition process depicted with reference to Figure 4A (e.g., atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process); or a single-crystal silicon layer is grown using an epitaxial growth process. Semiconductor layers 107a to 107c are doped with the same type of heavy doping as semiconductor layers 103a to 103g using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the 107 semiconductor layer deposition process. For PMOS cells, a P-type dopant, such as diborane (B2H6), is added during the 107 semiconductor layer deposition process.

[0134] Figure 4F illustrates how high-melting-point metals, such as tungsten (W), can be filled into the holes 111a to 111c of the vertical bit lines to form vertical bit lines, such as vertical bit lines 101a to 101c. Tungsten is deposited using any suitable deposition process, such as chemical vapor deposition (CVD) by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4). The metal bit lines 101a to 101c reduce the bit line resistivity.

[0135] Before depositing metal into the holes 111a to 111c of the vertical bit lines, adhesive layers such as titanium and titanium nitride (Ti / TiN) layers (not shown) can be formed on the surface of semiconductor layers 107a to 107c. The adhesive layers help prevent the metal bit lines 101a to 101c from peeling off from semiconductor layers 107a to 107c and improve reliability. The TiN and Ti layers are formed using chemical vapor deposition (CVD) and ion metal plasma (IMP) physical vapor deposition (PVD) processes, respectively. In various embodiments, the adhesive layer (e.g., the adhesive layer applied to semiconductor layer 107) is selectively applied and can be omitted if necessary.

[0136] Figure 4G illustrates how sacrificial layers 110a to 110f can be selectively removed using an isotropic etching process (such as wet etching). If the sacrificial layers 110a to 110f are oxide layers (SiO2), they can be etched using buffered hydrofluoric acid (HF), ammonium acid (NH4F), or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3). If the sacrificial layers 110a to 110f are nitride layers (Si3N4), they can be etched using concentrated hot orthophosphoric acid (H3PO4) at a temperature of 150 to 180 degrees Celsius.

[0137] Figure 4H shows how gate dielectric layers 105a to 105f, such as gate oxide (SiO2) layers or high-k material layers, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or titanium oxide (TiO2), are formed on the sidewall surfaces of the spaces previously occupied by sacrificial layers 110a to 110f. Gate dielectric layers 105a to 105f are formed by growing silicon oxide (SiO2) layers on the surfaces of semiconductor layers 103a to 103g and vertical bit lines (such as bit lines 101a to 101c) using thermal oxidation or dry oxidation, or by depositing a thin layer of gate dielectric material on the space surface using atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process.

[0138] Figure 4I shows how the space previously occupied by sacrificial layers 110a to 110f is filled with metallic materials, such as tungsten (W), tantalum (Ta), titanium (Ti), niobium (Nb) for NMOS cells, or ruthenium (Ru) for PMOS cells, or composite materials of metal nitrides, such as WN, TaN and TiN, or heavily doped polysilicon, to form the metal word lines (or gates) 104a to 104f of the cell transistor. The metal letter lines 104a to 104f are formed using deposition processes, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process. As a result, an array comprising the floating unit structure shown in Figure 1C is formed.

[0139] Figure 4J shows a diagram providing an overview of the process conditions and materials used for the process steps described in Figures 4A to 4I. It should be noted that these process conditions and materials are exemplary, and the same process results can be achieved using other suitable process conditions and materials. Therefore, such modifications and variations are within the scope of this invention. The diagram shown in Figure 4J illustrates process step 401, process type 402, temperature 403 for the process step, chemical materials used in the process step 404, and material concentration (CONC.) 405.

[0140] Figures 5A to 5C show embodiments of the general process steps for forming an array using the cell structure shown in Figure 1E according to the present invention.

[0141] Figure 5A shows the array structure formed after the process steps shown in Figures 4A to 4C. Readers can refer to Figures 4A to 4C for a detailed description of the array structure shown in Figure 5A.

[0142] Figure 5B illustrates how to form drain regions, such as drain regions 107a to 107c, by doping a heavy dopant of the opposite type into a float (e.g., floats 102a to 102c) using plasma doping, gate-phase doping, or any other suitable doping process. This doping process is performed through holes in vertical bit lines (e.g., bit line holes 111a to 111c). For NMOS cells, phosphorus or arsenic ions are implanted into a P-type float, such as floats 102a to 102c, using phosphine (PH3) or arsine (AsH3) plasma to form N+ drain regions, such as drain regions 107a to 107c, through reverse doping. For PMOS cells, diborane / hydrogen (B2H6 / H2) plasma is used to implant boron ions into N-type floats, such as floats 102a to 102c, to form P+ drain regions, such as drain regions 107a to 107c, through reverse doping.

[0143] After performing the process steps described with reference to FIG. 5B, the process steps shown in FIG. 4F to FIG. 4I are performed to form the array structure shown in FIG. 5C. The reader can refer to the detailed descriptions of these process steps in FIG. 4F to FIG. 4I. As a result, an array comprising floating unit structures formed as shown in FIG. 1E is formed.

[0144] Figures 6A to 6F illustrate a simplified process step for forming an array using the cell structure shown in Figure 1I according to the present invention.

[0145] Figure 6A shows the array structure formed after the process steps shown and described with reference to Figures 4A to 4B. The reader can refer to the detailed description of the process steps in Figures 4A to 4B for forming the array structure shown in Figure 6A. In this embodiment, the source line (SL) layers 103a to 103g are formed of a high-melting-point metal, such as tungsten (W). Tungsten is deposited using any suitable deposition process, such as chemical vapor deposition (CVD) by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4).

[0146] Figure 6B illustrates how an isotropic etching process (e.g., wet etching) is performed through holes in vertical bit lines (such as holes 111a to 111c) to selectively etch sacrificial layers 110a to 110f to form grooves, such as grooves 114a to 114c. The dimensions of grooves 114a to 114c are controlled by the etching rate and etching time of the etchant. If the first sacrificial layers 110a to 110f are formed of silicon oxide (SiO2), etching can be performed using buffered hydrofluoric acid (HF) and ammonium acid (NH4F) or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3).

[0147] Figure 6C illustrates how recesses (e.g., recesses 114a to 114c) and holes for vertical bit lines (e.g., holes for vertical bit lines 111a to 111c) are filled with a semiconductor material 116, such as polysilicon or silicon. In one embodiment, the polysilicon is formed using a polysilicon deposition process that includes a silicon epitaxial growth process as described with reference to Figure 4A. The reader can refer to the detailed description of the polysilicon deposition process in Figure 4A. The semiconductor material 116 is doped using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the deposition process. For PMOS cells, a P-type dopant, such as diborane (B2H6), is added during the deposition process.

[0148] Figure 6D illustrates how sacrificial layers 110a to 110f can be used as a hard mask to perform anisotropic etching processes, such as dry etching, to selectively etch semiconductor material 116 to reshape holes in vertical bit lines, such as holes 111a to 111c. Because this etching process is self-aligned, high yields can be achieved. After the holes in the vertical bit lines (e.g., holes 111a to 111c) are reshaped, the semiconductor material 116 in the recesses (e.g., recesses 114a to 114c) becomes a float for the unit transistor, such as floats 102a to 102c.

[0149] Figure 6E illustrates how holes in vertical bit lines (e.g., holes 111a to 111c) are filled with a high-melting-point metal (e.g., tungsten (W)) to form vertical metal bit lines, such as metal bit lines 101a to 101c. Tungsten is deposited using any suitable deposition process, such as chemical vapor deposition (CVD) by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4).

[0150] After filling the holes 111 of the vertical bit lines to form metal bit lines 101, process steps shown and described with reference to Figures 4G to 4I are performed to form the array structure shown in Figure 6F. For example, the sacrificial layer 110 is removed, and a gate dielectric layer 105 is deposited to form metal word lines 104. The reader can refer to the detailed description of these process steps in Figures 4G to 4I. In this embodiment, for example, the vertical bit lines such as metal bit lines 101a to 101c and the source line layers 103a to 103g are composed of metal. As a result, an array containing the floating unit structure shown in Figure 1I is formed.

[0151] Figures 7A to 7D show embodiments of simplified process steps for forming an array comprising the cell structure shown in Figure 1I according to the present invention.

[0152] Figure 7A shows the array structure constructed after performing the process steps shown in Figures 4A through 4D. The reader can refer to the detailed description of these process steps in Figures 4A through 4D. In this embodiment, layers 113a to 113g are formed of a second sacrificial material, such as an oxide or a nitride. The second sacrificial layers 113a to 113g and the first sacrificial layers 110a to 110f are configured to have different etching selectivity. For example, in one embodiment, the first sacrificial layers 110a to 110f are formed of an oxide, and the second sacrificial layers 103a to 103g are formed of a nitride.

[0153] Figure 7B illustrates how to selectively remove the second sacrificial layers 113a to 113g using an isotropic etching process (e.g., wet etching). If the second sacrificial layers 113a to 113g are formed of silicon oxide (SiO2), they can be etched using buffered hydrofluoric acid (HF) and ammonium acid (NH4F) or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3).

[0154] Figure 7C illustrates how a high-melting-point metal (e.g., tungsten (W)) is deposited to fill the space previously occupied by the second sacrificial layers 113a to 113g to form the metal source line layers 103a to 103g. Tungsten is deposited using any suitable deposition process, such as chemical vapor deposition (CVD) by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4).

[0155] Following the aforementioned metal deposition process, process steps shown and described with reference to Figures 4G to 4I are performed to form the array structure shown in Figure 7D. For example, the sacrificial layer 110 is removed, and the gate dielectric layer 105 is deposited to form metal word lines 104. The reader can refer to the detailed descriptions of these process steps in Figures 4G to 4I. As a result, an array comprising the floating unit structure shown in Figure 1I is formed.

[0156] Figures 8A to 8E show another embodiment of the simplified process steps for forming an array comprising the cell structure shown in Figure 1G according to the invention.

[0157] Figure 8A shows the array structure formed after performing the process steps shown in Figures 4A to 4F. The reader can refer to Figures 4A to 4F for a detailed description of the process steps for forming this array structure. In this embodiment, layers 113a to 113g are formed of a second sacrificial material, such as an oxide or a nitride. The second sacrificial layers 113a to 113g and the first sacrificial layers 110a to 110f are configured to have different etching selectivity. For example, in one embodiment, the first sacrificial layers 110a to 110f are formed of an oxide, and the second sacrificial layers 103a to 103g are formed of a nitride.

[0158] Figure 8B illustrates how to selectively remove the second sacrificial layers 113a to 113g using an isotropic etching process (e.g., wet etching). If the second sacrificial layers 113a to 113g are formed of silicon oxide (SiO2), they can be etched using buffered hydrofluoric acid (HF) and ammonium acid (NH4F) or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3).

[0159] Figure 8C shows how to use plasma doping (PLAD) or vapor phase doping processes or any other suitable doping process to reverse the doping type of the float, such as floats 102a to 102c, with the opposite type of heavy dopant, thereby forming source regions, such as source regions 108a to 108c.

[0160] Figure 8D illustrates how a high-melting-point metal (e.g., tungsten (W)) is deposited to fill the space previously occupied by the second sacrificial layers 113a to 113g to form the metal source line layers 103a to 103g. The tungsten is deposited using any suitable deposition process, such as chemical vapor deposition (CVD) by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4).

[0161] After depositing the metal as described above, the process steps shown in Figures 4G to 4I are performed to form the array structure shown in Figure 8E. For example, the first sacrificial layer 110 is removed, the gate dielectric layer 105 is deposited, and the metal word line 104 is formed. The reader can refer to the detailed description of these process steps in Figures 4G to 4I. As a result, an array containing the floating unit structure shown in Figure 1G is formed.

[0162] Figures 9A to 9C show alternative embodiments for forming source regions (e.g., source regions 108a to 108c) for an array having the cell structure shown in Figure 1G. The process steps shown in Figure 9A are performed after the process steps shown and described with reference to Figure 8B.

[0163] Figure 9A shows how semiconductor layers 108a to 108g (e.g., polysilicon or silicon) are formed on the sidewall surfaces of the space previously occupied by the second sacrificial layers 113a to 113g. Each semiconductor layer 108 forms a source region, such as source regions 108a(1) to 108a(3), on the sidewall of the float (e.g., floats 102a to 102c).

[0164] In one embodiment, the semiconductor layer 108 is formed by a polysilicon deposition process or a silicon epitaxial growth process as described with reference to FIG4A. The semiconductor layer 108 is doped using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the deposition process. For PMOS cells, a P-type dopant, such as diborane (B2H6), is added during the deposition process.

[0165] Figure 9B illustrates how a high-melting-point metal (such as tungsten (W)) is deposited to fill the space previously occupied by the second sacrificial layers 113a to 113g to form metal source line layers 103a to 103g. The tungsten is deposited using any suitable deposition process, such as chemical vapor deposition (CVD) by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4). After metal deposition, process steps are performed with reference to Figures 4G to 4I to form the array structure shown in Figure 9C. For example, the first sacrificial layer 110 is removed, a gate dielectric layer 105 is deposited, and metal word lines 104 are formed. The reader can refer to the detailed descriptions of these process steps in Figures 4G to 4I.

[0166] Figures 10A to 10E show another embodiment of simplified process steps performed to form an array comprising the cell structure shown in Figure 1K according to the invention.

[0167] Figure 10A shows the array structure constructed after performing the process steps shown in Figures 6A to 6B. Readers can refer to the detailed description of the process steps performed in Figures 6A to 6B to form this array structure.

[0168] Figure 10B illustrates how a semiconductor layer 115 (e.g., silicon, polycrystalline silicon, silicon-germanium (SiGe), indium gallium zinc oxide (IGZO), tungsten-doped indium oxide semiconductor, or any other suitable semiconductor material) is formed in the sidewall surfaces of the recess 114 (e.g., recesses 114a to 114c) and in the holes (e.g., 111a to 111c) of the vertical bit lines using an epitaxial or deposition process as described with reference to Figure 4A. The reader can refer to the detailed description of these processes in Figure 4A.

[0169] Figure 10C shows that after the semiconductor layer 115 is formed, an insulating material 116 (e.g., oxide or nitride) is deposited to fill the trenches (e.g., trenches 114a to 114c) and the holes 111a to 111c of the vertical bit lines.

[0170] Figure 10D illustrates how sacrificial layers 110a to 110f and semiconductor layer 115 are used as a hard mask to selectively etch insulating material 116 within holes in vertical bit lines (e.g., bit line holes 111a to 111c) for an anisotropic etching process (e.g., dry etching). Because this etching process is self-aligned, high yields are achieved.

[0171] After the above etching process, the holes of the vertical bit lines (e.g., bit line holes 111a to 111c) are filled with a conductive material such as metal or polysilicon using a deposition process to form vertical bit lines (e.g., bit lines 101a to 101c). Then, the process steps shown and described with reference to Figures 4G to 4I are performed to form the array structure shown in Figure 10E. For example, the first sacrificial layer 110 is removed, the gate dielectric layer 105 is deposited, and the metal word line 104 is formed. The reader can refer to the detailed description of these process steps in Figures 4G to 4I. As a result, an array containing the floating unit structure shown in Figure 1K is formed.

[0172] Figures 11A to 11D show another embodiment of a simplified process step configured to form an array comprising the cell structure shown in Figure 1M according to the invention.

[0173] Figure 11A shows the array structure produced after performing the process steps shown in Figures 6A to 6B. The reader can refer to the detailed description of the process steps performed in Figures 6A to 6B to form this array structure.

[0174] Figure 11B illustrates how a first semiconductor layer 118 (e.g., silicon or polysilicon) is formed on the sidewall surfaces of the recesses (e.g., recesses 114a to 114c) and in the holes of vertical bit lines (e.g., bit line holes 111a to 111c) using the silicon epitaxial process or polysilicon deposition process described with reference to Figure 4A. The reader can refer to the detailed description of these processes in Figure 4A.

[0175] After forming the first semiconductor layer 118, a second semiconductor material 119 is deposited to fill the trenches (e.g., trenches 114a to 114c) and the holes of the vertical bit lines (e.g., bit line holes 111a to 111c). In one embodiment, the second semiconductor material 119 is different from the first semiconductor layer 118. For example, in one embodiment, the first semiconductor layer 118 is formed of silicon or polycrystalline silicon, and the second semiconductor material 119 includes silicon germanium (SiGe), silicon carbide (SiC), or any other suitable semiconductor material.

[0176] Figure 11C illustrates how sacrificial layers 110a to 110f are used as a hard mask to perform an anisotropic etching process (e.g., dry etching) to selectively etch semiconductor layer 118 and second semiconductor material 119 within holes in vertical bit lines (e.g., bit line holes 111a to 111c). Because this etching process is self-aligned, high process yields can be achieved. After forming the holes in the vertical bit lines (e.g., bit line holes 111a to 111c), semiconductor layers 118a to 118c become individual floats for each cell, and second semiconductor materials 119a to 119c become second semiconductor regions for charge storage.

[0177] Following the etching process described above, the process steps shown in Figures 4E to 4I are performed to form the array structure shown in Figure 11D. For example, the first sacrificial layer 110 is removed, a gate dielectric layer 105 is deposited, a metal word line 104 is formed, a semiconductor layer 107 is deposited, and a vertical bit line 101 is formed. The reader can refer to the detailed descriptions of these process steps in Figures 4E to 4I. As a result, the array shown in Figure 11D is formed, which includes the floating cell structure shown in Figure 1M.

[0178] Figures 12A to 12E show another embodiment of a simplified process step configured to form an array comprising the cell structure shown in Figure 10 according to the invention.

[0179] Figure 12A shows the array structure produced after performing the process steps shown in Figures 4A to 4C. The reader can refer to the detailed description of the process steps used to form this array structure in Figures 4A to 4C.

[0180] Figure 12B illustrates how an isotropic etching process, such as wet etching, is performed through holes in vertical bit lines (e.g., bit line holes 111a to 111c) to selectively etch floats (e.g., floats 102a to 102c) to form recesses (e.g., recesses 114a to 114c). In another embodiment, the float 102 is formed after the recess 114 is formed. In this embodiment, after performing the process steps shown in Figure 4B, an isotropic etching process (e.g., wet etching) is performed through holes in vertical bit lines (e.g., bit line holes 111a to 111c) to selectively etch semiconductor layers 103a to 103g to form recesses (e.g., recesses 114a to 114c). Next, as shown in Figure 12B, an isotropic doping process (e.g., plasma doping or vapor phase doping) is performed to dope the semiconductor layers 103a to 103g with dopants of the opposite type to those used for the semiconductor layers 103a to 103g to form a float (e.g., floats 102a to 102c).

[0181] Figure 12C illustrates how a semiconductor material 109, such as semiconductors 109a to 109c, different from the material of the float 102, is deposited by filling the holes 111 and grooves 114 of the vertical bit lines using an appropriate deposition process. For example, in one embodiment, if the float 102 is formed of silicon or polycrystalline silicon, the semiconductor material 109 is formed of silicon germanium (SiGe) or silicon carbide (SiC).

[0182] Figure 12D illustrates how sacrificial layers 110a to 110f are used as a hard mask to selectively etch semiconductor material 109 to reshape the holes 111 of the vertical bit lines to perform an anisotropic etching process (e.g., dry etching). Because this etching process is self-aligned, high process yields can be achieved. As described with reference to Figure 10, after the holes 111 of the vertical bit lines are reshaped, the semiconductor material remaining in the grooves becomes semiconductor regions 109 (e.g., regions 109a to 109c), which form quantum wells to store charge, for example, by means of storage holes.

[0183] Figure 12E shows the array structure produced after performing the process steps shown in Figures 4E to 4I. The reader can refer to the detailed descriptions of these process steps in Figures 4E to 4I. For example, the first sacrificial layer 110 is removed, a gate dielectric layer 105 is deposited, a metal word line 104 is formed, a semiconductor layer 107 is deposited, and vertical bit lines 101 are formed. As a result, the array shown in Figure 12E is formed, which includes the floating cell structure shown in Figure 10.

[0184] While exemplary embodiments of the invention have been shown and described, it will be apparent to those skilled in the art, based on the teachings herein, that changes and modifications may be made without departing from the exemplary embodiments and their broader forms. Therefore, the appended claims are intended to include all such changes and modifications within the true spirit and scope of the exemplary embodiments of the invention.

[0185] 101: (Metallic) Bit Line / BL 101a: (Vertical) Bitline / Bitline Structure 101b~101d: (Vertical) Bit Line / Vertical Metal Bit Line 102: Floating body (material) / Floating body semiconductor / P-type floating body 102a~102e: Floating body 103: Source Line / SL 103a~103d: Source line (structure) / (metal) source line layer / horizontal bit line / semiconductor layer 103e: Source line (structure) / (metal) source line layer / semiconductor layer 103f~103g: (Metal) Source line layer / source line / semiconductor layer 103h: Source line layer / source line 104: Word line / (WL) 104a: (Front) Gate / Word Line / Word Line Structure / Word Line Layer / Metallic Word Line 104b: (Back) Gate / Word Line / Word Line Structure / Word Line Layer / Metallic Word Line 104c~104h: Character line (structure) / Character line layer / Metal character line 105: Dielectric layer 105a: Gate dielectric layer / First dielectric layer / Dielectric layer 105b: Gate dielectric layer / Second dielectric layer / Dielectric layer 106a, 106b: Insulating layer / charge trapping layer 107: Drain region / semiconductor layer 107a~107c: Semiconductor layer / drain region 108, 108a~108c: Source region / semiconductor layer 108d~108g: Semiconductor layer 108a(1)~108a(3): Source region 109: Semiconductor layer / semiconductor region / semiconductor material 109a~109c: Semiconductor / Region 110: First Sacrifice Layer 110a~110f: (First) Sacrificial Layer 111: Holes in vertical bit lines 111a~111c: Holes in vertical bit lines 112a, 112b: Vertical slits 113a~113g: Layer / Second Sacrificial Layer 114, 114a~114c: Grooves 115: Semiconductor layer 116, 116a: Insulator / Semiconductor Materials 118: First semiconductor layer 118a~118c: Semiconductor layer 119, 119a~119c: Second semiconductor material / second semiconductor region 120: Unit 130a~130d: Horizontal Pixel Lines 135a: (Vertical) Selective Gate 136a~136d: Select gate line 137a:Contact 161a~161b: Nitrided layer 170a, 170b: Gate dielectric layer 171a, 171b: Layer / Ferromagnetic material 301a~301h: Transistors 401: Process Steps 402: Process Type 403: Temperature 404: Chemical Materials 405: Concentration (CONC.) 1002: Inner surface 1004: Outer surface 1006: Bottom 1008: Top surface 1010: Inner surface 1012: Rear Gate Channel (BGC) 1014: Front Gate Channel (FGC) FB0~FB4: floating body SL0~SL4: Source lines WL0~WL3: Bit lines

Claims

1. A memory cell manufacturing process, comprising: Multiple semiconductor layers and sacrificial layers are alternately deposited to form a stack; A deep trench process is used to form holes for vertical bit lines on the stack; The holes of the vertical bit lines are coated with a boron-doped material; the boron-doped material is cured to form a capping layer to prevent outward diffusion; high-temperature driving is performed to diffuse boron into the semiconductor layer and crystallize a portion of the semiconductor layer to form polycrystalline silicon; any residual doped layer is removed from the holes of the vertical bit lines to form a float in the semiconductor layer; a conductor material is deposited to fill the holes of the bit lines. Remove the sacrificial layer; A gate dielectric layer is deposited between the semiconductor layers; And depositing the gate material onto the gate dielectric layer.

2. The memory cell manufacturing process as described in claim 1, wherein, The boron-doped material includes boron-doped silicon dioxide (BSG) conformally doped on the sidewalls of the holes in the vertical bit lines by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

3. The memory cell manufacturing process as described in claim 1, wherein, The capping layer includes one of the following: an undoped oxide layer, a nitride layer, or a nitrogen oxide layer formed by nitriding the top of the boron-doped material in a nitrogen-containing environment.

4. The memory cell manufacturing process as described in claim 1, wherein, The high-temperature induction system is performed in a nitrogen-containing atmosphere at a temperature between 950 and 1100 degrees Celsius, while simultaneously forming a P-type float by diffusing boron into the semiconductor layer and converting the amorphous silicon in the semiconductor layer into polycrystalline silicon.

5. The memory cell manufacturing process as described in claim 1, wherein, The conductor material deposited to fill the holes in the bit lines includes high-melting-point metals selected from the group consisting of tungsten (W), tantalum (Ta), titanium (Ti), and niobium (Nb).

6. The memory cell manufacturing process as described in claim 1, wherein, The float formed in the semiconductor layer includes P-type polysilicon surrounding each vertical bit line and connected to a horizontal source line formed of either polysilicon or a metal, thereby forming a three-dimensional (3D) NOR type float memory cell.

7. The memory cell process as described in claim 1, further comprising forming a drain region adjacent to the bit line by heavy doping with a conductivity type opposite to that of the float, wherein the drain region is formed in a portion of the float before the holes are filled with a conductive material, the portion being adjacent to the holes of the vertical bit line.

8. The memory cell process as described in claim 1, further comprising forming a source region between the float and the source line, wherein the source region comprises a heavily doped semiconductor material having a conductivity type opposite to that of the float.

9. The memory cell process of claim 1, wherein the semiconductor layer comprises N-type amorphous silicon before the high-temperature drive-in and the float comprises P-type polycrystalline silicon after boron diffusion and crystallization, and wherein the gate material comprises a metal selected from the group consisting of tungsten, tantalum, titanium nitride and ruthenium.

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