Non-volatile semiconductor memory devices

Abstract

This invention provides a non-volatile semiconductor memory device capable of high-density stacking at low cost. According to an embodiment, the non-volatile semiconductor memory device of this invention includes: a plurality of first wiring layers, all stacked separately; memory pillars passing through the plurality of first wiring layers; region bit lines connected to the memory pillars; bit lines; a plurality of second wiring layers, all stacked separately; a first pillar connected to the region bit lines through the plurality of second wiring layers; a second pillar connected to the bit lines and connected to the first pillar through the plurality of second wiring layers; a plurality of third wiring layers, all stacked separately; and a third pillar connected to the bit lines through the plurality of third wiring layers. At least one of the plurality of third wiring layers is connected to the region bit lines.

Description

Technical Field

[0001] This invention relates to a non-volatile semiconductor memory device. Prior Technology

[0002] As a type of non-volatile semiconductor memory device, a 3D stacked NAND (Not and) type flash memory with memory cells arranged in 3D is known. Summary of the Invention

[0003] In one embodiment of the present invention, a non-volatile semiconductor memory device that can be multiplyed at low cost is provided.

[0004] An embodiment of a non-volatile semiconductor memory device includes: a plurality of first wiring layers extending in a first direction and stacked separately in a second direction intersecting the first direction; memory pillars extending in the second direction and passing through the plurality of first wiring layers; region bit lines separated from the plurality of first wiring layers at one end of the plurality of first wiring layers in the second direction and extending in a third direction intersecting the first and second directions, electrically connected to one end of the memory pillars in the second direction; bit lines separated from the region bit lines at one end of the region bit lines in the second direction and extending in the third direction; and a plurality of second wiring layers extending in the first direction. The system comprises: a first post extending in the second direction, which is electrically connected to a region bit line at one end in the second direction via a plurality of second wiring layers; a second post extending in the second direction, which is electrically connected to a bit line at one end in the second direction via a plurality of second wiring layers and is electrically connected to the first post; a plurality of third wiring layers extending in the first direction, which are stacked separately in the second direction and arranged with the plurality of first wiring layers in the third direction; and a third post extending in the second direction, which is electrically connected to a bit line at one end in the second direction via a plurality of third wiring layers. At least one of the plurality of third wiring layers is electrically connected to the region bit line. Simple Explanation of the Diagram

[0005] Figure 1 is the equivalent circuit diagram of the gain block in the first embodiment. Figure 2 is a block diagram showing an example of the configuration of the memory cell array in the first embodiment. Figure 3 is a cross-sectional view of the bit line direction of the gain block in the first embodiment. Figure 4 is a top view showing an example of the plan layout of the write port in the first embodiment. Figure 5A is a top view showing a first example of the plan layout of the reading port in the first embodiment. Figure 5B is a top view showing a second example of the plan layout of the reading port in the first embodiment. Figure 6A is a cross-sectional view of the writing port cut along lines A1-A2 and B1-B2 in Figure 4. Figure 6B is a cross-sectional view of the reading port section cut along lines C1-C2 and D1-D2 of Figure 5A. Figure 7A is a layout diagram showing an example of the chip configuration of a non-volatile semiconductor memory device according to the first embodiment. Figure 7B is a cross-sectional view of the WL plane of the cell block corresponding to the first embodiment. Figure 7C shows an example of bonding an array chip and a CMOS chip in a non-volatile semiconductor memory device according to the first embodiment. Figure 7D shows a cross-sectional view of the memory cell array process layer and the transistor section below in a non-volatile semiconductor memory device according to the first embodiment. Figure 8 is a graph showing the relationship between the number of gain blocks (bit line divisions) per bit line layer of the memory cell array, the number of word line stacks that can be integrable, and the ratio of gain block consumption to the memory cell array. Figure 9 is a graph showing a comparison of the chip size between the comparative example and the embodiment when the processing speed is increased by 4 times. Figure 10 is a graph showing a comparison of the chip size between a comparative example and an embodiment when the memory capacity is increased by 4 times. Figure 11 shows the relationship between the number of gain blocks, (a) read latency (tR), and (b) wafer size for each bit line layer of the memory cell array. Figure 12 shows the relationship between memory capacity and chip size under constant speed conditions when increasing memory capacity by stacking word lines of 3D (Dimension)-NAND flash memory. Figure 13 shows the relationship between memory capacity and cost per gigabyte (GB) when increasing memory capacity by stacking word lines of 3D-NAND flash memory. Figure 14A is a top view showing the first example of the plan layout of the reading port in the second embodiment. Figure 14B is a top view showing a second example of the plan layout of the reading port in the second embodiment. Figure 14C is a cross-sectional view of the read port in the direction of the bit line in the second embodiment. Figure 15 is the equivalent circuit diagram of the gain block in the third embodiment. Figure 16 is a cross-sectional view of the bit line direction of the gain block in the third embodiment. Figure 17A is a cross-sectional view of the character line direction of the write port in the third embodiment. Figure 17B is a cross-sectional view of the character line direction of the read port in the third embodiment. Figure 18 is the equivalent circuit diagram of the gain block in the fourth embodiment. Figure 19 is a cross-sectional view of the bit line direction of the gain block in the fourth embodiment. Figure 20A is a cross-sectional view of the character line direction of the write port in the fourth embodiment. Figure 20B is a cross-sectional view of the character line direction of the read port in the fourth embodiment. Figure 21A shows the simplified equivalent circuit diagram of the gain block in the fifth embodiment. Figure 21B is a timing diagram showing an example of the voltage of each wiring during the write operation of a non-volatile semiconductor memory device in the fifth embodiment. Figure 21C is a timing diagram showing an example of the voltage of each wiring during the readout operation of a non-volatile semiconductor memory device in the fifth embodiment. Figure 22A is a timing diagram showing an example of the voltage of each wiring in a non-volatile semiconductor memory device according to the sixth embodiment, when performing a readout operation to reduce coupling noise between regional bit lines. Figure 22B is a cross-sectional view showing an example of a cross-sectional structure for reducing coupling noise between region bit lines in a non-volatile semiconductor memory device of the sixth embodiment. Figure 23 is a top view showing an example of the plan layout of the write port in the sixth embodiment. Figure 24 is a timing diagram showing an example of the voltage of each wiring in a non-volatile semiconductor memory device according to the seventh embodiment, when performing a readout operation to reduce coupling noise between region bit lines. Figure 25A is a timing diagram showing an example of a method for measuring the threshold voltage of the amplified transistor in the eighth embodiment. Figure 25B shows a timing diagram of a method for increasing the threshold voltage of the amplifying transistor in the eighth embodiment. Figure 25C shows a timing diagram of a method for reducing the threshold voltage of the amplifying transistor in the eighth embodiment. Figure 26A is a timing diagram showing the first example of a method for increasing the threshold voltage of the amplifying transistor in the ninth embodiment. Figure 26B is a timing diagram showing a second example of a method for increasing the threshold voltage of the amplifying transistor in the ninth embodiment. Figure 27A shows a timing diagram of a method for increasing the threshold voltage of the amplifying transistor in the 10th embodiment. Figure 27B shows a timing diagram of a method for reducing the threshold voltage of the amplifying transistor in the 10th embodiment. Figure 28A is a top view showing the first example of the plan layout of the reading port in the 11th embodiment. Figure 28B is a top view showing the second example of the plan layout of the reading port in the 11th embodiment. Figure 29 is a cross-sectional view of the bit line direction of the gain block in the 12th implementation. Figure 30 is a cross-sectional view of the bit line direction of the gain block in the 13th embodiment. Figure 31 shows an example of the cross-sectional structure of the gain block in the array chip of the non-volatile semiconductor memory device of the 14th embodiment along the bit line direction, and an example of the circuit configuration of the CMOS chip connected to the regional bit line. Figure 32A is a cross-sectional view of a memory cell array that can be applied to the implementation form. Figure 32B is a cross-sectional view along line E1-E2 of Figure 32A. Figure 32C shows a top view of the first example of a planar layout of a memory cell array that can be applied to an implementation configuration. Figure 32D shows a top view of a second example of a planar layout of a memory cell array that can be applied to an implementation form. Figure 33A is a graph comparing the silicon mobility required to increase the number of word lines stacked in 3D-NAND flash memory with a comparative example and an embodiment. Figure 33B is a circuit diagram showing an example of the circuit configuration used for the memory cell string calculated in Figure 33A. Implementation

[0006] The embodiments will now be described with reference to the diagrams. In the following description, constituent elements having the same function and structure will be marked with a common reference symbol. Furthermore, when distinguishing multiple constituent elements with a common reference symbol, a subscript will be used to differentiate the common reference symbol. Alternatively, when multiple constituent elements do not require special differentiation, only the common reference symbol will be used for each constituent element, without a subscript. Here, the subscript is not limited to subscripts or superscripts; it may include lowercase letters added to the end of the reference symbol and indexes indicating arrangement.

[0007] Before describing embodiments of the present invention, an example of the construction of a memory cell contemplated for application in the embodiments will be described below with reference to FIGS. 32A, 32B, 32C, and 32D. FIG. 32A is a cross-sectional view showing an example of a memory cell array applicable to the embodiments. FIG. 32B is a cross-sectional view along line E1-E2 of FIG. 32A. The example shown in FIG. 32B shows the cross-sectional structure of a memory cell cut along a word line. FIG. 32C is a top view showing a first example of a planar layout of a memory cell array applicable to the embodiments. FIG. 32D is a top view showing a second example of a planar layout of a memory cell array applicable to the embodiments. Furthermore, in the following description, the extension direction of a word line parallel to the substrate (silicon substrate) and described later will be denoted as the "X direction" or "word line direction". The extension direction of a bit line parallel to the substrate and intersecting the X direction and described later will be denoted as the "Y direction" or "bit line direction". The direction orthogonal to the XY plane parallel to the substrate is denoted as the "Z direction". Furthermore, since multiple character lines are stacked in the Z direction, it is also denoted as the "stack layer direction". When the Z direction is defined as the direction from the substrate toward the stack layer, it is also denoted as the "up direction" or "one end of the Z direction". When the Z direction is defined as the direction from the stack layer toward the substrate, it is also denoted as the "down direction" or "the other end of the Z direction".

[0008] First, the cross-sectional structure of the memory cell is explained using Figures 32A and 32B.

[0009] As shown in Figure 32A, the memory cell array includes insulating layers 11, 13 and 15, semiconductor layer 12, wiring layer 14, memory pillar MP, contact plug CP1, component SLT and component SHE1.

[0010] A semiconductor layer 12 is disposed on the insulating layer 11. The semiconductor layer 12 has a plate-like shape extending along the XY plane. The semiconductor layer 12 contains, for example, silicon (Si). Furthermore, the semiconductor layer 12 contains, for example, phosphorus (P) as an impurity in the semiconductor. The semiconductor layer 12 functions, for example, as the source line SL described later.

[0011] An insulating layer 13 is disposed on the semiconductor layer 12. On the insulating layer 13, a plurality of wiring layers 14 and a plurality of insulating layers 15 are stacked alternately layer by layer. In other words, the plurality of wiring layers 14 are stacked separately from each other in the Z direction. The plurality of wiring layers 14 are simply referred to as "stacked layers".

[0012] In the example shown in Figure 32A, the stacked layer includes 2009 wiring layers 14. Multiple wiring layers 14, located away from the semiconductor layer 12 (source line SL) (upper layer), function as 3-layer string selection signal lines SGDT, 3-layer string selection signal lines SGD, 2000-layer word lines WL0~WL1999, and 3-layer string selection signal lines SGS, respectively.

[0013] The character line WL is the gate line of the memory cell. Hereinafter, when limiting the function of the character line WL to wiring layer 14, wiring layer 14 will also be referred to as the "character line layer". Furthermore, the number of character line WL layers is arbitrary. The character line WL only needs to have one or more layers.

[0014] The string selection signal lines SGS, SGD, and SGDT are the gate lines of the string selection transistor. Hereinafter, when limiting the wiring layer 14 to function as the string selection signal lines SGS, SGD, and SGDT, wiring layer 14 is also referred to as the "string selection signal layer". Furthermore, the string selection signal lines SGS, SGD, and SGDT are arbitrary. Each of the string selection signal lines SGS, SGD, and SGDT only needs to be provided on one or more layers.

[0015] Insulating layers 13 and 15 may include, for example, silicon oxide (SiO). The conductive material of wiring layer 14 may be, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). In this case, titanium nitride is formed to cover tungsten. Titanium nitride, for example, functions as a barrier layer to inhibit tungsten oxidation or as an adhesion layer to improve the adhesion of tungsten when tungsten is deposited by CVD (Chemical Vapor Deposition). Furthermore, wiring layer 14 may include a high-dielectric-constant material such as aluminum oxide (AlO). In this case, the high-dielectric-constant material is formed to cover the conductive material. The high-dielectric-constant material is at least disposed between the memory pillar MP (described later) and the conductive material of wiring layer 14.

[0016] In the example shown in Figure 32A, a memory via MH is formed that penetrates the 2009 layer wiring layer 14 (i.e., the stacked layer). The bottom surface of the memory via MH (i.e., the memory pillar MP) reaches the semiconductor layer 12. For example, the memory via MH has a generally cylindrical shape extending in the Z direction. The memory pillar MP is formed by embedding the memory via MH. That is, the memory pillar MP has a generally cylindrical shape extending in the Z direction.

[0017] A memory cell is formed by combining a memory column MP with a wiring layer 14 (i.e., a word line layer) that functions as a word line WL. In other words, a memory cell with the word line layer as the gate electrode is formed. Similarly, a string select transistor is formed by combining a memory column MP with a wiring layer 14 (i.e., a string select signal layer) that functions as a string select signal line SGS, SGD, or SGDT. In other words, a string select transistor with the string select signal layer as the gate electrode is formed. A plurality of memory cells MC, each consisting of a memory column MP, and a plurality of string select transistors are connected in series to form a string of memory cells. Therefore, one memory column MP functions as one string of memory cells. Alternatively, the memory column MP can also be constructed with a plurality of columns connected in the Z direction.

[0018] The memory column MP includes a core membrane 20, a silicon channel layer 21, and a stacked membrane 22.

[0019] The core membrane 20 extends in the Z direction. For example, the core membrane 20 has a generally cylindrical shape extending in the Z direction. For example, the upper end of the core membrane 20 is located above the uppermost wiring layer 14, and the lower end is located below the lowermost wiring layer 14. The core membrane 20 may contain an insulator such as silicon oxide.

[0020] The silicon channel layer 21 extends in the Z direction and covers the side surface, top surface (the side facing the Z direction), and bottom surface of the core film 20. For example, the bottom surface of the silicon channel layer 21 is in contact with the semiconductor layer 12. The silicon channel layer 21 is used as a channel (current path) for memory cells and string selection transistors. The silicon channel layer 21 contains silicon.

[0021] The laminated film 22 extends in the Z direction and covers the side surface of the silicon channel layer 21. For example, the laminated film 22 has a generally cylindrical shape extending in the Z direction. The outer side surface of the laminated film 22 is in contact with the memory via MH. The inner side surface of the laminated film 22 is in contact with the silicon channel layer 21.

[0022] As shown in Figure 32B, the laminated film 22 includes, for example, a tunnel insulating layer 221, a charge trapping layer 222, and a block insulating layer 223.

[0023] In a cross-section including the wiring layer 14 along the XY plane, the core film 20 is, for example, disposed in the center of the memory pillar MP. A silicon channel layer 21 surrounds the outer periphery (side) of the core film 20. A tunnel insulation layer 221 surrounds the outer periphery (side) of the silicon channel layer 21. A charge trapping layer 222 surrounds the outer periphery (side) of the tunnel insulation layer 221. A barrier insulation layer 223 surrounds the outer periphery (side) of the charge trapping layer 222. The wiring layer 14 surrounds the outer periphery of the barrier insulation layer 223. The outer periphery (side) of the barrier insulation layer 223 is in contact with the wiring layer 14.

[0024] The tunnel insulation layer 221 and the barrier insulation layer 223, for example, contain silicon oxide. The charge trapping layer 222 has the function of accumulating charge. The memory cell can be of type FG (Floating Gate) or type MONOS (Metal-Oxide-Nitride-Oxide-Silicon). The FG type uses a conductor for the charge trapping layer 222. The MONOS type uses an insulating layer (e.g., containing silicon nitride (SiN)) for the charge trapping layer 222. Alternatively, if, for example, the wiring layer 14 uses aluminum oxide as a high dielectric constant material, the memory cell is also designated as type MANOS (Metal-Aluminum-Nitride-Oxide-Silicon). The memory cell stores information based on a threshold voltage by releasing or injecting electrons through FN (Fowler-Nordheim) tunneling into the charge trapping layer 222.

[0025] As shown in Figure 32A, a contact plug CP1 is disposed on the silicon channel layer 21 of the memory cylinder MP. The contact plug CP1 has, for example, a generally cylindrical shape extending in the Z direction. The contact plug CP1 contains, for example, tungsten or copper (Cu) as a conductive material.

[0026] The component SLT separates a plurality of wiring layers 14 (i.e., stacked layers) in the Y direction. The wiring layers 14 separated by the component SLT extend in the X direction. That is, the character line layer and the serial select signal layer extend in the X direction. The component SLT includes a conductor LI and a spacer SP. The conductor LI has a plate-like shape extending along the XZ plane. For example, the bottom surface of the conductor LI is in contact with the semiconductor layer 12. That is, the conductor LI is connected to the source line SL. The spacer SP is provided in such a way that it covers the side of the conductor LI. That is, the spacer SP is provided between the conductor LI and the wiring layer 14. The conductor LI and the wiring layer 14 are insulated by the spacer SP. The conductor LI may contain tungsten as a conductive material, for example. The spacer SP may contain an insulator such as silicon oxide. Alternatively, the conductor LI may be omitted. That is, the component SLT may also be embedded in an insulator.

[0027] Component SHE1 separates the wiring layer 14, which functions as a string select signal line SGD or SGDT, in the Y direction and extends in the X direction. Component SHE1 separates at least one of the wiring layers 14 located at the position furthest from the semiconductor layer 12 (the uppermost layer). The lower end of component SHE1 is located between the wiring layer 14, which functions as a string select signal line SGD, and the wiring layer 14, which functions as a character line WL. The height of component SHE1 in the Z direction is based on the number of wiring layers 14 that function as string select signal lines SGDT and SGD. Component SHE1 may contain an insulator such as silicon oxide.

[0028] As described above, a plurality of word line layers and a plurality of string select signal layers are stacked above semiconductor layer 12 (separated from semiconductor layer 12 at one end in the Z direction). A memory via MH extends in the Z direction perpendicular to the substrate, penetrating (through) the plurality of word line layers and the plurality of string select signal layers. A barrier insulating layer 223, a charge trapping layer 222, a tunnel insulating layer 221, and a silicon channel layer 21 are formed on the sidewalls of each word line layer inside the memory via MH, thereby forming individual memory cells with an electron injection / release memory threshold voltage. Furthermore, the memory principle of the memory cells can utilize not only charge injection and release but also strong dielectric polarization. In this case, the barrier insulating layer 223 contains a strong dielectric material and performs polarization. Alternatively, the barrier insulating layer 223 and the charge trapping layer 222 are replaced with a strong dielectric layer.

[0029] The memory cells are arranged in a stacked layer direction (Z-direction) to form a memory cell string. This memory cell string is connected in series with a plurality of memory cells whose gate electrodes are multiple word line layers, and a plurality of string select transistors whose gate electrodes are multiple string select signal layers. By fabricating a plurality of memory vias MH together, the series connection of multiple memory cells in the Z-direction can be realized at low cost. That is, a low-cost, non-volatile semiconductor memory device can be realized.

[0030] Next, the first example of a planar layout of a memory cell array will be described.

[0031] As shown in Figure 32C, in the region between two adjacent SLTs in the Y direction, a plurality of memory columns MP are arranged, for example, in the X direction with a width of 24 rows. Furthermore, the 24 rows of memory columns MP are staggered in such a way that the X-direction positions of adjacent memory columns MP in the Y direction are different from each other. The plurality of memory columns MP (a plurality of memory cells) located between two adjacent SLTs are contained in one cell block CB. The cell block CB is, for example, a set of a plurality of memory cell strings (memory columns MP) whose data is erased together. The number of cell blocks CB is arbitrary.

[0032] Between two components SLT, a plurality of components SHE1 extending in the X direction are arranged in the Y direction. In the example shown in Figure 32C, four components SHE1 are provided. The area between two adjacent components SLT or SHE1 in the Y direction corresponds to one string unit SU. That is, the cell block CB contains a plurality of string units SU. In the example shown in Figure 32C, the cell block CB contains five string units SU0 to SU4. The string unit SU, for example, contains a set of a plurality of memory cell strings (memory columns MP) selected together in a write operation or a read operation. In addition, the number of string units SU in the cell block CB is arbitrary.

[0033] In the example shown in Figure 32C, within the string unit SU, a plurality of memory columns MP are arranged in four rows along the X direction. Furthermore, the four rows of memory columns MP are staggered such that the X-direction positions of adjacent memory columns MP in the Y direction are different. A component SHE1 is provided above the memory columns MP in rows 5, 10, 15, and 20, starting from the left side of the paper in Figure 32C. The component SHE1 is positioned such that it interrupts the upper portion of the memory column MP by passing through the center of the XY plane of the memory column MP. Therefore, the memory columns MP in rows 5, 10, 15, and 20 do not function as a string of memory cells.

[0034] Next, the second example of a planar layout of a memory cell array will be described.

[0035] As shown in Figure 32D, in the region between two adjacent SLT components in the Y direction, a plurality of memory columns MP are arranged in a width of 20 rows in the X direction. Furthermore, the 20 rows of memory columns MP are arranged in an alternating manner such that the X-direction positions of adjacent memory columns MP in the Y direction are different from each other.

[0036] In the example shown in Figure 32D, a component SHE1 is placed between memory columns MP in the 4th and 5th rows, starting from the left side of the paper in Figure 32D. Similarly, a component SHE1 is placed between memory columns MP in the 8th and 9th rows, between memory columns MP in the 12th and 13th rows, and between memory columns MP in the 16th and 17th rows. In this case, a portion of memory columns MP in rows 4, 5, 8, 9, 12, 13, 16, and 17 can also be cut off by component SHE1. These memory columns MP function as memory cells.

[0037] Next, referring to Figures 33A and 33B, the relationship between the number of word lines (WL) in a 3D-NAND flash memory (also referred to as "3D-NAND flash memory") and the silicon mobility required for the memory cell will be explained. Figure 33A is a graph comparing the silicon mobility required to increase the number of word lines (WL) in a 3D-NAND flash memory with a comparative example and an embodiment of the implementation. Figure 33B is a circuit diagram showing an example of the circuit configuration for the memory cell string calculated in Figure 33A. Furthermore, in the following description, when the source and drain of the transistor are not limited, either the source or drain of the transistor will be referred to as "one end of the transistor," and the other will be referred to as "the other end of the transistor."

[0038] First, referring to Figure 33B, an example of the circuit configuration of a memory cell string will be explained.

[0039] As shown in Figure 33B, the memory cell string MSR comprises a plurality of memory cells MC and string select transistors ST1 and ST2. In the example shown in Figure 33B, the memory cell string MSR comprises 162 memory cells MC0~MC161. The current paths of the string select transistor ST1, memory cells MC0~MC161, and string select transistor ST2 within the memory cell string MSR are connected in series. The drain of string select transistor ST1 is connected to bit line BL. The source of string select transistor ST2 is connected to source line SL. The control gates of memory cells MC0~MC161 are connected to word lines WL0~WL161, respectively. The gate of string select transistor ST1 is connected to the string select signal line SGD. The gate of string select transistor ST2 is connected to the string select signal line SGS.

[0040] The character line WL and the serial select signal lines SGD and SGS are connected to different driver DRVs. The driver DRV applies voltages for various operations to the corresponding character line WL, serial select signal line SGD, or serial select signal line SGS.

[0041] One end of bit line BL is connected to the page buffer PB. The page buffer PB is the read / write circuit. Furthermore, the page buffer PB temporarily stores data for write or read operations. The load capacity of bit line BL is denoted as CBL.

[0042] Next, referring to Figure 33A, the relationship between the number of stacked layers of the character line layer and the required silicon mobility will be explained.

[0043] Currently, semiconductor memory is widely used in cloud servers, mainframe computers, personal computers, home appliances, mobile phones, and more. Types of semiconductor memory include volatile DRAM (Dynamic Read Only Memory), SRAM (Static Read Only Memory), non-volatile MROM (Mask Read Only Memory), NAND flash memory, NOR flash memory, and electronically erasable programmable read-only memory (EEPROM). In 3D-NAND flash memory, multiple word lines are stacked to form multiple memory cells (MPs), thus reducing manufacturing costs. Therefore, the current mainstream of the market for manufacturing 1 Tb high-capacity 3D-NAND flash memory is primarily driven by smartphones.

[0044] However, the current number of stacked word lines is around 150-250 layers. Further stacking would increase the number of serially connected cells (the number of memory cells MC in series within the memory cell string MSR), thus reducing the cell current (Icell) flowing within the MSR. When the size of the memory cell array is constant, the total number of memory cell strings connected to the bit line BL during readout is constant. That is, because the load capacity CBL is constant, an increase in the number of serially connected cells reduces the current driving that load capacity, resulting in a serious problem of significantly slower readout.

[0045] Figure 33A is a summary diagram illustrating the effects of the embodiment. Figure 33A shows the trend of silicon mobility (required Si mobility) required to maintain stable read performance when the number of word line stacked layers (WL stacked layers) is continuously increased to reduce costs relative to the year on the horizontal axis, while the bit line load capacity (CBL) remains constant. As shown in Figure 33A, the required Si mobility increases proportionally with the number of word line stacked layers. However, there are limits to high-temperature crystallization of silicon or to Mic / Milc (Metal-induced Crystallization / Metal-induced Lateral Crystallization) techniques that reduce the degradation of the migration rate at the particle boundaries of polycrystalline silicon. The limit for silicon mobility is analogously about five times the current level. Therefore, the comparative example of the previous method reaches the limit of word line stacked layers, i.e., the cost reduction limit. In contrast, in embodiments of the present invention, even if the silicon mobility remains at the current level, the number of character line stack layers can be set to 2000 or more. Therefore, during readout operations, the time required to drive the load capacity can be suppressed to the previous level.

[0046] The embodiments of the present invention will now be described with reference to the drawings.

[0047] 1. First Implementation Form 1.1 Composition of Memory Cell Array First, referring to Figures 1-3, an example of the configuration of a memory cell array will be described. Figure 1 shows an example of the equivalent circuit diagram of the gain block line (gBK) of the first embodiment. Figure 1 shows an example including a cell block CB containing multiple memory cell strings MSRs connected to a local bit line (LBL), a write port block (WPB) that transfers the potential of the bit line BL to the local bit line LBL, and amplifies the potential of the local bit line LBL and transfers it to the read port block (RPB) of the bit line BL. Figure 1 shows one cell block CB and four string cells SU, but in reality, multiple cell blocks CB and multiple string cells SU are arranged within each cell block CB. Figure 2 is a block diagram showing an example of the configuration of the memory cell array MA of the first embodiment. In the example shown in Figure 2, bit line BL is connected to page buffer PB, and multiple gain blocks gBK are connected to bit line BL. Figure 3 shows an example of a cross-sectional view of the gain block gBK in the bit line direction (Y direction) of the first embodiment. Figure 3 shows an example of a cell block CB including a portion of a multiple memory cell string (MSR) (memory cylinder MP) connected to a region bit line LBL, a write port WPB that transmits the potential of bit line BL to region bit line LBL, and a read port RPB that amplifies the potential of region bit line LBL and transmits it to bit line BL.

[0048] As shown in Figure 1, the gain block gBK contains the cell block CB, the read port RPB, and the write port WPB.

[0049] First, the structure of a cell block CB will be explained. A cell block CB is, for example, a collection of multiple memory cells whose data is being erased together. A cell block CB contains multiple string units SU. A string unit SU is a collection of multiple memory cell strings MSRs selected together during a write or read operation. In the example shown in Figure 1, the cell block CB contains 4 string units SU0 to SU3.

[0050] A memory cell string (MSR) comprises a plurality of memory cells (MC) and string select transistors (STT1, ST1, and ST2). In the example shown in Figure 1, the MSR comprises 2000 memory cells (MC0~MC1999) and one string select transistor (STT1, ST1, and ST2) for each cell. The current paths of the string select transistors STT1 and ST1, the memory cells (MC0~MC1999), and the string select transistor ST2 within the MSR are connected in series sequentially. The plurality of memory cells (MC) connected in series constitute a memory cell string. The drain of the string select transistor STT1 is connected to the region bit line LBL. The source of the string select transistor ST2 is connected to the source line SL. Furthermore, the number of string select transistors STT1 and the string select signal line SGDT can be changed by altering the manufacturing process or operating mode.

[0051] The gates of memory cells MC0 to MC1999 within cell block CB are respectively connected to word lines WL0 to WL1999. More specifically, the gates of multiple memory cells MC0 within cell block CB are all connected to word line WL0. The same applies to memory cells MC1 to MC1999.

[0052] The series selector transistors ST1, ST2, and STT1 are switching elements. ST1, ST2, and STT1 are used to select the series unit SU. The gates of ST1, ST2, and STT1 are connected to the series selector signal lines SGD, SGS, and SGDT, respectively.

[0053] More specifically, the gates of the plurality of string select transistors STT1 contained in string unit SU0 are connected to the string select signal line SGDT0. The gates of the plurality of string select transistors ST1 contained in string unit SU0 are connected to the string select signal line SGD0. Similarly, the gates of the string select transistors STT1 and ST1 contained in string unit SU1 are connected to the string select signal lines SGDT1 and SGD1, respectively. The gates of the string select transistors STT1 and ST1 contained in string unit SU2 are connected to the string select signal lines SGDT2 and SGD2, respectively. The gates of the string select transistors STT1 and ST1 contained in string unit SU3 are connected to the string select signal lines SGDT3 and SGD3, respectively. Furthermore, the gates of the plurality of string select transistors ST2 within cell block CB are connected to the string select signal line SGS. To suppress power consumption, the serial select signal line SGS, like the serial select signal line SGD, such as SGS0~SGS3, has a separate control signal for each serial unit SU.

[0054] Within the gain block gBK, a plurality of region bit lines LBL are configured. Each region bit line LBL is connected to one memory cell string MSR of each string unit SU within the cell block CB. In the example shown in Figure 1, the region bit line LBL is connected to one memory cell string MSR in string unit SU0, one memory cell string MSR in string unit SU1, one memory cell string MSR in string unit SU2, and one memory cell string MSR in string unit SU3. Other region bit lines LBL not shown are connected similarly. One end of each region bit line LBL is connected to the write port WPB, and the other end is connected to the read port RPB.

[0055] The source line SL can be shared among multiple cell blocks CB within a single gain block gBK.

[0056] Next, the configuration of the write port WPB will be explained. The write port WPB functions as a circuit that transfers charge from bit line BL to region bit line LBL. For example, during a write operation, the voltage of bit line BL based on the data being written is applied to region bit line LBL via the write port WPB. The write port WPB includes a plurality of serial WSRs. More specifically, two serial WSRs, WSR1 and WSR2, are provided for one region bit line LBL. The two serial WSRs, WSR1 and WSR2, are connected in series. Bit line BL is electrically connected to region bit line LBL via the two serially connected serial WSRs, WSR1 and WSR2. Hereinafter, when neither serial WSR1 nor WSR2 is limited, it will simply be referred to as "serial WSR".

[0057] More specifically, each string WSR in this embodiment includes transistors WST0 and WST1, a plurality of dummy cells DC, and a dummy transistor DT. The transistors WST0, WST1, the plurality of dummy cells DC, and the dummy transistor DT in string WSR1 are connected in series with the dummy transistor DT, the plurality of dummy cells DC, transistor WST1, and transistor WST0 in string WSR2. One end (drain) of transistor WST0 in string WSR1 is connected to bit line BL. One end (drain) of transistor WST0 in string WSR2 is connected to region bit line LBL. The source of the dummy transistor DT in string WSR1 is connected to the source of the dummy transistor DT in string WSR2.

[0058] Transistors WST0 and WST1 function as switching transistors. The gate of each WST0 transistor is connected to the write control signal line WBS0. Similarly, the gate of each WST1 transistor is connected to the write control signal line WBS1. The gate of the dummy cell DC is connected to the dummy word line dWL. The gate of the dummy transistor DT is connected to the dummy string select signal line dSGS. The drain and source of each dummy cell DC and dummy transistor DT are electrically connected regardless of the gate voltage.

[0059] Next, the configuration of the read port RPB will be explained. The read port RPB functions as a circuit that amplifies the potential of the region bit line LBL and transmits it to the bit line BL. For example, during a read operation, the read port RPB amplifies the voltage of the region bit line LBL based on the data stored in the memory cell MC and transmits it to the bit line BL. The read port RPB contains a plurality of serial RSRs. One serial RSR is set for each region bit line LBL.

[0060] More specifically, the string RSR in this embodiment includes transistors APT and RST, a plurality of dummy cells DC, and a dummy transistor DT. The transistors APT, RST, DC, and DT within the string RSR are connected in series sequentially. One end (drain) of transistor APT is connected to bit line BL. The source of the dummy transistor DT is connected to read source line RSL. Alternatively, the order of transistors APT and RST can be reversed.

[0061] The transistor APT functions as an amplifying transistor that amplifies the voltage of the region bit line LBL. The gate of the transistor APT is connected to the region bit line LBL. The transistor RST functions as a switching transistor. The gate of the transistor RST is connected to the read control signal line RBS. Similar to the write port WPB, the gate of the dummy cell DC is connected to the dummy word line dWL. The gate of the dummy transistor DT is connected to the dummy string select signal line dSGS. The drain and source of both the dummy cell DC and the dummy transistor DT are electrically connected regardless of the gate voltage.

[0062] For example, in a non-volatile semiconductor memory device of the previous type, one end of a memory cell string (MSR) is connected to a read / write bit line (BL), and the other end is connected to a source line (SL). Therefore, a memory cell array (MA) is constructed with multiple MSRs connected to a single bit line (BL). In this case, the capacity of the bit line (BL) increases with the number of connected MSRs. To reduce costs, if the number of word line stacks is doubled, for example, the number of cells in series within the MSR is doubled. In this case, the cell current (Icell) flowing within the MSR is halved, and the load capacity, i.e., the drive time of the bit line (BL), is doubled. As a result, the processing speed is reduced. To maintain a constant speed, for example, to halve the load capacity, the size of the memory cell array needs to be halved. However, if this method is used, the number of page buffers (PB) across the entire chip is doubled, thus leading to a larger chip size.

[0063] In contrast, in the non-volatile semiconductor memory device 1 of this embodiment, as shown in FIG1, one end of a plurality of memory cell strings MSRs is connected to a region bit line LBL, and the other end is connected to a source line SL. This forms a group of memory cell strings corresponding to the region bit line LBL. That is, the region bit line LBL is connected to the gain block gBK of the bit line BL via the read port RPB and the write port WPB.

[0064] As shown in Figure 2, the non-volatile semiconductor memory device 1 includes a memory cell array MA and a page buffer PB.

[0065] The memory cell array MA comprises a plurality of gain blocks gBK connected to the same bit line BL. In other words, the memory cell array MA is divided into a plurality of gain blocks gBK. Furthermore, the plurality of gain blocks gBK are connected to a common bit line BL. In the example shown in Figure 2, the memory cell array MA comprises 16 gain blocks gBK0~gBK15. The bit line BL is connected to the 16 gain blocks gBK0~gBK15, and the read / write circuitry, i.e., the page buffer PB (i.e., the page buffer PB includes a sense amplifier circuitry and a write circuitry).

[0066] The number of memory cell strings (MSRs) connected to each region bit line (LBL) within the gain block (gBK) decreases as the number of gain blocks (gBK) increases. For example, if the number of gain blocks (gBK) increases from 1 to 16, the number of memory cell strings (MSRs) connected to the region bit lines (LBL) decreases to 1 / 16. Therefore, the load capacity of the region bit lines (LBL) driven by cell current is significantly reduced to 1 / 16. This allows for a 16-fold increase in the speed of reading the region bit lines (LBL). Therefore, even if the number of memory cell (MC) stacks (number of word lines stacks) is increased to 16 times, the speed remains the same because the load on the region bit lines (LBL) is reduced to 1 / 16.

[0067] As shown in Figure 1, in the write port WPB, if a high-level voltage is applied to the write control signal lines WBS0 and WBS1, transistors WST0 and WST1 become ON. In this way, the write port WPB transmits the potential of bit line BL to the region bit line LBL via the two transistors WST0 and WST1 connected in series with WSR1 and WSR2.

[0068] Bit information from the page buffer PB is transmitted to the memory string MSR via transistors WST0 and WST1 and the region bit line LBL. Because the region bit line LBL is shorter than the bit line BL, the load is smaller, thus achieving the previous level of write speed. In addition, because the write speed follows the FN-tunneling current rule, the performance will not degrade even if the number of cells in series in the memory string MSR increases.

[0069] Additionally, in the read port RPB, the region bit line LBL is connected to the amplifying transistor APT, which sets the region bit line LBL as the gate input and the bit line BL as the drain. The source of the transistor APT is connected to the read source line RSL via the transistor RST, which sets the read control signal line RBS as the gate input.

[0070] For example, during a read operation, a high-level voltage is applied to the non-selection word line WL in the selected gain block gBK, turning on the non-selection memory cell MC. In this state, the selection word line WL is set to the threshold voltage determination potential. In other words, a read voltage is applied to the selection word line WL. When the threshold voltage of the selection memory cell MC is higher than the determination potential, the selection memory cell MC becomes OFF. Therefore, the voltage of the region bit line LBL remains at a high level. On the other hand, when the threshold voltage of the selection memory cell MC is lower than the determination potential, the selection memory cell MC becomes ON. Therefore, the voltage of the region bit line LBL drops to a low level. At this time, because the capacity of the region bit line LBL is relatively small, the potential of the region bit line LBL decreases relatively quickly. In this state, if a high-level voltage is applied to the read control signal line RBS, the amplifying transistor APT, which sets the bit line LBL of this region as the gate, drives the bit line BL with a larger load capacity and transmits the determination result to the page buffer PB.

[0071] The number of series connections between the amplifying transistor APT and the transistor RST, which sets the read control signal line RBS as the gate input, will be displayed later. However, because the multiple dummy cells DC of the read port RPB and the dummy transistor DT have low resistance in the manufacturing process (construction), they are actually several transistor levels. Therefore, even if the amplifying transistor APT drives the bit line BL, it can achieve a speedup of more than 10 times compared to the previous drive of the memory cell string MSR with 150 to 250 memory cells MC connected in series, and can operate at high speed regardless of the number of cells connected in series.

[0072] Next, the cross-sectional structure of the gain block gBK will be explained. First, the cell block CB will be explained.

[0073] As shown in Figure 3, multiple word line layers (WL0~WL1999) and string select signal layers (SGDi, SGDTi, SGS) (i is an integer greater than or equal to 0) are stacked separately in the Z direction. A memory via MH extends in the Z direction, penetrating (through) the multiple word line layers and the string select signal layers. The bottom surface of the memory via MH reaches the semiconductor layer 12. A stacked film 22 (barrier insulating layer 223, charge trapping layer 222, and tunnel insulating layer 221) and a silicon channel layer 21 are formed on the sidewalls of each word line layer inside the memory via MH, thus forming individual memory cells MC with an electron injection / release memory threshold voltage. These memory cells MC form a memory cell string MSR, which is connected in series in the Z direction to multiple memory cells MC with multiple word line layers as gate electrodes, and multiple string select transistors STT1, ST1, and ST2 with multiple string select signal layers as gate electrodes. By processing the memory vias MH together, multiple memory cells MC in the Z direction can be connected in series at low cost. That is, a low-cost, non-volatile semiconductor memory device 1 can be realized.

[0074] Furthermore, as shown in Figure 3, the stacked layers of multiple wiring layers 14 are constructed by stacking character line layers and serial select signal layers. The read port RPB and write port WPB also utilize wiring layers 14 stacked by the same film deposition process.

[0075] For example, transistors WST0 and WST1 in the write port WPB set the write control signal lines WBS0 and WBS1 as gate inputs and the string select signal layers (SGDT and SGD) used by the cell block CB as gate electrodes. Wiring layer 17, which functions as bit line BL, is electrically connected to one end of semiconductor layer 12 located below (separated from the other end in the Z direction) via contact plugs CP4 and CP3 and transistors WST0 and WST1. Semiconductor layer 12 in the write port WPB functions as bottom bit line bBL, which connects two strings WSR1 and WSR2, electrically connecting bit line BL to region bit line LBL. Semiconductor layer 12, which functions as bottom bit line bBL, is on the same layer as the source line layer of cell block CB. The other end of semiconductor layer 12 is electrically connected to wiring layer 16, which functions as a region bit line LBL, via transistors WST1 and WST0 disposed on top and contact plug CP1. At this time, in order to reduce the resistance of pillars WP1 and WP2 of the dummy word line dWL through the write port WPB, as shown in FIG3, a conductor 30 is disposed, for example, inside silicon channel layer 21. The material of conductor 30 is preferably a metallic material such as tungsten, or low-resistance silicon doped with a high concentration of impurities.

[0076] In the read port RPB, the wiring layer 14, which functions as the region bit line LBL, is connected as the gate input of the transistor APT, which sets the string select signal layer as the gate electrode. In the example shown in Figure 3, the wiring layer 16, which functions as the region bit line LBL, is electrically connected to the string select signal layer (wiring layer 14, which functions as the region bit line LBL) of the upper 3 layers above the stacked layer via the contact plug CP2. For the read control signal line RBS, the lower 3 layers of the string select signal layer (wiring layer 14, which functions as the read control signal line RBS) are used. The source of the control transistor RST, which sets the read control signal line RBS as the gate input, is connected to the read source line RSL (semiconductor layer 12) via a dummy word line layer in the read port RPB, through a conductor 30 (tungsten or low-resistance silicon with high concentration of doped impurities) that reduces the resistance of the pillar RP. If a stacked layer constituting the cell block CB is used to construct the read port RPB and write port WPB process, the increase in process cost can be significantly suppressed. Furthermore, if the read port RPB and write port WPB connect ten to hundreds of memory cell strings MSRs per unit area bit line (LBL), the increase in chip area is minimized. Thus, even if the number of word line stacked layers increases, increasing memory capacity, the cost of increasing the number of word line stacked layers can be used to suppress other costs or increases in chip area, resulting in a significant reduction in cost per bit.

[0077] The following description focuses on the differences in the construction of the memory cell array MA in this embodiment compared to the memory cell array described using Figures 32A and 32B, and details of the cross-sectional structure of the memory cell array MA in this embodiment will be explained.

[0078] As shown in Figure 3, the gain block gBK includes insulating layers 11, 13 and 15, semiconductor layer 12, wiring layers 14, 16 and 17, memory pillars MP, pillars WP1, WP2 and RP, contact plugs CP1~CP4, component SLT, and component SHE1.

[0079] A semiconductor layer 12 is disposed on the insulating layer 11. The semiconductor layer 12 disposed on the cell block CB functions as a source line SL. A plurality of memory pillars MP are disposed on the semiconductor layer 12 which functions as a source line SL. Each memory pillar MP functions as a memory cell string MSR.

[0080] A plurality of semiconductor layers 12 disposed on the write port WPB function as bottom bit lines bBL. On the semiconductor layers 12 that function as bottom bit lines bBL, two pillars WP1 and WP2 are disposed to electrically connect the bit line BL to the area bit line LBL. That is, the two pillars WP are electrically connected via one bottom bit line bBL. Pillars WP1 and WP2 function as serial lines WSR1 and WSR2, respectively. Hereinafter, the term "pillar WP" will be used without limitation on either pillar WP1 or WP2.

[0081] The semiconductor layer 12 located on the read port RPB functions as the read source line RSL. A plurality of pillars RP are disposed on the semiconductor layer 12 that functions as the read source line RSL. Each pillar RP functions as one string RSR.

[0082] An insulating layer 13 is disposed on the semiconductor layer 12. A plurality of wiring layers 14 and a plurality of insulating layers 15 are alternately deposited on the insulating layer 13. In the example shown in FIG3, similar to FIG32A, 2009 wiring layers 14 are disposed. Each wiring layer 14 is divided into cell blocks CB, write ports WPB, and read ports RPB by means of a component SLT extending in the X direction.

[0083] The 2009 layer wiring layer 14, located on the side furthest from the semiconductor layer 12 (source line SL) (upper layer), functions as the 3-layer serial select signal line SGDT, the 3-layer serial select signal line SGD, the 2000-layer word lines WL0~WL1999, and the 3-layer serial select signal line SGS. The wiring layer 14, which functions as the serial select signal line SGDT or serial select signal line SGD, is divided according to each serial unit SU by the X-direction extending member SHE1.

[0084] The 2009 layer wiring layer 14, located on the write port WPB, functions as three layer write control signal lines WBS0, WBS1, 2000 layer dummy word line dWL, and 3 layer dummy string select signal lines dSGS, respectively, on the side furthest from the semiconductor layer 12 (bottom bit line bBL). The wiring layer 14, which functions as either the write control signal line WBS0 or the write control signal line WBS1, can also be separated by the X-direction extending component SHE1.

[0085] The 2009 layer wiring layer 14, located on the read port RPB, functions as the 3-layer region bit line LBL, the 3-layer read control signal line RBS, the 2000 layer dummy word line dWL, and the 3-layer dummy string select signal line dSGS, located on the side furthest from the semiconductor layer 12 (read source line RSL). The wiring layer 14, which functions as the region bit line LBL or the read control signal line RBS, can also be interrupted by the X-direction extending component SHE1.

[0086] Therefore, in the example shown in Figure 3, the wiring layer 14 that functions as the serial select signal line SGDT, the wiring layer 14 that functions as the write control signal line WBS0, and the wiring layer 14 that functions as part of the region bit line LBL are all located on the same layer. The wiring layer 14 that functions as the serial select signal line SGD, the wiring layer 14 that functions as the write control signal line WBS1, and the wiring layer 14 that functions as the read control signal line RBS are all located on the same layer. The wiring layer 14 that functions as the word line WL and the wiring layer 14 that functions as the dummy word line dWL are all located on the same layer. The wiring layer 14 that functions as the serial select signal line SGS and the wiring layer 14 that functions as the dummy serial select signal line dSGS are all located on the same layer.

[0087] Within the cell block CB, a plurality of memory pillars MP are set. The construction of the memory pillars MP is the same as that described in Figures 32A and 32B.

[0088] A memory cell MC is formed by combining memory cylinders MP with wiring layer 14, which functions as word lines WL. A serial select transistor STT1 is formed by combining memory cylinders MP with wiring layer 14, which functions as serial select signal lines SGDT. A serial select transistor ST1 is formed by combining memory cylinders MP with wiring layer 14, which functions as serial select signal lines SGD. A serial select transistor ST2 is formed by combining memory cylinders MP with wiring layer 14, which functions as serial select signal lines SGS. In other words, a memory cell MC with word lines WL as gate electrodes is formed. A serial select transistor STT1 with serial select signal lines SGDT as gate electrodes is formed. A serial select transistor ST1 with serial select signal lines SGD as gate electrodes is formed. A serial select transistor ST2 with serial select signal lines SGS as gate electrodes is formed.

[0089] Within the write port WPB, a plurality of pillars WP are provided. Each pillar WP includes a core film 20, a silicon channel layer 21, a stacked film 22 (including a barrier insulating layer 223, a charge trapping layer 222, and a tunnel insulating layer 221), and a conductor 30. In this embodiment, the pillar WP is constructed by replacing the lower part of the core film 20 of the memory pillar MP with the conductor 30. The conductor 30 extends in the Z direction. The upper end of the conductor 30 is located between the wiring layer 14, which functions as a dummy word line (dWL), and the wiring layer 14, which functions as a write control signal line (WBS1). The core film 20 is disposed above the conductor 30. The upper end of the core film 20 is located above the uppermost wiring layer 14. The silicon channel layer 21 extends in the Z direction and covers the core film 20 and the conductor 30. That is, the bottom and side surfaces of the conductor 30 are in contact with the silicon channel layer 21. A multilayer film 22 is formed by covering the sides of the silicon channel layer 21. The material of the conductor 30 is preferably a metal such as tungsten, or low-resistivity silicon doped with a high concentration of impurities.

[0090] Transistor WST0 is constructed by combining post WP with wiring layer 14, which functions as the write control signal line WBS0. Transistor WST1 is constructed by combining post WP with wiring layer 14, which functions as the write control signal line WBS1. Virtual cell DC is constructed by combining post WP with wiring layer 14, which functions as the dummy word line dWL. Virtual transistor DT is constructed by combining post WP with wiring layer 14, which functions as the dummy string select signal line dSGS. In other words, transistor WST0 is constructed with write control signal line WBS0 as the gate electrode. Transistor WST1 is constructed with write control signal line WBS1 as the gate electrode. Virtual cell DC is constructed with dummy word line dWL as the gate electrode. Virtual transistor DT is constructed with dummy string select signal line dSGS as the gate electrode.

[0091] Within the read port RPB, there are multiple pillars RP. The construction of the pillars RP is the same as that of the pillars WP. For example, the memory hole MH, as well as the holes corresponding to the pillars WP and RP, are machined together.

[0092] A transistor APT is constructed by combining pillar RP with wiring layer 14, which functions as the region bit line LBL. A transistor RST is constructed by combining pillar RP with wiring layer 14, which functions as the read control signal line RBS. A dummy cell DC is constructed by combining pillar RP with wiring layer 14, which functions as the dummy word line dWL. A dummy transistor DT is constructed by combining pillar RP with wiring layer 14, which functions as the dummy string select signal line dSGS. In other words, a transistor APT is constructed with the region bit line LBL as the gate electrode. A transistor RST is constructed with the read control signal line RBS as the gate electrode. A dummy cell DC is constructed with the dummy word line dWL as the gate electrode. A dummy transistor DT is constructed with the dummy string select signal line dSGS as the gate electrode.

[0093] The drain and source of the dummy cell DC and dummy transistor DT, which are used for writing to the WPB and reading from the RPB, are electrically connected via conductor 30. Therefore, the current path of the dummy cell DC and dummy transistor DT has low resistance, and they are always in the on state regardless of the gate voltage.

[0094] In the cell block CB, a contact plug CP1 is disposed on top of the memory cylinder MP. A wiring layer 16 extending in the Y direction is disposed on top of the contact plug CP1. The memory cylinder MP is electrically connected to the wiring layer 16 via the contact plug CP1. The wiring layer 16 functions as the region bit line LBL. The wiring layer 16 and the contact plug CP1 may contain, for example, copper or tungsten as conductive materials. Alternatively, the contact plugs CP1 to CP4 may also partially contain an N+ diffusion layer or a P+ diffusion layer.

[0095] In the WPB (Write-in Port), a contact plug CP1 is provided on the two posts WP1 and WP2 on the bottom bit line bBL, corresponding to post WP2 of series WSR2. Post WP2 is electrically connected to wiring layer 16 (region bit line LBL) via contact plug CP1. A contact plug CP3 is provided on post WP1 corresponding to series WSR1. Furthermore, a contact plug CP4 is provided on contact plug CP3. A wiring layer 17 extending in the Y direction is provided on contact plug CP4. Wiring layer 17 is provided above wiring layer 16. Post WP1 is electrically connected to wiring layer 17 via contact plugs CP3 and CP4. Wiring layer 17 functions as bit line BL. Wiring layer 17 and contact plugs CP3 and CP4 contain, for example, copper or tungsten as conductive materials.

[0096] In the read port RPB, a contact plug CP2 is electrically connected to the upper 3rd layer wiring layer 14, which functions as the area bit line LBL. Contact plug CP2 connects to the lower 3rd layer wiring layer 14 via the upper 2nd layer wiring layer 14. The upper 3rd layer wiring layer 14 is electrically connected to wiring layer 16 (area bit line LBL) via contact plug CP2. A contact plug CP3 is provided on top of the post RP. Furthermore, a contact plug CP4 is provided on top of contact plug CP3. A wiring layer 17 is provided on top of contact plug CP4. The post RP is electrically connected to wiring layer 17 via contact plugs CP3 and CP4. Contact plug CP2 may contain copper or tungsten as a conductive material.

[0097] 1.2 Planar Layout of the Write Port Next, referring to Figure 4, an example of the planar layout of the write port WPB will be described. Figure 4 is a top view showing an example of the planar layout of the write port WPB.

[0098] As shown in Figure 4, a plurality of region bit lines LBL (wiring layer 16) extending in the Y direction are arranged in the X direction. Each region bit line LBL extends from the cell block CB (not shown) located in the left direction of the diagram to the write port WPB. The region bit line LBL is electrically connected to the post WP2 located below via contact plug CP1. The length of the region bit line LBL varies depending on the position of the post WP2 (contact plug CP1) to which it is connected. The region bit line LBL is electrically connected to the bottom bit line bBL (semiconductor layer 12) located below the post WP2 via the post WP2. The bottom bit line bBL is connected, for example, to the post WP1 located at the same position in the X direction and adjacent in the Y direction. That is, one bottom bit line bBL connects two posts WP1 and WP2. The post WP1, connected to the bottom bit line bBL, is electrically connected to the bit line BL (wiring layer 17) located above the regional bit line LBL via contact plugs CP3 and CP4. The right end of the regional bit line LBL does not extend above the contact plug CP3. Therefore, the contact plug CP3 is formed on the post WP1 without being obstructed by the regional bit line LBL.

[0099] The configuration of pillars WP is the same as that of memory pillars MP, for example, an interleaved configuration.

[0100] In the example shown in Figure 4, the bottom bit line bBL has a shape that curves towards the upper or lower side of the paper. However, the shape of the bottom bit line bBL is not limited to this. In the example shown in Figure 4, two posts WP in the same X-direction position and adjacent in the Y-direction of the first and third rows from the left side of the paper are connected to one bottom bit line bBL. For example, the area bit line LBL is electrically connected to the bit line BL via a contact plug CP1 disposed on the first row post WP2, the first row post WP2, the bottom bit line bBL, the third row post WP1, a contact plug CP3 disposed on the third row post WP1, and a contact plug CP4 disposed on the contact plug CP3. Additionally, other posts WP in different X-direction positions in the second row from the left side of the paper are also connected to the bottom bit line bBL, but the second row posts WP are dummy (floating) and do not contribute to electrical connection. Similarly, starting from the left side of the page, the two adjacent bars WP in the X direction of rows 4 and 6, which are in the same position and adjacent in the Y direction, are connected to a bottom bit line bBL by a dummy bar WP in row 5. Starting from the left side of the page, the two adjacent bars WP in the X direction of rows 7 and 9, which are in the same position and adjacent in the Y direction, are connected to a dummy bar WP in row 8 by a bottom bit line bBL. Starting from the left side of the page, the two adjacent bars WP in the X direction of rows 10 and 12, which are in the same position and adjacent in the Y direction, are connected to a dummy bar WP in row 11 by a bottom bit line bBL.

[0101] Since the bottom bit lines bBL are randomly processed, the spacing needs to be widened. As shown in Figure 4, the region bit lines LBL are staggered by 4 segments in the Y direction. More specifically, for example, the 4 region bit lines LBL arranged in the X direction are sequentially connected to the columns WP2 in the 1st, 7th, 4th, and 10th rows from the left side of the paper. Furthermore, when viewed in the X direction, the connection positions in the Y direction are repeated in units of 4. More specifically, for example, the 4 columns WP2 arranged in the 1st row from the left side of the paper are connected to the 1st, 5th, 9th, and 13th region bit lines LBL from the top of the paper. Since each LBL on the right side of the paper is different, the LBL (wiring layer 16) is preferably formed by tilted SAP (Semi-additive Process) (sidewall processing process) or NIL (Nano Imprint Lithography).

[0102] 1.3 Read the port layout Next, referring to Figures 5A and 5B, two examples of the planar layout of the read port RPB will be described. Figure 5A is a top view showing the first example of the planar layout of the read port RPB. Figure 5B is a top view showing the second example of the planar layout of the read port RPB.

[0103] First, referring to Figure 5A, the first example of the planar layout of the read port RPB will be described.

[0104] As shown in Figure 5A, in the read port RPB, an amplifying transistor APT is formed as the gate for each region bit line LBL (wiring layer 16). Furthermore, a plurality of transistors RST are formed as gates for each read control signal line RBS extending in the X direction. To form the gate electrode (wiring layer 14) of the amplifying transistor APT as a vertically and horizontally separated island in the X and Y directions, firstly, a member SHE1 extending in the X direction is formed, separating the upper 6 wiring layers 14, which function as region bit lines LBL or read control signal lines RBS, in the Y direction.

[0105] In the example shown in Figure 5A, a plurality of pillars RP disposed between three component SLTs are contained within a single read port RPB. In the region between two adjacent component SLTs in the Y direction, the plurality of pillars RP are arranged, for example, in the X direction with a width of 11 rows. Furthermore, the 11 rows of memory pillars MP are arranged in an alternating manner such that the X-direction positions of adjacent memory pillars MP in the Y direction are different from each other.

[0106] Between two components SLT, a plurality of components SHE1 extending in the X direction are arranged in the Y direction. In the example shown in Figure 5A, three components SHE1 are arranged between two components SLT. More specifically, components SHE1 are arranged above columns RP in rows 3, 6, 9, 14, 17, and 20 from the left side of the paper in Figure 5A, in a way that divides the area above the column RP. The area between two adjacent components SLT or components SHE1 in the Y direction corresponds to one read control signal line RBS. That is, the read port RPB contains a plurality of read control signal lines RBS. In the example shown in Figure 5A, the six-layer wiring layer 14 above the read port RPB is divided into eight sections in the Y direction by components SLT and components SHE1. That is, the wiring layer 14, which functions as area bit lines LBL or read control signal lines RBS, is divided into eight sections in the Y direction. The eight read control signal lines RBS0~RBS7 are arranged, for example, from the left side of the paper, in the order of read control signal lines RBS6, RBS0, RBS7, RBS1, RBS2, RBS4, RBS3 and RBS5.

[0107] Next, the component SHE2, extending in the Y direction, separates the upper 3 wiring layers 14, which function as the region bit line LBL, in the X direction. Thus, the upper 3 wiring layers 14 become floating gates separated in both the X and Y directions (vertical and horizontal separation). If wiring layers 16 (region bit lines LBL) are electrically connected to these layers, an amplifying transistor APT can be formed. Since the lower 3 wiring layers 14 in the upper 6 layers enable / disable the drive of the amplifying transistor APT, it functions as the read control signal line RBS, which is input to the gate of the transistor RST connected in series with the amplifying transistor APT.

[0108] For example, each region bit line LBL (wiring layer 16) is electrically connected to any of the cross-sectionally separated wiring layers 14 in the region of any of the read control signal lines RBS0 to RBS7. For example, in the cross-sectionally separated wiring layer 14 corresponding to the region of read control signal line RBSk (k is an integer from 0 to 7), the region bit line LBL(8j+k) (j is an integer greater than or equal to 0) is electrically connected. Furthermore, the number and arrangement order of the read control signal lines RBS divided in the Y direction are arbitrary.

[0109] The separation gate (gate of the amplifying transistor APT) separated by components SHE1 and SHE2, i.e., the wiring layer 14 which functions as the region bit line LBL, has an area of ​​2×2 pillars RP, with 2RP vertically (2 pillars RP in the X direction) and 2RP horizontally (2 pillars RP in the Y direction). Since the separation gate is formed according to each wiring layer 16 that functions as the region bit line LBL, 8 segments are formed in the horizontal direction (Y direction) of the paper. The region bit line LBL (wiring layer 16) extending from the cell block CB (not shown) located on the right side of the paper to the left side of the paper is electrically connected to the wiring layer 14, which functions as the gate of the amplifying transistor APT, via contact plug CP2. The bit line BL (wiring layer 17) is connected to the pillars RP via contact plugs CP4 and CP3. The pillars RP reach the read source line RSL (semiconductor layer 12) via the amplifying transistor APT and the transistor RST connected to the read control signal line RBS. The read source line RSL is electrically connected to the upper wiring layer (not shown) via the conductor LI of the component SLT located in the center of the read port RPB (between read control signal lines RBS1 and RBS2).

[0110] The signal (voltage) applied to the read source line RSL can be a different signal (different voltage) from the signal (voltage) applied to the source line SL, or can be the same signal (same voltage). In the case of different signals, the source potential of the amplification transistor APT can be adjusted separately from the potential of the source line SL. Therefore, when the potential of the local bit line LBL varies within the range of 0 V ("0" data) to 0.7 V ("1" data), it is desirable that the threshold voltage Vt of the amplification transistor APT satisfies 0 V < Vt < 0.7 V. For example, when the threshold voltage Vt is 0.7 V or higher, the potential of the read source line RSL can be lowered for adjustment. Also, in order to adjust the deviation of the threshold voltage Vt of the amplification transistor APT, when adjusting the threshold voltage Vt by the injection / release operation of electrons to / from the amplification transistor APT, it is desirable to apply an independent signal to the read source line RSL.

[0111] In FIG. 5A, there is an unused pillar RP near the contact plug CP2, but the contact plug CP2 is not electrically connected to the silicon channel layer 21 in the pillar RP. The contact plug CP2 is only electrically connected to the wiring layer 14 that functions as the local bit line LBL. Also, when electrically connected to the silicon channel layer 21 in the pillar RP, the semiconductor layer 12 directly below the bottom of the pillar RP can be removed to make the pillar RP floating.

[0112] Next, referring to FIG. 5B, a second example of the planar layout of the read port portion RPB will be described. Hereinafter, the description will focus on the differences from the first example.

[0113] As shown in FIG. 5B, in this example, in order to more easily connect the contact plug CP2 to the wiring layer 14, the unused pillar RP located near the contact plug CP2 described in FIG. 5A is removed. There is concern about the breakdown of the uniformity of the hole processing corresponding to the pillar RP. In this case, after forming a plurality of holes corresponding to the planar layout described in FIG. 5A, as shown in FIG. 5B, the useless holes can also be filled with an insulator and then the contact plug CP2 can be formed.

[0114] 1.4 Cross-sectional structure in the character line direction of the write port portion and the read port portion Next, referring to Figures 6A and 6B, an example of the cross-sectional structure of the write port WPB and read port RPB in the word line direction (X direction) will be described. Figure 6A shows a cross-sectional view of the write port WPB cut along lines A1-A2 and B1-B2 of Figure 4 in the word line direction (X direction). Figure 6B shows a cross-sectional view of the read port RPB cut along lines C1-C2 and D1-D2 of Figure 5A in the word line direction (X direction). Furthermore, in the description using Figures 6A and 6B, the differences from the cross-sectional structure of the gain block gBK in the bit line direction described using Figure 3 will be the focus of the explanation.

[0115] First, referring to Figure 6A, the cross-sectional structure of the character line direction of the WPB in the writing port will be explained.

[0116] Figure 6A(a) shows a cross-section along line A1-A2 of Figure 4, and Figure 6A(b) shows a cross-section along line B1-B2 of Figure 4. In other words, Figure 6A(a) shows the connection between wiring layer 16 (region bit line LBL) and post WP2, and Figure 6A(b) shows the connection between wiring layer 17 (bit line BL) and post WP1.

[0117] As shown in Figure 6A(a), the wiring layer 16, which functions as the regional bit line LBL, is connected to the semiconductor layer 12, which functions as the bottom bit line bBL, via the contact plug CP1 and the post WP2.

[0118] The semiconductor layer 12 on the right side of Figure 6A(a) is the same as the semiconductor layer 12 on the right side of Figure 6A(b). Similarly, the semiconductor layer 12 on the left side of Figure 6A(a) is the same as the semiconductor layer 12 on the left side of Figure 6A(b). Therefore, the pillar WP2 on the right side of Figure 6A(a) is electrically connected to the pillar WP1 on the right side of Figure 6A(b) via semiconductor layer 12. Also, the pillar WP2 on the left side of Figure 6A(a) is electrically connected to the pillar WP1 on the left side of Figure 6A(b) via semiconductor layer 12.

[0119] As shown in Figure 6A(b), post WP1 is electrically connected to the wiring layer 17, which functions as bit line BL, located above, via contact plugs CP3 and CP4. Therefore, the area bit line LBL is electrically connected to bit line BL via contact plug CP1, post WP2 in Figure 6A(a), bottom bit line bBL, post WP1 in Figure 6A(b), contact plugs CP3 and CP4.

[0120] Next, referring to Figure 6B, the cross-sectional structure of the character line direction of the read port RPB will be described.

[0121] Figure 6B(a) shows a cross section along line C1-C2 of Figure 5A, and Figure 6B(b) shows a cross section along line D1-D2 of Figure 5A.

[0122] As shown in Figure 6B(b), the wiring layer 16, which functions as the regional bit line (LBL), is connected to the gate of the amplifying transistor (APT) via the contact plug CP2, and is electrically connected to the wiring layer 14, which functions as the upper three layers of the LBL. The wiring layer 14, which functions as the LBL, is separated in the X direction by a component SHE2 extending in the Y direction (bit line direction). The component SHE2, for example, contains silicon oxide as an insulating material.

[0123] As shown in Figure 6B(a), the post RP is electrically connected to the wiring layer 17 above, which functions as the bit line BL, via contact plugs CP3 and CP4. The amplifying transistor APT, which sets the region bit line LBL as the gate, drives the bit line BL, and its current flows to the read source line RSL.

[0124] The semiconductor layer 12 (bottom bit line bBL) of the write port WPB is segmented according to the bit lines LBL of each electrically connected region. In contrast, the semiconductor layer 12 (read source line RSL) of the read port RPB is a common wiring for all read port RPBs. In this way, by sharing multiple process steps with the manufacturing steps of the memory cell MC (memory pillar MP), costs can be reduced.

[0125] 1.5 Chip Composition of Non-volatile Semiconductor Memory Devices Next, referring to Figures 7A, 7B, 7C, and 7D, an example of the wafer configuration of the non-volatile semiconductor memory device 1 will be described. Figure 7A is a layout diagram showing an example of the wafer layout of the non-volatile semiconductor memory device 1. Figure 7A(a) shows the layout of the memory cell array process layer. Figure 7A(b) shows the layout of the transistor section below the memory cell array or the CMOS (Complementary Metal Oxide Semiconductor) wafer side of the wafer bonding. Figure 7B shows an example of a cross-sectional view of the WL plane TR corresponding to the cell block CB. Figure 7C shows an example of the bonding of the array wafer and the CMOS wafer. Figure 7D shows an example of the cross-sectional configuration of the memory cell array process layer and the transistor section below it.

[0126] First, referring to Figures 7C and 7D, the configuration of the non-volatile semiconductor memory device 1 will be described.

[0127] As shown in Figure 7C, a gain block gBK, comprising a cell block CB, a read port RPB, and a write port WPB, is formed on the array chip. Furthermore, a page buffer PB, a WL_SG driver DV, and peripheral circuitry PC are formed on the CMOS chip. Alternatively, the array chip and the CMOS chip can be bonded together to form a bonded structure.

[0128] As shown in Figure 7D, multiple gain blocks gBK can also be formed on the memory cell array process layer, and the page buffer PB, WL_SG driver DV, and peripheral circuit PC can be formed in the transistor section (FEOL (Front End of Line) region) below.

[0129] As shown in Figure 7A(a), for example, in a memory cell array process layer, a plurality of gain blocks gBK, each with a read port RPB and a write port WPB on both sides of a cell block CB, are arranged vertically on the paper to form a memory cell array MA. The plurality of gain blocks gBK are commonly connected to a bit line BL. Furthermore, the bit line BL is connected to a page buffer PB located on the CMOS chip (or the FEOL area below the memory cell array). A region bit line LBL is configured on each gain block gBK. The word lines WL, string select signal lines SGDT, SGD, and SGS of the plurality of memory cell strings MSR are each connected to the WG_SG driver DV located on the CMOS chip via contact plugs CC located on the WL plane TR. The read control signal line RBS and the write control signal lines WBS0 and WBS1 are respectively connected to the RPB control unit and the WPB control unit located on the CMOS chip via contact plugs CC located on the RPB plane and the WPB plane, respectively. As shown in Figure 7A, the bit line BL is a single line along the entire vertical axis of the paper. Even if the number of page buffers PB is reduced to suppress the increase in chip area, and the number of serial cells of memory cell strings MSR is 1000~2000, high-speed operation can still be achieved.

[0130] More specifically, as shown in Figure 7A(a), a memory cell array MA and a pad region PD are set on the memory cell array process layer. In the example shown in Figure 7A(a), the memory cell array MA includes four gain blocks gBK. Each gain block gBK includes a cell block CB, a write port WPB, a read port RPB, a WL step surface TR, a WPB step surface, and an RPB step surface.

[0131] Multiple gain blocks gBK within the memory cell array MA are commonly connected to bit line BL. The cell blocks CB, write port WPB, and read port RPB within each gain block gBK are commonly connected to the region bit line LBL.

[0132] In each gain block gBK, a read port RPB and a write port WPB are arranged on both sides of the cell block CB in the vertical direction on the paper. For example, four gain blocks gBK are arranged in the vertical direction on the paper.

[0133] The wiring layer 14 of the TR cell block CB in the WL plane and the connection area of ​​the corresponding contact plug CC. The wiring layer 14 of the WPB write port and the connection area of ​​the corresponding contact plug CC. The wiring layer 14 of the RPB read port and the connection area of ​​the corresponding contact plug CC.

[0134] As shown in Figure 7B, for example, in the WL-step TR, the X-direction end of the wiring layer 14 disposed in cell block CB is pulled out in a stepped manner. Furthermore, a contact plug CC extending in the Z-direction is connected to each stepped wiring layer 14. The contact plug CC is electrically connected to a wiring layer (not shown) disposed on the upper layer. The contact plug CC contains, for example, tungsten or copper as a conductive material. The same applies to the WPB and RPB-step surfaces. The WL-step TR is also referred to as the "character line stepped section".

[0135] As shown in Figures 7A(a) and (b), the pad area PD is, for example, the area where a pad for connecting power lines, etc., is formed.

[0136] As shown in Figure 7A(b), the CMOS chip side (FEOL side) is provided with a page buffer PB, peripheral circuit PC, WL_SG driver DV, WPB control unit, RPB control unit and pad area PD.

[0137] The peripheral circuitry PC includes a sequencer (not shown), a voltage generation circuit, and input / output circuits. For example, the timing generator controls the operation of the entire non-volatile semiconductor memory device 1. For example, the timing generator performs write, read, and erase operations. The voltage generation circuit generates voltages for write, read, and erase operations. The input / output circuits are circuits that input and output various signals to and from external devices.

[0138] The WL_SG driver DV includes a driver that supplies voltage to the word lines WL and the serial select signal lines SGDT, SGD, and SGS of the cell block CB. The WL_SG driver DV is electrically connected to the WL step surface TR via the contact plug CC. That is, the WL_SG driver DV is electrically connected to the word lines WL and the serial select signal lines SGDT, SGD, and SGS. In the example shown in Figure 7A(b), four WL_SG driver DVs are provided corresponding to four cell blocks CB.

[0139] The WPB control unit is a circuit that controls the write control signal lines WBS0 and WBS1. The WPB control unit is electrically connected to the WPB surface via the contact plug CC. That is, the WPB control unit is electrically connected to the write control signal lines WBS0 and WBS1. In the example shown in Figure 7A(b), four WPB control units are provided for the four write ports.

[0140] The RPB control unit is a circuit that controls the read control signal line RBS. The RPB control unit is electrically connected to the RPB surface via a contact plug CC. That is, the RPB control unit is electrically connected to the read control signal line RBS. In the example shown in Figure 7A(b), four RPB control units are provided corresponding to the four read ports RPB.

[0141] 1.6 Effects of this implementation The effects of this embodiment will be explained.

[0142] Figure 8 is a graph showing the effect of the first embodiment, the number of gain blocks (bit line segments) per bit line of the memory cell array MA, the number of stackable word lines, and the ratio of the consumption of the gain block gBK to the memory cell array MA.

[0143] The gain block gBK includes the cell block CB, and the read port RPB and write port WPB located on both sides of the cell block CB. Therefore, the area of ​​the memory cell array MA includes the area of ​​the read port RPB and the write port WPB (hereinafter also referred to as "consumption").

[0144] As shown in Figure 8, if the number of gain blocks per bit line increases, the number of read port RPBs and write port WPBs (consumption) increases with the number of gain blocks gBK. However, for example, when the gain blocks gBK are divided into 16 parts, the consumption relative to the memory cell array MA is suppressed to about 3.3%. At this time, the number of stackable word lines is 2592, which is more than 2000 layers. For example, when the ratio of bit line length to region bit line length is 64 (divided into 64 parts), the area of ​​the memory cell array MA increases by 13%, achieving a word line stacking layer count of 10000 layers. This solves the low-speed problem caused by insufficient cell current Icell and the problem of increased chip area when the speed is constant. The inventors refer to this 3D-NAND flash memory as gNAND (gain NAND Flash, or gain Block NAND Flash Memory). Alternatively, the inventors also refer to it as gBiCS Flash (gain Bit Cost Scalable Flash).

[0145] Figure 9 is a diagram showing a comparison of the chip size of a comparative example with an embodiment of the present embodiment, illustrating the effect of the first embodiment when the processing speed is increased by 4 times. For example, high-speed NAND flash memory can be used as cache memory in memory such as CXL (Compute Express Link). Figure 9(a) shows an example of the chip size of 3D-NAND flash memory (e.g., BiCS Flash) before 4 times speed increase. Figure 9(b) shows the chip size when 4 times speed increase is performed while maintaining the previous method, as a comparative example. Figure 9(c) shows the chip size when 4 times speed increase is performed using the present embodiment, as an embodiment.

[0146] For example, to set the access time tR of the memory cell array MA to 1 / 4, each delay needs to be set to 1 / 4. If the memory cell array MA is divided into two parts in the word line direction (wafer lateral direction), the word line delay becomes 1 / 2 because the word line length becomes 1 / 2, so the resistance and capacitance also become 1 / 2, and the total delay can be set to 1 / 4. However, the bit line length is determined by the resistance R and the bit line capacitance C in the cell current Icell. Therefore, if the bit line length is not set to 1 / 4, the drive time of the bit line BL cannot achieve a 4-fold increase in speed. Thus, as shown in Figure 9(b), even if the bit line BL is divided into 4 parts, the area of ​​the page buffer PB of each bit line BL remains unchanged. Therefore, the page buffer PB in the vertical direction of the chip increases from 2 segments to 8 segments, the CMOS chip exposes the array chip, and the chip size increases by 223% compared to Figure 9(a). On the other hand, as shown in Figure 9(c), in this embodiment, even if the memory cell array MA is divided into two in the word line direction, the area occupied by the WL step surface TR (word line step portion) is smaller than that of the page buffer PB, resulting in a smaller area increase. The bit line BL is not divided in the bit line direction; a region bit line LBL of 1 / 4 the length of the bit line BL is formed. In this case, as shown in Figure 8, the power consumption of the read port RPB and write port WPB is only 0.4%. As a result, if this embodiment is applied, a 4x speed chip is achieved while maintaining a chip size of only 113%.

[0147] Figure 10 is a diagram showing a comparison of the chip size of a comparative example when the memory capacity is increased fourfold, illustrating the effect of the first embodiment, and an embodiment of this embodiment. Figure 10(a) shows an example of the chip size of a 3D-NAND flash memory (e.g., BiCS Flash (registered trademark)) before the fourfold increase in capacity. Figure 10(b) shows, as a comparative example, the chip size when the capacity is increased fourfold while maintaining the previous method. Figure 10(c) shows, as an embodiment, the chip size when the capacity is increased fourfold using this embodiment.

[0148] The chip size in Figure 10(a) is set to 100%. As shown in Figure 10(b), according to the previous method, when the capacity is increased fourfold under constant speed conditions, the number of word line divisions WL is the same as in Figure 10(a), but the number of word line stacks becomes fourfold. Therefore, the area of ​​the WL step surface TR (word line step portion) needs to be fourfold. Furthermore, since the number of word line stacks becomes fourfold, the cell current Icell becomes 1 / 4. Therefore, in order to set the bit line capacitance to 1 / 4, the bit line BL needs to be divided into four parts. As a result, the page buffer PB exceeds the size of the array chip and is exposed, resulting in the chip size becoming 260%. On the other hand, in the embodiment of Figure 10(c), when the capacity is increased fourfold, the area of ​​the WL step surface TR becomes fourfold in the word line direction, but in the bit line direction, according to the configuration of four gain blocks gBK connected to each bit line BL, the chip size increases slightly. As a result, 3D-NAND flash memory with 130% smaller chip size and 4 times the memory capacity can be achieved.

[0149] Figure 11 shows the relationship between the number of gain blocks per bit line of the memory cell array MA, (a) read latency (tR), and (b) wafer size, representing a more detailed effect of the first embodiment.

[0150] As shown in Figure 11(a), if the number of word line segments is increased to 2 or 4, the word line delay is reduced to 1 / 4 or 1 / 8, and the read delay (tR) becomes the delay rule of the bit line BL. Furthermore, if the number of bit line segments or gain blocks is increased to 2, 4, 8, or 16, the delay of the bit line BL is proportional to it, decreasing to 1 / 2, 1 / 4, 1 / 8, or 1 / 16.

[0151] As shown in Figure 11(b), in the comparative example (previous method), if bit line splitting is advanced, the area of ​​the page buffer PB becomes enormous, and the chip size increases sharply. In contrast, in this embodiment, even if the number of bit line splits increases, the chip size only increases slightly.

[0152] As shown in Figures 11(a) and (b), in the comparative example (previous method), to achieve a read latency tR = 10 µs, the word line WL needs to be divided into 4 parts, and the bit line BL needs to be divided into 4 parts. In this case, the chip size becomes 2.6 times. In contrast, in this embodiment, by combining the conditions of a relatively small increase in chip size, a bit line division number of 16, and a word line division number of 2, tR = 10 µs can be achieved with a 1.1 times increase in chip area.

[0153] Figure 12 shows the relationship between memory capacity and chip size under constant speed conditions when increasing memory capacity by stacking word lines (WL) of 3D-NAND flash memory, illustrating the effect of the first embodiment. In the comparative example (previous method) and the embodiment, increasing the number of word line stacking layers increases the area of ​​the WL step surface TR (word line step portion) and the WL_SG driver (drive circuit). Reducing the area requires other techniques, namely, shrinking the area of ​​the WL step surface TR (word line step portion). Because the number of word line stacking layers increases (N times) in the bit line direction, the area of ​​the page buffer PB increases (N times) in the comparative example (previous method), but hardly increases in the embodiment.

[0154] Figure 13 shows the effect of word line stacking (WL) in the first embodiment, relating memory capacity to cost per gigabyte (GB) as memory capacity increases from 1 Tb. Here, the silicon mobility and speed are constant. Figure 13(a) shows the case where the number of word line stacks per tier is constant. Here, 1 Tier is the unit for RIE (Reactive Ion Etching) opening of memory vias (MH). Figure 13(b) shows the case where the number of word line stacks per tier can increase slowly as the number of word line stacks increases.

[0155] As shown in Figure 13(a), in the comparative example (previous method), if the number of word line stacks is increased, the area of ​​the page buffer PB increases to compensate for the decrease in cell current Icell, thus leading to cost saturation at 2 Tb. On the other hand, in the embodiment, if the WL step surface TR (word line step portion) can be gradually reduced, the number of word line stacks can be increased, and if the memory capacity is increased to 4 Tb~16 Tb, the cost / GB continues to decrease.

[0156] For example, in previous configurations, multiple memory cell strings were connected to the bit line BL, resulting in reduced cell current and fatally slower operation. In contrast, with the configuration of this embodiment, the number of memory cell strings (MSRs) connected to each region bit line LBL can be reduced, significantly reducing the load capacity driven by cell current and enabling faster readout of the region bit line LBL. Therefore, even with high stacking of the word line WL and doubling the number of cascaded memory cell strings (MSRs), the load on the region bit line LBL is reduced, thus achieving the same or even higher speed as before. Furthermore, the potential of the region bit line LBL can drive the large-capacity bit line BL amplified by the amplifying transistor APT, but the number of cascaded transistors in the amplification section is relatively small, allowing this section to operate at high speed.

[0157] 2. Second Implementation Form Next, the second embodiment will be described. In the second embodiment, the case where the read source line RSL and the source line SL are shared by a single semiconductor layer 12 will be described. Alternatively, the read source line RSL and the source line SL can also be electrically connected via other wiring. Hereinafter, the differences from the first embodiment will be the focus of the description.

[0158] Referring to Figures 14A, 14B, and 14C, an example of the configuration of the read port RPB will be described. Figure 14A is a top view showing a first example of the plan layout of the read port RPB in the second embodiment. Figure 14B is a top view showing a second example of the plan layout of the read port RPB in the second embodiment. Figure 14C shows an example of a cross-sectional view of the read port RPB in the bit line direction (Y direction) of the second embodiment.

[0159] Referring to FIG14C, firstly, the cross-sectional structure of the read port RPB of the second embodiment will be described.

[0160] As shown in Figure 14C, the semiconductor layer 12, which functions as the read source line RSL, is not interrupted in the Y direction within the read port RPB. The semiconductor layer 12, which functions as the read source line RSL, extends in the Y direction and is shared with the semiconductor layer 12, which functions as the source line SL. In other words, the pillar RP is connected to the semiconductor layer 12, which functions as the source line SL. Other configurations are the same as in Figure 3 of the first embodiment.

[0161] Next, referring to FIG14A, the first example of the planar layout of the read port RPB in the second embodiment will be described.

[0162] As shown in Figure 14A, in this example, in Figure 5A of the first embodiment, the component SLT, which is located between the read control signal lines RBS1 and RBS2, is replaced with component SHE1. The other layouts are the same as those in Figure 5A of the first embodiment.

[0163] Next, referring to FIG14B, a second example of the planar layout of the read port RPB in the second embodiment will be described.

[0164] As shown in Figure 14B, in this example, the unused post RP located near the contact plug CP2 described using Figure 14A is removed. That is, in this example, in Figure 5B of the first embodiment, the component SLT disposed between the read control signal lines RBS1 and RBS2 is replaced with component SHE1.

[0165] The basic effect of this embodiment is the same as that of the first embodiment, using the cell block CB process structure to realize an amplifying transistor APT using multilayer layers and pillars RP. The differences from the first embodiment are as follows: the current flowing in the current path of the amplifying transistor APT passes through the transistor RST connected to the read control signal line RBS, and is shared with the source line SL of the cell block CB. The read source line RSL is shared with the source line SL of the component SLT connected to the end of the read port RPB.

[0166] 3. Third Implementation Form Next, the third embodiment will be described. In the third embodiment, the connection positions of the two pillars WP1 and WP2, and the connection position of pillar RP and the read source line RSL, are different from those in the first embodiment. Hereinafter, the description will focus on the differences from the first and second embodiments.

[0167] Referring to Figures 15, 16, 17A, and 17B, an example of the configuration of the gain block gBK in the third embodiment will be described. Figure 15 shows an example of the equivalent circuit diagram of the gain block gBK in the third embodiment. Figure 15 shows an example including a cell block CB comprising a plurality of memory cell strings MSRs connected to the region bit line LBL, a write port WPB that transfers the potential of the bit line BL to the region bit line LBL, and a read port RPB that amplifies the potential of the region bit line LBL and transfers it to the bit line BL. Figure 16 shows an example of a cross-sectional view of the gain block gBK in the bit line direction (Y direction) of the third embodiment. Figure 16 shows an example of a cross-sectional structure comprising a portion of a cell block CB of a plurality of memory cell strings (MSRs) connected to the region bit line LBL, a write port WPB that transfers the potential of the bit line BL to the region bit line LBL, and a read port RPB that amplifies and transfers the potential of the region bit line LBL to the bit line BL. Figures 17A(a) and (b) show cross-sectional views in the word line direction (X direction) of the write port WPB. Figures 17B(a) and (b) show cross-sectional views in the word line direction (X direction) of the read port RPB.

[0168] As shown in Figure 15, the circuit configuration of cell block CB is the same as that in the first embodiment.

[0169] The WPB port is connected to the source of transistor WST1, which is connected to bit line BL via string WSR1, and to the source of transistor WST1, which is connected to bit line LBL via string WSR2. In this embodiment, the sources of dummy transistor DT of string WSR1 and dummy transistor DT of string WSR2 are not connected to each other.

[0170] In the read port RPB, the source of transistor RST is connected to the read source line RSL. The source of dummy transistor DT is not connected to the read source line RSL. In this embodiment, the dummy cell DC and dummy transistor DT of the write port WPB and read port RPB are not used as current paths.

[0171] As shown in Figure 16, the memory column MP of this embodiment includes a lower memory column LMP and an upper memory column UMP disposed above the lower memory column LMP. The structure of the lower memory column LMP and the upper memory column UMP is the same as that of the memory column MP described using Figure 3 of the first embodiment. The lower memory column LMP has multiple wiring layers 14 that function as word lines WL or serial select signal lines SGS, and its bottom surface is connected to the semiconductor layer 12. The upper memory column UMP has multiple wiring layers 14 that function as serial select signal lines SGDT or SGD. A contact plug CP1 is disposed on the upper memory column UMP. In the Z direction, a wiring layer 40 is disposed between the wiring layer 14 that functions as word lines WL0 and the wiring layer 14 that functions as serial select signal lines SGD. The upper surface of the lower memory column LMP and the lower surface of the upper memory column UMP (the side facing the opposite end in the Z direction) are in contact with the wiring layer 40. The wiring layer 40 in the cell block CB functions as a junction JCT connecting the lower memory column LMP and the upper memory column UMP contained in a memory column MP. Therefore, a wiring layer 40 is provided for each memory column MP. The wiring layer 40 provided in the cell block CB is not in contact with the conductor LI of the component SLT. Alternatively, the wiring layer 40 of the cell block CB may be omitted. In this case, the upper memory column UMP is provided above the lower memory column LMP.

[0172] As shown in Figures 16 and 17A, in the write port WPB, the cylinder WP has the same structure as the memory cylinder MP. In the Z direction, a wiring layer 40 is provided between the wiring layer 14 that functions as the dummy character line dWL and the wiring layer 14 that functions as the write control signal line WBS1.

[0173] Pillar WP1 includes a lower pillar LWP1 and an upper pillar UWP1. Similarly, pillar WP2 includes a lower pillar LWP2 and an upper pillar UWP2. Hereinafter, when neither lower pillar LWP1 nor LWP2 is limited, it will only be referred to as "lower pillar LWP". When neither upper pillar UWP1 nor UWP2 is limited, it will only be referred to as "upper pillar UWP". No semiconductor layer 12 is provided below the lower pillars LWP1 and LWP2. That is, no semiconductor layer 12 is provided in the write port WPB. The upper surfaces of the lower pillars LWP1 and LWP2 and the lower surfaces of the upper pillars UWP1 and UWP2 are in contact with the wiring layer 40. A contact plug CP3 is provided on the upper pillar UWP1 connected to the bit line BL (wiring layer 17). A contact plug CP1 is provided on the upper pillar UWP2 connected to the area bit line LBL (wiring layer 16). On a single wiring layer 40, upper bit post UWP1, connected to bit line BL via contact plugs CP3 and CP4, and upper bit post UWP2, connected to area bit line LBL via contact plug CP1, are provided. The wiring layer 40 on the write port WPB functions as an intermediate bit line mBL that electrically connects the two upper bit posts UWP1 and UWP2, i.e., bit line BL and area bit line LBL.

[0174] As shown in Figures 16 and 17B, in the read port RPB, the cylinder RP has the same structure as the memory cylinder MP. In the Z direction, a wiring layer 40 is provided between the wiring layer 14, which functions as the dummy character line dWL, and the wiring layer 14, which functions as the read control signal line RBS.

[0175] Each post RP includes a lower post LRP and an upper post URP. Similar to the write port WPB, no semiconductor layer 12 is provided below the lower post LRP. That is, no semiconductor layer 12 is provided in the read port RPB. The upper surface of the lower post LRP and the lower surface of the upper post URP are in contact with the wiring layer 40. A contact plug CP3 is provided above the upper post URP. The wiring layer 40 provided in the read port RPB functions as the read source line RSL that electrically connects the upper post URP to the conductor LI of the component SLT. A plurality of upper posts URP are provided on one wiring layer 40.

[0176] The third embodiment achieves the same effect as the first embodiment. Because the capacitance of the region bit line LBL is reduced, even with an increase in the number of word line stacks and a decrease in cell current Icell, the driving time of the region bit line LBL can be shortened. Furthermore, the signal of the region bit line LBL serves as the input to the amplifying transistor APT of the read port RPB, enabling high-speed driving of the bit line BL. The write operation is performed by setting the voltages of the write control signal lines WBS0 and WBS1 of the write port WPB to a high level and electrically connecting the region bit line LBL to the bit line BL. The difference from the first embodiment is that no semiconductor layer 12 is provided in the read port RPB and the write port WPB. In the write port WPB, a wiring layer 40 is provided between the wiring layer 14, which functions as the dummy word line dWL, and the wiring layer 14 located above it, which functions as the write control signal line WBS1, to function as the intermediate bit line mBL. Similarly, in the read port RPB, a wiring layer 40 that functions as the read source line RSL is provided between the wiring layer 14 that functions as the dummy character line dWL and the wiring layer 14 located above that functions as the read control signal line RBS.

[0177] When written into the port WPB, the bit line BL is electrically connected to the region bit line LBL via transistors WST0 and WST1 connected in series with WSR1, wiring layer 40 (intermediate bit line mBL), and transistors WST1 and WST0 connected in series with WSR2.

[0178] In the read port RPB, the bit line BL is electrically connected to the wiring layer 40 (read source line RSL) via the amplifying transistor APT and the transistor RST.

[0179] In this embodiment, as in the first embodiment, the dummy cells DC and dummy transistors DT of the serial WSR and RSR are not used as current paths. In this embodiment, by providing a wiring layer 40 between the stacked layers, the parasitic resistance degradation of write and read operations can be suppressed. In the read port RPB and write port WPB, the dummy cell DC corresponding to the dummy word line dWL located below the wiring layer 40, and the dummy transistor DT corresponding to the dummy serial select signal line dSGS, become floating in a floating state by eliminating the semiconductor layer 12, so there is no problem in operation. When the uniformity of the processing of the memory via MH and the vias corresponding to the pillars WP and RP is important, it is sufficient to retain the dummy vias located below the wiring layer 40.

[0180] 4. Fourth Implementation Form Next, the fourth embodiment will be described. In the fourth embodiment, the structure of the lower memory column LMP, lower memory columns LWP and LRP described in the third embodiment is deleted. Hereinafter, the description will focus on the differences from the first to third embodiments.

[0181] Referring to Figures 18, 19, 20A, and 20B, an example of the configuration of the gain block gBK in the fourth embodiment will be described. Figure 18 shows an example of the equivalent circuit diagram of the gain block gBK in the fourth embodiment. Figure 18 shows an example including a cell block CB comprising a plurality of memory cell strings MSRs connected to the region bit line LBL, a write port WPB that transfers the potential of the bit line BL to the region bit line LBL, and a read port RPB that amplifies the potential of the region bit line LBL and transfers it to the bit line BL. Figure 19 shows an example of a cross-sectional view of the gain block gBK in the bit line direction (Y direction) of the fourth embodiment. Figure 19 shows an example of a cross-sectional structure comprising a portion of a cell block CB of a plurality of memory cell strings (MSRs) connected to the region bit line LBL, a write port WPB that transmits the potential of the bit line BL to the region bit line LBL, and a read port RPB that amplifies the potential of the region bit line LBL and transmits it to the bit line BL. Figures 20A(a) and (b) show cross-sectional views of the write port WPB in the word line direction (X direction) of the fourth embodiment. Figures 20B(a) and (b) show cross-sectional views of the read port RPB in the word line direction of the fourth embodiment.

[0182] As shown in Figure 18, the circuit configuration of cell block CB is the same as that in the first embodiment.

[0183] The difference from Figure 15 of the third embodiment is that the dummy cell DC and dummy transistor DT are eliminated in the write port WPB and read port RPB.

[0184] As shown in Figures 19 and 20A, in this embodiment, the lower posts LWP1 and LWP2, which are described in Figures 16 and 17A of the third embodiment, are abolished when writing into the port WPB.

[0185] As shown in Figures 19 and 20B, in this embodiment, the lower column LRP of the column RP described in Figures 16 and 17B of the third embodiment is abolished in the read port RPB.

[0186] The other components are the same as those in the third embodiment.

[0187] The fourth embodiment achieves the same effect as the first embodiment, and like the third embodiment, the wiring layer 40 can be used as a connection wiring for writing to the port WPB, or as a synchronous power supply for the current flowing in the amplifying transistor APT. The difference from the third embodiment is that the floating and useless pillars formed in the dummy vias lower than the wiring layer 40 are removed.

[0188] 5. Fifth Implementation Form Next, the fifth embodiment will be described. In the fifth embodiment, an example of the write operation and the read operation will be described. Hereinafter, the description will focus on the differences from the first to fourth embodiments.

[0189] The fifth embodiment will be described with reference to Figures 21A, 21B, and 21C. Figure 21A is a simplified equivalent circuit diagram of the gain block gBK in the fifth embodiment. Figure 21B is a timing diagram showing an example of the voltage of each wiring during the write operation of the non-volatile semiconductor memory device 1 in the fifth embodiment. Figure 21C is a timing diagram showing an example of the voltage of each wiring during the read operation of the non-volatile semiconductor memory device 1 in the fifth embodiment.

[0190] As shown in Figure 21A, in the write port WPB, the bit line BL is connected to the region bit line LBL via four transistors WST0, WST1, WST1, and WST0 connected in series. Write control signal lines WBS0 are connected to the gates of two transistors WST0. Write control signal lines WBS1 are connected to the gates of two transistors WST1.

[0191] Within the cell block CB, a memory cell string MSR (memory column MP) is connected to the region bit line LBL. The memory cell string MSR contains serial select transistors STT1, ST1, and ST2, and 2000 memory cells MC0~MC1999. The current paths of serial select transistors STT1 and ST1, memory cells MC0~MC1999, and serial select transistor ST2 within the memory cell string MSR are connected in series sequentially. A serial select signal line SGDT0 is connected to the gate of serial select transistor STT1. A serial select signal line SGD0 is connected to the gate of serial select transistor ST1. Word lines WL0~WL1999 are connected to the control gates of memory cells MC0~MC1999, respectively. A serial select signal line SGS is connected to the gate of serial select transistor ST2.

[0192] In the read port RPB, transistors APT and RST are connected in series. The drain of transistor APT is connected to bit line BL, the source is connected to the drain of transistor RST, and the gate is connected to the region bit line LBL. The source of transistor RST is connected to the read source line RSL, and the gate is connected to the read control signal line RBS.

[0193] Refer to Figure 21B for an explanation of the write operation.

[0194] As shown in Figure 21B, firstly, at time t0, the page buffer PB applies a voltage VBLPG to the bit line BL. The voltage VBLPG is a positive voltage higher than the ground voltage VSS.

[0195] Next, at time t1, a voltage VWBSon is applied to the write control signal lines WBS0 and WBS1 in the write port WPB. The voltage VWBSon is a high-level voltage that sets transistors WST0 and WST1 to the ON state. By applying the high-level voltage VWBSon to the write control signal lines WBS0 and WBS1, transistors WST0 and WST1 become ON. The potential of bit line BL is transferred to region bit line LBL via transistors WST0 and WST1. Bit information from the page buffer PB (which includes the sense amplifier circuit and the write circuit) is transferred to region bit line LBL and memory cell string MSR via transistors WST0 and WST1. Because region bit line LBL is shorter than bit line BL, the load is smaller, thus the non-volatile semiconductor memory device 1 can achieve a higher write speed.

[0196] During time t1~t2, in cell block CB, a write operation is performed on the memory cell MC (hereinafter also referred to as "selected memory cell MC") selected as the write target.

[0197] For example, during time t1 to t2, the word line WL (hereinafter also referred to as "selection word line WL") corresponding to the selected memory cell MC is boosted. At this time, if the potential (voltage VBLPG) of the region bit line LBL is low, the series select transistors STT1 and ST1 are turned on. In this case, the potential of the region bit line LBL is transferred to the silicon channel layer 21 of the selected memory cell MC that is being written to, injecting electrons into the charge trapping layer 222. Hereinafter, this writing operation is referred to as "programmed operation". On the other hand, when the potential (voltage VBLPG) of the region bit line LBL is high, the series select transistors STT1 and ST1 are turned off because the source potential is higher. The silicon channel layer 21 becomes floating, and as the word line WL is boosted, the silicon channel layer 21 is also boosted. Therefore, almost no electrons are injected into the charge trapping layer 222. Hereinafter, this action will be denoted as "Prohibited Programming". In addition, since the write speed follows the FN-tunneling current rule, the number of cells in series in the memory cell string MSR will not degrade even if the number of cells in series increases.

[0198] Next, at time t2, after the write operation in cell block CB is completed, voltage VSS is applied to write control signal lines WBS0 and WBS1.

[0199] Refer to Figure 21C for an explanation of the readout action.

[0200] As shown in Figure 21C, during the read operation, firstly, at time t0, a voltage VREAD is applied to the non-selected word line. Regardless of the threshold voltage, voltage VREAD sets the memory cell MC to the ON state. Next, a voltage VRBSon is applied to the read control signal line RBS. Voltage VRBSon sets the transistor RST to the ON state. Both voltages VREAD and VRBSon are positive voltages higher than the ground voltage VSS. Voltages VREAD and VRBSon can be the same or different.

[0201] Next, at time t1, a voltage VBLRD is applied to the bit line BL. The voltage VBLRD is a positive voltage higher than the ground voltage VSS.

[0202] Next, at time t2, a voltage VWBSon is applied to the write control signal lines WBS0 and WBS1. By turning on transistors WST0 and WST1, the potential of bit line BL is transferred to the region bit line LBL. For example, a voltage VBLRD is applied to the region bit line LBL.

[0203] Next, if at time t3, a voltage VSS is applied as a low-level voltage to the write control signal lines WBS0 and WBS1, then transistors WST0 and WST1 become off. As a result, the region bit line LBL becomes a floating state of precharge voltage VBLRD.

[0204] At this point, the potential of the select word line WL is gradually increased, or it has been preset to a certain potential. In other words, a readout voltage is applied to the select word line WL. When the potential of the select word line WL is lower than the threshold voltage Vt of the select memory cell MC, the select memory cell MC is in the off state, so no current flows from the region bit line LBL to the memory cell string MSR. Therefore, the potential of the region bit line LBL is maintained (LBL "1" in Figure 21C). Conversely, when the potential of the select word line WL is higher than the threshold voltage Vt of the select memory cell, the select memory cell MC is in the on state, so cell current Icell flows in the memory cell string MSR. Therefore, the potential of the region bit line LBL decreases to the ground voltage VSS (LBL "0" in Figure 21C). In this way, the write information to the memory cell MC (hereinafter also referred to as "cell signal") is read (sensed) to the region bit line LBL. At this time, because the capacitance of the region bit line LBL is relatively light, the potential of the region bit line LBL is determined relatively quickly. This result is transmitted to the amplifying transistor APT at the read port RPB. The gate of the amplifying transistor APT is connected to the region bit line LBL, and the drain is connected to the bit line BL. The source of the amplifying transistor APT is connected to the transistor RST, whose gate is connected to the read control signal line RBS. The source of the transistor RST is connected to the read source line RSL. When a high-level voltage VRBSon is applied to the read control signal line RBS, the amplifying transistor APT drives the bit line BL, which has a larger load capacity, and transmits the potential of the bit line BL to the page buffer PB.

[0205] Next, at time t4, the pre-charging of bit line BL by page buffer PB is deactivated (ends). For example, when the potential of the region bit line LBL is maintained (LBL "1" in Figure 21C), the potential of bit line BL decreases because the amplifying transistor APT is turned on (BL "1" in Figure 21C). Conversely, when the potential of the region bit line LBL decreases (LBL "0" in Figure 21C), the potential of bit line BL is maintained because the amplifying transistor APT is turned off (BL "0" in Figure 21C).

[0206] When the actual potential of the bit line BL is released (the pre-charge of the bit line BL is terminated) (the pre-charge signal is disconnected), the signal corresponding to the cell signal is read out. By connecting the amplifying transistor APT and the read control signal line RBS in series with the transistor RST (which is the gate input), the number of transistor levels is several. Even when driving the bit line BL, the driving speed can be more than 10 times faster than the previous 150-250 series-connected memory cell strings MSR, and this high-speed operation is independent of the number of series-connected cells.

[0207] 6. Sixth Implementation Form Next, the sixth embodiment will be explained. In the sixth embodiment, an example of a readout action that differs from the fifth embodiment will be explained. Hereinafter, the explanation will focus on the differences from the first to fifth embodiments.

[0208] Referring to Figures 22A and 22B, the sixth embodiment will be described. Figure 22A is a timing diagram showing an example of the voltage of each wiring when performing a readout operation to reduce coupling noise between region bit lines LBL in the non-volatile semiconductor memory device 1 of the sixth embodiment. Figure 22B is a cross-sectional view showing an example of the cross-sectional structure for reducing coupling noise between region bit lines LBL in the non-volatile semiconductor memory device 1 of the sixth embodiment.

[0209] For example, as illustrated in Figures 32C and 32D, when any one of the string select signal lines SGD separated from component SHE1 is selected, information of memory cells MC is read from all memory columns MP (memory cell strings MSR) connected to the string select signal line SGD. Therefore, when multiple region bit lines LBL connected to the plurality of memory columns MP operate simultaneously, a problem arises where the region bit lines LBL receive noise caused by signals from adjacent memory cell strings MSR due to capacitive coupling with adjacent region bit lines LBL.

[0210] As shown in Figure 22B, as a countermeasure to the above-mentioned problem, the following method can be applied: a thin shielding metal layer 36 is covered on the side and top surfaces of the wiring layer 16 that performs the function of the regional bit line LBL, through an insulating layer 35. More specifically, a thin film insulating layer 35 is formed to cover a plurality of wiring layers 16. The film thickness of the insulating layer 35 is set to the thickness that is not embedded in the inter-wires of the wiring layers 16. The insulating layer 35, for example, contains silicon oxide. And, a shielding metal layer 36 is formed on the insulating layer 35. In this case, it is preferable to also form a shielding metal layer 36 on the side surface of the regional bit line LBL (wiring layer 16). If the shielding metal layer 36 is covered on the wiring layer 16, the inter-wire capacitance of the regional bit line LBL increases. However, in this embodiment, since the length of the region bit line LBL is sufficiently short compared to the length of the bit line BL, the inter-wiring capacitance of the region bit line LBL can be reduced by setting multiple gain blocks gBK, so there is no problem in terms of power consumption and speed.

[0211] As another approach, consider reading the potential of the selected region bit line LBL instead of using adjacent region bit lines LBL.

[0212] As shown in Figure 22A, alternately select odd-numbered bit lines BLo and even-numbered bit lines BLe.

[0213] More specifically, firstly, at time t0, a voltage VREAD is applied to the non-select word line WL. Secondly, a voltage VRBSon is applied to the read control signal line RBS.

[0214] Next, at time t1, voltage VBLRD is applied to bit lines BLo and BLe.

[0215] Next, at time t2, a voltage VWBSon is applied to the write control signal lines WBS0e, WBS1e, WBS0o, and WBS1o on both the odd and even sides. By turning on the odd-numbered transistors WST0o and WST1o corresponding to bit line BLo, the potential of bit line BLo is transferred to the odd-numbered region bit line LBLo. Similarly, by turning on the even-numbered transistors WST0e and WST1e corresponding to bit line BLe, the potential of bit line BLe is transferred to the even-numbered region bit line LBLe. This applies a (pre-charge) voltage VBLRD to the region bit lines LBLo and LBLe.

[0216] Next, at time t3, while maintaining the write control signal lines WBS0o and WBS1o at a high level (voltage VWBSon) and fixing the potential of the region bit line LBLo at a high level (voltage VBLRD), a ground voltage VSS (a low-level voltage) is applied to the write control signal lines WBS0e and WBS1e. This disconnects the transistors WST0e and WST1e. At this time, the cell signal is read out to the region bit line LBLe. Because the potential of the adjacent region bit line LBLo is fixed at a high level, coupling noise of the cell signal read out to the region bit line LBLe is suppressed.

[0217] Next, at time t4, the pre-charge of the page buffer PB on bit line BLe is released. Based on the potential of the region bit line LBLe, the potential of bit line BLe is maintained or decreased. The page buffer PB determines the voltage of bit line BLe and reads the data from bit line BLe.

[0218] Next, at time t5, bit line BLe is precharged again. Ground voltage VSS (low-level voltage) is applied to write control signal lines WBS0o and WBS1o. This turns transistors WST0o and WST1o off. At this time, the cell signal is read out to the region bit line LBLo.

[0219] Next, at time t6, the pre-charge of bit line BLo by the page buffer PB is released. Based on the potential of the region bit line LBLo, the potential of bit line BLo is maintained or decreased. The page buffer PB determines the voltage of bit line BLo and reads the data from bit line BLo.

[0220] The signals of region bit lines LBLo and LBLe are read from bit line BL after the pre-charge is released, by applying a high-level voltage (VRBSon) to the read control signal line RBS and amplifying it with an APT transistor. Coupling between signals on bit line BL can be achieved by maintaining the potential of bit line BL constant and suppressing noise through charge transfer and other methods. Furthermore, the read control signal line RBS can be initially equipped with a high-level voltage, or it can be amplified by the APT transistor after the potential of region bit line LBL is determined, and then a high-level voltage is applied when transmitting signals to bit line BL. Additionally, when region bit lines LBLe and LBLo are to be operated separately with different timing sequences, even-numbered read control signal lines RBSe and odd-numbered read control signal lines RBSo can be used to separate the signals and operate with different timing sequences.

[0221] Next, referring to FIG23, an example of the planar layout of the write port WPB will be described. FIG23 is a top view showing an example of the planar layout of the write port WPB of the sixth embodiment. FIG23 shows a top view of a write port WPB that, corresponding to the description using FIG22A, alternately inputs write control signal lines WBS0o and WBS1o, and write control signal lines WBS0e and WBS1e, to shield adjacent area bit lines LBL.

[0222] As shown in Figure 23, in this embodiment, in the write port WPB, a plurality of wiring layers 14 that function as write control signal lines WBS0e or WBS1e and a plurality of wiring layers 14 that function as write control signal lines WBS0o or WBS1o are separated by component SHE1 in the Y direction (bit line direction).

[0223] The connection positions of the region bit line LBL (wiring layer 16) and the bit line BL (wiring layer 17) are divided into odd and even on the write control signal lines WBS0e and WBS1e, and on the write control signal lines WBS0o and WBS1o, relative to the adjacent region bit line LBL. This allows for easy setting of adjacent region bit lines LBL to a fixed potential, or to a floating potential, or for the cell current Icell to be invoked to the region bit line LBL.

[0224] 7. Seventh Implementation Form Next, the seventh embodiment will be explained. In the seventh embodiment, an example of a readout action that differs from the fifth and sixth embodiments will be explained. Hereinafter, the explanation will focus on the differences from the first to sixth embodiments.

[0225] Referring to FIG24, the seventh embodiment will be described. FIG24 is a timing diagram showing an example of the voltage of each wiring when performing a readout operation to reduce coupling noise between region bit lines LBL in the non-volatile semiconductor memory device 1 of the seventh embodiment.

[0226] In the example shown in Figure 22A of the sixth embodiment, the cell current Icell of the region bit line LBLe is read first. After the voltage of bit line BLe is determined, the cell current Icell of the region bit line LBLo is read. For example, if the region bit line LBLe remains in a floating state after the voltage of bit line BLe is determined, the signal of the region bit line LBLo will be affected by coupling noise caused by the nearby region bit line LBLo as it passes through the floating region bit line LBLe.

[0227] As shown in Figure 24, the actions from time t1 to t4 are the same as those from time t1 to t4 in Figure 22A. At time t3, a low-level voltage (voltage VSS) is applied to the write control signal lines WBS0e and WBS1e, setting transistors WST0e and WST1e to the off state, and the cell signal is read out to the region bit line LBLe. Then, during the period from time t4 to t5, the cell signal is transmitted to the bit line BLe by the amplifying transistor APT, and the result is input to the page buffer PB.

[0228] Next, at time t5, a high-level voltage (VWBSon) is applied to the write control signal lines WBS0e and WBS1e. This turns on transistors WST0e and WST1e, and fixes the region bit line LBLe to voltage VBLRD.

[0229] Next, at time t6, a low-level voltage (voltage VSS) is applied to the write control signal lines WBS0o and WBS1o to set the transistors WST0o and WST1o to the off state, and the cell signal is read out to the region bit line LBLo.

[0230] Next, during the period from t7 to t8, the cell signal is transmitted to the bit line BLo using the amplified transistor APT, and the result is input to the page buffer PB.

[0231] Next, at time t8, a low-level voltage (voltage VSS) is applied to the write control signal lines WBS0e and WBS1e.

[0232] The above process eliminates coupling noise from the region bit line LBL. While the operation of the word line WL slows down when simultaneously reading out the bit line BL in two separate readouts, according to this embodiment, increasing the number of gain blocks gBK significantly increases the operating speed of both the region bit line LBL and the bit line BL, thus eliminating the problem. Furthermore, the potential range of the bit line BL and the region bit line LBL can be 0~0.7 V, 0.3 V~1.0 V, or even... -0.2 V to 1.2 V. Furthermore, to detect memory cells (MC) with low threshold voltages, while setting the source line SL to 0 V, the potential range of the bit line BL and the region bit line LBL can be increased to 0.7 V to 1.4 V. At this time, the potential of the read source line RSL can also be set to approximately 0.7 V, and the threshold voltage of the amplifying transistor APT can be increased while setting the potential of the read source line RSL to approximately 0 V. The potential range of the bit line BL and the region bit line LBL can be freely changed according to the threshold voltage or tolerance of the amplifying transistor APT.

[0233] 8. Eighth Implementation Form Next, the eighth embodiment will be described. In the eighth embodiment, two examples of the method for controlling the threshold voltage Vt of the amplifying transistor APT will be explained. Hereinafter, the description will focus on the differences from the first to seventh embodiments.

[0234] The eighth embodiment will be described with reference to Figures 25A, 25B, and 25C. Figure 25A is a timing diagram showing an example of a method for measuring the threshold voltage Vt of the amplifying transistor APT in the eighth embodiment. Figure 25B is a timing diagram showing a method for fine-tuning the threshold voltage Vt of the amplifying transistor APT in the eighth embodiment. Figure 25C is a timing diagram showing a method for fine-tuning the threshold voltage Vt of the amplifying transistor APT in the eighth embodiment.

[0235] For example, when the potential of the read source line RSL is 0 V, and the potential of the local bit line LBL corresponding to the "1" data is 0.7 V, the amplifying transistor APT is in the on state (Vgs - Vt = 0.7 V - Vt > 0 V). When the potential of the local bit line LBL corresponding to the "0" data is 0 V, the amplifying transistor APT is in the off state (Vgs - Vt = 0 V - Vt < 0 V). Therefore, in order for the amplifying transistor APT with the local bit line LBL as the gate to operate correctly, 0 V < Vt < 0.7 V is the operating condition. If the potential (voltage VRSL) of the read source line RSL is changed, the gate-source voltage Vgs of the amplifying transistor APT can be adjusted. In this case, 0 V < Vt + VRSL < 0.7 V is the operating condition. That is, when the threshold voltage Vt is high, the voltage VRSL is set negative, and when it is low, the voltage VRSL is set positive. The threshold voltage Vt can be adjusted by an annealing process or the like after ion-implanting impurities into the silicon channel layer 21, and can be adjusted by the potential of the read source line RSL. On the other hand, in this embodiment, as the gate electrode of the amplifying transistor APT, the string selection signal layer of the 3D-NAND flash memory can be used, so the threshold voltage Vt can be adjusted by injecting / releasing electrons into / from the charge trapping layer 222 or the floating gate film. Since the size of the amplifying transistor APT formed by the pillar RP is relatively small, the deviation of the threshold voltage Vt is relatively large. Therefore, ideally, the threshold voltage Vt of each amplifying transistor APT is measured, and electrons are injected / released to each amplifying transistor APT to individually adjust the deviation from the desired threshold voltage Vt for the programming operation / verification operation / erase operation (this type of adjustment is also denoted as "fine tuning"). In addition, a multi-layer string selection signal layer (wiring layer 14 that functions as the local bit line LBL) of multiple layers can also be used to increase the effective channel area and suppress the deviation.

[0236] FIG. 25A is a timing diagram showing a method for measuring the deviation of the threshold voltage Vt of the amplifying transistor APT. The condition for switching the amplifying transistor APT from the off state to the on state is (the potential of the local bit line LBL) - (the potential of the read source line RSL) - the threshold voltage Vt = 0 V. Therefore, by measuring the relationship between the potential of the local bit line LBL, the potential of the read source line RSL, and the on / off operation of the amplifying transistor APT, the threshold voltage Vt can be measured.

[0237] As shown in Figure 25A, at time t0, a voltage VBLh is applied to the bit line BL. Voltage VBLh is positive. If the potential of the region bit line LBL is preset and the potential of the source line RSL is read in this state, then when the potential of the region bit line LBL is below the threshold voltage Vt of the amplifying transistor APT, the amplifying transistor APT is in the off state; when it is above the threshold voltage Vt, the amplifying transistor APT is in the on state. At time t1, the pre-charge of the bit line BL is released. If (potential of the region bit line LBL - read source potential - threshold voltage Vt) is positive (above 0 V), the amplifying transistor APT is in the on state, and the potential of the bit line BL decreases. On the other hand, if it is negative (below 0 V), the amplifying transistor APT is in the off state, maintaining the potential of the bit line BL. By changing the potential of the region bit line LBL and reading the potential of the source line RSL while performing the measurement, the threshold voltage Vt of the amplifying transistor APT can be measured. For example, it can be seen that when the potential of the region bit line LBL is kept at 0 V, and the RSL potential is swept from 0 V to negative, and the threshold voltage Vt is 0.3 V, if the RSL potential is lower than... If the voltage drops to -0.3 V, the potential of the bit line BL decreases due to discharge, and the threshold voltage Vt of the amplifying transistor is currently 0.3 V.

[0238] Regarding the measurement results of the threshold voltage Vt, if a higher threshold voltage Vt is desired, electron injection into the charge trapping layer 222 of the amplifying transistor APT is sufficient; if a lower threshold voltage Vt is desired, electron release from the charge trapping layer 222 of the amplifying transistor APT is sufficient. The specific method for adjusting the threshold voltage Vt can be any method, including: FN tunneling, where the source and drain voltages are, for example, 15 V or more higher than the gate voltage of the amplifying transistor APT, to release electrons from the charge trapping layer 222 and lower the threshold voltage Vt; FN tunneling, where the gate voltage is, for example, 15 V or more higher than the source and drain voltages, to inject electrons into the charge trapping layer 222 and increase the threshold voltage Vt; and FN tunneling, where the gate voltage is higher than the source voltage and the drain voltage is higher than the gate voltage, utilizing the hot carrier effect to inject electrons into the charge trapping layer 222 and increase the threshold voltage Vt. By using these methods, the threshold voltage Vt can be adjusted before the product is shipped.

[0239] Referring to Figure 25B, a method for fine-tuning the threshold voltage Vt of an amplifying transistor (APT) by increasing its threshold voltage Vt will be explained. Figure 25B is a timing diagram showing the method for fine-tuning the threshold voltage Vt of an APT by utilizing electron injection with the hot carrier effect. Furthermore, in the explanation of Figure 25B, the bit line BL and region bit line LBL of the APT corresponding to the increase in threshold voltage Vt due to electron injection are denoted as "Programmed," and the bit line BL and region bit line LBL of the APT corresponding to the increase in threshold voltage Vt due to no electron injection are denoted as "Non-prog."

[0240] As shown in Figure 25B, at time t0, a voltage VBLPG1 (e.g., 15 V) is applied to the bit line BL (“programmed”), and a voltage VWBSon (e.g., 10 V) is applied to the write control signal lines WBS0 and WBS1. Transistors WST0 and WST1 are turned on, and a voltage VLBLPG2 (e.g., 7 V) is applied to the region bit line LBL (“programmed”) after the threshold voltages of transistors WST0 and WST1 have decreased. In this way, for example, by applying a drain-source voltage Vds = 15 V and a gate-source voltage Vgs = 7 V to the amplifying transistor APT corresponding to the “programmed”, electrons can be injected into the charge trapping layer 222 using the hot carrier effect. In other words, by applying a voltage higher than the source to the gate and a voltage higher than the gate to the drain of the amplifying transistor APT corresponding to the “programmed”, electrons can be injected into the charge trapping layer 222 using the hot carrier effect. Apply a voltage VSS (e.g., 0 V) ​​to the unselected bit line BL ("unprogrammed"), and set the read control signal line RBS to a low level voltage (e.g., 0 V) ​​in the unselected gain block gBK to stop the hot carriers.

[0241] Referring to Figure 25C, a method for fine-tuning by reducing the threshold voltage Vt of the amplifying transistor APT will be explained. Figure 25C is a timing diagram showing a method for fine-tuning by releasing electrons using the FN tunneling method of erasure operation to reduce the threshold voltage Vt of all amplifying transistors APT.

[0242] As shown in Figure 25C, at time t0, a voltage VERASE is applied to the word line WL and the serial select signal lines SGDT, SGD, and SGS. The voltage VERASE is the voltage that sets the memory cell MC and the serial select transistors STT1, ST1, and ST2 to the ON state. This causes electrons from the region bit line LBL to be released to the source line SL. At this time, the potential of the region bit line LBL is, for example, 0 V.

[0243] Next, if a voltage VH (e.g., 20 V) is applied to the read source line RSL at time t1, hole injection is performed from the read source line RSL to the bit line BL through band-to-band tunneling, or the potential of the bit line BL is increased to a voltage VH (e.g., 20 V), and the source and drain potentials of the amplifying transistor APT are increased to a voltage VH (e.g., 20 V) higher than the gate potential (e.g., 0 V), then the erase operation of releasing electrons from the charge trapping layer 222 of the amplifying transistor APT can be performed, which can reduce the threshold voltage Vt. For example, when the potential of the region bit line LBL is 0 V and the potential of the bit line BL is 20 V, the high electric field difference between the bit line BL and the region bit line LBL can be mitigated in stages by applying a voltage VWBS, for example, 10 V, to the write control signal line WBS0 and a voltage VSS (e.g., 0 V) ​​to the write control signal line WBS1.

[0244] 9. Ninth Implementation Form Next, the ninth embodiment will be described. In the ninth embodiment, two examples will be given of a method for fine-tuning the threshold voltage Vt of the amplifying transistor APT, which differs from the eighth embodiment. Hereinafter, the description will focus on the differences from the first to eighth embodiments.

[0245] Referring to Figures 26A and 26B, the ninth embodiment will be described. Furthermore, in the description of Figures 26A and 26B, the bit line BL and region bit line LBL of the amplifying transistor APT that raises the threshold voltage Vt due to electron injection are denoted as "programmed," and the bit line BL and region bit line LBL of the amplifying transistor APT that does not raise the threshold voltage Vt due to no electron injection are denoted as "unprogrammed."

[0246] First, referring to FIG26A, the first example of a method for fine-tuning the threshold voltage Vt will be described. FIG26A is a timing diagram showing the first example of a method for fine-tuning the threshold voltage Vt of the amplifying transistor APT in the ninth embodiment.

[0247] As shown in Figure 26A, at time t0, a voltage VBL1 (e.g., 10 V) is applied to the bit line BL (“programmed”). A voltage VWBS1 (e.g., 10 V) is also applied to the write control signal lines WBS0 and WBS1. This turns on transistors WST0 and WST1. Furthermore, a voltage VWL1a (e.g., 10 V) is applied to the multiple word lines WL of the cell block CB and the string select signal lines SGDT and SGD. This turns on the memory cell MC and the string select transistors STT1 and ST1. A voltage VLBL1a (e.g., an intermediate voltage of approximately 10 V) is applied to the region bit line LBL (“programmed”) (and the silicon channel layer 21 connected to it). Voltage VLBL1a is a positive voltage lower than voltage VWBS1.

[0248] Next, at time t1, a voltage VSS is applied to bit line BL (“programmed”). A voltage VSS is also applied to write control signal line WBS1. This turns transistor WST1 off, suppressing the backflow of charge from bit line BL pre-charge to region bit line LBL (“programmed”).

[0249] Next, at time t2, a voltage VWL1b (e.g., 20 V) is applied to the multiple word lines WL of the cell block CB and the string select signal lines SGDT and SGD to boost the voltage. Voltage VWL1b is higher than voltage VWL1a. Using the gate-channel capacitor of the memory cell string MSR, the voltage of the region bit line LBL (“programmed”) is boosted to voltage VLBL1b (e.g., approximately 19 V) by self-boosting. At this time, the voltage of the region bit line LBL (“unprogrammed”) is boosted to voltage VLBL1c (e.g., approximately 9 V). Voltage VLBL1c is lower than voltage VLBL1b. A voltage VSS (e.g., 0 V) ​​is applied to the write control signal line WBS1. Voltage VSS is applied to the bit line BL and the read source line RSL. In this state, a voltage VLBL1b (e.g., 19 V) is applied to the gate of the amplifying transistor APT corresponding to the region bit line LBL (“programmed”), and a voltage VSS (e.g., 0 V) ​​is applied to the source and drain. This allows for fine-tuning by increasing the threshold voltage Vt of the amplifying transistor APT through electron injection via FN tunneling.

[0250] Next, at time t3, after the fine-tuning is completed, voltage VSS is applied to the character line WL and the serial select signal lines SGDT and SGD. This reduces the voltage of the boosted region bit line LBL.

[0251] Next, at time t4, a voltage VWBS1 is applied to the write control signal line WBS1. This turns on transistor WST0, releasing electrons from region bit line LBL to bit line BL.

[0252] Next, at time t5, voltage VSS is applied to the write control signal lines WBS0 and WBS1.

[0253] Next, referring to FIG26B, a second example of the method for fine-tuning the threshold voltage Vt will be described. FIG26B is a timing diagram showing a second example of a method for fine-tuning the threshold voltage Vt of the amplifying transistor APT in the ninth embodiment.

[0254] As shown in Figure 26B, at time t0, a voltage VBL2 (e.g., 2 V) is applied to bit line BL (“programmed”), and a voltage VSS (e.g., 0 V) ​​is applied to bit line BL (“unprogrammed”). Voltages VWBS2a (e.g., 2 V) and VWBS2b (e.g., 10 V) are applied to write control signal lines WBS1 and WBS0, respectively. Voltage VWBS2a is, for example, the same as voltage VBL2. Voltage VWBS2b is higher than voltage VWBS2a. Therefore, voltage VLBL2a is applied to the region bit line LBL (“programmed”). Voltage VLBL2a is lower than voltage VWBS2a.

[0255] Next, at time t1, as illustrated in Figure 26A, a voltage VWL2 (e.g., 20 V) is applied to the multiple word lines WL of cell block CB and the serial select signal lines SGDT and SGD to boost the voltage. In the case of bit line BL (“unprogrammed”), because the potential of the region bit line LBL (“unprogrammed”) escapes to bit line BL (“unprogrammed”), the potential of the region bit line LBL (“unprogrammed”) is maintained at voltage VSS (e.g., 0 V). In contrast, in the case of bit line BL (“programmed”), for example, because voltage VBL2 and voltage VWBS2a are the same value, the gate-source voltage Vgs of transistor WST1 is 0 V. Therefore, in transistor WST1, the reverse flow of charge from the region bit line LBL (“programmed”) to bit line BL (“programmed”) is prevented. By boosting the memory cell string (MSR), the region bit line LBL (“programmed”) is boosted to a voltage VBL2b (e.g., 18 V). In this state, a voltage VBL2b (e.g., 18 V) is applied to the gate of the amplifier transistor APT corresponding to the region bit line LBL (“programmed”), a voltage VSS (e.g., 0 V) ​​is applied to the source, and a voltage VBL2 (e.g., 2 V) is applied to the drain. This allows for fine-tuning by increasing the threshold voltage Vt of the amplifier transistor APT using electron injection via FN tunneling. If a voltage VBL2 (e.g., 2 V) is also applied to the drain of the amplifier transistor APT corresponding to the region bit line LBL (“unprogrammed”), and a low-level voltage that sets the transistor RST to the off state is applied to the read control signal line RBS, then the transistor RST becomes off, electrons in the bit line BL (“unprogrammed”) stop moving, and the source of the amplifier transistor APT becomes at the same potential as the gate.

[0256] Next, at time t2, after the fine-tuning is completed, voltage VSS is applied to the character line WL and the serial select signal lines SGDT and SGD. As a result, the voltage of the boosted region bit line LBL (“programmed”) is also reduced.

[0257] Next, at time t3, a voltage VSS is applied to bit line BL (“programmed”). This causes the region bit line LBL (“programmed”) to also decrease to voltage VSS.

[0258] Next, at time t4, a voltage VSS is applied to the write control signal line WBS1.

[0259] Next, at time t5, voltage VSS is applied to the write control signal line WBS0.

[0260] 10. Tenth Implementation Form Next, the tenth embodiment will be described. In the tenth embodiment, two examples will be given regarding the fine-tuning method of the threshold voltage Vt of the amplifying transistor APT, which differs from that of the eighth and ninth embodiments. Hereinafter, the description will focus on the differences from the first to ninth embodiments.

[0261] Referring to Figures 27A and 27B, the tenth embodiment will be described. Furthermore, in the description of Figures 27A and 27B, the bit line BL and region bit line LBL of the amplifying transistor APT that raises the threshold voltage Vt due to electron injection are denoted as "programmed," and the bit line BL and region bit line LBL of the amplifying transistor APT that does not raise the threshold voltage Vt due to no electron injection are denoted as "unprogrammed."

[0262] First, referring to FIG27A, the method for fine-tuning by increasing the threshold voltage Vt will be explained. FIG27A is a timing diagram showing the method for fine-tuning by increasing the threshold voltage Vt of the amplifying transistor APT in the tenth embodiment.

[0263] As shown in Figure 27A, firstly, at time t0, a voltage VBL3a (e.g., 10 V) is applied to bit lines BL (“programmed”) and BL (“unprogrammed”). A voltage VWBS3a (e.g., 20 V) is applied to write control signal lines WBS0 and WBS1. For example, voltage VWBS3a is higher than voltage VBL3a. Transistors WST0 and WST1 are turned on. Subsequently, a voltage VLBL3a is applied to region bit lines LBL (“programmed”) and LBL (“unprogrammed”). For example, voltage VLBL3a is the same value as voltage VBL3a.

[0264] Next, at time t1, a voltage VBL3b (e.g., 20 V) is applied to bit line BL (“programmed”). Voltage VBL3b is higher than voltage VBL3a. Then, a voltage VLBL3b (e.g., 19 V) is applied to region bit line LBL (“programmed”). Voltage VLBL3b is higher than voltage VLBL3a. That is, a boost potential is written from bit line BL (“programmed”) to region bit line LBL (“programmed”). Furthermore, in order to maintain bit line BL at 20 V (voltage VLBL3b), the RST transistor needs to be in the off state. However, to maintain the transistor's withstand voltage, as shown in Figure 27A, an RST transistor controlled by two series-connected read control signal lines RBS0 and RBS1 can be connected below the APT transistor. This allows for a phased mitigation of the 20 V potential difference and keeps the two series-connected RST transistors in the off state.

[0265] Next, at time t2, a voltage VBL3a is applied to bit line BL (“programming”). A voltage VWBS3b (e.g., 10 V) is applied to write control signal lines WBS0 and WBS1. Voltage VWBS3b is lower than voltage VWBS3a. Because transistors WST0 and WST1 corresponding to region bit line LBL (“programming”) are in the off state, the region bit line LBL (“programming”) maintains voltage VLBL3b.

[0266] Next, at time t3, a voltage VSS (e.g., 0 V) ​​is applied to bit lines BL (“programmed”) and BL (“unprogrammed”), write control signal line WBS1, and read control signal lines RBS0 and RBS1. In this state, a voltage VLBL3b (e.g., 19 V) is applied to the gate of the amplifier transistor APT corresponding to the region bit line LBL (“programmed”), a voltage VSS (e.g., 0 V) ​​is applied to the source, and a voltage VSS (e.g., 0 V) ​​is applied to the drain. This allows for fine-tuning by increasing the threshold voltage Vt of the amplifier transistor APT using electron injection via FN tunneling. The write control signal lines WBS0 and WBS1 are stepped at times t2 and t3 to mitigate the electric field, for example, by not applying stress greater than 10 V.

[0267] Next, at time t4, a voltage VWBS3b is applied to the write control signal line WBS1. This releases electrons from the region bit line LBL to the bit line BL.

[0268] Next, referring to FIG27B, the method for fine-tuning by reducing the threshold voltage Vt will be described. FIG27B is a timing diagram showing the method for fine-tuning by reducing the threshold voltage Vt of the amplification transistor APT in the tenth embodiment.

[0269] As shown in Figure 27B, firstly, at time t0, a voltage VBL4 (e.g., 10 V) is applied to the bit line BL (“unprogrammed”). A voltage VWBS4 (e.g., 10 V) is applied to the write control signal lines WBS0 and WBS1. Transistors WST0 and WST1 are turned on. This, in turn, a voltage VLBL4 (e.g., 10 V) is applied to the region bit line LBL (“unprogrammed”). Alternatively, voltage VLBL4 can be the same as voltage VBL4 or a lower voltage.

[0270] Next, at time t1, a voltage VSS (e.g., 0 V) ​​is applied to bit line BL (“unprogrammed”) and write control signal line WBS1. Transistor WST1 is turned off. Region bit line LBL (“programmed”) maintains voltage VSS (e.g., 0 V), and region bit line LBL (“unprogrammed”) maintains voltage VLBL4 (approximately 10 V).

[0271] Next, at time t2, a voltage VRSL (e.g., approximately 20 V) is applied to the read source line RSL and the bit line BL. By utilizing the electron release through FN tunneling, the threshold voltage Vt of the amplifying transistor APT corresponding to the region bit line LBL (“programmed”) can be selectively reduced for fine-tuning. For example, since the voltage of the region bit line LBL moves within the range of 0 V to 10 V, a boost trap is not required. In other words, in the method shown in FIG26B, for example, 0 V is applied to the bit line BL (“programmed”) and for example, 2 V is applied to the bit line BL (“unprogrammed”). Furthermore, by boosting the word line WL and the serial select signal lines SGDT and SGD, the voltage of the region bit line LBL (“programmed”) is set to, for example, 0 V, and the voltage of the region bit line LBL (“unprogrammed”) is set to, for example, 10 V. In this state, the readout source line RSL and bit line BL can also be boosted to 20 V, selectively releasing electrons from the charge trapping layer 222, thereby reducing the threshold voltage Vt of the amplification transistor APT. Applying, for example, 2 V instead of 10 V to the bit line BL, as shown in Figure 26B, can also utilize self-boosting to set the voltage of the region bit line LBL ("unprogrammed") to, for example, 10 V, and the voltage of the region bit line LBL ("programmed") to, for example, 0 V.

[0272] 11. 11th Implementation Form Next, the 11th embodiment will be described. In the 11th embodiment, two examples of the planar layout of the read port RPB will be described. Hereinafter, the description will focus on the differences from the planar layout of the read port RPB described using Figures 5A and 5B of the first embodiment.

[0273] Referring to Figures 28A and 28B, the 11th embodiment will be described.

[0274] First, referring to FIG28A, the first example of the planar layout of the read port RPB will be described. FIG28A is a top view showing the first example of the planar layout of the read port RPB in the eleventh embodiment.

[0275] As shown in Figure 28A, in this embodiment, in the region between two adjacent SLTs in the Y direction, a plurality of pillars RP are arranged in a width of, for example, nine rows in the X direction. Furthermore, the nine rows of memory pillars MP are arranged in an alternating manner, with the positions of adjacent memory pillars MP in the Y direction being different in the X direction. Three SHE1s are provided between the two SLTs. That is, six SHE1s are provided in the read port RPB. Similar to Figure 5A of the first embodiment, the upper six-layer wiring layer 14, which functions as the region bit line LBL or read control signal line RBS of the read port RPB, is divided into eight sections in the Y direction by the SLTs and SHE1s. That is, the wiring layer 14, which functions as the region bit line LBL or read control signal line RBS, is divided into eight sections in the Y direction. In this embodiment, the eight read control signal lines RBS0 to RBS7 are arranged in the order of read control signal lines RBS0 to RBS7, starting from the left side of the paper.

[0276] In the example shown in Figure 28A, the 1st, 3rd, 4th, and 6th components SHE1 from the left side of the paper are positioned between two adjacent columns RP in the Y direction. More specifically, the 1st component SHE1 from the left side of the paper is positioned between the 2nd and 3rd column RP from the left side of the paper. The 3rd component SHE1 from the left side of the paper is positioned between the 7th and 8th column RP from the left side of the paper. The 4th component SHE1 from the left side of the paper is positioned between the 11th and 12th column RP from the left side of the paper. The 6th component SHE1 from the left side of the paper is positioned between the 16th and 17th column RP from the left side of the paper. Furthermore, the 2nd and 5th components SHE1 from the left side of the paper are positioned in a manner that breaks the upper portion of the 5th and 14th column RP from the left side of the paper, respectively.

[0277] Multiple wiring layers 17, which function as bit lines BL, are electrically connected to any one of the columns RP in rows 1, 3, 6, 8, 10, 12, 15 and 17 from the left side of the paper.

[0278] The other components are the same as in the first embodiment.

[0279] Next, referring to FIG28B, a second example of the planar layout of the read port RPB will be described. FIG28B is a top view showing a second example of the planar layout of the read port RPB in the 11th embodiment. Hereinafter, the description will focus on the differences from the first example described using FIG28A.

[0280] As shown in Figure 28B, in this example, similar to Figure 5B of the first embodiment, in order to more easily connect the contact plug CP2 to the wiring layer 14 which functions as the regional bit line LBL, the post RP located near the contact plug CP2 is deleted in Figure 28A.

[0281] This embodiment is similar to Figures 5A and 5B of the first embodiment, and the main effects are also the same. The difference is that in Figures 5A and 5B, the string selection signal layer (the wiring layer 14 that functions as the area bit line LBL or the read control signal line RBS) of the component SHE1 is separated at the center of the pillars RP arranged in the X direction. In contrast, in Figures 28A and 28B, some of the components SHE1 are arranged between adjacent pillars RP in the Y direction. This reduces the gate area of ​​the amplifying transistor APT and decreases the size of the read port RPB.

[0282] 12. Twelfth Implementation Form Next, the 12th embodiment will be described. In the 12th embodiment, the cross-sectional structure of the gain block gBK, which differs from that of the 1st to 11th embodiments, will be described. Hereinafter, the description will focus on the differences from the 1st to 11th embodiments.

[0283] Referring to FIG29, the 12th embodiment will be described. FIG29 shows an example of a cross-sectional view of the gain block gBK in the bit line direction (Y direction) of the 12th embodiment. FIG29 shows an example of a cross-sectional structure of a cell block CB including a portion of a plurality of memory cell strings MSRs connected to a region bit line LBL, a write port WPB that transmits the potential of the bit line BL to the region bit line LBL, and a read port RPB that amplifies the potential of the region bit line LBL and transmits it to the bit line BL.

[0284] As shown in Figure 29, in this example, three additional wiring layers 14 (dummy string select signal layers) are provided above the stacked layers (2009 layer wiring layer 14) of the cell block CB, read port RPB, and write port WPB as illustrated in Figure 19 using the fourth embodiment. More specifically, in the illustration using Figure 19, six wiring layers 14 are provided above wiring layer 40, but as shown in Figure 29, in this example, nine wiring layers 14 are provided above wiring layer 40. In other words, nine wiring layers 14 (string select signal layers) are provided above the wiring layers 14 (character line layers) that perform the function of character lines WL or dummy character lines dWL.

[0285] In cell block CB, the 9-layer wiring layer 14 located above wiring layer 40 (JCT) functions as a 6-layer serial select signal line SGDT and a 3-layer serial select signal line SGD, respectively, starting from the upper layer side. The upper 9-layer wiring layer 14, functioning as either the serial select signal line SGDT or SGD, is divided according to each serial unit SU by a component SHE1 extending in the X direction. An upper memory pillar UMP is provided, penetrating the upper 9-layer wiring layer 14 and having its lower surface connected to wiring layer 40. Below wiring layer 40, similar to Figure 19, a lower memory pillar LMP is provided. The lower memory pillar LMP penetrates the 2000-layer wiring layer 14, which functions as word lines WL0~WL1999, and the 3-layer wiring layer 14, which functions as the serial select signal line SGS. In this embodiment, an N+ diffusion layer 50 (diffusion layer region) is formed above the silicon channel layer 21 in the upper memory pillar UMP. For example, phosphorus (P) or arsenic (As) is injected into the silicon channel layer 21 as an impurity in the N+ diffusion layer 50. For example, the N+ diffusion layer 50 is formed upward from a position near the third wiring layer 14 (serial select signal line SGDT) from the top layer. That is, the N+ diffusion layer 50 is formed in the region on the same layer as the upper three wiring layers 14 (serial select signal line SGDT). Alternatively, the position below the N+ diffusion layer 50 may also be higher than the third wiring layer 14 (serial select signal line SGDT) from the top layer.

[0286] In the write port WPB, the 9-layer wiring layer 14 located above the wiring layer 40 (mBL) functions as 6 layers of write control signal lines WBS0 and 3 layers of write control signal lines WBS1, respectively, starting from the upper layer side. The upper 9-layer wiring layer 14, which functions as either write control signal line WBS0 or write control signal line WBS1, is divided by a component SHE1 extending in the X direction. Upper posts UWP1 and UWP2 are provided, which penetrate the upper 9-layer wiring layer 14 and whose lower surfaces are in contact with the wiring layer 40. Similar to the upper memory post UMP, an N+ diffusion layer 50 is formed above the silicon channel layer 21 in the upper posts UWP1 and UWP2.

[0287] In the read port RPB, the 9-layer wiring layer 14, located above the wiring layer 40 (RSL), functions as the 6-layer region bit line (LBL) and the 3-layer read control signal line (RBS) respectively, starting from the upper layer side. The upper 9-layer wiring layer 14, which functions as the region bit line (LBL) or the read control signal line (RBS), is interrupted by the X-direction extending member SHE1. Furthermore, the upper 6-layer wiring layer 14, which functions as the region bit line (LBL), is electrically connected to the wiring layer 16, which also functions as the region bit line (LBL), via the contact plug CP2. Similar to the upper memory cylinder UMP and the upper cylinder UWP, an N+ diffusion layer 50 is formed above the silicon channel layer 21 in the upper cylinder URP.

[0288] By adding three wiring layers 14 (virtual string select signal layers) on top, when an N+ diffusion layer 50 is formed at the contact portion of the region bit line LBL or bit line BL, there is no problem even if the diffusion layer length of the N+ diffusion layer 50 is uneven, or if there is a lower end of the N+ diffusion layer 50 at some point between the top layer and layers 1 to 3. The reason is that the memory pillars MP, WP, and RP with the N+ diffusion layer 50 are always in the ON state because the threshold voltage Vt of the string select transistor STT1, transistor WST0, and amplification transistor APT on the wiring layer 14 located on the same layer as the N+ diffusion layer 50 is lower. Furthermore, the threshold voltage Vt is actually determined by the string select transistor STT1, transistor WST0, and amplifying transistor APT, which are located on the same layer as the undoped silicon channel layer 21 without the N+ diffusion layer 50, in the wiring layer 14. This dummy additional string select signal layer (wiring layer 14) can be applied to all other embodiments. In this embodiment, the read control signal line RBS and the write control signal lines WBS0 and WBS1 are shown as being composed of all three layers of string select signal layers (wiring layer 14), but each signal line can be composed of one or two layers, or more than three layers.

[0289] 13. Thirteenth Implementation Form Next, the 13th embodiment will be described. In the 13th embodiment, the cross-sectional structure of the gain block gBK, which differs from that of the 1st to 12th embodiments, will be described. Hereinafter, the description will focus on the differences from the 1st to 12th embodiments.

[0290] Referring to FIG30, the 13th embodiment will be described. FIG30 shows an example of a cross-sectional view of the gain block gBK in the bit line direction (Y direction) of the 13th embodiment. FIG30 shows an example of a cross-sectional structure including a portion of a cell block CB containing a plurality of memory cell strings MSRs connected to a region bit line LBL, a write port WPB that transmits the potential of the bit line BL to the region bit line LBL, and a read port RPB that amplifies the potential of the region bit line LBL and transmits it to the bit line BL.

[0291] As shown in Figure 30, in this embodiment, above the wiring layer 14 that functions as the string select signal line SGDT or SGD in the cell block CB, a plurality of wiring layers 14 are additionally provided, which function as dummy string select signal lines dSGD or dSGDT. In the example shown in Figure 30, the additional 6 wiring layers 14 are used in the cell block CB for the dummy string select signal lines dSGDT or dSGD, but in the write port WPB, they are used for the write control signal lines WBS0 or WBS1, and in the read port RPB, they are used for the area bit line LBL or the read control signal line RBS.

[0292] More specifically, for example, in cell block CB, a wiring layer 40 is provided above the wiring layer 14 that functions as the dummy SGDT signal line, serving as a contact JCT. Above the wiring layer 40, six wiring layers 14 are provided separately in the Z direction. Of the six wiring layers 14, the upper three layers function as the dummy SGDT signal line, and the lower three layers function as the dummy SGD signal line. The memory cylinder MP includes the upper memory cylinder UMP and the lower memory cylinder LMP. The upper memory cylinder UMP passes through the six wiring layers 14 that function as either the dummy SGDT or dSGD signal line, and its lower surface is connected to the wiring layer 40. The lower memory module (LMP) is connected to a 6-layer wiring layer 14 that functions as a serial select signal line (SGDT) or SGD, a 2000-layer wiring layer 14 that functions as word lines WL0 to WL1999, and a 3-layer wiring layer 14 that functions as a serial select signal line (SGS). The lower surface of the lower memory module (LMP) is connected to the semiconductor layer 12, and the upper surface is connected to the wiring layer 40.

[0293] Component SHE1 will break the 6-layer wiring layer 14, which functions as a dummy string selection signal line dSGDT or dSGD, and the 6-layer wiring layer 14, which functions as a string selection signal line SGDT or SGD, in the Y direction.

[0294] In the write port WPB, above the wiring layer 40 which functions as the intermediate bit line mBL, six wiring layers 14 are separately arranged in the Z direction. Of the six wiring layers 14, the upper three layers function as write control signal lines WBS0, and the lower three layers function as write control signal lines WBS1. Posts WP1 and WP2 respectively contain upper posts UWP1 and UWP2. Upper posts UWP1 and UWP2 pass through the six wiring layers 14 that function as write control signal lines WBS0 or WBS1, and their lower surfaces are connected to wiring layer 40 (mBL). Lower posts LWP1 and LWP2 are not provided. The six wiring layers 14 in the cell block CB, which function as serial select signal lines dSGDT or dSGD, function as write control signal lines WBS0 or WBS1 in the write port WPB. That is, the 2009 layer wiring layer 14, which is located below the wiring layer 40 (mBL), is treated as a virtual layer.

[0295] In the read port RPB, above the wiring layer 40 which functions as the read source line RSL, six wiring layers 14 are separately arranged in the Z direction. Of the six wiring layers 14, the upper three layers function as the region bit line LBL, and the lower three layers function as the read control signal line RBS. The post RP includes the upper post URP. The upper post URP passes through the six wiring layers 14 that function as either the region bit line LBL or the read control signal line RBS, and its lower surface is connected to the wiring layer 40 (RSL). No lower post LRP is provided. Similar to the write port WPB, the six wiring layers 14 in the cell block CB that function as the serial select signal line dSGDT or dSGD function as either the region bit line LBL or the read control signal line RBS in the read port RPB. That is, the 2009 wiring layer 14 located below the wiring layer 40 (RSL) is treated as a dummy layer.

[0296] Furthermore, in the write port WPB, the wiring layer 14 used as the write control signal line WBS0 or WBS1 can be arbitrarily selected. Alternatively, one layer from the stacked layers of multiple wiring layers 14 can be used as the write control signal line WBS0 or WBS1. Similarly, in the read port RPB, the wiring layer 14 used as the area bit line LBL or the read control signal line RBS can be arbitrarily selected. Alternatively, one layer from the stacked layers of multiple wiring layers 14 can be used as the gate electrode of the amplifying transistor APT. Because the stacked layers are separated together by components such as SLT and SHE1, even if the number of stacked layers increases, the manufacturing cost does not increase significantly. By configuring the device in this way, even if the number of word line stacks is multiplied, the read speed and write speed will not decrease. Furthermore, there is no need for additional transistors dedicated to the read port RPB and write port WPB. Therefore, the more word line stacks are increased, the more the bit cost can be reduced, and higher speed 3D-NAND flash memory can be realized.

[0297] 14. Implementation Form 14 Next, the 14th embodiment will be described. In the 14th embodiment, the configuration of the non-volatile semiconductor memory device 1, which differs from that of the 1st to 13th embodiments, will be described. Hereinafter, the description will focus on the differences from the 1st to 13th embodiments.

[0298] Referring to FIG31, the 14th embodiment will be described. FIG31 shows an example of the cross-sectional structure of the gain block gBK in the bit line direction (Y direction) of the array chip, and an example of the circuit configuration of the CMOS chip connected to the region bit line LBL.

[0299] As shown in Figure 31, the array chip includes a memory cell array MA. The memory cell array MA includes a plurality of cell blocks CB. Each cell block CB includes a plurality of wiring layers 16 that function as region bit lines LBL, and a plurality of memory pillars MP connected to each wiring layer 16. In other words, the memory cell array MA includes a plurality of cell blocks CB containing a plurality of memory cell strings MSR connected to the region bit lines LBL. The configuration of each cell block CB is the same as that described in Figure 3 using the first embodiment. In the example shown in Figure 31, the memory cell array MA includes N (N is a natural number) cell blocks CB0 to CB(N-1). For example, cell block CB0 includes a plurality of wiring layers 16 that function as region bit lines LBL0. Similarly, cell block CB(N-1) includes a plurality of wiring layers 16 that function as region bit lines LBL(N-1).

[0300] A CMOS chip includes a write port WPB that transmits the potential of bit line BL to region bit line LBL, and a read port RPB that amplifies the potential of region bit line LBL and transmits it to bit line BL. In the example shown in Figure 31, the CMOS chip includes N write ports WPB0~WPB(N-1) corresponding to cell blocks CB0~CB(N-1), and N read ports RPB0~RPB(N-1).

[0301] The write port WPB0 includes transistor WST0. The drain of transistor WST0 is connected to bit line BL. The source of transistor WST0 is electrically connected to the gate of amplifier transistor APT0 and the region bit line LBL0 of cell block CB0. The write control signal line WBS0 is connected to the gate of transistor WST0. Similarly, the write port WPB(N-1) includes transistor WST(N-1). The drain of transistor WST(N-1) is connected to bit line BL. The source of transistor WST(N-1) is electrically connected to the gate of amplifier transistor APT(N-1) and the region bit line LBL(N-1) of cell block CB(N-1). The write control signal line WBS(N-1) is connected to the gate of transistor WST(N-1).

[0302] Read port RPB0 includes amplifying transistor APT0 and transistor RST0. APT0 and RST0 are connected in series. The drain of APT0 is connected to bit line BL. The source of RST0 is connected to a proprietary power supply, similar to the read source line RSL, or ground. Similarly, read port RPB(N-1) includes amplifying transistor APT(N-1) and transistor RST(N-1). APT(N-1) and RST(N-1) are connected in series. The drain of APT(N-1) is connected to bit line BL. The source of RST(N-1) is connected to a proprietary power supply, similar to the read source line RSL, or ground.

[0303] In the example shown in Figure 31, the non-volatile semiconductor memory device 1 has a bonding structure for bonding an array chip and a CMOS chip. More specifically, the array chip includes a plurality of electrode pads 60 disposed on the surface opposite to the CMOS chip. The CMOS chip includes a plurality of electrode pads 61 disposed on the surface opposite to the array chip. In the bonding structure, the electrode pads 60 and 61 are bonded together to form a bonding pad. In other words, the conductors contained in the electrode pads 60 and 61 are bonded together. The bonding pad functions as a current path between the array chip and the CMOS chip. The surface on which the array chip and the CMOS chip are bonded is also referred to as the "bonding surface". Alternatively, the non-volatile semiconductor memory device 1 may not have a bonding structure. The circuitry on the CMOS chip side (including the write port WPB and the read port RPB) may also be disposed on the FEOL side (transistor section) of the same silicon substrate as the array chip. In this case, the region bit line LBL can also be pulled down from the memory cell array MA to the FEOL side, and a bulk transistor formed on the silicon substrate can be used to form the read port RPB and the write port WPB.

[0304] If configured as in this embodiment, it is unnecessary to form the read port RPB and write port WPB within the memory cell array MA, thus suppressing the increase in the size of the memory cell array MA. In this case, on the CMOS chip (FEOL side), there is a bit line BL with the same fine wiring spacing as the memory cell array MA, a high-voltage transistor is required due to the amplification transistor APT, and a triple-well configuration is required because the transistors in the write port WPB and read port RPB boost voltage during the erase operation. To suppress the deviation of the threshold voltage Vt of the amplification transistor APT, a relatively large amplification transistor APT is required, or the threshold voltage Vt of the amplification transistor APT needs to be finely adjusted. Since there is no charge trapping layer 222 in the amplification transistor APT, adjusting the threshold voltage Vt takes time.

[0305] 15. Other It is not limited to the above-mentioned implementation form and various variations can be applied.

[0306] Furthermore, the "connection" in the above-described embodiments also includes a state in which there is an indirect connection through an intervening object such as a transistor or resistor.

[0307] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0308] 1: Non-volatile semiconductor memory devices 11, 13, 15, 35: Insulation layer 12: Semiconductor layer 14, 16, 17, 40: Wiring layers 20: Core membrane 21: Silicon Channel Layer 22: Stacked membrane 30, LI: Conductor 36: Shielding metal layer 50:N + diffusion layer 60, 61: Electrode pads 221: Tunnel insulation layer 222: Charge trapping layer 223: Barrier Insulation Layer APT, APT0, APT(N-1): Amplifying transistors bBL: Bottom Pixel Line BL, BLe, BLo: Bit lines CB, CB0~CB(N-1): Cell blocks CBL: Load Capacity CC, CP1~CP4: Contact plugs dSGD, dSGDT, dSGS: Dummy string select signal lines dWL: Dummy character line DC: Virtual Cell DRV: Drive DT: Virtual Transistor DV:WL_SG driver gBK, gBK0~gBK15: Gain Block JCT: Contact LBL, LBL0~LBL(N-1), LBLe, LBLo: Region bit lines LMP: Lower Memory Column LRP, LWP, LWP1, LWP2: lower column mBL: Intermediate Bit Line MA: Memory Cell Array MC, MC0~MC1999: Memory Cells MH: Memory Hole MP: Memory Column MSR: memory cell string PB: Page Buffer PC: Peripheral Circuits PD: Pad Area RBS, RBS0~RBS7, RBS(N-1): Read control signal lines RP, WP, WP1, WP2: Columns RPB, RPB0~RPB(N-1): Read port RSL: Read Source Line RSR, WSR1, WSR2: Strings RST, RST0, RST(N-1), WST, WST0, WST0e, WST0o, WST1, WST1e, WST1o, WST(N-1): Transistor SGD, SGD0~SGD3, SGDT, SGDT0~SGDT3, SGS: Serial select signal lines SHE1, SHE2, SLT: Components SL: Source Line SP: Spacer ST1, STT1, ST2: String select transistors SU, SU0~SU4: Serial units t0~t6: Time points TR:WL Surface UMP: Upper Memory Column URP, UWP, UWP1, UWP2: upper column VBL1, VBL2, VBL3a, VBL3b, VBL4, VBLh, VBLPG, VBLPG1, VBLPG2, VBLRD, VERASE, VH, VLBL1a, VLBL1b, VLBL1c, VLBL2a, VLBL2b, VLBL3a, VLBL3b, VLBL4, VREAD, VWBS, VWBS1, VWBS2a, VWBS2b, VWBS3a, VWBS3b, VWBS4, VWBSon, VWL1a, VWL1b: Voltage VSS: Grounding voltage Vt: Threshold voltage WBS0, WBS0e, WBS0o, WBS1, WBS1e, WBS1o, WBS(N-1): Write control signal lines WL, WL0~WL1999: Character Line WPB, WPB0~WPB(N-1): Write port

Claims

1. A non-volatile semiconductor memory device comprising: a plurality of first wiring layers extending in a first direction and stacked separately in a second direction intersecting the first direction; memory pillars extending in the second direction and passing through the plurality of first wiring layers; region bit lines disposed separately from the plurality of first wiring layers at one end of the plurality of first wiring layers in the second direction, extending in a third direction intersecting the first and second directions, and electrically connected to the end of the memory pillar in the second direction; bit lines disposed separately from the region bit lines at one end of the region bit lines in the second direction, extending in the third direction; and a plurality of second wiring layers extending in the first direction and stacked separately in the second direction, arranged with the plurality of first wiring layers in the third direction. A first post, extending in the second direction, is electrically connected to the region bit line at one end in the second direction via the plurality of second wiring layers; a second post, extending in the second direction, is electrically connected to the bit line at one end in the second direction via the plurality of second wiring layers and is electrically connected to the first post; a plurality of third wiring layers, extending in the first direction, are stacked separately in the second direction and arranged with the plurality of first wiring layers in the third direction; and a third post, extending in the second direction, is electrically connected to the bit line at one end in the second direction via the plurality of third wiring layers; and at least one of the plurality of third wiring layers is electrically connected to the region bit line.

2. The non-volatile semiconductor memory device of claim 1, wherein each of the memory pillars and the first to third pillars comprises: an insulator extending in the second direction; a silicon channel layer extending in the second direction and disposed to surround the insulator; a tunnel insulating layer extending in the second direction and surrounding the side surface of the silicon channel layer; a charge trapping layer extending in the second direction and surrounding the side surface of the tunnel insulating layer; and a barrier insulating layer extending in the second direction and surrounding the side surface of the charge trapping layer.

3. The non-volatile semiconductor memory device of claim 1, wherein the memory pillar comprises: an insulator extending in the second direction; and a silicon channel layer extending in the second direction and disposed such that it surrounds the insulator. A tunnel insulating layer extending in the second direction and surrounding the side of the silicon channel layer; a charge trapping layer extending in the second direction and surrounding the side of the tunnel insulating layer; and a barrier insulating layer extending in the second direction and surrounding the side of the charge trapping layer; and each of the first to third pillars includes: a conductor extending in the second direction; and an insulator extending in the second direction, disposed in a manner that connects to one end of the conductor in the second direction. The aforementioned silicon channel layer extends in the aforementioned second direction and is disposed in such a way as to surround the aforementioned conductor and the aforementioned insulator; the aforementioned tunnel insulating layer extends in the aforementioned second direction and surrounds the side surface of the aforementioned silicon channel layer; the aforementioned charge trapping layer extends in the aforementioned second direction and surrounds the side surface of the aforementioned tunnel insulating layer; and the aforementioned barrier insulating layer extends in the aforementioned second direction and surrounds the side surface of the aforementioned charge trapping layer.

4. The non-volatile semiconductor memory device of claim 1 further comprises: a first semiconductor layer, which is disposed separately from the plurality of first wiring layers at the other end of the plurality of first wiring layers in the second direction and is connected to the other end of the memory pillar in the second direction; a second semiconductor layer, which is disposed separately from the plurality of second wiring layers at the other end of the plurality of second wiring layers in the second direction and is connected to the other end of the first pillar in the second direction and the other end of the second pillar in the second direction; and a third semiconductor layer, which is disposed separately from the plurality of third wiring layers at the other end of the plurality of third wiring layers in the second direction, is located on the same layer as the second semiconductor layer, and is connected to the other end of the third pillar in the second direction.

5. The non-volatile semiconductor memory device of claim 1, further comprising: a fourth wiring layer disposed between any of the plurality of second wiring layers in the second direction; and a fifth wiring layer disposed between any of the plurality of third wiring layers in the second direction, located on the same layer as the fourth wiring layer; and the memory pillar comprising: a lower memory pillar extending in the second direction; and a higher memory pillar extending in the second direction, disposed at one end of the lower memory pillar in the second direction, and electrically connected to the lower memory pillar; the first pillar comprising: a fourth pillar extending in the second direction, the other end of the second direction being connected to the fourth wiring layer; the second pillar comprising: a fifth pillar extending in the second direction, the other end of the second direction being connected to the fourth wiring layer; The aforementioned third post includes a sixth post that extends in the aforementioned second direction, and the other end of the aforementioned second direction is connected to the aforementioned fifth wiring layer.

6. The non-volatile semiconductor memory device of claim 2, wherein the silicon channel layer includes a diffusion layer region disposed on one end side in the second direction.

7. The non-volatile semiconductor memory device of claim 2, wherein the aforementioned barrier insulating layer comprises a strong dielectric material and performs polarization operation.

8. The non-volatile semiconductor memory device of claim 2, wherein the barrier insulating layer and the charge trapping layer are strong dielectric layers.

9. A non-volatile semiconductor memory device comprising: a page buffer; bit lines connected to the page buffer; and a plurality of gain blocks connected to the bit lines; wherein each gain block includes: a region bit line; a cell block including a first string of select transistors, a plurality of memory cells, and a second string of select transistors connected in series, and including a string of memory cells with one end connected to the region bit line and the other end connected to a source line; a write port configured to transfer the potential of the bit lines to the region bit lines; and a read port configured to amplify the potential of the region bit lines and transfer it to the bit lines; wherein the read port and the write port are respectively disposed at both ends of the extension direction of the region bit lines of the cell block.

10. The non-volatile semiconductor memory device of claim 9, wherein the write port comprises: a first transistor connected to the bit line; a second transistor connected to the region bit line; and a first control signal line connected to the gates of the first transistor and the second transistor.

11. The non-volatile semiconductor memory device of claim 9, wherein the read port comprises: a fourth transistor, one end of which is connected to the bit line and the gate is connected to the region bit line; and a fifth transistor, one end of which is connected to the other end of the fourth transistor and the other end of which is connected to the read source line and the gate is connected to the second control signal line.

12. The non-volatile semiconductor memory device of claim 11, wherein the threshold voltage of the fourth transistor is higher than 0 V and less than 0.7 V.

13. The non-volatile semiconductor memory device of claim 11, wherein the fourth transistor includes a charge trapping layer; and when the threshold voltage of the fourth transistor is reduced, a first voltage is applied to the gate, and a second voltage higher than the first voltage is applied to the source and drain, thereby releasing electrons from the charge trapping layer.

14. The non-volatile semiconductor memory device of claim 11, wherein the fourth transistor includes a charge trapping layer; and when the threshold voltage of the fourth transistor is increased, a third voltage is applied to the source and drain, a fourth voltage higher than the third voltage is applied to the gate, and electrons are injected into the charge trapping layer.

15. The non-volatile semiconductor memory device of claim 11, wherein the fourth transistor includes a charge trapping layer; and when the threshold voltage of the fourth transistor is increased, a fifth voltage is applied to the source, a sixth voltage higher than the fifth voltage is applied to the gate, and a seventh voltage higher than the sixth voltage is applied to the drain, thereby injecting electrons into the charge trapping layer by means of the hot carrier effect.

16. The non-volatile semiconductor memory device of claim 11, wherein during the readout operation of a selected memory cell among the plurality of memory cells, when the threshold voltage of the selected memory cell is higher than the determination potential, the selected memory cell becomes off, the voltage of the region bit line is higher than the threshold voltage of the fourth transistor, and the fourth transistor becomes on; when the pre-charge of the bit line is released, the voltage of the bit line decreases; when the threshold voltage of the selected memory cell is lower than the determination potential, the selected memory cell becomes on, the voltage of the region bit line is lower than the threshold voltage of the fourth transistor, and the fourth transistor becomes off; even if the pre-charge of the bit line is released, the voltage of the bit line does not decrease.

17. A non-volatile semiconductor memory device comprising: a cell block including: a plurality of first wiring layers extending in a first direction and stacked separately in a second direction intersecting the first direction; a memory pillar extending in the second direction through the plurality of first wiring layers; and a region bit line disposed separately from the plurality of first wiring layers at one end of the plurality of first wiring layers in the second direction, extending in a third direction intersecting the first and second directions, and electrically connected to the end of the memory pillar in the second direction; a page buffer; a bit line connected to the page buffer; a write port configured to transfer the potential of the bit line to the region bit line; and a read port configured to amplify the potential of the region bit line and transfer it to the bit line; and the memory pillar comprising: an insulator extending in the second direction. A silicon channel layer extending in the second direction and disposed to surround the insulator; a tunnel insulation layer extending in the second direction and surrounding the side of the silicon channel layer; a charge trapping layer extending in the second direction and surrounding the side of the tunnel insulation layer; and a barrier insulation layer extending in the second direction and surrounding the side of the charge trapping layer.

18. The non-volatile semiconductor memory device of claim 17, wherein the write port comprises: a first transistor, one end of which is connected to the bit line and the other end of which is connected to the region bit line, and the gate is connected to a first control signal line.

19. The non-volatile semiconductor memory device of claim 18, wherein the read port comprises: a second transistor, one end of which is connected to the bit line and the gate of which is connected to the other end of the first transistor and the region bit line; and a third transistor, one end of which is connected to the other end of the second transistor and the other end of which is connected to an inherent power supply and the gate of which is connected to a second control signal line.

20. The non-volatile semiconductor memory device of claim 17, further comprising: a first chip including the page buffer, the bit lines, the write port and the read port; and a second chip including the cell blocks; and the first chip and the second chip being bonded together.

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