Lower electrode system, semiconductor process equipment, and control methods

Abstract

A lower electrode system, semiconductor process equipment, and control method are disclosed. The system includes a carrier device and a ejector device. The ejector device is used to lift or place a wafer on the carrier device. The system also includes a grounding device, which comprises a grounding circuit, a grounding switch, and a control unit. The grounding circuit is electrically connected to the lower electrode in the carrier device via the grounding switch, and is used to ground the lower electrode when the grounding switch is closed. The control unit is used to control the grounding switch to open in response to the start of the semiconductor process and to control the grounding switch to close in response to the end of the semiconductor process. The end of the semiconductor process includes the end of the plasma generation stage and the ejector device lifting the wafer on the carrier device.

Description

[Technical Field]

[0001] This application relates to the field of semiconductor manufacturing, and more specifically, to a lower electrode system, semiconductor process equipment and control method. [Previous Technology]

[0002] In advanced semiconductor edge etching equipment, the etching machine etches the edges of wafers after photolithography, resist removal, deposition, or etching processes to remove edge polymers, thereby reducing defects in subsequent processes and improving product yield. For edge etching equipment, the wafer is typically placed on a carrier within the process chamber. During the edge etching process, due to DC bias, both the wafer and the lower electrode in the carrier are negatively charged. If the accumulated charge cannot be effectively discharged in time, it will accumulate on the wafer surface, causing particle problems. The charge will also accumulate inside the lower electrode. Since the lower electrode usually has gaps and channels, for example, if a gas delivery channel is provided in the lower electrode, the accumulated charge on the lower electrode will create a potential difference with the cooling gas flowing into the channel. If the channel space is large, there is a risk of arcing. Once arcing occurs, it often causes electrical damage or even severe damage to the lower electrode. Therefore, the lower electrode needs to be grounded to conduct away the negative charge of the lower electrode. At the same time, the wafer also needs to be grounded to conduct away the negative charge of the wafer, so as to avoid particle and arcing problems.

[0003] However, at the end of the process, the lower electrode, which has been in a grounded state, will conduct the negative charge accumulated inside the lower electrode to the ground when the RF power is turned off. At this time, the wafer on the carrier device is still negatively charged, and there is a potential difference between the wafer and the lower electrode, which in turn causes electrostatic attraction between the wafer and the lower electrode, resulting in the wafer shifting during the needle lifting process, thus causing the AWC (Active Wafer Centering) result to fail to meet the requirements. [Summary of the Invention]

[0004] This application aims to solve at least one of the technical problems existing in the prior art, and proposes a lower electrode system, semiconductor process equipment and control method, which can solve the problem of wafer displacement during the needle lifting process caused by electrostatic adsorption between the wafer and the lower electrode.

[0005] To achieve the purpose of this application, a lower electrode system is provided, which is applied to a semiconductor process equipment, including a carrier device and a ejector device. The ejector device is used to lift or place a wafer on the carrier device. It also includes a grounding device, which includes a grounding circuit, a grounding switch and a control unit. The grounding circuit is electrically connected to the lower electrode in the carrier device through the grounding switch, and is used to ground the lower electrode when the grounding switch is turned on.

[0006] The control unit is used to control the grounding switch to open in response to the start of the semiconductor process and to control the grounding switch to close in response to the end of the semiconductor process; wherein the end of the semiconductor process includes: the end of the plasma generation stage and the ejector device lifting the wafer on the carrier device.

[0007] In some embodiments, the ejector pin device is configured to ground the wafer after lifting it from the carrier device.

[0008] In some embodiments, the ejector pin device is configured to be electrically connected to the grounding switch via the lower electrode, so as to ground the wafer on the ejector pin device while the control unit controls the grounding switch to be turned on.

[0009] In some embodiments, the ejector pin device includes a plurality of conductive ejector pins and a plurality of conductive ejector pin bellows. A plurality of through holes are provided in the support device at intervals along the circumference of the support device. The plurality of ejector pins are corresponding to each other and are vertically and vertically inserted through the plurality of through holes. The plurality of ejector pin bellows are corresponding to each other and are sleeved on the plurality of ejector pins. The upper end of each ejector pin bellows is sealed to the support device and is electrically conductive. The lower end of each ejector pin bellows is sealed to the corresponding ejector pin and is electrically conductive.

[0010] In some embodiments, an RF feed-in device is also included, which is electrically connected to the lower electrode and is used to be electrically connected to an RF power supply via a matching unit to load RF power onto the lower electrode.

[0011] In some embodiments, the grounding circuit includes a circuit for connecting the lower electrode to ground, and a grounding resistor connected in series in the grounding circuit; the grounding switch is connected in series in the grounding circuit and is located on the side of the grounding resistor closer to the lower electrode.

[0012] In some embodiments, the resistance of the grounding resistor is greater than or equal to 5MΩ and less than or equal to 20MΩ.

[0013] As another technical solution, this application also provides a semiconductor process apparatus, including a process chamber, and also includes the lower electrode system provided in this application, wherein at least some components of the lower electrode system are located in the process chamber.

[0014] In some embodiments, the semiconductor process equipment includes a crystal edge etching device.

[0015] As another technical solution, this application also provides a semiconductor process equipment control method, applied to the lower electrode system provided in this application, comprising:

[0016] In response to the start of a semiconductor manufacturing process, the grounding switch is controlled to open;

[0017] In response to the completion of the semiconductor process, the grounding switch is controlled to be turned on;

[0018] The semiconductor process includes: the plasma generation stage ends, and the ejector device lifts the wafer on the carrier device.

[0019] In some embodiments, before the semiconductor process begins, the process further includes:

[0020] Control the chamber pressure to reach the first pressure value;

[0021] In response to placing the wafer in the carrier device, process gas is introduced into the process chamber and the pressure in the chamber is controlled to reach a second pressure value; the second pressure value is greater than the first pressure value, so as to form a pressure difference between the upper surface and the lower surface of the wafer, and fix the wafer to the carrier device.

[0022] This application has the following beneficial effects:

[0023] In the technical solution of the lower electrode system, semiconductor process equipment, and control method provided in this application, by controlling the grounding switch to be disconnected before the plasma generation stage of the semiconductor process begins, the lower electrode in the carrier device can be disconnected from the ground. Therefore, during the plasma generation stage, the negative charge accumulated on the lower electrode will not be released. The lower electrode and the wafer accumulate negative charges synchronously, resulting in both the lower electrode and the wafer being negatively charged and having essentially the same potential. This avoids a potential difference between the wafer and the lower electrode, preventing electrostatic adsorption between them. Consequently, when the ejector device lifts the wafer from the carrier device, the wafer will not shift due to electrostatic adsorption, effectively improving the wafer's repeatability and ensuring that the AWC (Automatic Wafer Correction) results meet the requirements. Furthermore, after the plasma generation stage ends and the ejector device lifts the wafer from the carrier device, the grounding switch is turned on, grounding the lower electrode. This allows the accumulated charge in the lower electrode to be released, preventing arcing problems inside the lower electrode.

Implementation Method

[0025] To enable those skilled in the art to better understand the technical solutions of this application, the lower electrode system, semiconductor process equipment and control method provided in this application will be described in detail below with reference to the accompanying drawings.

[0026] Please refer to Figure 1. The lower electrode system 100 provided in this embodiment is applied to a semiconductor manufacturing process apparatus. This semiconductor manufacturing process apparatus includes, for example, the edge etching apparatus shown in Figure 1, for etching the edge region of the wafer 3 to remove the edge polymer. Of course, in practical applications, the semiconductor manufacturing process apparatus may also include other types of manufacturing process apparatus, and this embodiment does not have any particular limitations in this regard.

[0027] Specifically, the lower electrode system 100 includes a support device 1 and a push pin device 2. The push pin device 2 is used to lift the wafer 3 on the support device 1 or place the wafer 3 on the support device 1 so as to cooperate with the robot to realize the wafer 3 picking or placing operation.

[0028] In some embodiments, the ejector device 2 includes a plurality of ejector pins 21 and a plurality of ejector pin bellows 22. A plurality of through holes 23 are provided in the support device 1 at intervals along the circumference of the support device 1. The plurality of ejector pins 21 are arranged one-to-one with the plurality of through holes 23 and can be raised and lowered through the plurality of through holes 23. The lower end of each ejector pin 21 can penetrate the bottom of the process chamber 200 of the semiconductor process equipment and extend outside the process chamber 200 so as to be connected to an external lifting drive source (not shown in the figure). Under the drive of the lifting drive source, the plurality of ejector pins 21 can be raised and lowered synchronously so that their top ends can rise to a position higher than the support surface of the support device 1, thereby lifting the wafer 3 on the support device 1; or the top ends of the ejector pins 21 can be lowered to a position lower than the support surface of the support device 1, thereby placing the wafer 3 placed on the top ends of the plurality of ejector pins 21 on the support surface of the support device 1. Of course, in practical applications, the aforementioned lifting drive source can also be located inside the process chamber 200. In this case, the lower ends of the plurality of ejector pins 21 do not need to extend outside the process chamber 200 and can be connected to the lifting drive source inside the process chamber 200. For example, the aforementioned lifting drive source consists of a plurality of drive components mounted on the support device 1 and connected one-to-one with the plurality of ejector pins 21. Each of the plurality of drive components is used to drive one of the ejector pins 21 connected to it to move up and down synchronously. The drive components are, for example, lifting cylinders, lifting electric cylinders, etc.

[0029] With the lower ends of multiple ejector pins 21 extending outside the process chamber 200, multiple ejector pin bellows 22 are correspondingly fitted onto the multiple ejector pins 21, and the upper end of each ejector pin bellows 22 is sealed to the support device 1, for example, by welding; the lower end of each ejector pin bellows 22 extends outside the process chamber 200 through a through hole 201 penetrating the bottom of the chamber by the ejector pin 21, and is sealed to the corresponding ejector pin 21, for example, by welding. In this way, each ejector pin bellows 22 can seal one of the aforementioned through holes 23 in the support device 1. Since the upper end of the through hole 23 is located on the support surface of the support device 1, sealing the through hole 23 can ensure the airtightness of the process chamber 200 of the semiconductor process equipment. At the same time, the ejector pin bellows 22 can also allow the ejector pins 21 to rise and fall. In addition, the through hole 201 at the bottom of the chamber through which the ejector pin 21 penetrates needs to be sealed by an additional sealing structure to ensure the airtightness of the process chamber 200.

[0030] The aforementioned support device 1 can have various structures, such as including a base disk 11, a chuck 12, and an interface disk 13 arranged sequentially from top to bottom. The base disk 11, chuck 12, and interface disk 13 are integrated together and electrically conductive, forming the lower electrode. The base disk 11 is made of a conductive material, such as Al, and its upper surface is provided with a hard anodized coating 11a for supporting the wafer 3 and electrically insulating the base disk 11 from the wafer 3. The hard anodized coating 11a is, for example, Al2O3. The main body of the chuck 12 is made of a conductive material, such as Al. A temperature control channel can also be provided in the main body of the chuck 12 for conveying a temperature control medium (heating medium or cooling medium) to achieve temperature control of the lower electrode. In some embodiments, the outer peripheral surfaces of the chuck 12 and the interface disk 13 are provided with a hard anodized coating or other insulating layer to prevent the chuck 12 and the interface disk 13 from contacting the plasma. The body of the chuck 12 can be electrically connected to the lower electrode RF device 400 (including a matching unit 401 and an RF power supply 402). In some embodiments, the lower electrode system 100 further includes an RF feed device 14, which is mounted, for example, on the interface disk 13 and electrically connected to the body of the chuck 12. The RF feed device 14 is used to electrically connect to the RF power supply 402 through the matching unit 401. The RF power supply 402 applies RF power to the body of the chuck 12 to excite the process gas in the process chamber 200 to form plasma for etching the wafer 3.

[0031] In addition, taking a wafer edge etching apparatus as an example, the wafer edge etching apparatus includes a cavity 202 and an upper electrode cover plate 203 disposed on the top of the cavity 202. The cavity 202 and the upper electrode cover plate 203 together constitute a process chamber 200. Furthermore, a central hole 301a is provided in the upper electrode cover plate 203. The wafer edge etching apparatus also includes an upper electrode 300, a lifting drive device 302, and a top bellows 301. The lifting drive device 302 is installed on the upper electrode cover plate 203, and its drive shaft extends into the process chamber 200 through the central hole 301a and is fixedly connected to the upper electrode 300. It is used to drive the upper electrode 300 to rise and fall, so as to adjust the vertical distance between the upper electrode 300 and the support device 1. For example, during operations such as wafer pick-up and wafer placement, the lifting drive device 302 can be controlled to drive the upper electrode 300 to rise, thereby increasing the aforementioned vertical distance. Alternatively, during the manufacturing process, the lifting drive device 302 can be controlled to drive the upper electrode 300 downwards, thereby reducing the aforementioned vertical distance to meet the requirements of the crystal edge etching process. The top bellows 301 is arranged around the drive shaft of the lifting drive device 302 and is sealed to the upper electrode cover plate 203, sealing the central hole 301a and ensuring smooth lifting and lowering of the drive shaft of the lifting drive device 302. Of course, in practical applications, the top bellows 301 can also be replaced by other dynamic sealing components such as magnetohydrodynamic seals.

[0032] The upper electrode 300, together with the lower electrode, forms an electric field to excite the process gas within the process chamber 200 to form plasma. The upper electrode 300 is, for example, an upper electrode plate. An edge inlet channel is also provided in the edge region of the upper electrode plate for introducing the process gas (for etching) into the edge portion of the wafer 3. Additionally, in some embodiments, a central inlet channel may be provided in the central region of the upper electrode plate for introducing an inert gas (e.g., nitrogen) into the central region of the process chamber 200 to prevent plasma from entering the central region of the process chamber 200. Furthermore, to prevent plasma from etching the central region of the wafer 3, a shielding component, such as a glass plate, may be covered in the central region of the upper surface of the wafer 3.

[0033] When etching the edge portion of wafer 3 to remove the edge polymer, before turning on the RF power supply 402, the chamber pressure of the process chamber 200 is first controlled to a relatively low pressure range (e.g., 70 mTorr ~ 100 mTorr) by evacuation. Then, wafer 3 is placed on the hard anodized coating 11a, and process gas is introduced into the process chamber 200 to raise the chamber pressure of the process chamber 200 to a relatively high pressure range (e.g., 1 Torr ~ 3 Torr). At this time, there is a pressure difference between the upper surface and the lower surface of wafer 3, that is, the pressure on the upper surface of wafer 3 is greater than the pressure on the lower surface, so that wafer 3 can be fixed on the hard anodized coating 11a. It is easy to understand that the gas in the process chamber 200 also slowly flows into the gap between the lower surface of the wafer 3 and the hard anodized coating 11a, causing the pressure on the lower surface of the wafer 3 to slowly increase. The pressure difference between the upper and lower surfaces of the wafer 3 gradually decreases. However, since this is a slow process, there is enough time to fix the wafer 3 onto the hard anodized coating 11a during the RF power supply 402 turn-on. By adjusting the pressure range, it can be ensured that the pressure difference decreases to zero or near zero before the ejector device 2 lifts the wafer 3 from the hard anodized coating 11a, thus ensuring that the ejector device 2 can properly lift the wafer 3. As can be seen from the above, the carrier device 1 does not need to set up an additional structure to fix the wafer 3, such as an electrostatic adsorption electrode like in an electrostatic chuck; the wafer 3 can be fixed using only the pressure difference.

[0034] The interface plate 13 is fixed to the bottom of the cavity 202 and is electrically insulated from the cavity 202. For example, the interface plate 13 can be electrically insulated from the cavity 202 by an insulating ring 15. The interface plate 13 is provided with a variety of interfaces with different functions, such as an RF interface for installing the RF feed device 14. It also includes an interface for installing the aforementioned ejector pin bellows 22, which passes through the ejector pin bellows 22 and is sealed to the body of the chuck 12 at its upper end. Furthermore, through holes for the ejector pin 21 to pass through are correspondingly provided in the hard anodized coating 11a, the base plate 11, and the chuck 12, thus forming the aforementioned through holes 23.

[0035] The lower electrode system 100 also includes a grounding device, which includes a grounding circuit, a grounding switch 102, and a control unit. The grounding circuit is electrically connected to the lower electrode in the carrier device 1 (e.g., integrally formed by the base plate 11, chuck 12, and interface plate 13) via the grounding switch 102, and is used to ground the lower electrode when the grounding switch 102 is turned on. The grounding circuit that performs this function includes, for example, a circuit 101 connected between the lower electrode and ground, and a grounding resistor 103 connected in series with the circuit 101; the grounding switch 102 is connected in series with the circuit 101 and is located on the side of the grounding resistor 103 closer to the lower electrode. The grounding resistor 103 can slowly discharge the charge of the lower electrode when the grounding switch 102 is turned on. Furthermore, when the lower electrode radio frequency device 400 is connected in parallel with the circuit 101, the grounding resistor 103 can also prevent radio frequency leakage when the grounding switch 102 is turned on, that is, prevent radio frequency current from flowing into the ground through the circuit 101. In some embodiments, the resistance value of the grounding resistor 103 is in the range of 5MΩ to 20MΩ (inclusive of the endpoint value), and the specific resistance value of the grounding resistor 103 is, for example, 5MΩ, 10MΩ, 20MΩ, etc. The resistance value of the grounding resistor 103 should not be too large, otherwise it will lead to slow charge discharge and easy accumulation of static electricity on the lower electrode (accumulation of static charge without discharge); the resistance value of the grounding resistor 103 should also not be too small, otherwise it cannot effectively prevent radio frequency leakage.

[0036] In some embodiments, the grounding switch 102 is, for example, a relay, so as to automatically disconnect or connect when an input signal (e.g., 0V or 24V in FIG2) is received from the control unit.

[0037] Referring to Figure 2, the control unit controls the grounding switch 102 to be disconnected before the plasma generation stage of the semiconductor process (i.e., the RF turn-on stage T2~T3 in Figure 2) begins, for example, disconnected at the process start time T1 in Figure 2, and connected after the plasma generation stage ends (i.e., at time T3 in Figure 2) and the ejector device 2 lifts the wafer 3 on the carrier device 1 (i.e., the ejector lifting stage T3~T4 in Figure 2), for example, connected at the process end time T4 in Figure 2. This means that the grounding switch 102 is always in the disconnected state during the RF turn-on stage. When the lower electrode RF device 400 is turned on (i.e., time T2 in Figure 2), RF power is applied to the lower electrode. At this time, the electric field formed between the lower electrode and the upper electrode 300 can ionize the process gas in the process chamber 200 to form plasma, realizing plasma ignition. Time T2 is the start time of the plasma generation stage. When the lower electrode RF device 400 is turned off (i.e., time T3 in Figure 2), the application of RF power to the lower electrode stops. Time T3 is the end time of the plasma generation stage. Of course, the embodiments of this application are not limited to this. In practical applications, plasma can be generated in the process chamber 200 in any other way. For example, RF power can be applied to the upper electrode (e.g., a coil or electrode plate) by the upper electrode RF device to ionize the process gas in the process chamber 200 to form plasma. The control unit can be a host computer or a slave computer.

[0038] By controlling the grounding switch 102 to be disconnected before the plasma generation stage of the semiconductor process begins, the lower electrode in the carrier device 1 can be disconnected from the ground. Therefore, during the plasma generation stage, the negative charge accumulated on the lower electrode will not be released. The lower electrode and wafer 3 accumulate negative charges synchronously, and both are negatively charged overall, with essentially the same potential, as shown in Figure 3. Specifically, during the plasma generation stage, the gas in the process chamber 200 is ionized under the action of radio frequency energy to form a plasma containing ions and electrons. Ions and electrons repeatedly accelerate and then decelerate under the action of radio frequency energy. Since the mass of electrons is much smaller than that of ions, the speed of electron movement is much greater than that of ions, thus accumulating electrons on wafer 3 and exhibiting a negative polarity to ground. This is the DC bias phenomenon. At the same time, the plasma inevitably comes into contact with the lower electrode through the gap (the outer peripheral surface of the base disk 11 will come into contact with the plasma), meaning that the lower electrode will also accumulate negative charges. Based on this, since the lower electrode in the carrier device 1 is disconnected from ground before the plasma generation stage begins, the process of accumulating charge on the lower electrode is the same as the process of accumulating charge on wafer 3. Because they accumulate charge synchronously, they achieve the same potential, thus avoiding a potential difference between wafer 3 and the lower electrode. No electrostatic adsorption occurs between them, and therefore, when the ejector device 2 lifts wafer 3 from the carrier device 1, as shown in Figure 4, wafer 3 will not shift due to electrostatic adsorption. This effectively improves the repeatability of wafer transfer and ensures that the AWC (Automatic Wafer Correction) results meet the requirements. It is easy to understand that the lower electrode in the carrier device 1 must be disconnected from ground before the plasma generation stage begins. Disconnecting the lower electrode in the carrier device 1 from ground during the plasma generation stage, or after the plasma generation stage ends, will prevent the lower electrode and wafer 3 from accumulating charge synchronously, thus failing to achieve the same potential.

[0039] Based on this, after the plasma generation stage ends and the ejector device 2 lifts the wafer 3 on the carrier device 1, as shown in Figure 5, the grounding switch 102 is turned on so that the lower electrode can be grounded, thereby allowing the charge accumulated in the lower electrode to be discharged and avoiding arcing problems inside the lower electrode.

[0040] In related technologies, the lower electrode is kept grounded during the plasma generation stage. In this case, the black box in Figure 6 represents the distribution range of the center position points (black dots) of multiple wafers in the related technologies (i.e., the AWC range, representing the wafer repeatability accuracy). In the embodiment of this application, the grounding switch 102 is opened before the plasma generation stage begins. During the plasma generation stage, the negative charge accumulated on the lower electrode will not be discharged. In this case, the black box in Figure 7 represents the distribution range of the center position points (black dots) of multiple wafers in the embodiment of this application. Comparing the sizes of the black boxes in Figures 6 and 7, it can be seen that the AWC range of the related technologies is relatively large, while the embodiment of this application can control the AWC range within a smaller range, thereby effectively improving the wafer repeatability accuracy.

[0041] In some embodiments, the ejector pin device 2 is configured to ground the wafer 3 after lifting it from the carrier device 1, thereby solving the particle problem caused by accumulated charge on the wafer 3. Further, in some embodiments, the ejector pin device 2 is configured to be electrically connected to the grounding switch 102 via its lower electrode, so that the wafer 3 on the ejector pin device 2 is grounded simultaneously when the control unit controls the grounding switch 102 to be turned on. This allows the negative charge in the wafer 3 and the lower electrode to be discharged synchronously, thereby avoiding a potential difference between the wafer 3 and the lower electrode, and solving the particle problem caused by accumulated charge on the wafer 3 and the arcing problem caused by accumulated charge on the lower electrode.

[0042] Further, in some embodiments, the specific way in which the above-mentioned ejector pin device 2 is electrically connected to the grounding switch 102 via the lower electrode is as follows: both the ejector pin 21 and the ejector pin bellows 22 are made of conductive material, such as stainless steel. Since the ejector pin 21 and the ejector pin bellows 22 are interconnected to ensure electrical conduction, and the ejector pin bellows 22 is interconnected with the bottom of the support device 1 (i.e., the lower electrode) to ensure electrical conduction, when multiple ejector pins 21 lift the wafer 3 on the support device 1, when the grounding switch 102 is turned on, the negative charge in the wafer 3 is sequentially conducted to the ground via the ejector pin 21, the ejector pin bellows 22, the lower electrode, and the grounding circuit. Of course, in practical applications, the above-mentioned ejector pin device 2 can also be grounded in any other way, or the wafer 3 can also be grounded in any other way; this application embodiment does not have any particular limitations on this.

[0043] In addition, in some embodiments, the control unit is also used to control the grounding switch 102 to be in the ON state during non-processing stages (e.g., stages T0~T2, and stages after time T4) before the start of the process and after the end of the process. That is, during non-processing stages, the grounding switch 102 is always in the normally closed state to conduct the negative charge in the lower electrode to the ground.

[0044] As another technical solution, this application embodiment also provides a semiconductor process apparatus, including a process chamber 200 and a lower electrode system 100, wherein at least some components of the lower electrode system 100 are located in the process chamber 200. The lower electrode system 100 includes, for example, a support device 1, a ejector pin device 2, and a grounding device. Since the structure and function of these devices have been described in detail in the above embodiments, they will not be repeated here.

[0045] The semiconductor process equipment includes, for example, the edge etching equipment shown in FIG1, for etching the edge region of the wafer 3 to remove the edge polymer.

[0046] As another technical solution, this application embodiment also provides a semiconductor process equipment control method, applied to the lower electrode system provided in the above-mentioned embodiment of this application, as shown in FIG8, the control method includes:

[0047] S1. In response to the start of the semiconductor process, the control grounding switch is opened;

[0048] S2. In response to the end of the semiconductor manufacturing process, the grounding switch is turned on;

[0049] The semiconductor process includes: the plasma generation stage ends, and the ejector device 2 lifts the wafer on the carrier device 1.

[0050] By disconnecting the grounding switch 102 before the plasma generation stage of the semiconductor process begins, the lower electrode in the carrier device 1 can be disconnected from the ground. Therefore, during the plasma generation stage, the negative charge accumulated on the lower electrode will not be released. The lower electrode and wafer 3 accumulate negative charges synchronously, resulting in the lower electrode and wafer 3 being negatively charged as a whole, with essentially the same potential. This avoids a potential difference between wafer 3 and the lower electrode, preventing electrostatic adsorption between them. Consequently, when the ejector device 2 lifts the wafer on the carrier device 1, the wafer 3 will not shift due to electrostatic adsorption, effectively improving the repeatability accuracy of wafer 3 and ensuring that the AWC (Automatic Wafer Correction) results meet the requirements. Furthermore, after the plasma generation stage ends and the ejector device 2 lifts the wafer 3 on the carrier device 1, the grounding switch 102 is turned on, grounding the lower electrode. This allows the accumulated charge in the lower electrode to be released, preventing arcing problems inside the lower electrode.

[0051] In some embodiments, before the semiconductor process begins, the method further includes:

[0052] S01, control the chamber pressure to reach the first pressure value;

[0053] S02. In response to placing the wafer 3 on the carrier device 1, process gas is introduced into the process chamber 200 and the chamber pressure is controlled to reach a second pressure value; the second pressure value is greater than the first pressure value, so as to form a pressure difference between the upper surface and the lower surface of the wafer 3 and fix the wafer 3 to the carrier device 1.

[0054] In some embodiments, the range of the first pressure value is, for example, 70mTorr to 100mTorr.

[0055] In some embodiments, the range of the second pressure value is, for example, 1 Torr to 3 Torr.

[0056] Before the RF power is turned on, the chamber pressure of the process chamber 200 is first controlled at the first pressure value by evacuation. Then the wafer 3 is placed on the base plate 11 and process gas is introduced into the process chamber 200 to raise the chamber pressure of the process chamber 200 to the second pressure value. At this time, there is a pressure difference between the upper surface and the lower surface of the wafer 3, that is, the pressure on the upper surface of the wafer 3 is greater than the pressure on the lower surface, so that the wafer 3 can be fixed on the base plate 11. It is easy to understand that during this process, the gas in the process chamber 200 also slowly flows into the gap between the lower surface of the wafer 3 and the base plate 11, causing the pressure on the lower surface of the wafer 3 to slowly increase. The pressure difference between the upper and lower surfaces of the wafer 3 gradually decreases. However, since this is a slow process, there is enough time to fix the wafer 3 onto the base plate 11 during the RF power-on process. By adjusting the pressure range, it can be ensured that the pressure difference decreases to zero or near zero before the ejector pin device 2 lifts the wafer 3 from the base plate 11, thus ensuring that the ejector pin device 2 can properly lift the wafer 3. As can be seen from the above, the chuck 12 does not need to have an additional structure for fixing the wafer 3, such as an electrostatic chuck; the wafer 3 can be fixed using only the aforementioned pressure difference.

[0057] In some embodiments, as shown in FIG9, after step S2 above, the control method further includes step S3:

[0058] S3. After lifting the wafer 3 on the carrier device 1, the wafer 3 on the ejector device 2 is grounded through the ejector device 2.

[0059] Further, in some embodiments, the wafer 3 on the ejector device 2 is grounded at the same time as the lower electrode is grounded. In this way, the negative charge in the wafer 3 and the lower electrode can be discharged synchronously, thereby avoiding the potential difference between the wafer 3 and the lower electrode at all times, and solving the particle problem caused by the accumulated charge on the wafer 3 and the arcing problem caused by the accumulated charge on the lower electrode.

[0060] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this application, and this application is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this application, and these modifications and improvements are also considered to be within the scope of protection of this application. [Simplified Explanation of the Diagram]

[0024] The following detailed description is best understood when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the various components are not drawn to scale. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a structural diagram of the lower electrode system and semiconductor process equipment provided in an embodiment of this application; Figure 2 is a timing diagram of the grounding switch input signal and radio frequency power in an embodiment of this application; Figure 3 is a state diagram of the lower electrode system provided in an embodiment of this application during the plasma generation stage; Figure 4 is a state diagram of the lower electrode system provided in an embodiment of this application when the ejector device lifts the wafer; Figure 5 is a state diagram of the lower electrode system provided in an embodiment of this application when the plasma generation stage ends and the ejector device lifts the wafer; Figure 6 is an AWC result diagram of the related art; Figure 7 is an AWC result diagram of an embodiment of this application; Figure 8 is a flowchart of one lower electrode system control method used in the semiconductor process equipment provided in an embodiment of this application; Figure 9 is another flowchart of the lower electrode system control method used in the semiconductor process equipment provided in an embodiment of this application.

Claims

1. A lower electrode system applied in a semiconductor manufacturing apparatus, comprising a carrier device and a ejector device, the ejector device being used to lift a wafer on the carrier device or place a wafer on the carrier device, wherein, It also includes a grounding device, which includes a grounding circuit, a grounding switch, and a control unit. The grounding circuit is electrically connected to a lower electrode in the carrier device through the grounding switch, and is used to ground the lower electrode when the grounding switch is turned on. The control unit is used to control the grounding switch to turn off in response to the start of a semiconductor process and to control the grounding switch to turn on in response to the end of the semiconductor process. The end of the semiconductor process includes the end of the plasma generation stage and the ejector device lifting the wafer on the carrier device.

2. The lower electrode system as described in claim 1, wherein, The ejector pin device is configured to ground the wafer after lifting it from the carrier.

3. The lower electrode system as described in claim 2, wherein, The ejector pin device is configured to be electrically connected to the grounding switch via the lower electrode, so that the wafer on the ejector pin device is grounded when the control unit controls the grounding switch to be turned on.

4. The lower electrode system as described in claim 2, wherein, The ejector pin device includes multiple conductive ejector pins and multiple conductive ejector pin bellows. A plurality of through holes are provided in the supporting device at circumferential intervals. Each ejector pin is correspondingly and vertically inserted through one of the through holes. Each ejector pin bellows is correspondingly sleeved on one of the ejector pins. The upper end of each ejector pin bellows is sealed to the supporting device and electrically conductive. The lower end of each ejector pin bellows is sealed to the corresponding ejector pin and electrically conductive.

5. The lower electrode system as described in claim 1, wherein, It also includes an RF feed device electrically connected to the lower electrode, which is used to connect to an RF power supply via a matching unit to load RF power onto the lower electrode.

6. The lower electrode system as described in any one of claims 1-5, wherein, The grounding circuit includes a circuit for connecting the lower electrode to ground, and a grounding resistor connected in series in the grounding circuit; the grounding switch is connected in series in the grounding circuit and is located on the side of the grounding resistor closer to the lower electrode.

7. The lower electrode system as described in claim 6, wherein, The grounding resistor has a resistance value greater than or equal to 5MΩ and less than or equal to 20MΩ.

8. A semiconductor manufacturing apparatus, comprising a process chamber, wherein, It also includes a lower electrode system as described in any one of claims 1-7, wherein at least some components of the lower electrode system are located in the process chamber.

9. The semiconductor manufacturing apparatus as claimed in claim 8, wherein, The semiconductor manufacturing equipment includes a crystal edge etching device.

10. A semiconductor process equipment control method, applied to a lower electrode system as described in any one of claims 1-7, comprising: In response to the start of a semiconductor manufacturing process, the grounding switch is controlled to open; In response to the completion of the semiconductor process, the grounding switch is turned on; wherein the semiconductor process includes the completion of the plasma generation stage and the lifting device lifting the wafer on the carrier device.

11. The method as described in claim 10, wherein, Before the semiconductor process begins, the method further includes: controlling a chamber pressure to reach a first pressure value; in response to placing the wafer in the carrier device, introducing a process gas into the process chamber of the semiconductor process equipment and controlling the chamber pressure to reach a second pressure value; the second pressure value is greater than the first pressure value, so as to form a pressure difference between the upper and lower surfaces of the wafer, thereby fixing the wafer to the carrier device.

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