Semiconductor device and methods of formation

Abstract

A semiconductor device includes an image sensor element comprising a capacitor structure containing an amorphous component as a dielectric material, the amorphous component comprising a mixture of metal oxides. The amorphous component replaces the crystalline metal oxide dielectric layer stacks used in other methods. Compared to crystalline metal oxide dielectric layer stacks, the amorphous component reduces or prevents interface defects and electron trapping. A single amorphous layer avoids interfaces between metal oxides and crystalline defects in the metal oxides, where electron trapping is easily formed. Compared to other methods using crystalline metal oxide dielectric layer stacks, the resulting image sensor element exhibits reduced latency. Furthermore, using a single amorphous layer comprising a metal oxide mixture increases the capacitance of the corresponding capacitor structure compared to other methods using crystalline metal oxide dielectric layer stacks.

Description

Prior Technology

[0001] Complementary metal-oxide-semiconductor (CMOS) image sensors may include multiple pixel sensors arranged in an array of pixel sensors. The pixel sensors of a CMOS image sensor may include photodiodes configured to convert photons of incident light into an electronic photocurrent. The magnitude of the photocurrent is at least partially based on the intensity of the incident light. Therefore, if the pixel sensors in the pixel sensor array are capable of sensing incident light over a wide range of intensities, the images and / or videos produced by the CMOS image sensor can achieve a high range of brightness and contrast. Simple Explanation of the Diagram

[0002] The best understanding of all aspects of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various feature elements are not drawn to scale. In fact, for clarity, the dimensions of the various feature elements may be arbitrarily increased or decreased. Figures 1A and 1B are example circuit diagrams of the pixel sensor described herein. Figures 2A and 2B are diagrams of the example semiconductor devices described herein. Figures 3A to 3E are examples of forming semiconductor devices as described herein. Figures 4A to 4Q are illustrations of embodiments of the trench capacitor structure described herein. Figures 5A and 5B are examples of the insulating layer of the capacitor structure described herein. Figure 6 illustrates the elemental composition of the insulating layer of the capacitor structure described in this paper. Figure 7 is a diagram of the example semiconductor device described in this article. Figure 8 is a diagram of the example semiconductor device described in this article. Figure 9 is a diagram of the example semiconductor element described in this article. Figure 10 is an example process flow diagram related to the formation of semiconductor devices as described herein. Figure 11 is an example process flow diagram related to the formation of semiconductor devices as described herein. Implementation

[0003] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided protected object. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used in this document to facilitate the description of the relationship between one element or feature shown in the figure and another (other) element or feature. These spatially relative terms are intended to also encompass orientations shown in the figure other than those of the element in use or operation. Elements may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0005] In some cases, the number of incident photons a pixel sensor can absorb before reaching saturation may be limited. "Saturation" refers to the point at which a pixel sensor can no longer absorb additional photons after the initial absorption. Pixel sensor saturation limits its dynamic range because it cannot obtain additional brightness and color information from further photon absorption.

[0006] The amount of photocurrent charge that a pixel sensor can store before reaching saturation is called the full-well capacity (FWC) of the pixel sensor. The full-well capacity of a pixel sensor can be based at least in part on the size (e.g., depth, width, volume) and / or shape of the photodiode. While increasing the size of the photodiode can increase the full-well capacity of the pixel sensor, doing so may sacrifice the pixel density in the pixel sensor array, which may reduce the resolution of the pixel sensor array.

[0007] To increase the full-well capacity of a pixel sensor, image sensor elements (e.g., complementary metal-oxide-semiconductor (CMOS) image sensor elements) may include a capacitor structure configured to store the charge associated with the photocurrent generated by the pixel sensor before the charge is transferred to the floating diffusion node associated with the pixel sensor. The photocurrent can be transferred from the pixel sensor to the capacitor structure, allowing the pixel sensor to generate more charge for the photocurrent instead of storing it entirely in the photodiode and / or floating diffusion node. Therefore, the capacitor structure increases the full-well capacity of the pixel sensor, potentially enabling a wider range of brightness and / or contrast in the images and / or videos produced by the pixel sensor array. The capacitor structure is designed to achieve a small lateral footprint and may include a metal-insulator-metal (MIM) layer stack, wherein the bottom and top electrode layers are arranged alternately and separated by an insulating layer.

[0008] However, some high-density MIM capacitors may suffer from reduced imaging performance when their insulating layers contain stacks of crystalline material. For example, stacks of crystalline insulating layers composed of zirconium oxide (ZrOx, such as ZrO2) and alumina (AlxOy, such as Al2O3) (such as ZrO2 / Al2O3 / ZrO2 (ZAZ) dielectric layers) may be prone to charge trapping, which can lead to discharge delays in MIM capacitors containing such crystalline insulating layer stacks. In ZrO2 / Al2O3 / ZrO2 (ZAZ) arrangements, the interface between the zirconium oxide and alumina layers, as well as crystalline defects in the zirconium oxide layer, can contribute to current leakage paths and electron traps. More specifically, oxygen may migrate from the crystalline zirconium oxide in the zirconium oxide layer (especially at the interface between the zirconium oxide and alumina layers), resulting in crystalline defects known as oxygen vacancies. These oxygen vacancies may act as electron traps, capturing electrons in the MIM capacitor (e.g., from the electrode layers of the MIM capacitor), which increases the discharge time of the MIM capacitor and causes delays in the generation of images and / or videos.

[0009] In some embodiments described herein, the image sensor element (e.g., a CMOS image sensor element) includes a capacitor structure (e.g., a MIM capacitor) comprising an insulating layer with an amorphous composition, comprising a mixture of zirconium, aluminum, and oxygen. Compared to crystalline insulating layer stacks (such as zirconium dioxide / aluminum oxide / zirconium dioxide (ZrO₂ / Al₂O₃ / ZrO₂) (ZAZ) dielectric layer stacks), the amorphous composition reduces or prevents interface defects and electron trapping. In particular, the amorphous composition of the insulating layer avoids interfaces between different zirconium dioxide and aluminum oxide layers, which reduces and / or prevents the formation of crystal defects (such as oxygen vacancies) in the insulating layer. Because charge trapping in the capacitor structure is reduced, minimized, and / or prevented due to the reduction and / or prevention of crystal defects, the resulting image sensor element exhibits reduced latency in generating images and / or videos. For example, in some embodiments, image sensor elements may exhibit a latency reduction of more than 20% when generating images and / or videos compared to other capacitor structures that include ZAZ dielectric layer stacks. Furthermore, the amorphous composition of the insulating layer may increase the capacitance of the capacitor structure compared to other capacitor structures that include ZAZ dielectric layer stacks. For example, in some embodiments, the capacitance of the capacitor structure can be increased by approximately 30% compared to other methods.

[0010] Figures 1A and 1B are example circuit diagrams of the pixel sensor 100 described herein. The pixel sensor 100 may include a front-side pixel sensor (e.g., a pixel sensor configured to receive photons from the front side of a sensor die), a back-side pixel sensor (e.g., a pixel sensor configured to receive photons from the back side of a sensor die), and / or other types of pixel sensors.

[0011] As shown in the example circuit of Figure 1A, the pixel sensor 100 includes a photodiode 102, which can be configured to sense and / or accumulate incident light (e.g., light directed toward the pixel sensor 100) and convert photons of the incident light into a photocurrent. The magnitude of the photocurrent may be based on the number of photons collected in the photodiode 102 (e.g., the intensity of the incident light). Therefore, the accumulation of photons in the photodiode 102 produces an accumulation of charge, representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a larger intensity or brightness, while a smaller amount of charge may correspond to a lower intensity or brightness).

[0012] Photodiode 102 is electrically connected to transmission gate 104. Transmission gate 104 is configured to control the transfer of photocurrent from photodiode to floating diffusion node 106. Transmission gate 104 can be selectively switched by applying a transmission voltage (Vtx) to transmission gate 104. In some embodiments, the transmission voltage applied to transmission gate 104 causes a leakage path (e.g., a buried channel) to be formed across transmission gate 104 between photodiode 102 and floating diffusion node 106, allowing photocurrent to be transmitted along the leakage path to floating diffusion node 106. In some embodiments, removing the transmission voltage from transmission gate 104 (or the absence of the transmission voltage) causes the leakage path to be removed, preventing photocurrent from being transmitted from photodiode 102 to floating diffusion node 106.

[0013] The circuitry of the pixel sensor 100 may further include a reset gate 108. The reset gate 108 is electrically connected to a voltage source 110. The reset gate 108 may be controlled to selectively apply a reset voltage (Vrst) from the voltage source 110 to the floating diffusion node 106. The transmission gate 104 and the reset gate 108 may be electrically coupled to the floating diffusion node 106 such that the reset voltage is applied to the floating diffusion node 106 to "reset" the floating diffusion node 106 (e.g., by draining any residual charge in the floating diffusion node 106), which occurs before activating the transmission gate 104 to transfer photocurrent from the photodiode 102 to the floating diffusion node 106.

[0014] Pixel sensor 100 may be a lateral overflow integration capacitor (LOFIC) pixel sensor with an overflow gate 112 and an overflow capacitor 114. The overflow capacitor 114 may be electrically coupled to a floating diffusion node 106 through the overflow gate 112, allowing photocurrent to be transferred from the floating diffusion node 106 to the overflow capacitor 114 for temporary storage. The overflow gate 112 may selectively control the flow of photocurrent to and / or from the overflow capacitor 114. This allows additional photocurrent to be transferred from the photodiode 102 to the floating diffusion node 106 without causing pixel sensor 100 to saturate, thereby increasing the full-well capacity and dynamic range of pixel sensor 100.

[0015] The photocurrent can be used to apply a floating diffusion voltage (Vfd) to the source follower gate 116 of the pixel sensor 100 circuit. This allows the photocurrent to be observed without removing or discharging it from the floating diffusion node 106 and / or the overflow capacitor 114. A reset gate 108 can be used instead to remove or discharge the photocurrent from the floating diffusion node 106 and / or the overflow capacitor 114.

[0016] In order to apply a floating diffusion voltage to the source follower gate 116, the transfer gate 104 can be closed (e.g., to prevent photocurrent from flowing back to the photodiode 102) and the overflow gate 112 can be opened. This configuration allows the photocurrent stored in the floating diffusion node 106 and the overflow capacitor 114 to be used to apply the floating diffusion voltage to the source follower gate 116.

[0017] The source follower gate 116 acts as a high-impedance amplifier for the pixel sensor 100. The source follower gate 116 provides voltage-to-current conversion for the floating diffuse voltage. The output of the source follower gate 116 is electrically connected to a row select gate 118, which is configured to control the flow of photocurrent to external circuitry. The row select gate 118 is controlled by selectively applying a selection voltage (Vdi) to its gate. This allows photocurrent to flow to the output of the pixel sensor 100.

[0018] As shown in another example circuit in Figure 1B, the pixel sensor 100 may include multiple sub-circuits. These sub-circuits may include small pixel sub-circuits and large pixel sub-circuits. The small pixel sub-circuit may include a small photodiode 102a, a transmission gate 104a, a floating diffusion node 106a, an overflow gate 112a, and an overflow capacitor 114a. The large pixel sensor sub-circuit may include a large photodiode 102b, a transmission gate 104b, a floating diffusion node 106b, an overflow gate 112b, and an overflow capacitor 114b. Both the small and large pixel sub-circuits may be connected to a reset gate 108, a voltage source 110, a source follower gate 116, and a row selection gate 118. The large photodiode 102b may be physically larger than the small photodiode 102a, thereby allowing the pixel sensor 100 to have photon sensitivities in different regions.

[0019] As shown above, Figures 1A and 1B are used as examples. Other examples may differ from those described with respect to Figures 1A and 1B.

[0020] Figures 2A and 2B are illustrations of the example semiconductor element 200 described herein. Semiconductor element 200 may include system-on-chip (SoC) elements, logic elements such as central processing units (CPUs) or graphics processing units (GPUs), memory elements (e.g., high-bandwidth memory (HBM) elements), image sensor elements (e.g., complementary metal-oxide-semiconductor (CMOS) image sensor elements), and / or other types of semiconductor elements. With regard to image sensor elements, semiconductor element 200 may include an example structural embodiment of the overflow capacitor 114 of the pixel sensor 100 described herein.

[0021] Figure 2A depicts a cross-sectional view of semiconductor device 200. As shown in Figure 2A, semiconductor device 200 may include device layer 202 and interconnect layer 204, the interconnect layer 204 being arranged in the semiconductor device 200 along the z-direction relative to device layer 202. For example, interconnect layer 204 may be located above device layer 202. In another example, interconnect layer 204 may be located below device layer 202.

[0022] Interconnect layer 204 may include conductive structures arranged to transmit signals and / or provide power distribution throughout semiconductor device 200. In some embodiments, semiconductor device 200 includes interconnect layers 204 located above and below device layer 202. A first interconnect layer 204 located on a first side of device layer 202 may be used for signal propagation throughout semiconductor device 200, while a second interconnect layer 204 located on a opposite second side of device layer 202 may be used for power distribution within semiconductor device 200.

[0023] Component layer 202 includes a substrate 206 of semiconductor component 200. Substrate 206 may correspond to a portion of the semiconductor wafer in which semiconductor component 200 is formed. Substrate 206 may include a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of substrates. Substrate 206 may extend in the semiconductor component 200 along the x-direction and / or y-direction such that the top and bottom surfaces of substrate 206 are substantially perpendicular to the z-direction in the semiconductor component 200.

[0024] Integrated circuit element 208 may be contained within and / or on substrate 206 in element layer 202 of semiconductor element 200. Integrated circuit element 208 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (FinFET) structures, front-end gate all-around (GAA) transistor structures), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuitry, and / or other types of front-end semiconductor elements.

[0025] The front-end transistor structure may include multiple source / drain regions that may correspond to doped regions of substrate 206 and are separated by channel regions in substrate 206. In some embodiments, the source / drain regions are doped with a first type of dopant (e.g., p-type dopant such as boron (B) and / or gallium (Ga), n-type dopant such as phosphorus (P) and / or arsenic (As)), while the channel regions are doped with a second type of dopant different from the first type of dopant. The front-end transistor structure may include a gate structure located above and / or around the channel regions. The gate dielectric layer of the front-end transistor structure may be located between the gate structure and the channel regions. The gate structure may include a polysilicon gate, a metal gate having a high-dielectric gate dielectric layer (such as hafnium oxide (HfO x, such as HfO 2),) and / or other types of gate structures.

[0026] A dielectric layer 210 is disposed on the substrate 206. The dielectric layer 210 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 210 includes a dielectric material that allows for selective etching or protects portions of the substrate 206 and / or integrated circuit elements 208 from etching, and / or electrically isolates the integrated circuit elements 208 in the element layer 202. The dielectric layer 210 includes silicon nitride (SixNy), oxides (e.g., silicon oxide (SiOx) and / or other oxide materials), and / or other types of dielectric materials. The dielectric layer 210 may extend in the semiconductor element 200 along the x-direction and / or y-direction. Contact windows 212 (e.g., source / drain contact windows, gate contact windows) may pass through the dielectric layer 210 and extend between the integrated circuit element 208 and the interconnect layer 204. The contact window can electrically connect the integrated circuit element 208 to the interconnect layer 204. The contact window 212 may include vias, plugs, and / or other types of elongated conductive structures. The contact window 212 may include conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au).

[0027] The interconnect layer 204 includes multiple dielectric layers (e.g., back-end dielectric layers) arranged in one direction (e.g., the z-direction) approximately perpendicular to the top surface of the substrate 206. The dielectric layers may include interlayer dielectric layers 214 and etch stop layers 216, which are alternately arranged in the z-direction. The interlayer dielectric layers 214 and etch stop layers 216 may extend in the semiconductor device 200 along the x-direction and / or y-direction.

[0028] The interlayer dielectric layer 214 may each comprise a low-dielectric oxide material, such as silicon oxide (SiO₂x) or undoped silicate glass (USG). Additionally and / or alternatively, the interlayer dielectric layer 214 may each comprise boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TES), hydrogen silsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 214 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of extremely low dielectric materials include carbon-doped silicon oxide (C-SiOx), amorphous fluorinated carbon (a-CxFy), parylene, bis-benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbide (SiOC) polymers, porous HSQ, porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiOx).

[0029] The etch stop layers 216 may each comprise silicon nitride (Si xN y), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 214 and the etch stop layers 216 comprise different dielectric materials to provide etch selectivity, thereby enabling the formation of various structures in the interconnect layer 204. For example, the interlayer dielectric layer 214 may each comprise a low-dielectric material, such as borosilicate glass (USG), while the etch stop layers 216 may each comprise a high-dielectric material, such as silicon nitride (Si xN y) or silicon carbide (SiC). Furthermore and / or alternatively, the two or more etch stop layers 216 may comprise different materials. For example, one or more first etch stop layers 216 may comprise silicon nitride (Si xN y), while one or more second etch stop layers 216 may comprise silicon carbide (SiC).

[0030] Interconnect layer 204 includes multiple conductive structures arranged in multiple layers. These conductive structures can be electrically coupled and / or physically coupled to one or more integrated circuit elements 208 in element layer 202. The conductive structures provide electrical wiring, enabling signals and / or power to be supplied to and / or transmitted from integrated circuit elements 208.

[0031] The conductive structure may include multiple layers 218a to 218e arranged in a vertical direction and alternating with multiple layers 220a to 220d in the z-direction (e.g., vertically alternating). Each of layers 218a to 218e includes a metallization structure 222, while each of layers 220a to 220d includes an interconnect structure 224.

[0032] Layers 218a to 218e of the metallization structure 222 may be referred to as M layers. For example, layer 218a of the metallization structure 222 (referred to as the metal-0 (M0) layer) may be located at the bottom of the interconnect layer 204 and may be coupled to the component layer 202. In particular, the metallization structure 222 in the M0 layer may be coupled to the contact window 212 (e.g., the contact layer referred to as the "CO" layer) of the integrated circuit element 208 in the component layer 202. Layer 218b of the metallization structure 222 (referred to as the metal-1 (M1) layer) may be located above layer 218a of the metallization structure 222 in the interconnect layer 204, layer 218c of the metallization structure 222 (referred to as the metal-2 (M2) layer) may be located above layer 218b of the metallization structure 222, and so on.

[0033] Layer 220a of interconnect structure 224 (referred to as via-1 (V0) layer) may be included between M0 layer and M1 layer to interconnect M0 layer and M1 layer, layer 220b of interconnect structure 224 (referred to as via-2 (V1) layer) may be included between M1 layer and M2 layer to interconnect M1 layer and M2 layer, and so on.

[0034] Metallization structure 222 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. Interconnect structure 224 may include vias, interconnects, and / or combinations of other types of conductive structures. Metallization structure 222 and interconnect structure 224 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as examples of other conductive materials. In some embodiments, one or more pad layers are included between the dielectric layer of interconnect layer 204 and metallization structure 222, and / or between the dielectric layer of interconnect layer 204 and interconnect structure 224. One or more pad layers may include barrier pads, adhesive pads, and / or other types of pads. Example materials for one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN), as well as other examples.

[0035] In some embodiments, the top layer of the conductive structure (e.g., the top layer of the metallization structure 222, the top layer of the interconnect structure 224) may be coupled to a connection structure on top of the semiconductor element 200. The connection structure may include solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under-bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, controlled-collapse wafer connection (C4) bumps, and / or other types of connection structures. In some embodiments, the top layer of the conductive structure (e.g., the top layer of the metallization structure 222, the top layer of the interconnect structure 224) may be coupled to a bonding structure, such as a bonding pad and / or a bonding via.

[0036] As further shown in Figure 2A, the trench capacitor structure 226 is included in the interconnect layer 204 of the semiconductor element 200. The trench capacitor structure 226 is an example structural embodiment of the overflow capacitor 114 of the pixel sensor 100.

[0037] Generally, a capacitor structure may include a metal-in-metal (MIM) structure, in which an insulating layer is sandwiched between two conductive electrode layers. The capacitance of a capacitor structure (e.g., the amount of charge it can store) depends directly on the geometry of the conductive electrode layers. The larger the area of ​​the conductive electrode layers, the larger the capacitance of the capacitor structure. Therefore, increasing the size of the metal electrode layers can increase the capacitance of the capacitor structure.

[0038] Increasing the lateral dimensions of the capacitor structure directly contradicts the semiconductor industry's design principle of minimizing semiconductor device size. The goal of minimizing semiconductor device size is to reduce power consumption, improve operational performance and efficiency, and / or enable semiconductor devices to be used in increasingly smaller form factor applications. Therefore, in some cases, the size of the capacitor structure can be increased vertically within the semiconductor device, allowing the capacitor structure to extend through multiple layers. Deep trench capacitors (DTCs) are a type of capacitor structure formed in trenches within a semiconductor device, with the electrode layers and insulating layers extending along and conforming to the trench contour. This allows for an increase in the area of ​​the conductive electrode layer (thus increasing capacitance) while minimizing the increase in the lateral dimensions of the capacitor structure. The trenches in a deep trench capacitor structure are typically formed with a high aspect ratio between the trench depth and trench width.

[0039] Referring to FIG2A, the trench capacitor structure 226 may include a deep trench capacitor structure extending through and / or contained in one or more dielectric layers in the interconnect layer 204, such as one or more interlayer dielectric layers 214 and / or one or more etch stop layers 216. In some embodiments, the trench capacitor structure 226 is configured to store charge (e.g., photocurrent) of integrated circuit elements 208 (e.g., pixel sensors) in the semiconductor device 200. In some embodiments, the integrated circuit elements 208 are electrically coupled to the trench capacitor structure 226 to form memory cells (e.g., dynamic random access memory (DRAM) cells or other capacitance-based memory cells) in the semiconductor device 200. In some embodiments, the trench capacitor structure 226 is configured to provide charge decoupling for one or more integrated circuit elements 208. In some embodiments, the trench capacitor structure 226 is configured to perform another function in the semiconductor device 200.

[0040] The trench capacitor structure 226 may be electrically coupled and / or physically coupled to the bottom contact window 228 and electrically coupled and / or physically coupled to the top contact window 230. Alternatively, the trench capacitor structure 226 may be electrically coupled and / or physically coupled to multiple top contact windows. The bottom contact window 228 and the top contact window 230 may each include one or more conductive structures in the interconnect layer 204, such as one or more metallized structures 222 and / or one or more interconnect structures 224, etc.

[0041] Figure 2B illustrates a detailed cross-sectional view of the trench capacitor structure 226. As shown in Figure 2B, the trench capacitor structure 226 includes one or more trenches 232 on a bottom contact window 228. The bottom contact window 228 may be contained in an interlayer dielectric layer 214a in the interconnect layer 204 of the semiconductor device 200. The trenches 232 of the trench capacitor structure 226 may extend through one or more dielectric layers in the interconnect layer 204 of the semiconductor device 200, including through etch stop layers 216a, interlayer dielectric layers 214a, etch stop layers 216b, interlayer dielectric layers 214c, etch stop layers 216c and / or interlayer dielectric layers 214d, etc. In some embodiments, the trenches 232 may have a high aspect ratio, i.e., the ratio of the depth (or height) of the trenches 232 to the lateral width (or critical dimension) of the trenches 232. Therefore, the trench capacitor structure 226 may be referred to as a deep trench capacitor structure. In some embodiments, the aspect ratio of the trench 232 may be about 10:1 or greater. In some embodiments, the trench 232 may have an aspect ratio that ranges from about 20:1 to about 50:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0042] As further shown in Figure 2B, the trench capacitor structure 226 includes multiple conformal layers that conform to the contour of the trench 232. The conformal layers may include an adhesive layer 234, a bottom electrode layer 236 on the adhesive layer 234, a buffer layer 238 on the bottom electrode layer 236, and an insulating layer 240 on the buffer layer 238. The adhesive layer 234, bottom electrode layer 236, buffer layer 238, and insulating layer 240 may each conform to the contour of the trench 232, such that the adhesive layer 234, bottom electrode layer 236, buffer layer 238, and insulating layer 240 conform to the sidewalls and bottom surface of the trench 232. The trench capacitor structure 226 also includes a top electrode layer 242 on the insulating layer 240. In some embodiments, the top electrode layer 242 is a filler layer that fills the remaining area of ​​the trench 232. Alternatively, the top electrode layer 242 may be conformal to the sidewalls and bottom surface of the trench 232, and may further include a dielectric plug layer or a fill layer in the remaining area of ​​the trench 232.

[0043] The adhesive layer 234, also known as the glue layer, can be used to promote adhesion between the bottom electrode layer 236 and the dielectric layers (e.g., interlayer dielectric layers 214b, 214c, and 214d, etch stop layers 216a, 216b, and 216c) and / or the bottom contact window 228. The adhesive layer 234 can also serve as a barrier layer to prevent conductive material (e.g., copper (Cu)) from the bottom contact window 228 from migrating upwards into the bottom electrode layer 236. The adhesive layer 234 may include tantalum (Ta), tantalum nitride (TaN), and / or other suitable adhesive materials.

[0044] The bottom electrode layer 236, insulating layer 240, and top electrode layer 242 correspond to the metal-insulator-metal (MIM) structure of the trench capacitor structure 226. Therefore, the trench capacitor structure 226 can also be referred to as an MIM capacitor structure. The bottom electrode layer 236 (also called capacitor bottom metal (CBM)) and the top electrode layer 242 (also called capacitor top metal (CTM)) may each include one or more conductive metals, one or more conductive metal-containing materials, one or more conductive ceramic materials, and / or other types of conductive materials. For example, these include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN). In some embodiments, the bottom electrode layer 236 and the top electrode layer 242 include the same material or the same material composition. In some embodiments, the bottom electrode layer 236 and the top electrode layer 242 include different materials or different material compositions.

[0045] The buffer layer 238 may include one or more materials. For example, the buffer layer 238 may include a material that promotes or facilitates lattice matching between the bottom electrode layer 236 and the buffer layer 238, and / or may include a material that promotes or facilitates lattice matching between the insulating layer 240 and the buffer layer 238.

[0046] In embodiments where the bottom electrode layer 236 comprises a nitrogen-containing material or a nitride-containing material (such as titanium nitride (Ti xN, e.g., Ti 2N)), the material of the buffer layer 238 may also comprise a nitrogen-containing material or a nitride-containing material, such as titanium nitride (TiN) and / or titanium oxynitride (TiO xN y), which promotes or facilitates lattice matching through chemical bonding between the bottom electrode layer 236 and the buffer layer 238.

[0047] In embodiments where the insulating layer 240 comprises an oxygen-containing material or an oxide-containing material (such as alumina or zirconium oxide), the material of the buffer layer 238 may also comprise an oxygen-containing material or an oxide-containing material, such as titanium oxide (TiO₂, for example, TiO₂), which may promote or facilitate lattice matching between the buffer layer 238 and the insulating layer 240.

[0048] A surface treatment operation can be performed on the bottom electrode layer 236 using surface treatment chemicals. The surface treatment chemicals may include nitrous oxide (N₂O) and / or other types of surface treatment chemicals that react with the material of the bottom electrode layer 236. The surface treatment operation forms a buffer layer 238 in and / or on the bottom electrode layer 236. In particular, the nitrous oxide (N₂O) in the surface treatment chemicals may react with, for example, titanium nitride (such as TiₓN, e.g., Ti₂N) in the bottom electrode layer 236 to form a buffer layer 238 comprising titanium oxide (such as TiOₓ, e.g., TiO₂) and titanium nitride (TiN). The reaction between the material of the bottom electrode layer 236 and the nitrous oxide (N₂O) in the surface treatment chemicals may include: In this process, titanium nitride (such as TixN, e.g., Ti2N) in the bottom electrode layer 236 reacts with nitrous oxide (N2O) in the surface treatment chemicals to form titanium oxide (such as TiOx, e.g., TiO2) and titanium nitride (TiN) in the buffer layer 238. An additional reaction between nitrous oxide (N2O) and titanium oxide may also form titanium oxynitride (TiOxNy) as a component of the buffer layer 238.

[0049] The insulating layer 240 comprises an amorphous mixture or composition of various materials and is an electrical insulating layer overall. As used herein, the term "amorphous" refers to a mixture or composition of molecules and atoms in a variable arrangement. In other words, the molecules and atoms of an amorphous structure are in an amorphous disordered arrangement. Although short-range ordered molecules and atoms may exist in the amorphous composition, the entire amorphous composition lacks a regular arrangement of its elements. In some embodiments, the amorphous composition is a disordered structure comprising oxygen and one or more metals (e.g., aluminum and / or zirconium). In some portions of the amorphous composition, the metal may be bonded to oxygen in the form of metal oxides (e.g., high-dielectric metal oxides). For example, the amorphous composition may comprise an amorphous component containing two or more high-dielectric oxide materials, such as zirconium oxide (ZrOx, e.g., ZrO2) and aluminum oxide (AlxOy, e.g., Al2O3).

[0050] In some embodiments, the insulating layer 240 comprises an amorphous composition of zirconium, aluminum, and oxygen (ZrAlO). The amorphous composition of zirconium, aluminum, and oxygen may contain molecules with Zr-O bonds, Al-O bonds, Zr-O-Al bonds, and / or Zr-Al bonds, forming an amorphous thin film. For example, the insulating layer 240 may be an amorphous thin film comprising two or more high-dielectric oxides, such as zirconium oxide (ZrOx, e.g., ZrO 2) and aluminum oxide (Al xO y, e.g., Al 2O 3).

[0051] In some embodiments, the trench capacitor structure 226 includes a plurality of trenches 232, and the MIM structure of the trench capacitor structure 226 (e.g., bottom electrode layer 236, insulating layer 240, and top electrode layer 242) extends along the sidewalls and bottom surface of the plurality of trenches 232 and extends between the plurality of trenches 232. The trenches 232 may be laterally arranged in the x-direction and spaced apart by a distance (denoted as dimension D1 in FIG. 2B). In this way, including a plurality of trenches 232 in the trench capacitor structure 226 allows the length (and therefore area) of the MIM structure of the trench capacitor structure 226 (e.g., bottom electrode layer 236, insulating layer 240, and top electrode layer 242) to be extended, thereby increasing the capacitance of the trench capacitor structure 226.

[0052] As further shown in Figure 2B, the trench capacitor structure 226 may include one or more capping layers located above the trench 232 and above the MIM structure of the trench capacitor structure 226. The one or more capping layers may include an oxide capping layer 244, an oxide nitride capping layer 246, and / or a nitride capping layer 248, etc. The capping layers may provide electrical isolation for the MIM structure of the trench capacitor structure 226, and / or may also serve as a hard mask layer stack forming the top contact window 230. The oxide capping layer 244 may contain an oxide-containing dielectric material, such as silicon oxide (SiOx, e.g., SiO2). The oxide nitride capping layer 246 may contain an oxide nitride-containing dielectric material, such as silicon nitride (SiON), etc. The nitride capping layer 248 may contain a nitride-containing dielectric material, such as silicon nitride (SixNy, e.g., Si3N4), etc.

[0053] As further shown in Figure 2B, the trench capacitor structure 226 may include one or more sidewall spacers 250 and / or 252 located on the sidewalls of the capping layers 244-248 and / or on the sidewalls of the top electrode layer 242 above the trench 232. The combination of the capping layers 244-248 and the sidewall spacers 250 and 252 can serve as a self-aligned mask when etching the adhesive layer 234, the bottom electrode layer 236, the buffer layer 238, the insulating layer 240, and / or the top electrode layer 242 to define the MIM structure of the trench capacitor structure 226. The sidewall spacers 250 may contain oxide-containing dielectric materials, such as silicon oxide (SiOx, e.g., SiO2). The sidewall spacers 252 may contain nitride-containing dielectric materials, such as silicon nitride (SixNy, e.g., Si3N4).

[0054] As described above, Figures 2A and 2B are provided as examples. Other examples may differ from those shown in Figures 2A and 2B.

[0055] Figures 3A to 3E are illustrations of an embodiment 300 forming the semiconductor element 200 described herein. In some embodiments, one or more semiconductor process operations related to Figures 3A to 3E may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor process tools.

[0056] Turning to Figure 3A, a substrate 206 is provided. The substrate 206 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor wafers. Semiconductor element 200 may be formed on the semiconductor wafer together with other semiconductor elements.

[0057] As shown in Figure 3B, an integrated circuit element 208 may be formed in the element layer 202 of the semiconductor element 200 and / or on the substrate 206. One or more portions of the integrated circuit element 208 may be formed using one or more semiconductor process tools. For example, an ion implantation tool may be used to dope one or more regions of the substrate 206 with one or more types of dopant to form well regions, implantation regions, and / or other types of doped regions of the integrated circuit element 208 in the substrate 206. Alternatively, a deposition tool may be used to perform various deposition operations to deposit layers and / or structures of the integrated circuit element 208, and / or to deposit a photoresist layer to etch portions of the substrate 206 and / or the deposited layer. Alternatively, an exposure tool may be used to expose the photoresist layer to form a pattern in the photoresist layer. Alternatively, a development tool may be used to develop the pattern in the photoresist layer. Alternatively, an etching tool may be used to etch portions of the substrate 206 and / or the deposited layer to form the integrated circuit element 208. Alternatively, a planarization tool may be used to planarize portions of the integrated circuit element 208. For example, electroplating tools can be used to deposit the metal structure and / or layers of the integrated circuit element 208.

[0058] As further shown in FIG3B, a dielectric layer 210 is deposited on and / or above the substrate 206 and on and / or above the integrated circuit elements 208 using a deposition tool. The dielectric layer 210 can be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization operation, such as a chemical mechanical planarization (CMP) operation, can be performed using a planarization tool to planarize the dielectric layer 210 after deposition.

[0059] As further shown in FIG3B, contact windows 212 of integrated circuit element 208 can be formed through dielectric layer 210. Contact windows 212 can be formed in grooves in dielectric layer 210. In some embodiments, the dielectric layer 210 is etched using a pattern in a photoresist layer to form grooves. In these embodiments, a photoresist layer can be formed on dielectric layer 210 using a deposition tool. The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A portion of the photoresist layer can be developed and removed using a development tool to expose the pattern. The dielectric layer can be etched based on the pattern using an etching tool to form grooves. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to etch the dielectric layer 210 based on the pattern to form grooves.

[0060] Contact windows 212 may be formed in a groove. In some embodiments, contact windows 212 (e.g., gate contact windows) are formed on the gate structure of integrated circuit element 208. In some embodiments, contact windows 212 (e.g., source / drain contact windows) are formed on the source / drain regions of integrated circuit element 208. Material for contact windows 212 may be deposited in the groove using deposition tools through chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. Material for contact windows 212 may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then material for contact windows 212 is deposited on the seed layer. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) is performed using a planarization tool to planarize contact windows 212 after deposition, such that the top of contact windows 212 is substantially coplanar with the top of dielectric layer 210.

[0061] As shown in Figure 3C, a first portion of the interconnect layer 204 of the semiconductor device 200 is formed on the dielectric layer 210. Alternating interlayer dielectric layers 214 and etch stop layers 216 are deposited in the first portion of the interconnect layer 204 of the semiconductor device 200 using one or more deposition tools. In this manner, the interlayer dielectric layers 214 and etch stop layers 216 can be arranged along the z-direction in the semiconductor device 200. Each interlayer dielectric layer 214 and each etch stop layer 216 can be deposited using one or more deposition tools through physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, the interlayer dielectric layers 214 and / or etch stop layers 216 can be planarized using a planarization tool after deposition.

[0062] As further shown in Figure 3C, various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools to form a metallization structure 222 and an interconnect structure 224 in the first portion of the interconnect layer 204 of the semiconductor device 200. The bottom contact window 228 of the trench capacitor structure 226 can also be formed in the first portion of the interconnect layer 204.

[0063] In some embodiments, a first portion of the interconnect layer 204 may be formed in multiple layers. For example, an interlayer dielectric layer 214 and an etch stop layer 216 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), grooves may be formed in and / or through the interlayer dielectric layer 214 and the etch stop layer 216 (e.g., using an exposure tool, a development tool, and / or an etching tool), and a layer 218a (e.g., an MO layer) of the metallization structure 222 may be formed in the interlayer dielectric layer 214 and the etch stop layer 216 (e.g., using one or more deposition tools and / or one or more planarization tools). Another interlayer dielectric layer 214 and another etch stop layer 216 may be formed, and a layer 220a (e.g., a VO layer) of the interconnect structure 224 may be formed in the interlayer dielectric layer 214 and the etch stop layer 216. Layers 218b, 218c, 220b, and 220c may be formed in a similar manner.

[0064] The metallized structure 222, interconnect structure 224, and / or bottom contact window 228 can be deposited using one or more deposition tools through physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some embodiments, the metallized structure 222, interconnect structure 224, and / or bottom contact window 228 can be planarized using a planarization tool after deposition.

[0065] As shown in Figure 3D, a trench capacitor structure 226 can be formed in one or more dielectric layers in the interconnect layer 204. The trench capacitor structure 226 can be formed such that the trenches 232 of the trench capacitor structure 226 fall on the bottom contact windows 228 in the interconnect layer 204. An example process for forming the trench capacitor structure 226 is illustrated and described in Figures 4A-4Q.

[0066] As shown in Figure 3E, a second portion of the interconnect layer 204 of the semiconductor element 200 is formed over the first portion of the interconnect layer 204, including over the trench capacitor structure 226. The second portion of the interconnect layer 204 can be formed in a manner similar to that of the first portion of the interconnect layer 204 described in Figure 3C. The top contact window 230 of the trench capacitor structure 226 can be formed in the second portion of the interconnect layer 204.

[0067] As described above, Figures 3A to 3E are provided as examples. Other examples may differ from those depicted in Figures 3A to 3E.

[0068] Figures 4A through 4Q are diagrams of an embodiment 400 of forming a trench capacitor structure 226 as described herein. In some embodiments, one or more semiconductor process operations described in connection with Figures 4A through 4Q may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, wafer / die transfer tools, and / or other types of semiconductor process tools. In some embodiments, one or more semiconductor process operations described in connection with Figures 4A through 4Q may be performed as part of a process for forming a semiconductor element 200 as described in connection with Figures 3A through 3E.

[0069] As shown in Figure 4A, a masking layer can be formed on the interlayer dielectric layer 214d in the interconnect layer 204 of the semiconductor device 200. For example, a dielectric masking layer 402 can be formed on the interlayer dielectric layer 214d. The dielectric masking layer 402 may contain silicon oxynitride (SiON) and / or other suitable dielectric materials.

[0070] The dielectric mask layer 402 can be deposited using deposition tools through physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) is performed using a planarization tool after the dielectric mask layer 402 is deposited to planarize the dielectric mask layer 402.

[0071] As shown in Figure 4B, a photoresist layer 404 can be formed over the dielectric masking layer 402, and a pattern 406 can be formed in the photoresist layer 404. The photoresist layer can be formed on the dielectric masking layer 402 using a deposition tool (e.g., using spin coating or other suitable deposition techniques). In some embodiments, a bottom anti-reflective coating (BARC) is first deposited on the dielectric masking layer 402, and then the photoresist layer 404 is deposited on the bottom anti-reflective coating. The photoresist layer 404 can be exposed to a radiation source using an exposure tool to pattern the photoresist layer 404. A development tool can be used to develop and remove portions of the photoresist layer 404 to expose the pattern 406.

[0072] As shown in Figure 4C, an etching tool can be used to etch the dielectric mask layer 402 based on the pattern 406 in the photoresist layer 404 to transfer the pattern 406 to the dielectric mask layer 402. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using chemical stripping agents, plasma ashing, and / or other techniques). The etchant may have a higher etching rate on the dielectric mask layer 402 compared to the material of the underlying interlayer dielectric layer 214d. Therefore, the etching operation can be stopped on the interlayer dielectric layer 214d, with minimal etching of the interlayer dielectric layer 214d.

[0073] As shown in Figure 4D, another etching operation is performed to etch through the interlayer dielectric layers 214b, 214c, and 214d, and through the etch stop layers 216b and 216c, to form the trench 232 of the trench capacitor structure 226. This etching operation can include, for example, a gas-based etching operation using different types of etchants, compared to the etchant used to transfer the pattern 406 to the dielectric mask layer 402. Therefore, a wafer / die transfer tool can be used to transfer the semiconductor element 200 from a first etching tool (where the pattern 406 is transferred to the dielectric mask layer 402) to a second etching tool (where the interlayer dielectric layers 214b, 214c, 214d and ESL 216b and 216c are etched) to reduce the possibility of cross-contamination between the first and second etching tools. Alternatively, an etching tool with multiple process chambers (e.g., a cluster tool) can be used, allowing the semiconductor element 200 to be transferred between the process chambers of the etching tool for etching using different types of etchants.

[0074] The gas-based etchant used for etching the interlayer dielectric layers 214b, 214c, 214d and the etch stop layers 216b, 216c may include a fluorine-based gas etchant that exhibits a higher etching rate for the dielectric material of the interlayer dielectric layers 214b, 214c, 214d and the etch stop layers 216b, 216c compared to the etching rate of the dielectric mask layer 402. This allows the interlayer dielectric layers 214b, 214c, 214d and the etch stop layers 216b, 216c to be etched while minimizing the etching of the dielectric mask layer 402 (therefore, the width or critical dimension of the top of the trench 232 is hardly increased). The fluorine-based etchant may include a fluoride-based (CFx) gas etchant, such as a carbon tetrafluoride (CF4) gas etchant.

[0075] In some embodiments, multiple etching operations (e.g., multiple gas-based etching operations using a fluorine-based etchant) are performed to form the trench 232 of the trench capacitor structure 226. For example, a first etching operation (referred to as a "master etching" operation) may be performed to form the trench 232 extending to an etch stop layer 216a. In other words, the etching of the first etching operation stops at the etch stop layer 216a, such that the etch stop layer 216a remains between the bottom of the trench 232 and the bottom contact window 228 at the bottom. The etch stop layer 216a remains above the bottom contact window 228 to prevent the bottom contact window 228 from being exposed to oxygen and other contaminants that may cause the bottom contact window 228 to oxidize. After the first etching operation, the trench 232 may have tapered sidewalls, resulting in the lateral width of the trench 232 gradually decreasing from the top to the bottom of the trench 232.

[0076] A second etching operation (referred to as an "over-etching" operation) may be performed after the first etching operation to shape the bottom of trench 232. Specifically, the second etching operation may be performed to increase the verticality of the sidewalls of trench 232, thereby reducing the taper of the sidewalls of trench 232. During both the first and second etching operations, a dielectric masking layer 402 remains on the interlayer dielectric layer 214d to form and shape trench 232, such that the dielectric masking layer 402 protects the interlayer dielectric layer 214d from etching, which reduces the likelihood of critical dimension widening and the likelihood of rounded corners appearing at the top of trench 232.

[0077] As shown in Figure 4E, a third etch operation (referred to as a "linear removal" etch operation) is performed to etch through the ESL 216a to the bottom of the trench 232, extending the trench 232 through the ESL 216a and reaching the bottom contact window 228. Therefore, after the third etch operation, the bottom contact window 228 is exposed through the trench 232. The third etch operation can use a second etch tool and a fluorine-based etchant, such as a fluorocarbon (CFx, e.g., CF4) gas etchant. During the third etch operation, a dielectric masking layer 402 remains on the interlayer dielectric layer 214d to etch through the etch stop layer 216a, thus protecting the interlayer dielectric layer 214d from etching, which reduces the likelihood of critical dimension reduction. After the bottom contact window 228 is exposed in the trench 232, the dielectric masking layer 402 is removed from the interlayer dielectric layer 214d.

[0078] As shown in Figure 4F, the adhesive layer 234 can be deposited on the sidewalls and bottom surface of the trench 232. The bottom surface of the trench 232 corresponds to the top surface of the bottom contact window 228, so the adhesive layer 234 can be in physical contact with the top surface of the bottom contact window 228. The adhesive layer 234 can also be deposited on the top surface of the interlayer dielectric layer 214d between adjacent trenches 232, such that the adhesive layer 234 can be in physical contact with the top surface of the interlayer dielectric layer 214d. In some embodiments, the adhesive layer 234 is conformally deposited using a deposition tool to conform to the contour of the trench 232. In some embodiments, the adhesive layer 234 is deposited using conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0079] As shown in Figure 4G, the bottom electrode layer 236 can be deposited on the adhesive layer 234. Therefore, the bottom electrode layer 236 is deposited on the sidewalls and bottom surface of the trench 232 (corresponding to the top surface of the bottom contact window 228). The bottom electrode layer 236 can also be deposited on the top surface of the adhesive layer 234 between adjacent trenches 232. In some embodiments, the bottom electrode layer 236 is conformally deposited using a deposition tool, such that the bottom electrode layer 236 conforms to the contour of the trench 232. In some embodiments, the bottom electrode layer 236 is deposited using conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0080] As shown in Figure 4H, a surface treatment operation is performed on the bottom electrode layer 236 using surface treatment chemicals. The surface treatment chemicals may include nitrous oxide (N₂O) and / or other types of surface treatment chemicals that react with the material of the bottom electrode layer 236. The surface treatment operation forms a buffer layer 238 in and / or on the bottom electrode layer 236. As a result, the external portion of the bottom electrode layer 236 exposed to nitrous oxide (N₂O) is transformed into the buffer layer 238. The nitrous oxide (N₂O) in the surface treatment chemicals reacts with, for example, titanium nitride (such as TiₓN, e.g., Ti₂N) in the bottom electrode layer 236 to form a buffer layer 238 comprising titanium oxide (such as TiOₓ, e.g., TiO₂) and titanium nitride (TiN). Additional reactions of nitrous oxide (N₂O) with titanium oxide may also form titanium oxynitride (TiOₓN₂) as a component of the buffer layer 238.

[0081] As shown in Figure 4I, the insulating layer 240 can be deposited on the buffer layer 238. Therefore, the insulating layer 240 is deposited on the sidewalls and bottom surface of the trench 232 (corresponding to the top surface of the bottom contact window 228). The insulating layer 240 can also be deposited on the top surface of the buffer layer 238 between adjacent trenches 232. In some embodiments, the insulating layer 240 is conformally deposited using a deposition tool so that the insulating layer 240 conforms to the contour of the trench 232. In some embodiments, the insulating layer 240 is deposited using conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0082] In some embodiments, multiple atomic layer deposition cycles are performed to deposit an insulating layer 240. As described in more detail in FIG5A, performing an atomic layer deposition cycle may include depositing zirconium oxide (ZrO x, such as ZrO 2) using a first material precursor and depositing alumina (Al xO y, such as Al 2O 3) on the zirconium oxide using a second material precursor. The first material precursor is oxidized to form zirconium oxide, and the second material precursor is oxidized to form alumina. Multiple atomic layer deposition cycles are performed to deposit alternating zirconium oxide and alumina atomic layers. The alternating zirconium oxide and alumina atomic layers are mixed together to form the insulating layer 240. The insulating layer 240 comprises an amorphous composition of zirconium, aluminum, and oxygen (ZrAlO), wherein molecules having Zr-O bonds, Al-O bonds, Zr-O-Al bonds, and / or Zr-Al bonds may be present in the amorphous film. The insulating layer 240 may be an amorphous film comprising amorphous components of zirconium oxide and alumina.

[0083] As shown in Figure 4J, a top electrode layer 242 may be deposited on an insulating layer 240. The top electrode layer 242 may be deposited to fill the remaining area of ​​the trench 232. The top electrode layer 242 may also be deposited on the top surface of the insulating layer 240 between adjacent trenches 232. In some embodiments, the top electrode layer 242 is conformally deposited using deposition tools with physical vapor deposition, chemical vapor deposition, atomic layer deposition, and / or other suitable deposition techniques.

[0084] As shown in Figure 4K, a capping layer is formed on the trench 232 of the trench capacitor structure 226. For example, an oxide capping layer 244 may be formed on and / or on the top electrode layer 242, an oxynitride capping layer 246 may be formed on and / or on the oxide capping layer 244, and / or a nitride capping layer 248 may be formed on and / or on the oxynitride capping layer 246, and other examples.

[0085] An oxide capping layer 244, an oxynitride capping layer 246, and / or a nitride capping layer 248 can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The oxide capping layer 244, the oxynitride capping layer 246, and / or the nitride capping layer 248 may be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., a chemical mechanical planarization operation) can be performed using a planarization tool to planarize the oxide capping layer 244, the oxynitride capping layer 246, and / or the nitride capping layer 248 after deposition.

[0086] As shown in Figure 4L, capping layers (e.g., oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248) can be used to etch and define the top electrode layer 242 of the trench capacitor structure 226. In some embodiments, the oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248 are etched using a pattern in a photoresist layer to form a hard mask on the top electrode layer 242. In these embodiments, a photoresist layer can be formed on the nitride capping layer 248 using a deposition tool. The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248 can be etched based on the pattern using an etching tool to define the hard mask layer. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer may be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). The top electrode layer 242 may then be etched using an etching tool based on a hard masking layer (e.g., based on a pattern in oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248) to define the top electrode layer 242.

[0087] As shown in Figure 4M, spacer layers 408 and 410 are formed on the capping layers (e.g., oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248). Spacer layers 408 and 410 extend along the ends of the capping layers (e.g., along the ends of oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248) and along the ends of the top electrode layer 242. Furthermore, spacer layers 408 and 410 are formed on the exposed portions of the insulating layer 240.

[0088] The spacer layers 408 and / or 410 can be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The spacer layers 408 and / or 410 can be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) can be performed after the deposition of the spacer layers 408 and / or 410 to planarize them.

[0089] As shown in Figure 4N, spacer layers 408 and 410 are etched together with portions of insulating layer 240, buffer layer 238, bottom electrode layer 236, and adhesive layer 234 to define the bottom electrode layer 236 of the MIM structure of trench capacitor structure 226. This etching operation may be referred to as a CBM etching operation. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. Etching of spacer layers 408 and 410 removes portions of spacer layers 408 and 410 from the top of nitride capping layer 248, resulting in the formation of sidewall spacers 250 and 252 at the ends of oxide capping layer 244, oxynitride capping layer 246, nitride capping layer 248, and top electrode layer 242. Furthermore, etching of spacer layers 408 and 410 results in sidewall spacers 252 having a circular outer surface.

[0090] Anisotropic etching of spacer layers 408 and 410 can be achieved using etchants (e.g., gas-based etchants, plasma-based etchants). Spacer layers 408 and 410 can be etched together with portions of insulating layer 240, buffer layer 238, bottom electrode layer 236, and adhesive layer 234. This anisotropic etching primarily occurs along the z-direction in the semiconductor device 200, enabling minimal lateral etching of the bottom electrode layer 236 and insulating layer 240.

[0091] As shown in Figure 4O, additional material can be formed to form the interlayer dielectric layer 214d to encapsulate the trench capacitor structure 226. The additional material for the interlayer dielectric layer 214d can be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, epitaxy, oxidation, and / or other suitable deposition techniques. The additional material for the interlayer dielectric layer 214d can be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) can be performed on the interlayer dielectric layer 214d after the deposition of the additional material to planarize it.

[0092] As shown in Figure 4P, a groove 412 can be formed in the interlayer dielectric layer 214d, passing through the capping layers 244-248 and extending to the top electrode layer 242 of the trench capacitor structure 226. Therefore, the top electrode layer 242 can be exposed through the groove 412.

[0093] In some embodiments, the pattern in the photoresist layer is used to etch the interlayer dielectric layer 214d, oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248 to form a groove 412. In these embodiments, a deposition tool can be used to form the photoresist layer on the interlayer dielectric layer 214d. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the interlayer dielectric layer 214d, oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248 based on the pattern to form the groove 412. In some embodiments, one or more etching operations are performed to etch the interlayer dielectric layer 214d, oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248. In some embodiments, one or more etching operations may include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer may be removed using a photoresist removal tool (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative to the pattern-forming groove 412.

[0094] As shown in Figure 4Q, a top contact window 230 can be formed in the groove 412. The material of the top contact window 230 can be deposited using deposition tools through chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. The top contact window 230 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then the top contact window 230 is deposited on the seed layer. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) is performed after the deposition of the top contact window 230 using a planarization tool to planarize the top contact window 230.

[0095] As mentioned above, Figures 4A through 4Q are provided as examples. Other examples may differ from those described in Figures 4A through 4Q.

[0096] Figures 5A and 5B illustrate Example 500 of the insulating layer 240 described herein. Example 500 includes an atomic layer deposition technique in which atomic layers of zirconium oxide 502 and aluminum oxide 504 are alternately deposited on a buffer layer 238. These alternating atomic layers are mixed together to form an amorphous structure of the insulating layer 240. Multiple operations in the atomic layer deposition technique are performed over time.

[0097] Multiple atomic layer deposition cycles are performed to form an insulating layer 240. The atomic layer deposition cycle in Example 500 includes the use of a sequence of gaseous precursors (or reactants). A semiconductor device 200 is placed in the process chamber of the deposition tool, and oxygen-containing gas is pulsed during the atomic layer deposition cycle to oxygenate the semiconductor device 200. The oxygen-containing gas may include ozone (O3), oxygen (O2), water vapor (H2O), and / or other oxygen-containing gases. The pulse duration of the oxygen-containing gas may range from about 0.1 seconds to about 3 seconds. However, other range values ​​are included in this disclosure.

[0098] The pulse of oxygen-containing gas may be followed by the first pulse of a first metallic material precursor, which is provided into the process chamber of the deposition tool. The first metallic material precursor may include a zirconium vapor precursor for the zirconium oxide layer 502. Examples of zirconium precursors include tetratetra(tert-butoxy)zirconium(IV)(Zr(OC(CH3)3)4), zirconium tetraiodide(IV)(ZrI4), zirconium tetrachloride(IV)(ZrCl4), and tetratetra(dimethylamino)zirconium(IV)(Zr(NMe2)4), among others. The duration of the first pulse of the first metallic material precursor may range from about 0.1 seconds to about 3 seconds. However, other range values ​​are included in this disclosure.

[0099] The first metallic material precursor is then removed from the process chamber, and a pulse of oxygen-containing gas may be supplied to the process chamber again. This pulse of oxygen-containing gas may be followed by a pulse of a second metallic material precursor, which is supplied to the process chamber of the deposition tool. The second metallic material precursor may include an aluminum vapor precursor for the alumina layer 504. Examples of aluminum precursors include trimethylaluminum (TMA) (C3H9Al), dimethylaluminum hydride (DMAH) ((CH3)2AlH), and dimethylethylamine (DMEAA) (AIH3:N(CH3)2(CH2CH3)), among others. The pulse duration of the second metallic material precursor may range from about 0.1 seconds to about 3 seconds. However, other range values ​​are included in this disclosure.

[0100] The first pulse of the first metallic material precursor may react with oxygen-containing gas to form a first zirconium oxide layer 502 of the insulating layer 240. The first zirconium oxide layer 502 includes an oxygen-containing metallic material (e.g., a metal oxide material) containing the metal (e.g., zirconium) of the first metallic material precursor. The first pulse of the second metallic material precursor may react with oxygen-containing gas to form a first aluminum oxide layer 504 of the insulating layer 240 on the first zirconium oxide layer 502. The first aluminum oxide layer 504 includes an oxygen-containing metallic material (e.g., a metal oxide material) containing the metal (e.g., aluminum) of the second metallic material precursor.

[0101] Additional atomic layer deposition cycles can be performed to form repeating alternating atomic layers (e.g., zirconium oxide layer 502 and aluminum oxide layer 504) on the first zirconium oxide layer 502 and the first aluminum oxide layer 504, as shown in FIG5A. The number of atomic layer deposition cycles performed may be based on the desired thickness of the insulating layer 240.

[0102] In some embodiments, multiple atomic layer deposition cycles are performed to deposit alternating layers of zirconium oxide and alumina at the same or different deposition rates. In particular, in one atomic layer deposition cycle, a first high-dielectric metal oxide (e.g., zirconium oxide) atomic layer may be deposited with a second high-dielectric metal oxide (e.g., alumina) atomic layer at approximately the same rate, a faster rate, or a slower rate.

[0103] In some embodiments, the deposition rate per atomic layer deposition cycle is in the range of about 0.5 angstroms to about 2 angstroms per atomic layer deposition cycle. However, other range values ​​are included in this disclosure.

[0104] The duration of each atomic layer deposition cycle may range from about 3 seconds to about 6 seconds. However, other ranges are included in this disclosure. In some embodiments, the amount of time for the first metal precursor pulse to react with oxygen-containing gas and / or the amount of the first metal precursor are controlled to increase or decrease the concentration and / or deposition thickness of the zirconium oxide layer 502. Similarly, the amount of time for the second metal precursor pulse to react with oxygen-containing gas and / or the amount of the second metal precursor are controlled to increase or decrease the concentration and / or deposition thickness of the alumina layer 504.

[0105] In some embodiments, in one or more atomic layer deposition cycles, each cycle may contain a greater number of first metal material precursor pulses than the number of second metal material precursor pulses, to achieve a higher concentration and a greater deposition thickness of the first metal oxide (e.g., zirconium oxide) in the insulating layer 240. For example, an atomic layer deposition cycle may contain three zirconium pulses and one aluminum pulse to achieve a thickness ratio of approximately 3:1 between the zirconium oxide layer 502 thickness and the aluminum oxide layer 504 thickness.

[0106] Alternatively, in one or more atomic layer deposition cycles, each cycle may contain a greater number of second metal precursor pulses than the number of first metal precursor pulses, to achieve a higher concentration and greater deposition thickness of the second metal oxide (e.g., alumina) in the insulating layer 240. For example, an atomic layer deposition cycle may contain 3 zirconium pulses and 4 aluminum pulses to achieve a thickness ratio of approximately 3:4 between the zirconium oxide layer 502 and the alumina layer 504.

[0107] In some embodiments, one or more atomic layer deposition cycles may include the same number of first metal precursor pulses and second metal precursor pulses to achieve approximately the same concentration and approximately the same deposition thickness of the first and second metal oxides. As used herein, “concentration” refers to the amount of a given substance relative to volume (e.g., atoms per cubic centimeter).

[0108] The combined deposition thickness of the zirconia layer 502 in the z-direction can be greater than, less than, or approximately equal to the combined deposition thickness of the alumina layer 504 in the z-direction. Similarly, the thickness of the individual zirconia layer 502 and alumina layer 504 in the z-direction can be increased or decreased by varying the reaction time and / or the amount of precursor during a given atomic layer deposition cycle.

[0109] In some embodiments, atomic layer deposition cycles are repeated until the thickness of the insulating layer 240 in the z-direction is approximately 50 to approximately 80 angstroms. However, other range values ​​are included within the scope of this disclosure.

[0110] Referring to Figure 5B, in some embodiments, the repeating alternating atomic layers shown in Figure 5A (e.g., zirconium oxide layer 502 and aluminum oxide layer 504) are not visible in the final structure of semiconductor device 200. As shown in Figure 5B, due to subsequent heat treatment, zirconium oxide layer 502 and aluminum oxide layer 504 are mixed together to form an insulating layer 240 comprising an amorphous composition of zirconium, aluminum, and oxygen (ZrAlO), wherein molecules may be present having Zr-O bonds, Al-O bonds, Zr-O-Al bonds, and / or Zr-Al bonds, forming an amorphous thin film. The insulating layer 240 may be an amorphous thin film comprising amorphous components of zirconium oxide and aluminum oxide.

[0111] The amorphous structure of insulating layer 240 exhibits higher stability compared to other methods using ZrO₂ / Al₂O₃ / ZrO₂ (ZAZ) dielectric layer stacks as insulating layers. In particular, the amorphous structure of insulating layer 240 can withstand high-temperature conditions better than crystals containing ZAZ stacks, resulting in lower oxygen migration. However, in some cases, the amorphous structure of insulating layer 240 may contain multiple phases, such as a tetragonal phase and / or a cubic phase, which are more stable than other phases.

[0112] As described above, Figures 5A and 5B are provided as examples. Other examples may differ from those described with respect to Figures 5A and 5B.

[0113] Figure 6 illustrates the elemental composition 600 of the insulating layer 240 along its depth profile 602 in Example 500. The elemental composition is described as the atomic percentage 604 of one or more elements in the insulating layer 240 as a function of the depth 606 of the insulating layer 240. In particular, the atomic percentage 604 of one or more elements is described from the top surface to the bottom surface of the insulating layer 240.

[0114] As shown in the depth profile 602 of Figure 6, the insulating layer 240 may include aluminum oxide (AlxOy) and zirconium oxide (ZrOx). The atomic percentage 604 (or concentration) of aluminum (e.g., aluminum oxide (AlxOy)) and the atomic percentage 604 (or concentration) of zirconium (e.g., zirconium oxide (ZrOx)) increase along the depth 606 of the insulating layer 240, reach a peak, and then decrease, such that the concentration of aluminum and zirconium in or near the middle portion of the insulating layer 240 in the z-direction is greater than the concentration at or near the top and bottom surfaces of the insulating layer 240.

[0115] Because the curves for alumina and zirconium oxide have approximately the same parabolic shape and approximately parallel line segments along the depth 606 of the insulating layer 240, in some embodiments, the ratio of the atomic percentage 604 (or concentration) of aluminum (e.g., alumina (AlxOy)) to the atomic percentage 604 (or concentration) of zirconium (e.g., zirconium oxide (ZrOx)) is substantially uniform (e.g., remains constant) along the depth 606 of the insulating layer 240.

[0116] As can be seen from the higher peaks and higher points of the alumina curve compared to the lower peaks and lower points of the zirconium oxide curve, in some embodiments, along the depth 606 of the insulating layer 240, the insulating layer 240 may contain a higher atomic percentage 604 (or concentration) of aluminum (e.g., aluminum oxide (AlxOy)) than that of zirconium (e.g., zirconium oxide (ZrOx)).

[0117] In some embodiments, the ratio of the atomic percentage 604 (or concentration) of zirconium oxide 604 to the atomic percentage 604 (or concentration) of aluminum oxide 604 (or concentration) in insulating layer 240 may be in the range of approximately 3:4 to approximately 9:2. As described herein, insulating layer 240, as a single amorphous layer, avoids the interface between zirconium oxide and aluminum oxide, as well as the formation of easily trapped crystal defects in zirconium oxide. The resulting image sensor element exhibits reduced latency. For example, in some embodiments, when using a single amorphous insulating layer, latency can be reduced by more than 20% compared to other methods using a ZrO2 / Al2O3 / ZrO2 (ZAZ) dielectric layer stack as the insulating layer. With a zirconium oxide atomic percentage 604 (or concentration) to aluminum oxide atomic percentage 604 (or concentration) ratio in insulating layer 240 of approximately 3:4, latency is reduced by approximately 5% compared to other methods. When the ratio of the atomic percentage 604 (or concentration) of zirconium oxide to the atomic percentage 604 (or concentration) of aluminum oxide in insulating layer 240 is approximately 3:2, the delay is reduced by approximately 10% compared to other methods. When the ratio of the atomic percentage 604 (or concentration) of zirconium oxide to the atomic percentage 604 (or concentration) of aluminum oxide in insulating layer 240 is approximately 3:1, the delay is reduced by approximately 21% compared to other methods. When the ratio of the atomic percentage 604 (or concentration) of zirconium oxide to the atomic percentage 604 (or concentration) of aluminum oxide in insulating layer 240 is approximately 9:2, the delay is reduced by approximately 23% compared to other methods.

[0118] Figure 7 is an illustration of an example semiconductor element 700 described herein. Semiconductor element 700 may include an example of a three-dimensional image sensor (e.g., a 3D CMOS image sensor). Semiconductor element 700 may be configured to be deployed in various embodiments, such as digital cameras, video recorders, night vision cameras, automotive sensors, and cameras and / or other types of light sensing embodiments.

[0119] As shown in Figure 7, the semiconductor device 700 may include a pixel sensor array 702. The semiconductor device 700 may also include a black level correction (BLC) region 704, a bonding pad region 706, and / or a sealing ring region 708, etc. The pixel sensor array 702 may include a plurality of pixel sensors 100 arranged in an array. Pixel sensors 100 are configured to sense incident light and convert photons of the incident light into photocurrent. Pixel sensors 100 may be contained in a device layer 710 of the semiconductor device 700. Each pixel sensor 100 may include one or more photodiodes 102 configured to generate a photocurrent based on photons of the incident light. Pixel sensors 100 may also include floating diffusion nodes 106 in the device layer 710, configured to temporarily store the photocurrent generated by the associated pixel sensors 100, and may each include a transmission gate 104 configured to control the flow of photocurrent from the photodiodes 102 to the floating diffusion node 106. The pixel sensor 100 can be formed by one or more semiconductor process tools using various semiconductor process technologies, such as lithography, etching, deposition, chemical mechanical planarization and / or ion implantation.

[0120] The black level correction region 704 includes a metal shielding layer over a portion of the component layer 710 to allow baseline current measurements to be performed within the component layer 710 of the black level correction region 704 to determine the dark current of the pixel sensor array 702 (e.g., current generated in the component layer 710 by non-incident light sources such as heat), thereby allowing the black level of the pixel sensor array 702 to be adjusted to compensate for the dark current. The bonding pad region 706 may include one or more conductive bonding pads (or electronic pads) and / or metallization layers through which electrical connections can be established between the semiconductor component 700 and external components and / or external packages. The sealing ring region 708 may include an arrangement of metallization structures and interconnect structures to provide structural rigidity to the semiconductor component 700 and protect the semiconductor component 700 from moisture and other contaminants.

[0121] As further shown in FIG7, the semiconductor device 700 may include an interconnect layer 712 located below the device layer 710. The interconnect layer 712 may include a dielectric region 714, which includes one or more dielectric layers (e.g., interlayer dielectric layers, interlayer metal dielectric layers, etch stop layers) and an arrangement of metallization structures 716 and interconnect structures 718 in the dielectric region 714. A passivation layer 720 may be included below the interconnect layer 712.

[0122] As further shown in Figure 7, one or more overflow capacitors 114 may be included in the interconnect layer 712. The overflow capacitor 114 may be structurally implemented as the trench capacitor structure 226 shown and described herein. The overflow capacitor 114 may be electrically coupled to the floating diffusion node 106 of the pixel sensor 100 and may be configured to store the overflow photocurrent from the floating diffusion node 106.

[0123] As described above, Figure 7 is provided as an example. Other examples may differ from those described with respect to Figure 7.

[0124] Figure 8 is a diagram of an example semiconductor device 800 described herein. Semiconductor device 800 may include an example of a three-dimensional image sensor (e.g., a 3D CMOS image sensor). Semiconductor device 800 may be configured to be deployed in various implementations, such as digital cameras, video recorders, night vision cameras, automotive sensors and cameras, and / or other types of light sensing implementations.

[0125] As shown in Figure 8, semiconductor element 800 includes a combination of structures and / or layers similar to those of semiconductor element 700. For example, semiconductor element 800 may include elements 802 to 818, which are similar to elements 702 to 718 of semiconductor element 700.

[0126] However, the semiconductor device 800 includes multiple semiconductor dies, including a first semiconductor die 820a and a second semiconductor die 820b. The first semiconductor die 820a and the second semiconductor die 820b can be directly bonded together at a bonding interface 822, such that the first semiconductor die 820a and the second semiconductor die 820b are stacked and vertically arranged along the z-direction in the semiconductor device 800. The first semiconductor die 820a may be referred to as an image sensor die and may include a pixel sensor array 802 (including pixel sensor 100), a black level correction region 804, and a bonding pad region 806. The first semiconductor die 820a may also include a photodiode 102, a transmission gate 104, a floating diffusion node 106, a device layer 810, and an interconnect layer 812 (including a dielectric region 814, a metallization structure 816, and an interconnect structure 818). In the example of FIG8, an overflow capacitor 114 is included in the interconnect layer 812 of the first semiconductor die 820a. The sealing ring region 808 can extend through the first semiconductor die 820a and the second semiconductor die 820b.

[0127] As further shown in FIG8, the second semiconductor die 820b of the semiconductor device 800 may include a device layer 824, one or more integrated circuit elements 826 contained in the device layer 824, and an interconnect layer 828 located above the device layer 824. The interconnect layer 828 may include a dielectric region 830, which includes one or more dielectric layers (e.g., interlayer dielectric layers, etch stop layers) and an arrangement of metallization structures 832 and interconnect structures 834 in the dielectric region 830 of the interconnect layer 828 of the second semiconductor die 820b.

[0128] The first semiconductor die 820a and the second semiconductor die 820b can be joined at the bonding interface 822 via dielectric-to-dielectric bonding between the dielectric region 814 of the first semiconductor die 820a and the dielectric region 830 of the second semiconductor die 820b. Furthermore, the first semiconductor die 820a and the second semiconductor die 820b can be joined at the bonding interface 822 via metal-to-metal bonding between bonding pad 836 contained in the interconnect layer 812 of the first semiconductor die 820a and bonding pad 838 contained in the interconnect layer 828 of the second semiconductor die 820b. Bonding pad 836 can be electrically connected to the metallization structure 816 and the interconnect structure 818 in the interconnect layer 812 via bonding via 840, while bonding pad 838 can be electrically connected to the metallization structure 832 and the interconnect structure 834 in the interconnect layer 828 via bonding via 842.

[0129] As described above, Figure 8 is provided as an example. Other examples may differ from those described with respect to Figure 8.

[0130] Figure 9 is a diagram of an example semiconductor element 900 described herein. Semiconductor element 900 may include an example of a three-dimensional image sensor (e.g., a three-dimensional complementary metal-oxide-semiconductor image sensor). Semiconductor element 900 may be configured to be deployed in various embodiments, such as digital cameras, video recorders, night vision cameras, automotive sensors and cameras, and / or other types of light-sensing embodiments.

[0131] As shown in Figure 9, semiconductor element 900 includes a combination of structures and / or layers similar to those of semiconductor element 800. For example, semiconductor element 900 may include elements 902 to 942, which are similar to elements 802 to 842 of semiconductor element 800. Semiconductor element 900 may also include pixel sensor 100, photodiode 102, transmission gate 104, floating diffusion node 106, and one or more overflow capacitors 114.

[0132] However, in semiconductor element 900, one or more overflow capacitors 114 are contained in a second semiconductor die 920b (e.g., an application-specific integrated circuit (ASIC) die) and not (or except) contained in a first semiconductor die 920a (e.g., a sensor die). Including one or more overflow capacitors 114 in the second semiconductor die 920b instead of the first semiconductor die 920a allows a larger area in the first semiconductor die 920a to be used for the photodiode 102 (which provides increased full-well capacitance for the photodiode 102) and / or for control circuitry of the pixel sensor 100 (e.g., for the transmission gate 104, reset gate 108, overflow gate 112), which may increase the performance of semiconductor element 900.

[0133] As described above, Figure 9 is provided as an example. Other examples may differ from those described with respect to Figure 9.

[0134] Figure 10 is a flowchart of an example process 1000 associated with the formation of a semiconductor device. In some embodiments, one or more process blocks of Figure 10 are performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0135] As shown in Figure 10, process 1000 may include forming trenches (block 1010) in the dielectric layer. For example, one or more semiconductor process tools may be used to form trenches (e.g., trench 232) in the dielectric layer (e.g., interlayer dielectric layer 214 and / or etch stop layer 216), as described herein.

[0136] As further shown in Figure 10, process 1000 may include a first electrode layer (block 1020) deposited in a trench, consisting of a stack of semiconductor layers. For example, a first electrode layer (e.g., bottom electrode layer 236) of a stack of semiconductor layers for a capacitor structure (e.g., trench capacitor structure 226) may be deposited in a trench using one or more semiconductor process tools, as described herein.

[0137] As further shown in Figure 10, process 1000 may include depositing an insulating layer of semiconductor layer stacks in a trench onto the first electrode layer (block 1030). For example, one or more semiconductor process tools may be used to deposit an insulating layer of semiconductor layer stacks (e.g., insulating layer 240) on the first electrode layer in a trench, as described herein.

[0138] As further shown in Figure 10, process 1000 may include depositing a second electrode layer of a semiconductor layer stack on an insulating layer in a trench (block 1040). For example, one or more semiconductor process tools may be used to deposit a second electrode layer (e.g., top electrode layer 242) of a semiconductor layer stack on an insulating layer in a trench, as described herein. In some embodiments, the semiconductor layer stack extends along the sidewalls and bottom surface of the trench. In some embodiments, the insulating layer is an amorphous layer comprising a combination of metal and oxygen.

[0139] Process 1000 may include additional embodiments, such as any single embodiment or combination of any embodiments described below and / or one or more other related processes described elsewhere herein.

[0140] In a first embodiment, depositing an insulating layer includes performing multiple atomic layer deposition cycles to deposit the insulating layer, wherein performing one atomic layer deposition cycle includes depositing zirconium oxide (e.g., zirconium oxide layer 502) using a first material precursor and depositing alumina (e.g., alumina layer 504) on the zirconium oxide using a second material precursor.

[0141] In the second embodiment, the atomic layer deposition cycle, performed alone or in combination with the first embodiment, further includes oxidizing a first material precursor to form zirconium oxide and oxidizing a second material precursor to form aluminum oxide.

[0142] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the thickness of the deposited zirconium oxide is greater than the thickness of the deposited alumina.

[0143] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the thickness of the deposited zirconium oxide is less than the thickness of the deposited alumina.

[0144] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the thickness of the deposited zirconium oxide is approximately equal to the thickness of the deposited alumina.

[0145] In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, multiple atomic layer deposition cycles are performed to deposit alternating zirconium oxide and alumina atomic layers.

[0146] In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, process 1000 includes performing a surface treatment operation on the first electrode layer to transform a portion of the first electrode layer into a buffer layer (e.g., buffer layer 238) on the first electrode layer, wherein the surface treatment operation is performed prior to the deposition of an insulating layer, and the insulating layer is deposited on the buffer layer.

[0147] In the eighth embodiment, the insulating layer comprises, alone or in combination with one or more of the first to seventh embodiments, at least one of a tetragonal or cubic crystal phase.

[0148] In the ninth embodiment, alone or in combination with one or more of the first to eighth embodiments, the metal comprises aluminum and zirconium, wherein the ratio of zirconium concentration to aluminum concentration in the insulating layer is substantially uniform at different depths of the insulating layer.

[0149] In the tenth embodiment, alone or in combination with one or more of the first to ninth embodiments, the metal comprises aluminum and zirconium, wherein the concentration of zirconium in the insulating layer is greater than the concentration of aluminum in the insulating layer.

[0150] While Figure 10 shows an example block of process 1000, in some embodiments, process 1000 may include additional blocks, fewer blocks, different blocks, or blocks with different configurations compared to the blocks depicted in Figure 10. Alternatively, two or more blocks of process 1000 may be executed simultaneously.

[0151] Figure 11 is a flowchart of an example process 1100 associated with the formation of a semiconductor device. In some embodiments, one or more process blocks of Figure 11 are performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0152] As shown in Figure 11, process 1100 may include depositing a first conductive layer (block 1110) within a trench formed in a dielectric layer. For example, one or more semiconductor process tools may be used to deposit a first conductive layer (e.g., bottom electrode layer 236) within a trench (e.g., trench 232) formed in a dielectric layer (e.g., interlayer dielectric layer 214 and / or etch stop layer 216), as described herein. In some embodiments, the first conductive layer extends along the sidewalls and bottom surface of the trench.

[0153] As further shown in Figure 11, process 1100 may include performing processing operations to transform a portion of the first conductive layer into a buffer layer (block 1120). For example, one or more semiconductor process tools may be used to perform the processing operations to transform a portion of the first conductive layer into a buffer layer (e.g., buffer layer 238), as described herein.

[0154] As further shown in Figure 11, process 1100 may include depositing an insulating layer (block 1130) on the buffer layer. For example, an insulating layer (e.g., insulating layer 240) may be deposited on the buffer layer using one or more semiconductor process tools, as described herein. In some embodiments, the insulating layer is an amorphous composition comprising a mixture of a first metallic material, a second metallic material, and oxygen.

[0155] As further shown in Figure 11, process 1100 may include depositing a second conductive layer (block 1140) on the insulating layer. For example, one or more semiconductor process tools may be used to deposit the second conductive layer (e.g., top electrode layer 242) on the insulating layer, as described herein.

[0156] Process 1100 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and / or one or more other processes described elsewhere herein.

[0157] In the first embodiment, at least some of the first metal material and the oxygen of the first portion bond together to form a first high-dielectric metal oxide, and at least some of the second metal material and the oxygen of the second portion bond together to form a second high-dielectric metal oxide.

[0158] In the second embodiment, alone or in combination with the first embodiment, depositing an insulating layer includes performing multiple atomic layer deposition cycles to deposit alternating first high-dielectric metal oxide layers and second high-dielectric metal oxide layers.

[0159] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the atomic layer of the first high-dielectric metal oxide is deposited at a higher rate than the atomic layer of the second high-dielectric metal oxide.

[0160] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the deposition of the insulating layer is such that the ratio of the first high-dielectric metal oxide to the second high-dielectric metal oxide is in the range of about 3:4 to about 9:2.

[0161] Although Figure 11 shows an example block of process 1100, in some embodiments, process 1100 includes additional blocks, fewer blocks, different blocks, or blocks with different configurations compared to the blocks depicted in Figure 11. Alternatively, two or more blocks of process 1100 may be executed in parallel.

[0162] Thus, image sensor elements (e.g., CMOS image sensor elements) include capacitor structures (e.g., MIM capacitors) with an insulating layer having an amorphous composition, which comprises a mixture of zirconium, aluminum, and oxygen. Compared to crystalline insulating layer stacks (such as ZrO₂ / Al₂O₃ / ZrO₂ (ZAZ) dielectric layer stacks), this amorphous composition reduces or prevents interface defects and electron trapping. In particular, the amorphous composition of the insulating layer avoids interfaces between different zirconium oxide and aluminum oxide layers, which reduces and / or prevents the formation of crystal defects (such as oxygen vacancies) in the insulating layer. Because charge trapping in the capacitor structure is reduced, minimized, and / or prevented due to reduced and / or prevented crystal defects, the resulting image sensor element exhibits reduced latency when generating images and / or videos. For example, in some embodiments, the image sensor element may exhibit a latency reduction of greater than 20% when generating images and / or videos compared to other capacitor structures including ZAZ dielectric layer stacks. Furthermore, the amorphous composition of the insulating layer may increase the capacitance of the capacitor structure compared to other capacitor structures that include ZAZ dielectric layer stacks. For example, in some embodiments, the capacitance of the capacitor structure can be increased by approximately 30% compared to other methods.

[0163] As described in detail above, some embodiments described herein provide a method. The method includes forming a trench in a dielectric layer. The method includes depositing a first electrode layer of a semiconductor layer stack in the trench. The method includes depositing an insulating layer of the semiconductor layer stack on the first electrode layer in the trench. The method includes depositing a second electrode layer of the semiconductor layer stack on the insulating layer in the trench, wherein the semiconductor layer stack extends along the sidewalls and bottom surface of the trench, and wherein the insulating layer is an amorphous layer comprising a combination of metal and oxygen.

[0164] As described in detail above, some embodiments described herein provide a method. The method includes depositing a first conductive layer within a trench formed in a dielectric layer, wherein the first conductive layer extends along the sidewalls and bottom surface of the trench. The method includes performing processing operations to transform a portion of the first conductive layer into a buffer layer. The method includes depositing an insulating layer on the buffer layer, wherein the insulating layer is an amorphous composition comprising a mixture of a first metallic material, a second metallic material, and oxygen. The method includes depositing a second conductive layer on the insulating layer.

[0165] As described in detail above, some embodiments described herein provide a capacitor structure. The capacitor structure includes a first electrode layer extending along the sidewalls and bottom surface of a trench. The capacitor structure includes a second electrode layer within the trench. The capacitor structure includes an insulating layer between the first and second electrode layers, wherein the insulating layer extends along the sidewalls and bottom surface of the trench, and wherein the insulating layer has an amorphous structure comprising a mixture of multiple high-k dielectric oxide materials.

[0166] The terms "approximately" and "substantially" can indicate that the value of a given quantity varies within a range of 5% (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and not limiting. The terms "approximately" and "substantially" can also refer to a percentage of a value as interpreted by someone of ordinary skill in the art based on the teachings herein.

[0167] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

[0168] 100: Pixel sensor 102: Photodiode 102a: Miniature photodiode 102b: Large photodiode 104, 104a, 104b: Transmission gate 106, 106a, 106b: Floating diffusion nodes 108: Reset Gate 110: Voltage source 112, 112a, 112b: Overflow gate 114, 114a, 114b: Overflow capacitors 116: Source follower gate 118: Row Select Gate 200, 700, 800, 900: Semiconductor components 202, 710, 810, 824, 910, 924: Component layer 204, 712, 812, 828, 912, 928: Interconnect layers 206:Substrate 208, 826, 926: Integrated circuit elements 210: Dielectric layer 212: Contact Window 214, 214a, 214b, 214c, 214d: Interlayer dielectric layers 216, 216a, 216b, 216c: Etching stop layers 218a, 218b, 218c, 218d, 218e, 220a, 220b, 220c, 220d: Layers 222, 716, 816, 830, 916: Metallized Structure 224, 718, 818, 834, 918: Internal connection structure 226: Trench Capacitor Structure 228: Bottom contact window 230: Top contact window 232: Trench 234: Adhesive layer 236: Bottom Electrode Layer 238: Buffer layer 240: Insulation layer 242: Top electrode layer 244, 246, 248: Cap layer 250, 252: Sidewall gap wall 300, 400, 500: Examples 402: Dielectric shielding layer 404: Photoresist layer 406: Pattern 412: Groove 502: Zirconia layer 504: Alumina layer 600: Elemental composition 602: Depth Profile 604: Atomic percentage 606: Depth 702, 802, 902: Pixel sensor array 704, 804, 904: Black level correction area 706, 806, 906: Joint pad area 708, 808, 908: Sealing ring area 714, 814, 830, 914, 930: Dielectric region 720: Passivation layer 820a, 920a: First semiconductor die 820b: Second semiconductor die 822, 922: Joint interface 836, 838, 936, 938: Joint pads 840, 842, 940, 942: Through holes 1000, 1100: Example process 1010, 1020, 1030, 1040, 1110, 1120, 1130, 1140: Square D1: Dimensions

Claims

1. A method for forming a semiconductor device, comprising: Trenches are formed in the dielectric layer; A first electrode layer of semiconductor layer stacks is deposited in the trench; In the trench, an insulating layer of the semiconductor layer stack is deposited on the first electrode layer; and in the trench, a second electrode layer of the semiconductor layer stack is deposited on the insulating layer, wherein the semiconductor layer stack extends along the sidewalls and bottom surface of the trench, and wherein the insulating layer is an amorphous layer comprising a combination of metal and oxygen, wherein the metal comprises aluminum and zirconium, wherein the top surface of the insulating layer, the bottom surface of the insulating layer, and the intermediate portion of the insulating layer between the top surface and the bottom surface all simultaneously comprise the aluminum, the zirconium, and the oxygen.

2. The method of claim 1, wherein depositing the insulating layer comprises: Performing multiple atomic layer deposition (ALD) cycles to deposit the insulating layer, wherein performing one of the multiple atomic layer deposition cycles includes: depositing zirconium oxide using a first material precursor; and depositing aluminum oxide on the zirconium oxide using a second material precursor.

3. The method as described in claim 2, wherein the deposition thickness of the zirconium oxide is greater than the deposition thickness of the alumina.

4. The method as described in claim 2, wherein the deposition thickness of the zirconium oxide is less than the deposition thickness of the alumina.

5. The method as described in claim 2, wherein the deposition thickness of the zirconium oxide is approximately equal to the deposition thickness of the alumina.

6. The method as described in claim 2, wherein the plurality of atomic layer deposition cycles are performed to deposit alternating zirconium oxide atomic layers and alumina atomic layers.

7. The method of claim 1, wherein the ratio of the concentration of zirconium to the concentration of aluminum in the insulating layer is substantially uniform at different depths of the insulating layer.

8. The method of claim 1, wherein the concentration of zirconium in the insulating layer is greater than the concentration of aluminum in the insulating layer.

9. A method of forming a semiconductor device, comprising: A first conductive layer is deposited in a trench formed in a dielectric layer, wherein the first conductive layer extends along the sidewalls and bottom surface of the trench; Perform a processing operation to transform a portion of the first conductive layer into a buffer layer; deposit an insulating layer on the buffer layer, wherein the insulating layer is an amorphous composition comprising a mixture of zirconium, aluminum, and oxygen, and the top surface, the bottom surface, and the intermediate portion of the insulating layer between the top and bottom surfaces all contain the aluminum, the zirconium, and the oxygen; and deposit a second conductive layer on the insulating layer.

10. A semiconductor element, comprising: The first electrode layer extends along the sidewalls and bottom surface of the trench; The second electrode layer is located in the trench; An insulating layer is provided between the first electrode layer and the second electrode layer, wherein the insulating layer extends along the sidewalls and bottom surface of the trench, and wherein the insulating layer has an amorphous structure, comprises a mixture of zirconium oxide and aluminum oxide, and aluminum, zirconium and oxygen are simultaneously present on the top surface, the bottom surface and the middle portion of the insulating layer between the top surface and the bottom surface.

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