Single-ended sense amplifiers and methods for operating same

Abstract

A bit line is pre-charged to ground. A first and second node of a latch circuit are coupled to ground and a reference voltage, respectively. A DRAM cell is activated, thereby coupling a DRAM cell capacitor to the bit line and generating a read voltage on the bit line. When the DRAM cell is activated, the bit line is isolated from the latch circuit. The first node is decoupled from ground, and then the bit line is coupled to the first node, thereby generating the read voltage on the first node. Next, the second node is decoupled from the reference voltage, and the bit line is isolated from the first node. The latch circuit is activated to amplify the voltage difference between the first and second nodes, resulting in a read data voltage on the first node. The bit line is then recoupled to the first node, applying the read data voltage to the bit line.

Description

Technical Field

[0001] This application claims priority to the following U.S. patent applications filed by Richard S. Roy: Patent Application No. 19 / 002,313, filed December 26, 2024, entitled "Single-Ended Sense Amplifiers And Methods For Operating Same," which is a partial continuation of Patent Application No. 18 / 399,579, filed December 28, 2023, entitled "Dynamic Random Access Memory System Including Single-Ended Sense Amplifiers And Methods For Operating Same"; Provisional Application No. 63 / 685,629, filed August 21, 2024, entitled "Multi-Threaded Dynamic Random Access Memory Systems And Methods Of Operating Same"; and Provisional Application No. 63 / 708,219, filed October 16, 2024, entitled "Single-Ended Sense Amplifier Structures And Methods For Operating Same."

[0002] This invention relates to dynamic random access memory (DRAM) systems. Specifically, this invention relates to a single-ended inductive amplifier for DRAM systems, and a method of operating such a single-ended inductive amplifier. Prior Technology

[0003] DRAM is already used in many system configurations to provide data storage for applications such as machine learning. As these applications become more complex, it becomes increasingly difficult to provide DRAM systems capable of handling all the access requirements of these applications, such as random access bandwidth, latency, power, random access capability, memory capacity and density, and refresh rate. JEDEC standard 238A describes High Bandwidth Memory (HBM3) DRAM, which is coupled to a host computer chip through a distributed interface. HBM3 DRAM utilizes a wide-interface architecture to attempt to achieve high-speed, low-power operation. However, there is still a need for an improved DRAM system that offers increased random access bandwidth, reduced access latency, lower operating / standby power, improved random access capability, improved memory capacity capability, higher memory density, and improved refresh rate. Current HBM architectures focus on expanding the data bandwidth of large data block access to extend the capabilities of existing examples (which result in significant power losses for analog circuitry required to achieve data rates close to 10Gb / sec / pin), and their ability to apply random (or near-random) addressing at high speeds is very limited. Therefore, it would be desirable to have an improved DRAM system that overcomes the aforementioned shortcomings of conventional DRAM systems. Summary of the Invention

[0004] Therefore, this invention focuses on single-ended inductor amplifiers for DRAM systems. Such single-ended inductor amplifiers advantageously reduce the operating voltage, power consumption, and required layout area of ​​DRAM systems.

[0005] According to one embodiment, the present invention includes a method for operating a single-ended inductive amplifier coupled to a bit line of a DRAM lattice array. The method includes pre-charging the bit line to ground, coupling a first internal node of a latch circuit to ground, and coupling a second internal node of the latch circuit to a reference voltage (Vref). A word line voltage is initiated by applying a word line voltage to the gate of a transistor of a DRAM lattice, thereby coupling a lattice capacitor of the DRAM lattice to the bit line, thereby generating a read voltage on the bit line. When the word line voltage is initially initiated, the bit line is isolated from the latch circuit.

[0006] The first internal node of the latch circuit is decoupled from ground, and then the bit line is coupled to the first internal node of the latch circuit, wherein the read voltage generated on the bit line is applied to the first internal node of the latch circuit. The second internal node of the latch circuit is then decoupled from the reference voltage, and the bit line is isolated from the first internal node of the latch circuit.

[0007] The latch circuit is activated, amplifying the difference between the read voltage at the first internal node and the reference voltage at the second internal node, resulting in a read data voltage being stored at the first internal node. The bit line is then recoupled to the first internal node, with the read data voltage at the first internal node applied to the bit line.

[0008] In one embodiment, the latch circuit includes: a first transistor whose source is coupled to a first voltage supply node, whose gate is coupled to the first internal node, and whose drain is coupled to the second internal node; a second transistor whose source is coupled to the first voltage supply node, whose gate is coupled to the second internal node, and whose drain is coupled to the first internal node; a third transistor whose source is coupled to a second voltage supply node, whose gate is coupled to the first internal node, and whose drain is coupled to the second internal node; and a fourth transistor whose source is coupled to the second voltage supply node, whose gate is coupled to the second internal node, and whose drain is coupled to the first internal node. In this embodiment, activating the latch circuit includes increasing the voltage applied to the first voltage supply node from ground to a positive voltmeter voltage. In a variation of this embodiment, the second voltage supply node remains grounded. In another variation, a control voltage applied to the second voltage supply node switches between ground and a negative voltage.

[0009] According to another embodiment, the reference voltage is a positive voltage. In a variation of this embodiment, the reference voltage is a positive voltage less than or equal to 109 mV, less than or equal to 54 mV, or less than or equal to 27 mV. These relatively low reference voltages achieve significant power savings in a single-ended induction amplifier.

[0010] In another embodiment, the reference voltage is grounded.

[0011] According to another embodiment, the method of the present invention includes applying a negative kick voltage to the bit line after coupling the bit line to a first internal node of the latch circuit, but before activating the latch circuit. In different variations of this embodiment, the reference voltage is a positive voltage or ground.

[0012] According to another embodiment, the read data voltage is lower than the conventional Vdd supply voltage (e.g., 1.1 V). In different variations of this embodiment, the read data voltage is a positive voltage less than or equal to 985 mV, a positive voltage less than or equal to 488 mV, or a positive voltage less than or equal to 331 mV.

[0013] In another embodiment, the logic low-order cell voltage of the DRAM bit cell is 0 volts, and the read voltage generated on the bit line has a maximum logic low voltage, which is specified by the 0 volt logic low-order cell voltage plus the positive voltage that couples the bit line to one or more adjacent bit lines when the DRAM bit cell has a logic low-order cell voltage. Furthermore, a reference voltage is selected such that when the first internal node is at the maximum logic low voltage and the second internal node is at the reference voltage, the latch circuit can reliably pull the first internal node to ground.

[0014] In one variation, the difference between the maximum logic low voltage and the reference voltage is equal to a first voltage difference, wherein the logic high cell voltage of the DRAM bit cell corresponds to the read data voltage. The read data voltage is selected such that the minimum logic high voltage of the read voltage generated on the bit line is equal to or greater than the reference voltage plus the first voltage difference when the DRAM bit cell has a logic high cell voltage. When the first internal node is at the minimum logic high voltage and the second internal node is at the reference voltage, the latch circuit can reliably pull the first internal node to the read data voltage.

[0015] According to a second embodiment of the present invention, a single-ended inductive amplifier includes a latching circuit comprising: a first transistor, the source of which is coupled to a first voltage supply node, the gate of which is coupled to a first internal node, and the drain of which is coupled to a second internal node; a second transistor, the source of which is coupled to the first voltage supply node, the gate of which is coupled to the second internal node, and the drain of which is coupled to the first internal node; a third transistor, the source of which is coupled to a second voltage supply node, the gate of which is coupled to the first internal node, and the drain of which is coupled to the second internal node; and a fourth transistor, the source of which is coupled to the second voltage supply node, the gate of which is coupled to the second internal node, and the drain of which is coupled to the first internal node.

[0016] The single-ended inductive amplifier further includes: a first precharge transistor, whose drain is coupled to the first internal node, whose source is coupled to receive a ground supply voltage, and whose gate is coupled to receive a first precharge control signal; a second precharge transistor, whose drain is coupled to the second internal node, whose source is coupled to receive a reference voltage, and whose gate is coupled to receive a second precharge control signal different from the first precharge control signal; and a first isolation transistor, which couples the first internal node to a first bit line, wherein the first bit line is further coupled to a first DRAM cell in a first DRAM array.

[0017] In one embodiment, the second voltage supply node pulls the sources of the third and fourth transistors to ground. In another embodiment, a control voltage applied to one of the second voltage supply nodes switches between ground and a negative voltage.

[0018] In another embodiment, the reference voltage is a positive voltage. In a variation, the reference voltage is a positive voltage less than or equal to 109 mV. In another embodiment, the reference voltage is ground.

[0019] In another embodiment, during read access to the DRAM cell, the control voltage applied to the first voltage supply node switches between ground and 985 mV or lower.

[0020] In another embodiment, the latch circuit, the first precharged crystal, the second precharged crystal, and the isolation crystal are the only circuit elements used to sense, amplify, and latch the read voltage generated on the first bit line.

[0021] In another embodiment, a second isolation transistor couples the first internal node to a second bit line, wherein the second bit line is further coupled to a second DRAM cell in a second DRAM array, wherein the first and second isolation transistors are not simultaneously turned on.

[0022] In another embodiment, the first, second, third and fourth transistors of the latching circuit each include a superlattice channel extending between their source and drain regions.

[0023] In another embodiment, a switched-skip capacitor is coupled to the first bit line. In one variation, during a read access to the first DRAM cell, the switched-skip capacitor is activated to kick down the read voltage on the first bit line. In another variation, the read voltage on the first bit line is negative if the first DRAM cell stores a logic low data value, and positive if the first DRAM cell stores a logic high data value. In yet another variation, the reference voltage is ground, and the first DRAM cell has a negative bit voltage when storing a logic low data value.

[0024] Please refer to the following description and accompanying drawings for a more comprehensive understanding of the present invention. Simple Explanation of the Diagram

[0025] Figure 1 illustrates a multithreaded dynamic random access memory (MTDRAM) system according to an embodiment of the present invention.

[0026] Figure 2 is a top view of the MTDRAM chip in Figure 1, illustrating the layout of 2048 MTDRAM cells according to an embodiment of the present invention.

[0027] Figure 3 is a top view of two horizontally adjacent MTDRAM cells on an MTDRAM chip in Figure 2, according to an embodiment of the present invention, including the through-silicon vias (TSVs) associated with these cells.

[0028] Figure 4 is a side view of two adjacent MTDRAM unit stacks according to an embodiment of the present invention, including the MTDRAM unit cell of Figure 3.

[0029] Figure 5 is a top view of a stack of 2048 units within the MTDRAM system of Figure 1, according to an embodiment of the present invention.

[0030] Figure 6 is a block diagram of an MTDRAM cell according to an embodiment of the present invention.

[0031] Figure 7 illustrates, according to an embodiment of the present invention, the eight rows preceding the MTDRAM subarray included in the topmost MTDRAM stripe of Figure 6, along with the corresponding master word line drivers, corresponding sub-word line drivers, and corresponding primary induction amplifier sub-circuit pairs.

[0032] Figure 8 illustrates a method by which the primary induction amplifier driver circuit controls access to the single-ended induction amplifier within the primary induction amplifier sub-circuit according to an embodiment of the present invention.

[0033] Figure 9 is a block diagram illustrating the connections between the bit lines, single-ended inductive amplifiers and corresponding global bit lines within the MTDRAM unit cell in Figure 6, according to an embodiment of the present invention.

[0034] Figure 10 illustrates the MTDRAM subarray in Figure 7 and the Y decoder logic for selectively routing data from the primary induction amplifier subcircuit to a set of global bit lines, according to an embodiment of the present invention.

[0035] Figure 11A is a waveform diagram illustrating the signals involved in reading and accessing the MTDRAM subarray in Figure 7 according to an embodiment of the present invention.

[0036] Figure 11B is a waveform diagram illustrating the signals involved in writing and accessing the MTDRAM subarray in Figure 7 according to an embodiment of the present invention.

[0037] Figure 12 illustrates the data channel of the MTDRAM cell in Figure 6 according to an embodiment of the present invention.

[0038] Figure 13 illustrates, according to an embodiment of the present invention, a method for routing data on a global bit line associated with the first data channel of an MTDRAM cell to a multiplexer segment.

[0039] Figure 14 illustrates, according to an embodiment of the present invention, the distribution of global bit lines of Figure 10 to a multiplexer segment, and the manner in which the multiplexer segment routes data on the global bit lines to global input / output (I / O) lines.

[0040] Figure 15 is a schematic diagram of a two-stage inductive amplifier according to an embodiment of the present invention. The amplifier transmits the read value from the global input / output line in Figure 14 to the silicon via of the first data channel of the MTDRAM cell, and transmits the write data value from the first data channel of the MTDRAM cell to the global input / output line in Figure 14.

[0041] Figure 16 is a circuit diagram of the even-number readout secondary inductive amplifier circuit of the secondary inductive amplifier in Figure 15 according to an embodiment of the present invention, which is used to receive and transmit the readout data value received on the even-number global input / output line.

[0042] Figure 17 is a circuit diagram of the odd-reading second-stage inductive amplifier circuit of the second-stage inductive amplifier in Figure 15 according to an embodiment of the present invention, which is used to receive and transmit read data values ​​received on the odd-number global input / output lines.

[0043] Figure 18 is a waveform diagram illustrating the operation of the even-number readout secondary inductive amplifier circuit in Figure 15 and the odd-number readout secondary inductive amplifier circuit in Figure 16, according to an embodiment of the present invention.

[0044] Figure 19 is a circuit diagram of the even-numbered write secondary induction amplifier circuit of the secondary induction amplifier in Figure 15 according to an embodiment of the present invention, which is used to receive and transmit the write data value received on the even-numbered data line of the first data channel.

[0045] Figure 20 is a circuit diagram of the odd-number write secondary induction amplifier circuit of the secondary induction amplifier in Figure 15 according to an embodiment of the present invention, which is used to receive and transmit the write data value received on the odd-number data line of the first data channel.

[0046] Figure 21 is a waveform diagram illustrating the operation of the even-number writing secondary inductive amplifier circuit in Figure 19 and the odd-number writing secondary inductive amplifier circuit in Figure 20, according to an embodiment of the present invention.

[0047] Figure 22 is a block diagram illustrating the instruction format for accessing MTDRAM unit stacks according to an embodiment of the present invention.

[0048] Figure 23 illustrates a master word line decoder circuit associated with the MTDRAM stripe in an MTDRAM cell, according to an embodiment of the present invention.

[0049] Figure 24 illustrates a subarray decoder circuit associated with MTDRAM stripes in an MTDRAM cell, according to an embodiment of the present invention.

[0050] Figure 25 illustrates the TSV layout required for a stack of MTDRAM units with four MTDRAM unit cells, according to an embodiment of the present invention.

[0051] Figure 26 illustrates a circuit diagram of a single-ended induction amplifier according to an alternative embodiment of the primary induction amplifier circuit of the present invention.

[0052] Figure 27 illustrates a signal waveform diagram associated with the read access of a bit cell coupled to the single-ended inductive amplifier in Figure 26 according to an embodiment of the present invention.

[0053] Figure 28 is a signal waveform diagram illustrating the read access associated with a bit cell coupled to a single-ended inductive amplifier including an MST transistor, according to a first alternative embodiment of the present invention.

[0054] Figure 29 illustrates a circuit diagram of a single-ended MST inductive amplifier including kick capacitors according to a second alternative embodiment of the present invention.

[0055] Figure 30 is a waveform diagram illustrating the signal associated with the read access of a bit cell coupled to the single-ended inductive amplifier in Figure 29, according to a second alternative embodiment of the present invention.

[0056] Figure 31 illustrates a circuit diagram of a single-ended MST sensing amplifier according to a third alternative embodiment of the present invention, including a grounded reference voltage and a negative logic "0" bit voltage.

[0057] Figure 32 is a signal waveform diagram illustrating the read access associated with a bit cell coupled to the single-ended inductive amplifier in Figure 31, according to a third alternative embodiment of the present invention.

[0058] Figure 33 illustrates a circuit diagram of a single-ended MST sensing amplifier according to a fourth alternative embodiment of the present invention, including a ground reference voltage, a negative logic "0" bit voltage, and a jump capacitor.

[0059] Figure 34 is a signal waveform diagram illustrating the read access associated with a bit cell coupled to the single-ended inductive amplifier in Figure 33, according to a fourth alternative embodiment of the present invention. Implementation

[0060] Figure 1 illustrates a multithreaded dynamic random access memory (MTDRAM) processor system 100 according to one embodiment of the present invention. The MTDRAM processor system 100 includes four MTDRAM chips 101-104 and an ASIC controller chip 105, which are stacked as shown. Each MTDRAM chip 101-104 includes a corresponding plurality of MTDRAM cells 1010-1040 and a plurality of through-silicon vias (TSVs) (not shown in Figure 1), which will be described in detail below. The TSVs of the MTDRAM chip 101 are connected to the processor array 1050 of the ASIC controller chip 105 through a first plurality of TSV connectors (TSVCs) 111. The TSVs of the MTDRAM chip 101 are also connected to the TSVs of the MTDRAM chip 102 using a second plurality of TSVCs 112. Similarly, the silicon vias of MTDRAM chip 102 are connected to the silicon vias of MTDRAM chip 103 using a third plurality of TSVCs 113, and the silicon vias of MTDRAM chip 103 are connected to the silicon vias of MTDRAM chip 104 using a fourth plurality of TSVCs 114. In this manner, MTDRAM chips 101 to 104 are connected in a stacked configuration.

[0061] In the first embodiment described herein, each MTDRAM chip 101-104 comprises 2048 individual MTDRAM cells, each cell having 18Mb of storage capacity, thus each MTDRAM chip 101-104 has 32Gb of storage capacity. As will be understood from the description below, in other embodiments, the number of MTDRAM cells can be adjusted to include additional MTDRAM cells of other capacities. Figure 1 also illustrates the X, Y, and Z axes, which are consistently used throughout the diagram to more clearly define the MTDRAM system 100.

[0062] Figure 2 is a top view of the MTDRAM chip 101, showing the layout of the 2048 MTDRAM cells UC1,1 to UC1,2048 (cells UC1,1, UC1,8, UC1,16, UC1,24, UC1,32, UC1,33, UC1,64, UC1,225, UC1,256, UC1,481, UC1,512, UC1,993, UC1,1024, UC1,2017, and UC1,2048 are specifically marked to illustrate the numbering convention for MTDRAM cells). The 2048 MTDRAM cells UC1,1 to UC1,2048 are organized into 32 columns and 64 rows, with each row of MTDRAM cells extending along the X-axis width of the MTDRAM chip 101, as shown, and each column of MTDRAM cells extending along the Y-axis height of the MTDRAM chip 101.

[0063] As shown in the figure, the main TSV regions TSVR1,0 to TSVR1,15 are located in the center between the unit grid columns. Specifically, the main TSV region TSVR1,0 is located between the first pair of MTDRAM unit grid columns (i.e., between the first and second MTDRAM unit grid columns). The main TSV region TSVR1,1 is located between the second pair of MTDRAM unit grid columns (i.e., between the third and fourth MTDRAM unit grid columns). This pattern is repeated throughout the entire MTDRAM wafer 101. Each main TSV region TSVR1,0 to TSVR1,15 extends along the Y-axis height of the MTDRAM wafer 101.

[0064] As detailed below, each MTDRAM cell UC1,1 to UC1,2048 has a set of dedicated TSVs in adjacent areas within the primary TSV regions TSVR1,0 to TSVR1,15. These dedicated TSVs are used to transmit data, address, and control information between the corresponding MTDRAM cells. Although the primary TSV regions in Figure 2 are adjacent to the cells, it is understood that other TSVs (not shown in Figure 2) may extend through other locations within the cells (including unused areas of those cells that do not contain the circuitry required for the MTDRAM array structure). The silicon vias (and other TSVs not located within the primary TSV regions TSVR1,0 to TSVR1,15) contained in the primary TSV regions TSVR1,0 to TSVR1,15 are coupled to TSVCs 111 and 112 as shown in Figure 1.

[0065] Figure 3 is a top view according to an embodiment of the present invention, illustrating the horizontally adjacent MTDRAM cells UC1,1 and UC1,2 in Figure 2 and the corresponding portions of the main TSV region TSVR1,0 located between these cells.

[0066] Each MTDRAM cell UC1,1 to UC1,2048 comprises 16 1.125 Mb MTDRAM stripes, each stripe extending vertically along the height (Y-axis) of the cell. The 16 MTDRAM stripes in each cell are arranged parallel to the Y-axis. As shown in Figure 3, MTDRAM cell UC1,1 comprises 16 MTDRAM stripes S(1,1)0 to S(1,1)15, and MTDRAM cell UC1,2 comprises 16 MTDRAM stripes S(1,2)0 to S(1,2)15.

[0067] Each MTDRAM cell UC1,1 to UC1,2048 further includes a multiplexer and a first- and second-stage induction amplifier circuit, located between the 16 MTDRAM stripes of that cell and the corresponding primary TSV region. For example, cell UC1,1 includes a multiplexer MUX1,1 and a second-stage induction amplifier circuit SSA1,1, located between MTDRAM stripes S(1,1)0 to S(1,1)15 and the primary TSV region TSVR1,0. Similarly, cell UC1,2 includes a multiplexer MUX1,2 and a second-stage induction amplifier circuit SSA1,2, located between MTDRAM stripes S(1,2)0 to S(1,2)15 and the primary TSV region TSVR1,0.

[0068] Each of the MTDRAM cells UC1,1 to UC1,2048 further includes a set of dedicated TSVs within its respective primary TSV region. For example, cell UC1,1 includes a dedicated silicon via group TSV1,1 within its respective primary TSV region TSVR1,0, while cell UC1,2 includes a dedicated silicon via group TSV1,2 within its respective primary TSV region TSVR1,0.

[0069] As shown in Figure 3, horizontally adjacent MTDRAM cell grids UC1,1 and UC1,2 are arranged as mirror images of each other on the MTDRAM wafer 101. In this embodiment, each pair of horizontally adjacent MTDRAM cell grids separated by a primary TSV region has the same configuration as MTDRAM cell grids UC1,1 and UC1,2.

[0070] Although the unit cells UC1,1 to UC1,2048 have the same logical structure in the described embodiment, it will be understood that in other embodiments, different unit cells on the MTDRAM chip 101 may have different logical structures. For example, in other embodiments, different unit cells may have different numbers of MTDRAM stripes, different numbers of MTDRAM bit cells, different data word widths, different numbers of data channels, etc., which will be obvious to those skilled in the art.

[0071] The following details the configuration and operation of the MTDRAM stripes S(1,1)0~S(1,1)15, the multiplexer MUX1,1, and the secondary induction amplifier circuit SSA1,1 (as well as the signals transmitted on the corresponding silicon via groups TSV1,1).

[0072] MTDRAM chips 102, 103, and 104 have the same layout as MTDRAM chip 101 in Figure 2, wherein the 2048 cells UC1,1 to UC1,2048 of MTDRAM chip 101 are renumbered as cells UC2,1 to UC2,2048 of MTDRAM chip 102, cells UC3,1 to UC3,2048 of MTDRAM chip 103, and cells UC4,1 to UC4,2048 of MTDRAM chip 104. Similarly, the main TSV regions TSVR1,0 to TSVR1,15 of MTDRAM chip 101 are renumbered as the main TSV regions TSVR2,0 to TSVR2,15 of MTDRAM chip 102, the main TSV regions TSVR3,0 to TSVR3,15 of MTDRAM chip 103, and the main TSV regions TSVR4,0 to TSVR4,15 of MTDRAM chip 104. The unit cells UC1,x, UC2,x, UC3,x, and UC4,x (x = 1 to 2048) of the MTDRAM wafers 101 to 104 are vertically aligned along the Z-axis. Similarly, the main TSV regions TSVrey,0 to TSVrey,15 (y = 1 to 4) are vertically aligned along the Z-axis. This configuration allows the vertically aligned MTDRAM unit cells to be connected to form MTDRAM unit stacks, as shown in Figure 4.

[0073] Figure 4 illustrates a side view of two adjacent MTDRAM unit stacks US1 and US2 according to an embodiment of the present invention. Unit stack US1 includes four vertically aligned MTDRAM unit cells UC1,1, UC2,1, UC3,1 and UC4,1 from MTDRAM chips 101, 102, 103 and 104. Unit cells UC1,1, UC2,1, UC3,1 and UC4,1 are connected to each other (and to processor block 1051) through vias in corresponding silicon via groups TSV1,1, TSV2,1, TSV3,1 and TSV4,1 and TSVC 111~114 (Figure 1). In detail, the unit stack US1 includes an instruction bus INST1 and two independent 36-bit data buses DATA_A1 and DATA_B1, which are configured using silicon vias and TSVC 111~114 in TSV regions TSV1,1, TSV2,1, TSV3,1 and TSV4,1.

[0074] The 16 stripes within each unit cell UCx,1 are labeled as stripes S(x,1)0 to S(x,1)15, where x = 1 to 4. The multiplexer within each unit cell UCx,1 is labeled MUXx,1, where x = 1 to 4, and the secondary induction amplifier circuit within each unit cell UCx,1 is labeled SSAx,1, where x = 1 to 4.

[0075] Similarly, the independent unit stack US2 includes four vertically aligned MTDRAM unit cells UC1,2,UC2,2,UC3,2 and UC4,2 in MTDRAM chips 101,102,103 and 104. Unit cells UC1,2,UC2,2,UC3,2 and UC4,2 are interconnected via vias in the corresponding via groups TSV1,2, TSV2,2, TSV3,2 and TSV4,2 and TSVC 111~114 (Figure 2) (and the corresponding processor block 1052). Specifically, the unit stack US2 includes an instruction bus INST2 and two independent 36-bit data buses DATA_A2 and DATA_B2, which are configured using vias in the TSV regions TSV1,2, TSV2,2, TSV3,2 and TSV4,2 and TSVC 111~114.

[0076] The 16 stripes within each unit cell UCx,2 are labeled as stripes S(x,2)0 to S(x,2)15, where x = 1 to 4. The multiplexer within each unit cell UCx,2 is labeled MUXx,2, where x = 1 to 4, and the secondary inductive amplifier within each unit cell UCx,2 is labeled SSAx,2, where x = 1 to 4.

[0077] Although Figure 4 illustrates two unit stacks, US1 and US2, it is understood that the unit cells of MTDRAM chips 101–104 constitute a total of 2048 independent unit stacks, each of which is identical to unit stack US1 (or US2). Specifically, each unit stack USx includes four unit cells UC1,x, UC2,x, UC3,x, and UC4,x (x = 1 to 2048) of MTDRAM chips 101, 102, 103, and 104. Figure 5 is a top view of 2048 unit stacks US1 to US2048 of the MTDRAM system 100 according to this embodiment (where unit stacks US1,1, US1,8, US1,16, US1,24, US1,32, US1,33, US1,64, US1,225, US1,256, US1,481, US1,512, US1,993, US1,1024, US1,2017 and US1,2048 are specially marked to illustrate the numbering system).

[0078] The following details the MTDRAM cell UC1,1. It is understood that each of the other cells in the unit stack US1, UC2,1, UC3,1, and UC4,1, can be accessed in the same manner as cell UC1,1, responding to instructions provided on the instruction bus INST1. As detailed below, each of the four cells in the unit stack US1 can be individually addressed via instructions provided on the instruction bus INST1.

[0079] As detailed below, processor array 1050 can simultaneously access up to two nearly random address locations within each unit stack US1~US2048. Processor array 1050 comprises multiple processor blocks 1051~1052048, each coupled to a corresponding unit stack US1~US2048. The following access modes can be implemented within unit stack US1. Generally, instructions transmitted on instruction bus INST1 can simultaneously access up to two data values ​​in the same MTDRAM stripe of unit stack US1 (subject to access limitations imposed by the MTDRAM architecture, detailed below). Data is routed out of / into unit stack US1 via two independent 36-bit data channels DATA_A1 and DATA_B1. The following access modes are generally permitted.

[0080] Processor block 1051 can access a data value from any strip S(1,1)0~S(1,1)15, S(2,1)0~S(2,1)15, S(3,1)0~S(3,1)15, or S(4,1)0~S(4,1)15 in any cell UC1,1, UC2,1, UC3,1, or UC4,1 of the unit stack US1. For example, processor block 1051 can access any data value in the MTDRAM strip S(1,1)14 of cell UC1,1 in response to a single instruction on instruction bus INST1 (subject to access restrictions imposed by the MTDRAM architecture).

[0081] Processor block 1051 can also simultaneously access two data values ​​within any stripe in any unit cell of unit stack US1. As detailed below, the first half of each MTDRAM stripe is designated to store data associated with the first data channel DATA_A1, and the second half of each MTDRAM stripe is designated to store data associated with the second data channel DATA_B1. Processor block 1051 can simultaneously access the first data value of the first half of MTDRAM stripe S(1,1)14 on the first data channel DATA_A1, and the second data value of the second half of MTDRAM stripe S(1,1)14 on the second data channel DATA_B1, in response to a single instruction on instruction bus INST1 (subject to access restrictions imposed by the MTDRAM architecture). The specific addressing scheme used for accessing unit stack US1 is detailed below.

[0082] Please note that each unit stack US1~US2048 can be accessed simultaneously and independently in the manner described above for unit stack US1. Therefore, the processor array 1050 has sufficient address bandwidth to simultaneously access data from up to 4096 almost random address locations within the unit stacks US1~US2048.

[0083] As mentioned above, the architecture of MTDRAM cells imposes certain access restrictions. These cell architectures (and restrictions) are detailed below.

[0084] Figure 6 illustrates an MTDRAM cell UC1,1 according to an embodiment of the present invention. Although Figure 6 specifically illustrates the MTDRAM stripes S(1,1)0, S(1,1)1, and S(1,1)15 of cell UC1,1, it will be understood that the remaining MTDRAM stripes S(1,1)2 to S(1,1)14 of cell UC1,1 have the same configuration. Note that the layout of the MTDRAM stripes in Figure 6 is rotated 90 degrees clockwise relative to the orientation shown in Figures 2 and 3. This rotation is indicated by the XYZ axis markings in these figures.

[0085] Each MTDRAM stripe S(1,1)x contains eight corresponding subarrays SUBAx,0 to SUBAx,7 (where x = 0 to 15, corresponding to stripes S(1,1)0 to S(1,0)15 respectively). Each MTDRAM stripe S(1,1)0 to S(1,1)15 extends along the Y-axis through the height of unit cell UC1,1. The subarrays of MTDRAM stripes S(1,1)0 to S(1,1)15 are arranged in eight subarray columns CoSA0 to CoSA7, which extend along the X-axis, as shown in the figure. Each subarray column CoSAy includes subarrays SUBA0,y to SUBA15,y (where y = 0 to 7, corresponding to subarray columns CoSA0 to CoSA7 respectively). As detailed below, in the embodiment described, subarrays CoSA0 to CoSA3 are dedicated to the data channel DATA_A1 of the unit stack US1, while subarrays CoSA4 to CoSA7 are dedicated to the data channel DATA_B1 of the unit stack US1. It is worth noting that in other embodiments, subarrays CoSA0 to CoSA7 may be dedicated to data channels DATA_A1 and DATA_B1 in different ways.

[0086] Each MTDRAM stripe S(1,1)x further includes a central main word line driver circuit MWDx (where x = 0 to 15, corresponding to stripes S(1,1)0 to S(1,1)15, respectively). As detailed below, each main word line driver circuit is configured to drive the addressed main word line in the corresponding stripe.

[0087] Each MTDRAM stripe S(1,1)x further includes a corresponding pair of primary sense amplifier circuits PSAx and PSA(x+1) (where x = 0 to 15). For example, MTDRAM stripe S(1,1)0 includes primary sense amplifier circuits PSA0 and PSA1, and each primary sense amplifier circuit PSAx is further subdivided into eight corresponding primary sense amplifier sub-circuits PSAx,0 to PSAx,7 (where x = 0 to 15, corresponding to stripes S(1,1)0 to S(1,1)15 respectively). For example, primary sense amplifier circuit PSA1 is subdivided into eight corresponding primary sense amplifier sub-circuits PSA1,0 to PSA1,7. As shown in the figure, each primary sense amplifier sub-circuit is coupled to one (or two) adjacent MTDRAM subarrays. For example, the primary sense amplifier sub-circuits PSA0,0 to PSA0,7 of primary sense amplifier circuit PSA0 are coupled to adjacent MTDRAM subarrays SUBA0,0 to SUBA0,7 respectively. Similarly, the primary induction amplifier sub-circuits PSA1,0 to PSA1,7 of the primary induction amplifier circuit PSA1 are coupled to the adjacent MTDRAM sub-arrays SUBA0,0 to SUBA0,7 and SUBA1,0 to SUBA1,7, respectively.

[0088] Vertically adjacent subarrays (along the X-axis) share a primary induction amplifier subcircuit. For example, accessing subarray SUBA0,0 requires activating primary induction amplifier subcircuits PSA0,0 and PSA1,0. Similarly, accessing vertically adjacent subarray SUBA1,0 requires activating primary induction amplifier subcircuits PSA1,0 and PSA2,0. Therefore, subarrays SUBA0,0 and SUBA1,0 "share" primary induction amplifier subcircuit PSA1,0. In the described embodiment, the time required to cycle (reset) each primary induction amplifier subcircuit after each activation (i.e., row cycle time) is approximately 32 nanoseconds (ns). Therefore, after accessing subarray SUBA0,0, subarray SUBA0,0 and / or subarray SUBA1,0 cannot be accessed again within 32 nanoseconds (i.e., until the shared primary induction amplifier subcircuit PSA1,0 has been reset). This is a limitation to achieving fully random access within unit cell UC1,1. Although the listed row cycle time is approximately 32 nanoseconds, based on relevant circuit tests, it is understood that the row cycle time may be even shorter.

[0089] Each primary induction amplifier subcircuit (e.g., PSA0,0) includes a plurality of (288) single-ended induction amplifiers and corresponding primary induction amplifier driver circuits (e.g., PSAD0,0), which are described in detail below with reference to Figures 7-8. Each primary induction amplifier driver circuit generates a signal to control the plurality of single-ended induction amplifiers in the corresponding primary induction amplifier subcircuit.

[0090] Each primary induction amplifier circuit PSA0~PSA16 also includes a corresponding central region PSAR0~PSAR16. While in the described embodiment, the primary induction amplifier driver circuit (e.g., PSAD0,0) is located within the corresponding primary induction amplifier sub-circuit (e.g., PSA0,0), in other embodiments, it is understood that some or all of these primary induction amplifier driver circuits may be located within the central region PSAR0~PSAR16. In an alternative embodiment, the primary induction amplifier driver circuit is located on the ASIC controller chip 105, and vias transmit the required control signals from the primary induction amplifier driver circuit on the ASIC controller chip 105 to the primary induction amplifier sub-circuits PSA0,0 to PSA16,7. However, it is understood that this embodiment does not require more vias within the unit cell UC1,1.

[0091] As described above in conjunction with Figures 3-4, the MTDRAM unit cell UC1,1 further includes a multiplexer MUX1,1 and a secondary induction amplifier circuit SSA1,1. The multiplexer MUX1,1 includes a first multiplexer circuit MUX(1,1)A associated with the dedicated subarray columns CoSA0~CoSA3 of the data channel DATA_A1, and a second multiplexer circuit MUX(1,1)B associated with the dedicated subarray columns CoSA4~CoSA7 of the data channel DATA_B1.

[0092] The secondary inductive amplifier circuit SSA1,1 includes a 72-bit first secondary inductive amplifier segment SSA(1,1)A, which is coupled to a first multiplexer circuit MUX(1,1)A and dedicated to the data channel DATA_A1. The secondary inductive amplifier circuit SSA1,1 further includes a 72-bit second secondary inductive amplifier segment SSA(1,1)B, which is coupled to a second multiplexer circuit MUX(1,1)B and dedicated to the data channel DATA_B1. The secondary inductive amplifier circuit SSA1,1 further includes a centrally located secondary inductive amplifier driver circuit SSAD1,1, which generates signals for controlling the secondary inductive amplifier segments SSA(1,1)A and SSA(1,1)B. The operation and control of the multiplexer MUX1,1 and the secondary inductive amplifier circuit SSA1,1 are described in detail below.

[0093] Figure 7 illustrates the first 8 rows of the subarray SUBA0,0, the corresponding main character line driver MWD (included in the main character line driver circuit MWD0), and the corresponding primary induction amplifier subcircuits PSA0,0 and PSA1,0.

[0094] In the embodiments described herein, each MTDRAM subarray comprises 256 rows and 576 columns of MTDRAM bit cells. Although other numbers of rows and columns are possible in other embodiments, the number of rows and columns chosen here provides advantages for the configuration of unit cells UC1,1, as will be highlighted in the description below.

[0095] As shown in Figure 7, the first eight rows of the subarray SUBA0,0 include one main word line MWL0 and eight associated sub-word lines SWL0,0 to SWL7,0. Each sub-word line SWL0,0 to SWL7,0 is coupled to a corresponding row of 576 corresponding MTDRAM bit cells within the subarray SUBA0,0. For example, sub-word line SWL0,0 is coupled to MTDRAM bit cells bc0,0 to bc0,575, as shown in the figure. Bit cell bc0,0 is illustrated with the configuration of the corresponding bit cell transmission gate transistor G0 and bit cell capacitor C0. In this embodiment, all bit cells have the same structure.

[0096] The 576 data bits associated with each sub-character line correspond to eight 72-bit values. In various embodiments, these 72-bit values ​​may include: eight 8-bit data values ​​and an 8-bit error correction code (ECC) value, eight 8-bit data values ​​and an 8-bit packet header value, or two separate 36-bit data values.

[0097] Sub-word lines SWL0,0 to SWL7,0 are selectively driven by sub-word line driver circuits SWD0,0 to SWD7,0. For access to subarray SUBA0,0, at most one of the eight sub-word line driver circuits SWD0,0 to SWD7,0 is activated. Each of the sub-word line driver circuits SWD0,0 to SWD7,0 is located at the center of subarray SUBA0,0 (along the Y-axis), and the sub-word line driver circuits SWD0,0 to SWD7,0 are arranged vertically in a column (along the X-axis), as shown in Figure 7.

[0098] Each of the sub-word line driver circuits SWD0,0 to SWD7,0 is coupled to receive the signal on the corresponding main word line MWL0. In order to access data associated with one of the sub-word lines SWL0,0 to SWL7,0, the main word line MWL0, along with the corresponding sub-word line driver circuit associated with the accessed sub-word line, is activated.

[0099] Each of the sub-word line driver circuits SWD0,0 to SWD7,0 is also coupled to receive the subarray enable signal EN_SUBA0,0, which is applied to each sub-word line driver circuit within the subarray SUBA0,0. The sub-word line driver circuits SWD0,0 to SWD7,0 are further coupled to receive sub-word line address signals SWLA[0] to SWLA[7], respectively. Each sub-word line driver circuit SWDx,0 (x=0 to 7) is configured to activate the sub-word line voltage on the corresponding sub-word line SWLx,0 in response to the received master word line signal MWL0, the activated sub-word line address signal SWLA[x], and the activated subarray enable signal EN_SUBA0,0. A particular mode of operation of the sub-character line drive circuits SWD0,0 to SWD7,0 is described in detail in commonly owned U.S. Patent Application No. 18 / 399,579, the entire contents of which are incorporated herein by reference.

[0100] The circuitry associated with the first 8 rows of subarray SUBA0,0 is repeated 32 times along the X-axis, resulting in a subarray SUBA0,0 comprising 32 main word lines, 256 sub-word line drivers, and 256 sub-word lines. Therefore, each main word line is coupled to a corresponding set of 8 sub-word line drivers (similar to sub-word line drivers SWD0,0 to SWD7,0). Each set of 8 sub-word line drivers is coupled to receive 8 corresponding sub-word line address signals SWLA[0] to SWLA[7] (in the same order as shown in Figure 7). Each of the 256 sub-word line drivers in subarray SUBA0,0 is further coupled to receive the same subarray enable signal EN_SUBA0,0. As detailed below, each subarray in the unit stack is independently enabled by the corresponding subarray enable signal.

[0101] Each of the 32 main word lines associated with subarray SUBA0,0 extends along the Y-axis to each subarray contained in the same stripe S(1,1)0 (i.e., each main word line extends along the Y-axis height of unit cell UC1,1). For example, main word line MWL0 extends to each subarray SUBA0,1 to SUBA0,7 of MTDRAM stripe S(1,1)0. In the embodiment described herein, access to unit cell UC1,1 results in the activation of a single one of the 512 main word lines within that unit cell. As detailed below, the activated main word line is specified by the 12-bit main word line address value MWL[11:0] and the 16-bit stripe address value STRIP[15:0] on instruction bus INST1.

[0102] In the embodiment described herein, the subarrays SUBAx,0 to SUBAx,3 (x=0 to 15) to the left of the centrally located main word line driver circuits MWD0~MWD15 (FIG. 6) are coupled to receive the first sub-word line address value SWLA[7:0] associated with the first data channel DATA_A1. The subarrays SUBAx,4 to SUBAx,7 (x=0 to 15) to the right of the centrally located main word line driver circuits MWD0~MWD15 (FIG. 6) are coupled to receive the second sub-word line address value SWLB[7:0] associated with the second data channel DATA_B1.

[0103] Therefore, to access cell UC1,1, a single master word line (e.g., MWL0) is initiated within a stripe (e.g., stripe S(1,1)0), a first sub-word line (defined by SWLA[7:0]) associated with the initiated master word line is initiated within the left subarray (e.g., SUBA0,0) within the selected stripe, and a second sub-word line (defined by SWLB[7:0]) associated with the initiated master word line is initiated within the right subarray (e.g., SUBA4,0) within the selected stripe, wherein the first and second sub-word lines may have different (or the same) addresses. Providing independent sub-word line address values ​​SWLA[7:0] and SWLB[7:0] provides flexibility for addressing cell UC1,1. In an alternative embodiment, a single sub-word line address value can be used to access cell UC1,1, thereby reducing the number of vias required in instruction bus INST1 by 8.

[0104] Using a single main word line address value and a single stripe address value simultaneously for two data channels DATA_A1 and DATA_B1 can limit random address access within the unit stack US1. In an alternative embodiment, providing separate main word line addresses (and / or separate stripe addresses) for the left and right subarrays of the unit stack reduces or eliminates the aforementioned random access limitation. It will be understood that in such an embodiment, additional vias are required to route the separate main word line addresses (and / or separate stripe addresses).

[0105] As described above, accessing an MTDRAM stripe requires activating one main word line that extends along the entire length of the MTDRAM stripe. Before subsequent accesses to different subarrays (CoSAs) within the same stripe, the previously activated main word line must be precharged to its initial (deactivated) state. This main word line precharge operation limits the access rate to the MTDRAM stripe. According to one embodiment, the main word line precharge operation requires 4 ns (while accesses may occur at a rate of 1 GHz or a period of 1 ns). In this case, once a stripe is accessed, a new address within the same stripe cannot be accessed within 4 ns. The required main word line precharge operation further limits the random access of a unit stack US1.

[0106] Each column of bits in subarray SUBA,0 is coupled to a corresponding bit line. Specifically, all 256 bits in the same column as bit cell bc0,x are coupled to bit line bl0,x (where x = 0 to 575). Bit line bl0,y (where y represents an even value between 0 and 575) is coupled to the corresponding single-ended induction amplifier in the primary induction amplifier subcircuit PSA,0. Specifically, in the primary induction amplifier subcircuit PSA,0, the even-numbered bit lines bl0,0, bl0,2, ..., bl0,574 of subarray SUBA,0 are coupled to the corresponding single-ended induction amplifiers SA0,0, SA0,2, ..., SA0,574, respectively.

[0107] The bit lines bl0,Z (where z represents an odd value between 0 and 575) are coupled to the corresponding single-ended inductors in the primary inductor amplifier subcircuit PSA1,0. Specifically, in the primary inductor amplifier subcircuit PSA0,1, bl0,3, ..., bl0,575 of the subarray SUBA0,0 are coupled to the corresponding single-ended inductors SA0,1, SA0,3, ..., SA0,575, respectively.

[0108] In the primary inductive amplifier subcircuit PSA1,0, the odd-numbered bit lines bl1,1,bl0,3,...,bl1,575 of the vertically adjacent subarrays SUBA1,0 are also coupled to the corresponding single-ended inductive amplifiers SA0,1,SA0,3,...SA0,575 (thus allowing subarrays SUBA0,0 and SUBA1,0 to share the primary inductive amplifier subcircuit PSA1,0).

[0109] As shown in Figure 7, the primary inductive amplifier driver circuits PSAD0,0 and PSAD1,0 are centered within the primary inductive amplifier sub-circuits PSA0,0 and PSA1,0, respectively. These driver circuits PSAD0,0 and PSAD1,0 are vertically aligned along the X-axis with the sub-word line driver circuits SWD0,0 to SWD7,0, which advantageously simplifies the layout of the associated subarray column CoSA0. The primary inductive amplifier driver circuits PSAD0,0 and PSAD1,0 are coupled to receive the subarray enable signal EN_SUBA0,0, which is activated when subarray SUBA0,0 is accessed. The primary inductive amplifier driver circuit PSAD1,0 is also coupled to receive the subarray enable signal EN_SUBA1,0, which is activated when subarray SUBA1,0 is accessed.

[0110] Figure 8 illustrates, according to an embodiment of the present invention, the access method of the primary inductor amplifier driver circuit PSAD1,0 controlling the single-ended inductors SA0,1 and SA0,3 within the primary inductor amplifier sub-circuit PSA1,0. It is understood that the control signals generated by the primary inductor amplifier driver circuit PSAD1,0 are provided in parallel to all the single-ended inductors of the primary inductor amplifier sub-circuit PSA1,0. It should also be understood that, in alternative embodiments of the present invention, the single-ended inductors SA0,1 and SA0,3 (and any other single-ended inductors contained in unit cell UC1,1) can be replaced by any of the single-ended inductors described below in conjunction with Figures 26 to 32.

[0111] The single-ended induction amplifier SA0,1 includes p-channel transistors P1~P2, n-channel transistors N1~N2, N11~N12 and N20, internal induction amplifier nodes INT0 and INT0#, thick oxide high-voltage NMOS transistors 801 and 803, and bit line voltage jumper capacitors 821 and 823, as shown in the figure. Similarly, the single-ended induction amplifier SA0,3 includes p-channel transistors P3~P4, n-channel transistors N3~N4, N13~N14 and N22, internal induction amplifier nodes INT2 and INT2#, thick oxide high-voltage NMOS transistors 802 and 804, and bit line voltage jumper capacitors 822 and 824, as shown in the figure.

[0112] Single-ended inductive amplifiers SA0,1 and SA0,3 operate in response to control signals provided by the primary inductive amplifier drive circuit PSAD1,0. These signals include a kick control signal Vk (provided to capacitors 821-824 as shown), PCOM and NCOM (provided to the latching circuit formed by transistors P1-P4 and N1-N4 as shown), ISOS0 and ISOS1 (isolation signals provided to transistors 801-802 and 803-804 as shown), and precharge signals PRE0 and PRE1 (provided to transistors N11-N14 as shown). The specific timing of the above control signals and the corresponding operation of single-ended inductive amplifiers SA0,1 and SA0,3 are described in detail in U.S. Patent Application No. 18 / 399,579, the entire contents of which are incorporated herein by reference. The operation and control of single-ended inductive amplifiers SA0,1 and SA0,3 in response to the above control signals will also be described in detail below with reference to Figures 11A and 11B. In one embodiment, the primary induction amplifier driver circuit PSAD1,0 generates the aforementioned control signal in response to the clock signal (CLK) provided on the silicon via of the command bus INST1. Advantageously, only the enabled primary induction amplifier driver circuit is activated to generate the required control signal, thereby significantly reducing power consumption within the unit cell UC1,1.

[0113] As described above, single-ended inductive amplifier SA0,1 is coupled to the odd-numbered bit lines bl0,1 of subarray SUBA0,0 and bl1,1 of subarray SUBA1,0. Similarly, single-ended inductive amplifier SA0,3 is coupled to the odd-numbered bit lines bl0,3 of subarray SUBA0,0 and bl1,3 of subarray SUBA1,0.

[0114] If the subarray enable signal EN_SUBA0,0 is activated (indicating access to subarray SUBA0,0), the primary inductor driver circuit PSAD1,0 generates control signals ISOS0, Vk, PCOM, NCOM, PRE0, and PRE1, effectively coupling the bit lines bl0,1 and bl0,3 of subarray SUBA0,0 to single-ended inductor amplifiers SA0,1 and SA0,3, respectively. During this access, the primary inductor driver circuit PSAD1,0 disables the isolation control signal ISOS1, effectively decoupling the bit lines bl1,1 and bl1,3 of subarray SUBA1,0 from single-ended inductor amplifiers SA0,1 and SA0,3, respectively. Note that each single-ended inductor amplifier SA0,1 and SA0,3 latches one data bit entirely based on the signal developing on a single bit line.

[0115] Conversely, if the subarray enable signal EN_SUBA1,0 is activated (indicating access to subarray SUBA1,0), the primary inductor amplifier driver circuit PSAD1,0 generates control signals ISOS1, Vk, PCOM, NCOM, PRE0, and PRE1, effectively coupling the bit lines bl1,1 and bl1,3 of subarray SUBA1,0 to single-ended inductor amplifiers SA0,1 and SA0,3, respectively. During this access, the primary inductor amplifier driver circuit PSAD1,0 disables the isolation control signal ISOS0, thereby effectively decoupling the bit lines bl0,1 and bl0,3 of subarray SUBA0,0 from single-ended inductor amplifiers SA0,1 and SA0,3, respectively.

[0116] In accordance with the above method, during a single access of unit cell UC1,1, only the primary induction amplifier sub-circuit associated with the accessed sub-array is activated, thus significantly saving power.

[0117] In an alternative embodiment, the primary inductive amplifier driver PSAD1,0 generates a first trigger control voltage (e.g., VK1), which is activated and applied to trigger transistors 821 and 822 when the EN_SUBA0,0 signal is initiated, and generates a second trigger control voltage (e.g., VK2), which is activated and applied to trigger transistors 823 and 824 when the EN_SUBA1,0 signal is initiated, resulting in further power savings within the unit cell UC1,1. Note that this embodiment requires additional decoding circuitry within the primary inductive amplifier driver circuit PSAD1,0.

[0118] In the example described, the data transfer rate between the subarray and the primary inductive amplifier subcircuit is 1 GHz. However, it is understood that higher data transfer rates can be achieved in other embodiments based on the actual silicon performance capabilities known for silicon technology. In other embodiments, other considerations may necessitate slower data transfer rates.

[0119] Returning to Figure 7, a read access to subarray SUBA0,0 results in 288 data bits being transferred from the cell associated with the address subword line to the primary induction amplifier subcircuit PSA0,0, and another 288 data bits being transferred from the cell associated with that address subword line to the primary induction amplifier subcircuit PSA1,0. As described above, each of these data bits is latched into a single-ended induction amplifier. While this example describes a read access to subarray SUBA0,0 (i.e., via data channel DATA_A1), it is understood that simultaneous (parallel) read accesses (i.e., via data channel DATA_B1) can be performed on any of the right-hand subarrays SUBA0,0 through SUBA0,7. Furthermore, although this example illustrates a read access, it is understood that a write access can be similarly performed within cell UC1,1.

[0120] Data stored in the primary induction amplifier circuit is selectively routed to the global bit line (GBL), which extends along the X-axis through the unit cell UC1,1. The manner in which the global bit line extends from the primary induction amplifier circuit to the multiplexer circuit MUX1,1 is described in detail below.

[0121] Figure 9 illustrates the connections of the first eight bit lines in the first three stripes S(1,1)0~S(1,1)2 of the unit cell UC1,1 to the primary inductor amplifier, and the associated global bit line GBL0. In the first strip S(1,1)0, the even-numbered bit lines bl0,0, bl0,2, bl0,4, and bl0,6 are coupled to the corresponding single-ended inductors SA0,0, SA0,2, SA0,4, and SA0,6 in the primary inductor amplifier subcircuit PSA0,0. The odd-numbered bit lines bl0,1, bl0,3, bl0,5, and bl0,7 of the first strip S(1,1)0 are coupled to the corresponding single-ended inductors SA0,1, SA0,3, SA0,5, and SA0,7 in the primary inductor amplifier subcircuit PSA1,0.

[0122] In the second band S(1,1)1, the odd-numbered bit lines bl1,1,bl1,3,bl1,5, and bl1,7 are coupled to the corresponding single-ended inductors SA0,1,SA0,3,SA0,5, and SA0,7 in the primary inductor amplifier subcircuit PSA1,0. The even-numbered bit lines bl1,0,bl1,2,bl1,4, and bl1,6 of the second band S(1,1)1 are coupled to the corresponding single-ended inductors SA1,0,SA1,2,SA1,4, and SA1,6 in the primary inductor amplifier subcircuit PSA2,0.

[0123] In the third band S(1,1)2, the even-numbered bit lines bl2,0,bl2,2,bl2,4, and bl2,6 are coupled to the corresponding single-ended inductive amplifiers SA1,0,SA1,2,SA1,4, and SA1,6 in the primary inductive amplifier sub-circuit PSA2,0. The odd-numbered bit lines bl2,1,bl2,3,bl2,5, and bl2,7 of the third band S(1,1)2 are coupled to the corresponding single-ended inductive amplifiers SA1,1,SA1,3,SA1,5, and SA1,7 in the primary inductive amplifier sub-circuit PSA2,0.

[0124] As detailed below, the Y-address signal Y-DEC[7:0] controls the data routing between the unit cell UC1,1 single-ended inductive amplifier and the corresponding global bit line. Generally, the Y-address signals Y-DEC[0], Y-DEC[2], Y-DEC[4] and Y-DEC[6] control the output routing of the primary inductive amplifier circuits PSA0, PSA2, PSA4, PSA6, PSA8, PSA10, PSA12, PSA14 and PSA16, while the Y-address signals Y-DEC[1], Y-DEC[3], Y-DEC[5] and Y-DEC[7] control the output routing from the primary inductive amplifier circuits PSA1, PSA3, PSA5, PSA7, PSA9, PSA11, PSA13 and PSA15.

[0125] Figure 10 illustrates, according to an embodiment of the present invention, an MTDRAM subarray SUBA0,0, the corresponding primary induction amplifier subcircuits PSA1,0 and PSA1,1, and the corresponding global bit lines GBL0~GBL71. Global bit lines GBL0~GBL71 are shared by all subarrays in subarray column CoSA0. Figure 10 also illustrates, according to an embodiment of the present invention, the Y address signal Y-DEC[7:0] routing data from the single-ended induction amplifiers of the primary induction amplifier subcircuits PSA0,0 and PSA1,0 to the global bit lines GBL0~GBL71.

[0126] As described above, reading and accessing a row of subarray SUBA0,0 results in 288 data bits being transferred to the primary induction amplifier subcircuit PSA1,0 on the even-numbered bit lines of subarray SUBA0,0, and 288 data bits being transferred to the primary induction amplifier subcircuit PSA1,1 on the odd-numbered bit lines of subarray SUBA0,0. As shown in Figure 10, the primary induction amplifier subcircuit PSA1,0 includes 288 single-ended induction amplifiers SA0,Y (where Y = even numbers from 0 to 574), and the primary induction amplifier subcircuit PSA1,1 includes 288 single-ended induction amplifiers SA0,Z (where Z = odd numbers from 1 to 575), which store the data read from a row of bits in subarray SUBA0,0.

[0127] The column select circuitry inside the primary induction amplifier sub-circuits PSA1,0 and PSA1,1 is controlled to selectively route 72-bit data values ​​to global bit lines GBL0~GBL71 in response to the pre-decoded Y address value Y-DEC[0:7] provided on the instruction bus INST1.

[0128] As shown in Figure 10, each global bit line GBL is coupled to eight corresponding single-ended induction amplifiers in the primary induction amplifier subcircuits PSA1,0 and PSA1,1. For example, global bit line GBL0 is coupled to four single-ended induction amplifiers SA0,0, SA0,2, SA0,4 and SA0,6 in the primary induction amplifier subcircuit PSA1,0, and four single-ended induction amplifiers SA0,1, SA0,3, SA0,5 and SA0,7 in the primary induction amplifier subcircuit PSA1,1. Each of these eight single-ended induction amplifiers SA0,0 to SA0,7 is coupled to global bit line GBL0 through a corresponding transistor controlled by Y address values ​​Y-DEC[0] to Y-DEC[7]. Please note that Figure 8 illustrates example transistors N20 and N22, which couple single-ended inductor amplifiers SA0,1 and SA0,3 to global bit line GBL0 to respond to Y address values ​​Y-DEC[1] and Y-DEC[3], respectively. Therefore, if Y address value Y-DEC[1] is enabled (and Y address values ​​Y-DEC[0] and Y-DEC[2:7] are disabled), the data value stored in single-ended inductor amplifier SA0,1 is transmitted to global bit line GBL0 (through the on-state transistor N20).

[0129] As shown in the figure, the above mode can be repeated for eight consecutive single-ended inductive amplifier groups, thereby transferring 72-bit data values ​​to the global bit lines GBL0~GBL71. It is worth noting that by changing (e.g., incrementing) the Y address value Y-DEC[0:7] within consecutive cycles, burst read access of up to eight 72-bit data values ​​can be performed on the data stored in the primary inductive amplifier subcircuits PSA1,0 and PSA1,1 without restarting the primary inductive amplifier subcircuits PSA1,0 and PSA1,1. As detailed below, the Y address value Y-DEC[0:7] is controlled by processor block 1051 (via instruction bus INST1).

[0130] Please note that the global bit lines GBL0~GBL71 are shared by all subarrays in subarray column CoSA0. As detailed below, each of the eight subarray columns CoSA0~CoSA7 of unit cell UC1,1 has a corresponding set of 72 global bit lines. In the embodiment described herein, all primary induction amplifiers in a unit stack share the same Y address value Y-DEC[0:7].

[0131] As shown in Figures 9 and 10, when accessing the subarray SUBA1,0 of stripe S(1,1)1, the single-ended induction amplifier in the primary induction amplifier subcircuit PSA1,0 is selectively coupled to global bit lines GBL0~GBL71 to respond to Y address signals Y-DEC[1], Y-DEC[3], Y-DEC[5] and Y-DEC[7], and the single-ended induction amplifier in the primary induction amplifier subcircuit PSA2,0 is selectively coupled to global bit lines GBL0~GBL71 to respond to Y address signals Y-DEC[0], Y-DEC[2], Y-DEC[4] and Y-DEC[6]. Using this mode, each primary induction amplifier circuit PSA0~PSA16 only needs to receive 4 Y address signals, which helps to reduce wiring congestion in unit cell UC1,1.

[0132] The timing of the Y address value Y-DEC[0:7] (and the timing of the read / write signals on the global bit line) is different during read access and write access.

[0133] Figure 11A illustrates a waveform diagram of a control signal according to one embodiment. This control signal is used to read the (logic high) data value of bit cell bc0,1 from subarray SUBA0,0 into single-ended inductive amplifier SA0,1, and then transfer this data value from single-ended inductive amplifier SA0,1 to global bit line GBL0. Generally, precharge signals PRE0 and PRE1 are activated (high) to precharge single-ended inductive amplifier SA0,1 before time T1. At time T1, the precharge control voltage PRE0 is driven to GND, thereby turning off n-channel transistors N11 and N13, so that internal inductive amplifier nodes INT0 and INT2 are no longer actively pulled to GND through transistors N11 and N13.

[0134] At time T2, sub-word line SWL0,0 is driven high by the corresponding sub-word line drive circuit SWD0,0 (responding to MWL0, SWLA[0] and EN_SUBA0,0 signals), thereby providing positive charge to the corresponding bit line bl0,1 via bit cell bc0,1. At time T3, trigger voltage VK is activated to low voltage, further amplifying the signal on bit line bl0,1. At time T4, ISOS0 signal is activated, coupling bit line bl0,1 to the internal node INT0 of single-ended induction amplifier SA0,1. At time T5, precharge signals PRE1 and ISOS0 are deactivated, while PCOM and NCOM voltages are activated, effectively enabling single-ended induction amplifier SA0,1 to latch logic high data values ​​(i.e., developing full read voltages on internal nodes INT0 and INT0# of single-ended induction amplifier SA0,1). At time T6, the ISOS0 signal is restarted, causing the read voltage generated on the internal node INT0 to be driven onto the bit line bl0,1 to refresh the bit cell bc0,0. Shortly after time T6 (i.e., at time T7), the Y address signal (i.e., Y-DEC[1]) associated with bit line bl0,1 is activated to a high voltage (e.g., 1.1V), thereby coupling the internal node INT0 to the global bit line GBL0. Under these conditions, the voltage on the global bit line GBL0 is driven to a logic high voltage of approximately 250 mV (due to the capacitance of the global bit line structure, which will be detailed below). Note that when reading a logic low data value from bit cell bc0,1, a read data voltage of approximately -200 mV is provided on the global bit line GBL0. The operation of the single-ended inductive amplifier SA0,1 is described in detail in U.S. Patent Application No. 18 / 399,579, the entire contents of which are incorporated herein by reference. Please note that the Y-DEC[1] and GBL0 signals are deactivated around time T9.

[0135] Figure 11B illustrates a waveform diagram of a control signal according to one embodiment. This control signal is used to write a logic high data value from the global bit line GBL0 to a single-ended inductive amplifier SA0,1, and then transfer this data value from the single-ended inductive amplifier SA0,1 to bit line bl0,1 and then to bit cell bc0,1. This process is performed in a manner similar to the read access in Figure 11A between times T1 and T5, but exceptions are noted below. In the illustrated embodiment, bit cell bc0,1 stores a logic low data value, such that when sub-word line SWL0,0 is activated at time T2, the voltage on bit line bl0,1 is initially pulled down to below 0V. Furthermore, at time T2, the write drive circuit (described in detail below) within the secondary inductive amplifier circuit SSA1,1 drives a logic high write data value (250 mV) to the global bit line GBL0. Additionally, at time T2, the Y-address signal (i.e., Y-DEC[1]) associated with bit line bl0,1 is activated at a high voltage (e.g., 1.1V), thereby coupling the internal node INT0 to the global bit line GBL0. Under these conditions, the internal node INT0 is driven to a voltage of 250 mV. At time T3, the activated trigger voltage Vk drops the voltage on bit line bl0,1 to -40 mV. The ISOS0 signal is activated between times T4 and T5, thereby applying a 250 mV voltage on the internal node INT0 to bit line bl0,1. Advantageously, the single-ended induction amplifier SA0,1 is not activated until time T5 (i.e., PCOM and NCOM are not switched until time T5). Therefore, the write drive circuit does not need to toggle the state of the single-ended induction amplifier SA0,1 (i.e., the write drive circuit only needs to overcome the relatively small voltage (-40 mV) initially generated on bit line bl0,1 at time T4).

[0136] At time T5, the precharge signals PRE1 and ISOS0 are deactivated, while the PCOM and NCOM voltages are activated, effectively enabling the single-ended inductive amplifier SA0,1 to latch the logic high write data value (i.e., a full write voltage is developed on the internal nodes INT0 and INT0# of the single-ended inductive amplifier SA0,1). At time T6, the ISOS0 signal is reactivated, causing the write voltage generated on the internal node INT0 to be driven onto the bit line bl0,1 to write the bit cell bc0,1. Signal processing is performed as shown in Figure 11B to complete the write access. Note that the write drive circuit drives a voltage of -200 mV on the global bit line GBL0 to write the logic low data value into the bit cell bc0,1. Note that the Y-DEC[1] and GBL0 signals are deactivated around time T9.

[0137] Figure 12 illustrates a data channel of cell UC1,1 according to an embodiment of the present invention. As described above in conjunction with Figure 10, each subarray column CoSA0~CoSA7 contains a set of 72 global bit lines, which extend parallel to the X-axis through stripes S(1,1)0~S(1,1)15. Specifically, subarray columns CoSA0, CoSA1, CoSA2, CoSA3, CoSA4, CoSA5, CoSA6 and CoSA7 respectively include 72-bit global bit line groups GBL0~GBL71, GBL72~GBL143, GBL144~GBL215, GBL216~GBL287, GBL288~GBL359, GBL360~GBL431, GBL432~GBL503 and GBL504~GBL575, as shown in the figure. These global bit lines GBL0~GBL575 are coupled to multiplexers MUX1,1. Specifically, global bit lines GBL0~GBL287 (associated with the left subarray) are coupled to the first multiplexer segment MUX(1,1)A of multiplexer MUX1,1, which is dedicated to the data channel DATA_A1 of the unit stack US1. Similarly, global bit lines GBL288~GBL575 (associated with the right subarray) are coupled to the second multiplexer segment MUX(1,1)B of multiplexer MUX1,1, which is dedicated to the data channel DATA_B1 of the unit stack US1.

[0138] If cell UC1,1 is read from data channel DATA_A1, the multiplexer segment MUX(1,1)A will be controlled to route the 72-bit data value of one of the 72-bit global bit line groups GBL0~GBL71, GBL72~GBL143, GBL144~GBL215 or GBL216~GBL287 on global input / output lines GIO0~GIO71.

[0139] Similarly, if the unit cell UC1,1 is read and accessed on the data channel DATA_B1, the multiplexer segment MUX(1,1)B will be controlled to route the 72-bit data value of one of the 72-bit global bit line groups GBL288~GBL359, GBL360~GBL431, GBL432~GBL503 or GBL504~GBL575 on the global input / output lines GIO72~GIO143.

[0140] Global input / output lines GIO0~GIO143 are coupled to the second-stage induction amplifier circuit SSA1,1. Specifically, global input / output lines GIO0~GIO71 are coupled to the first second-stage induction amplifier section SSA(1,1)A of the second-stage induction amplifier circuit SSA1,1, which is dedicated to the data channel DATA_A1 of the unit stack US1. Similarly, global input / output lines GIO72~GIO143 are coupled to the second second-stage induction amplifier section SSA(1,1)B of the second-stage induction amplifier circuit SSA1,1, which is dedicated to the data channel DATA_B1 of the unit stack US1.

[0141] If a unit cell UC1,1 is read from data channel DATA_A1, the secondary inductive amplifier segment SSA(1,1)A is controlled to route the 72-bit data value received from the multiplexer segment MUX(1,1)A as two 36-bit data values ​​to data channel DATA_A1. As detailed below, the frequency (2 GHz) at which the secondary inductive amplifier segment SSA(1,1)A routes these two 36-bit data values ​​is twice the frequency (1 GHz) at which the 72-bit data value is read from the subarray. In Figure 12, the 36-bit data value routed by the secondary inductive amplifier segment SSA(1,1)A is labeled DATA_A1[0:35].

[0142] Similarly, if a unit cell UC1,1 is read from or accessed on data channel DATA_B1, the secondary inductive amplifier section SSA(1,1)B will be controlled to amplify the 72-bit data value received from the multiplexer section MUX(1,1)B and route it to data channel DATA_B1 as two 36-bit data values, in the same way that the secondary inductive amplifier section SSA(1,1)A amplifies and routes the 72-bit data value to data channel DATA_A1. In Figure 12, the 36-bit data value routed by the secondary inductive amplifier section SSA(1,1)B is labeled DATA_B1[0:35].

[0143] Understandably, the secondary inductive amplifier section SSA(1,1)A drives the output data value DATA_A1[0:35] to the corresponding 36 silicon vias in the silicon via group TSV1,1. Similarly, the secondary inductive amplifier section SSA(1,1)B drives the output data value DATA_B1[0:35] to the corresponding 36 silicon vias in the silicon via group TSV1,1.

[0144] Please note that in other embodiments, the secondary inductive amplifier sections SSA(1,1)A and SSA(1,1)B may route the received 72-bit data values ​​in other ways. For example, in an alternative embodiment, the secondary inductive amplifier sections SSA(1,1)A and SSA(1,1)B may be configured to route the 72-bit data values ​​received from the multiplexer sections MUX(1,1)A and MUX(1,1)B as four 18-bit data values ​​to data channels DATA_A1 and DATA_B1 at a frequency of 4 GHz. In this embodiment, the number of silicon vias required to implement the corresponding unit stack US1 is advantageously reduced by 36.

[0145] It should also be noted that for write operations, the data read path is the reverse of that described above, where the second-stage inductive amplifier sections SSA(1,1)A and SSA(1,1)B include write drive circuitry, which will be detailed below.

[0146] Figure 13 illustrates a method for routing signals on global bit lines GBL0~GBL287 to multiplexer segment MUX(1,1)A according to an embodiment of the present invention. It will be understood that signals on global bit lines GBL288~GBL575 are routed to multiplexer segment MUX(1,1)B in the same manner.

[0147] Generally, the global bit lines GBL0~GBL287 extend parallel to the X-axis width of stripes S(1,1)0~S(1,1)15, as shown in the figure. The signal from each group of 72 global bit lines is divided into eight 9-bit groups, horizontally distributed along the X-axis width of the multiplexer MUX(1,1)A. In one embodiment, horizontal metal lines (along the Y-axis) are used to distribute the signals from these global bit lines.

[0148] For example, a group of 36 metal lines ML0 distributes the signals on global bit lines GBL0~GBL35 along the Y-axis, as shown in the figure. Nine of these 36 metal lines ML0 distribute global bit lines GBL0~GBL8 on the left (along the negative direction of the Y-axis), while 27 of these 36 metal lines distribute global bit lines GBL9~GBL35 on the right (along the positive direction of the Y-axis). Therefore, the required layout height of metal lines ML0 along the X-axis is only the height of 27 metal lines.

[0149] Similarly, a set of 36 metal lines ML1 distributes the signals on global bit lines GBL36~GBL71 along the Y-axis, as shown in the figure. All 36 metal lines ML1 distribute global bit lines GBL36~GBL71 on the right side (along the positive direction of the Y-axis). Therefore, the required layout height of the metal lines ML1 along the X-axis is the height of 36 metal lines.

[0150] A set of 36 metal lines ML2 distributes the signals on global bit lines GBL72~GBL107 along the Y-axis, as shown in the figure. Nine of these 36 metal lines ML2 place global bit lines GBL99~GBL107 on the right (along the positive Y-axis), while 27 of these 36 metal lines place global bit lines GBL72~GBL98 on the left (along the negative Y-axis). Therefore, the required layout height of metal lines ML2 along the X-axis is only the height of 27 metal lines.

[0151] Similarly, a set of 36 metal lines ML3 distributes the signals on global bit lines GBL108~GBL143 along the Y-axis, as shown in the figure. All 36 metal lines ML3 distribute global bit lines GBL108~GBL143 on the right side (along the positive direction of the Y-axis). Therefore, the required layout height of the metal lines ML3 along the X-axis is the height of 36 metal lines.

[0152] A set of 36 metal lines ML4 are distributed along the Y-axis to the signals on global bit lines GBL144~GBL179. The distribution pattern is that there are 36 metal lines along the X-axis, as shown in the figure.

[0153] A group of 36 metal lines ML5 are distributed across global bit lines GBL180~GBL215, with a distribution pattern of 27 metal lines at a height along the X-axis, as shown in the figure. In the illustrated embodiment, this group of metal lines ML5 is located at the same latitude as the group of metal lines ML0, therefore, this group of metal lines ML5 does not increase the required height of the metal line structure along the X-axis.

[0154] A set of 36 metal lines ML6 are distributed along the Y-axis to represent the signals on global bit lines GBL216~GBL251. The distribution pattern is such that there are 36 metal lines along the X-axis, as shown in the figure.

[0155] A group of 36 metal lines ML7 are distributed across global bit lines GBL252~GBL287, with a distribution pattern of 27 metal lines at a height along the X-axis, as shown in the figure. In the illustrated embodiment, this group of metal lines ML7 is located at the same latitude as the group of metal lines ML2, therefore, this group of metal lines ML7 does not increase the required height of the metal line structure along the X-axis.

[0156] The configuration in Figure 13 requires a total of 27+27+36+36+36+36, or 198 horizontal metal line tracks, each extending parallel to the Y-axis. Note that by restricting the main character line configuration to one (metal) character line for every eight sub-character lines, as described above in conjunction with Figure 7, where the sub-character lines SWL0,0~SWL7,0 are implemented using a conductive polysilicon structure instead of metal layer lines, sufficient area is provided for these 198 horizontal metal line tracks. The spacing between the metal main character lines (MWL) (along the X-axis) is equal to the height of four bit cells (along the X-axis). Therefore, the above configuration (one metal main character line for every eight bit cells) advantageously reduces the number of main character line tracks required within a unit cell by half, thereby freeing up the necessary horizontal tracks for routing the global bit lines as shown in Figure 13.

[0157] The configuration in Figure 13 requires 288 x 2, or 576 vertical metal lines, including 288 global bit lines GBL0~GBL287, and 288 metal lines extending vertically along the X-axis from metal line group ML0~ML7 to multiplexer segment MUX(1,1)A.

[0158] Figure 14 illustrates the distribution of global bit lines GBL0~GBL287 to the multiplexer segment MUX(1,1)A according to the present invention. The multiplexer segment MUX(1,1)A comprises eight 4-to-1 multiplexers MUXA0~MUXA7, each multiplexer coupled to nine global bit lines of each of the four subarray columns CoSA0~CoSA3. For example, multiplexer MUXA0 is coupled to nine global bit lines GBL0~GBL8 of subarray column CoSA0, nine global bit lines GBL72~GBL80 of subarray column CoSA1, nine global bit lines GBL144~GBL152 of subarray column CoSA2, and nine global bit lines GBL216~GBL224 of subarray column CoSA3. The remaining multiplexers MUXA1~MUXA7 repeat this pattern.

[0159] Multiplexers MUXA0~MUXA7 are controlled by pre-decoded subarray column addresses CoSAA[3:0]. When address values ​​CoSAA[0], CoSAA[1], CoSAA[2], and CoSAA[3] are activated, the global bit lines of subarray columns CoSA0, CoSA1, CoSA2, and CoSA3 are connected to global input / output lines GIO0~GIO71, respectively. For example, when the subarray column address CoSAA[3:0] is "0001", multiplexers MUXA0~MUXA7 will connect the global bit lines GBL0~GBL71 of subarray column CoSA0 to global input / output lines GIO0~GIO71. The pre-decoded subarray column addresses CoSAA[3:0] are provided by instruction bus INST1.

[0160] Understandably, the multiplexer section MUX(1,1)B operates in the same way as the multiplexer section MUX(1,1)A. However, the multiplexer section MUX(1,1)B operates in response to signals on the global bit lines GBL288~GBL575 and is controlled by separate pre-decoding subarray column addresses CoSAB[3:0]. When the address values ​​CoSAB[0], CoSAB[1], CoSAB[2], and CoSAB[3] are activated, they will connect the global bit lines from subarray columns CoSA4, CoSA5, CoSA6, and CoSA7 to the global input / output lines GIO72~GIO143, respectively. The pre-decoding subarray column addresses CoSAB[3:0] are provided by the instruction bus INST1.

[0161] Figure 15 illustrates a secondary inductive amplifier section SSA(1,1)A according to an embodiment of the present invention. It is understood that the secondary inductive amplifier section SSA(1,1)B is configured and operated in the same manner as the secondary inductive amplifier circuit SSA(1,1)A. The secondary inductive amplifier circuit SSA(1,1)A includes 36 identical "even-number" readout secondary inductive amplifier circuits RSA0, RSA2, ... RSA70, coupled to receive readout data values ​​from the "even-number" global input / output lines GIO0, GIO2, ... GIO70, respectively, and 36 identical "odd-number" readout secondary inductive amplifier circuits RSA1, RSA3, ... RSA71, coupled to receive readout data values ​​from the "odd-number" global input / output lines GIO1, GIO3, ... GIO71, respectively. Each pair of consecutive even / odd readout secondary inductive amplifier circuits is coupled to the corresponding single bit (silicon via) of the data bus DATA_A1[0:35]. For example, the even readout secondary inductive amplifier RSA0 and the odd readout secondary inductive amplifier RSA1 are coupled to global input / output lines GIO0 and GIO1, respectively, and are jointly coupled to a silicon via of the silicon via group TSV1,1 carrying the data bus signal DATA_A1[0].

[0162] As detailed below, 72-bit read data on global input / output lines GIO0~GIO71 is transmitted to the secondary inductive amplifier circuit SSA(1,1)A at a data rate of 1 GHz, while 36-bit data is read from the secondary inductive amplifier circuit SSA(1,1)A at a data rate of 2 GHz. This advantageously minimizes the number of silicon vias required to transmit read data from the unit stack US1 to the ASIC processor block 1051.

[0163] The secondary inductive amplifier circuit SSA(1,1)A further includes 36 identical "even-number" write secondary inductive amplifier circuits WSA0, WSA2, ... WSA70, which are coupled to provide write data values ​​to the "even-number" global input / output lines GIO0, GIO2, ... GIO70, respectively, and 36 identical "odd-number" write secondary inductive amplifier circuits WSA1, WSA3, ... WSA71, which are coupled to provide write data values ​​to the "odd-number" global input / output lines GIO1, GIO3, ... GIO71, respectively. Each pair of consecutive even / odd write secondary inductive amplifier circuits is coupled to the corresponding single bit (silicon via) of the data bus DATA_A1[0:35]. For example, even-numbered write secondary inductive amplifiers WSA0 and odd-numbered write secondary inductive amplifiers WSA1 are coupled to global input / output lines GIO0 and GIO1, respectively, and are jointly coupled to a silicon via of the silicon via group TSV1,1 carrying the data bus signal DATA_A1[0].

[0164] As detailed below, 36-bit write data on the data bus DATA_A1[0:35] is transmitted at a data rate of 2 GHz to the secondary inductive amplifier section SSA(1,1)A, and 72-bit write data is transmitted from the secondary inductive amplifier section SSA(1,1)A to the global input / output lines GIO0~GIO71 at a data rate of 1 GHz. This advantageously minimizes the number of silicon vias required to transmit write data from the ASIC processor block 1051 to the unit stack US1.

[0165] Figures 16 and 17 illustrate circuit diagrams of an "even-number" readout second-stage inductive amplifier circuit RSA0 and an "odd-number" readout second-stage inductive amplifier circuit RSA1, according to an embodiment of the present invention. Since each of these readout second-stage inductive amplifier circuits operates based on a signal received on a single global input / output line, these readout second-stage inductive amplifiers are "single-ended inductive amplifiers" as described herein.

[0166] The even-numbered readout secondary inductive amplifier circuit RSA0 includes n-channel transistors 1601-1608, p-channel transistors 1610-1613, and capacitors 1630-1631, as shown in Figure 16. The n-channel transistors 1605-1606 and the p-channel transistors 1612-1613 are connected to form an inductive amplifier latch 1620 containing a cross-coupled inverter. The p-channel transistors 1610 and 1611 form a pre-amplifier differential pair.

[0167] As shown in Figure 17, the odd-numbered readout second-stage inductive amplifier circuit RSA1 includes n-channel transistors 1701-1708, p-channel transistors 1710-1713, and capacitors 1730-1731, connected in the same way as the even-numbered readout second-stage inductive amplifier circuit RSA0, which includes n-channel transistors 1601-1608, p-channel transistors 1610-1613, and capacitors 1630-1631. N-channel transistors 1705-1706 and p-channel transistors 1712-1713 are connected to form an inductive amplifier latch 1720 containing a cross-coupled inverter. P-channel transistors 1710 and 1711 form a preamplifier differential pair. The odd-numbered readout second-stage inductive amplifier circuit RSA1 further includes an additional input stage, which includes an n-channel transistor 1740 and capacitor 1750.

[0168] Figure 18 illustrates the operating waveforms of the "even number" readout secondary inductive amplifier circuit RSA0 and the "odd number" readout secondary inductive amplifier circuit RSA1 according to an embodiment of the present invention.

[0169] While this embodiment uses a specific voltage as the logic high voltage to drive the individual transistors within RSA0 and RSA1, it is understood that other embodiments may specify different logic high voltages. It is generally desirable for the logic high voltage to be as low as possible to save power, while still being high enough to allow the controlled circuitry to meet speed and / or headroom requirements. In various embodiments, the logic high voltage has values ​​ranging from 250 mV to 1.1 Volts. Notably, using dedicated n-channel transistors manufactured using the MST process (described in the applicant's common U.S. Patents Nos. 10,109,342 and 10,107,854, the entire contents of which are incorporated herein by reference) can increase the logic high voltage (e.g., 200 mV higher than the baseline Vdd supply voltage of 1.1 V), thereby effectively overdriving the n-channel transistors within RSA0 and RSA1.

[0170] In the following embodiments, control signals SAMPLE_E, SAMPLE_O, PRE_O, and PRE_E have a logic high voltage of approximately 250 mV, control signals COMP1_E, COMP1_O, COMP2_E, and COMP2_O have a logic high voltage of approximately 1.1 V to 1.3 V, and control signals OUT_ODD and OUT_EVEN have a logic high voltage of 250 mV to 350 mV.

[0171] At time T0, data values ​​D0 and D1 are read from one of the subarray columns CoSA0 to CoSA3 in the manner described above, and are respectively read onto the global input / output lines GIO0 and GIO1.

[0172] At time T1, the read sampling signal SAMPLE_E applied to the gates of n-channel transistors 1601 and 1602 in RSA0 and the gate of n-channel transistor 1740 in RSA1 starts from logic low (0 V) to logic high (250 mV). Under these conditions, transistors 1601 and 1740 are turned on, causing the read data values ​​(i.e., D0 and D1, respectively) on global input / output lines GIO0 and GIO1 to be applied to capacitors 1630 and 1750, and stored by these capacitors as input signals IN_E and HOLD_O, respectively. In the embodiment described herein, the data values ​​transmitted on global input / output lines GIO0 and GIO1 exhibit a logic low voltage (0 V) to ground and a logic high voltage of 250 mV. Capacitor 1750 is large enough to ensure that no significant charge leakage occurs in this component during the time (e.g., a few nanoseconds) during which the sampled data value must be stored as HOLD_O.

[0173] Under the same conditions, transistor 1602 is turned on, causing the reference voltage VREF to be applied as a reference signal REF_E to capacitor 1631 and stored therein. In the embodiments described herein, the reference voltage VREF (and the reference signal REF_E) is slightly less than half the logic high voltage on the global input / output lines (e.g., slightly less than half of 250 mV, or approximately 110 mV in one embodiment). Capacitors 1601 and 1602 are matched and have sufficiently large capacitances that the differential signal coupling mismatch with transistors 1610 and 1611 is not significant, for example, 5% or less.

[0174] As shown in the figure, the input signal IN_E stored in capacitor 1630 is applied to the gate of p-channel transistor 1610, while the input signal REF_E stored in capacitor 1631 is applied to the gate of p-channel transistor 1611. In this embodiment, transistors 1610-1611 are identical, transistors 1601-1602 are identical, and capacitors 1630-1631 are identical, thereby balancing the input of the second-stage inductive amplifier RSA0.

[0175] At time T2, within the readout of the secondary inductive amplifier circuit RSA0, the comparator enable signal COMP1_E is initiated from a logic low voltage (0V) to a logic high voltage of approximately 1.1 to 1.3 volts. Under these conditions, differential voltages UP_E and DOWN_E are generated at the drains of p-channel transistors 1610 and 1611, respectively, where the DOWN_E voltage generated at the drain of transistor 1610 represents the voltage of the input signal IN_E, and the UP_E voltage at the drain of transistor 1611 represents the reference voltage REF_E applied to the gate of transistor 1611. In this embodiment, the reference voltage REF_E is equal to 110 mV, slightly less than half the logic high voltage of the input signal IN_E (250 mV).

[0176] If the voltage of the input signal IN_E is less than the reference voltage REF_E (i.e., if IN_E = 0V), then the voltage of the UP_E signal will be less than the voltage of the DOWN_E signal. Conversely, if the voltage of the input signal IN_E is greater than the reference voltage REF_E (i.e., if IN_E = 250 mV), then the voltage of the UP_E signal will be greater than the voltage of the DOWN_E signal.

[0177] At time T2, the comparator enable signal COMP1_E is deactivated from logic high to logic low (0V), as shown in the figure. Also at time T2, the comparator enable signal COMP2_E is activated from logic low (0V) to a logic high of approximately 1.1 to 1.3V, thereby enabling the induction amplifier latch 1620.

[0178] Under these conditions, the inductive amplifier latch 1620 amplifies the difference between the differential UP_E and DOWN_E voltages so that it stores a data value representing the voltage received on the global input / output line GIO0. For example, if the UP_E voltage is less than the DOWN_E voltage, the latch 1620 will pull the DOWN_E voltage high to the COMP2_E signal voltage (350 mV) and pull the UP_E voltage to ground. Conversely, if the UP_E voltage is greater than the DOWN_E voltage, the latch 1620 will pull the DOWN_E voltage low to ground and pull the UP_E voltage high to the COMP2_E signal voltage (e.g., 1.1 V to 1.3 V).

[0179] The UP_E and DOWN_E voltages are applied to the gates of the n-channel transistors 1607 and 1608, respectively. As described above, when the inductive amplifier latch 1620 is enabled, the UP_E or DOWN_E voltage will be pulled up to 1.1 to 1.3 V, thereby turning on the corresponding n-channel transistors 1607 or 1608, respectively.

[0180] Just before time T2, the output control signal OUT_EVEN is driven from ground (0V) to a slightly boosted voltage of 350 mV. Therefore, if the UP_E voltage is pulled high to 350 mV, the corresponding n-channel transistor 1607 will turn on, and the DATA_A1[0] output signal will initially be pulled high to 350 mV at the output of the second-stage inductive amplifier RSA0. Shortly after the inductive amplifier latch 1620 is enabled (e.g., at time T4), the output control signal OUT_EVEN drops from 350 mV to 250 mV, causing the DATA_A1[0] output signal to be pulled high to 250 mV at the output of the second-stage inductive amplifier RSA0. The initial voltage at the output of the second-stage inductive amplifier RSA0 is due to the significant capacitance of the DATA_A1[0] signal line structure (see Figure 4). The duration of this voltage boost is controlled so that the voltage received by processor block 1051 can be quickly reached but not exceed 250 mV.

[0181] Maintaining the OUT_EVEN signal at 0V from time T0 until time T3 helps minimize leakage current in the n-channel transistor 1607 and reduces the power requirement of the readout secondary induction amplifier RSA0. However, it is understood that in other embodiments, the OUT_EVEN voltage may be maintained at 250 mV (or 350 mV) from time T0 to time T3.

[0182] When the inductive amplifier latch 1620 is enabled at time T2, if the DOWN_E voltage is pulled up to a logic high voltage of 1.1 to 1.3 V, the corresponding n-channel transistor 1608 is turned on, and the DATA_A1[0] output signal is pulled down to ground (0V) at the output of the secondary inductive amplifier RSA0.

[0183] At time T5, the COMP2_E signal is deactivated from logic high (1.1 to 1.3 V) to logic low (0 V), as shown in the figure, thereby disabling the inductive amplifier latch 1620 so that the secondary inductive amplifier SSAEVEN no longer actively drives the DATA_A1[0] signal. In the illustrated embodiment, the duration from time T2 to T5 (i.e., the time during which reading the output of the secondary inductive amplifier RSA0 can effectively drive the data value D0 to DATA_A1[0]) is 0.5 ns, corresponding to an output data rate of 2 GHz.

[0184] Then, a precharge operation is performed as follows, preparing the second-stage inductive amplifier RSA0 to receive the next data value on the global input / output line GIO0.

[0185] Shortly after time T5, the PRE_E signal is initiated from a logic low state (0V) to a logic high state (250 mV), thereby turning on the n-channel precharge transistors 1603 and 1604. Under these conditions, the voltages of the UP_E and DOWN_E signals are pulled low to ground, thereby precharging these signals. The PRE_E signal is deactivated to a low voltage (0V) to turn off transistors 1603-1604 before the next activation of the induction amplifier latch 1620 (e.g., at time T7 in Figure 18).

[0186] During continuous access to the secondary inductive amplifier RSA0, the above signal pattern will repeat. Therefore, as shown in Figure 18, the next read access starting from the secondary inductive amplifier RSA0 will start at time T6 (with the start of the SAMPLE_E signal), and will continue to read the next read data value D2 as DATA_A1[0] signal from time T7 to time T8.

[0187] Now turning to the "odd" readout secondary inductive amplifier RSA1 (Figure 17), at time T10, the sampling signal SAMPLE_O applied to the gates of n-channel transistors 1701 and 1702 is activated from logic low (0V) to logic high (250 mV). Under this condition, transistor 1701 turns on, causing the data value previously received on the global input / output line GIO1 and stored as the HOLD_O voltage by capacitor 1750 to be applied as the input signal IN_O to capacitor 1730 (and stored therein).

[0188] Under the same conditions, transistor 1702 is turned on, causing the reference voltage VREF to be applied to (and stored therein) the capacitor 1731 as the reference signal REF_O. As described above, in this embodiment, the reference voltage VREF (and the reference signal REF_O) has a voltage of approximately 110 mV.

[0189] At time T11, the comparator enable signal COMP1_O is activated from logic low (0V) to logic high (1.1 to 1.3V) in the odd-numbered read-second-stage inductive amplifier circuit RSA1. Under these conditions, the differential UP_O and DOWN_O voltages are generated at the drains of p-channel transistors 1710 and 1711 in the same manner as the differential UP_E and DOWN_E voltages are generated at the drains of p-channel transistors 1610 and 1611 in the even-numbered read-second-stage inductive amplifier RSA0.

[0190] At time T5, the comparator enable signal COMP1_O is deactivated from logic high (1.1 to 1.3 V) to logic low (0 V), as shown in the figure. Also at time T5, the comparator enable signal COMP2_O is activated from logic low (0 V) to a boosted logic high (1.1 to 1.3 V), thereby enabling the induction amplifier latch 1720. Just before time T5, the output control signal OUT_ODD is driven from ground (0 V) to a slightly boosted 350 mV voltage.

[0191] Under these conditions, the operation of the inductive amplifier latch 1720 is the same as that of the inductive amplifier latch 1620 described above, wherein the inductive amplifier latch 1720 amplifies the difference between the differential voltages UP_O and DOWN_O, so that the inductive amplifier latch 1720 stores the data value D1 representing the voltage received on the global input / output line GIO1.

[0192] The UP_O and DOWN_O voltages are applied to the gates of the n-channel transistors 1707 and 1708, respectively. When the inductive amplifier latch 1720 is enabled, the UP_O voltage or the DOWN_O voltage will be pulled up to 1.1 to 1.3V, thereby turning on the corresponding n-channel transistors 1707 or 1708, respectively. The method of controlling the OUT_ODD output control signal of the secondary inductive amplifier RSA1 is the same as that of the OUT_EVEN output control signal of the secondary inductive amplifier RSA0 described above. Therefore, starting from time T5, the secondary inductive amplifier RSA1 drives the data value D1 received on the global input / output line GIO1 to the DATA_A1[0] signal line.

[0193] At time T7, the COMP2_O signal is deactivated from a logic high state (1.1 to 1.3 V) to a logic low state (0 V), as shown in the figure, thereby disabling the inductive amplifier latch 1720, so that the reading of the secondary inductive amplifier RSA1 no longer actively drives the DATA_A1[0] signal. In the illustrated embodiment, the duration from time T5 to T7 (i.e., the time during which the output of the secondary inductive amplifier RSA1 can effectively drive the data value D1 to DATA_A1[0]) is 0.5 ns, corresponding to an output data rate of 2 GHz.

[0194] The precharge operation of reading the secondary inductive amplifier RSA1 is the same as the precharge operation of reading the secondary inductive amplifier RSA0 described above. In fact, it is worth noting that the signal used to operate the "even-number" reading of the secondary inductive amplifier RSA0 between time T0 and time T8 is exactly the same as the signal used to operate the "odd-number" reading of the secondary inductive amplifier RSA1 between time T3 and time T9.

[0195] Note that the above operations are repeated sequentially in Figure 18, wherein during the time period from time T7 to time T8, the next data value D2 received on the global input / output line GIO0 is read out onto the DATA_A1[0] signal line, and during the time period from time T8 to time T9, the next data value D3 received on the global input / output line GIO1 is read out onto the DATA_A1[0] signal line.

[0196] Although Figures 16-18 depict data transmission from global input / output lines GIO0 and GIO1 to the corresponding DATA_A1[0] signal lines, it is understood that data is simultaneously transmitted from all global input / output lines GIO0-GIO71 to the corresponding DATA_A1[0:35] signal lines. Thus, 36-bit read data is provided at a frequency of 2 GHz on the DATA_A1[0:35] vias. Further, it is understood that if the DATA_B1 channel is also accessed, data is also transmitted in parallel from all global input / output lines GIO72-GIO143 to the corresponding DATA_B1[0:35] vias, so that 36-bit read data is also provided at a frequency of 2 GHz on the DATA_B1[0:35] signal lines.

[0197] Connect the 72-bit data received at a frequency of 1 GHz on the global input / output lines GIO0~GIO71 (and / or GIO72~GIO143) to 2 GHz frequency multitasking is to associate 36-bit data on the silicon vias with data bus DATA_A1 [0:71] (and / or DATA_B1 [0:71]), which is conducive to reducing the number of silicon vias required to implement unit stack US1 while maintaining relatively low data transmission frequencies on these silicon vias. Furthermore, operating the data bus DATA_A1 [0:71] and DATA_B1 [0:71] with a 250 mV signal swing can advantageously minimize the power demand for data transmission on the corresponding silicon vias.

[0198] Despite the specific control voltage illustrative read operation combined above, it should be understood that in other embodiments control voltages with other voltage levels may be used to correspond to specific characteristics of the unit cell UC1,1 (and the unit stack US1). For example, despite the above embodiments specifying the logic high voltage on the global bitline as 250 mV and the reference voltage VREF as 110 mV, it is understandable that in other embodiments these voltages can be increased or decreased. For example, in an embodiment (which is a transistor manufactured in accordance with MST process technology), the logic high voltage on the global bit line may be specified as 110 mV, and the reference voltage VREF may be specified as 45 mV.

[0199] Figs. Since each of these write secondary sensing amplifier circuits operates in response to a signal received on a single data line, these read secondary sensing amplifiers are “single-ended sensing amplifiers” as described herein.

[0200] The secondary inductive amplifier circuit WSA0 includes n-channel transistors 1901-1909 and 1940, p-channel transistors 1910-1915, and capacitors 1930-1931 and 1950, connected as shown in Figure 19. N-channel transistors 1905-1906 and p-channel transistors 1912-1913 are connected to form an inductive amplifier latch 1920 containing a cross-coupled inverter. P-channel transistors 1910 and 1911 form a preamplifier differential pair. N-channel transistor 1940 and capacitor 1950 form an additional input stage for providing even-numbered data values ​​to the global I / O signal line GIO0. N-channel transistor 1909 and p-channel transistor 1914 are very small components that form an inverter 1960, which, together with p-channel transistor 1915, operates as a keeper circuit, as detailed below.

[0201] As shown in Figure 20, the "odd-number" write-through secondary inductive amplifier circuit WSA1 includes n-channel transistors 2001-2009, p-channel transistors 2010-2015, and capacitors 2030-2031, connected in the same way as the "even-number" write-through secondary inductive amplifier circuit WSA0, which includes n-channel transistors 1901-1909, p-channel transistors 1910-1915, and capacitors 1930-1931. Thus, n-channel transistors 2005-2006 and p-channel transistors 2012-2013 are connected to form an inductive amplifier latch 2020 containing a cross-coupled inverter. P-channel transistors 2010 and 2011 form a preamplifier differential pair. P-channel transistor 2014 and n-channel transistor 2009 form an inverter 2060, which, together with p-channel transistor 2015, operates as a protection circuit, as detailed below.

[0202] Figure 21 is a waveform diagram illustrating the operation of the "even number" write secondary inductive amplifier circuit WSA0 and the "odd number" write secondary inductive amplifier circuit WSA1 according to an embodiment of the present invention.

[0203] At time T0, the even-numbered data value D0 is provided by processor block 1051 on data bus DATA_A1 as data signal DATA_A1[0].

[0204] At time T1, the write sampling signal wSAMPLE_E applied to the gate of the n-channel transistor 1940 in WSA0 is initiated from a logic low voltage (0 V) to a logic high voltage (250 mV or higher). Under these conditions, transistor 1940 is turned on, causing the write data value D0 on DATA_A1[0] to be applied as the input signal HOLD_E to capacitor 1950 and stored therein. In the embodiment described herein, the data value transmitted on the data bus DATA_A1 exhibits a logic low voltage to ground (0 V) and a logic high voltage of approximately 250 mV. Capacitor 1950 is large enough to ensure that no significant charge leakage occurs in this component during the time (e.g., a few nanoseconds) during which the sampled data value must be stored as the HOLD_E value.

[0205] At time T2, the odd-numbered write data value D1 is provided by processor block 1051 on data bus DATA_A1 as data signal DATA_A1[0].

[0206] At time T3, the write sampling signal wSAMPLE_E applied to the gates of n-channel transistors 1901-1902 in WSA0 and the gates of n-channel transistors 2001-2002 in WSA1 is activated from logic low (0 V) to logic high (250 mV or higher). Under these conditions, transistor 1901 of WSA0 turns on, thereby transmitting the data value D0 stored in capacitor 1950 as the HOLD_E signal, and applying it to capacitor 1930 as the write input signal wIN_E for storage. Similarly, under these conditions, transistor 2001 of WSA1 turns on, causing the data value D1 on DATA_A1[0] to be applied to capacitor 2030 as the write input signal wIN_O for storage.

[0207] Under the same conditions, transistors 1902 and 2002 will conduct, causing the reference voltage VREF to be applied to and stored by capacitors 1931 and 2031 as reference signals wREF_E and wREF_O. In the embodiments described herein, the voltage of the reference voltage VREF (and the reference signals wREF_E and wREF_O) is slightly less than half of the logic high voltage on the DATA_A1 bus (e.g., slightly less than half of 250 mV, or approximately 110 mV in one embodiment).

[0208] Inside WSA0, the input signal wIN_E stored in capacitor 1930 is applied to the gate of p-channel transistor 1910, while the input signal wREF_E stored in capacitor 1931 is applied to the gate of p-channel transistor 1911, as shown in Figure 19. Similarly, inside WSA1, the input signal wIN_O stored in capacitor 2030 is applied to the gate of p-channel transistor 2010, while the input signal wREF_O stored in capacitor 2031 is applied to the gate of p-channel transistor 2011, as shown in Figure 20.

[0209] In the embodiment, transistors 1910-1911 and 2010-201 are identical, transistors 1901-1902 and 2001-2002 are identical, and capacitors 1930-1931 and 2030-2031 are identical, thereby balancing the inputs written to the secondary inductive amplifiers WSA0-WSA1.

[0210] At time T4, the comparator enable signal wCOMP1 is written to the secondary inductive amplifier circuits WSA0 and WSA1, starting from logic low (0V) and increasing to logic high (e.g., 1.1 to 1.3V). Under these conditions, differential voltages wDOWN_E and wUP_E are generated on the drains of p-channel transistors 1910 and 1911 in WSA0, respectively, and differential voltages wDOWN_O and wUP_O are generated on the drains of p-channel transistors 2010 and 2011 in WSA1, respectively.

[0211] If the voltage of the input signal wIN_E is less than the reference voltage wREF_E (i.e., if wIN_E = 0V), then the voltage of the wDOWN_E signal will be greater than the voltage of the wUP_E signal. Conversely, if the voltage of the input signal wIN_E is greater than the reference voltage wREF_E (i.e., if wIN_E = 250 mV), then the voltage of the wDOWN_E signal will be less than the voltage of the wUP_E signal. The wUP_O and wDOWN_O signals are generated in WSA1 in a similar manner in response to the wIN_O and wREF_O signals.

[0212] At time T5, the comparator enable signal wCOMP1_E is deactivated from logic high to logic low (0V), as shown in the figure. Also at time T5, the comparator enable signal wCOMP2 is activated from logic low (0V) to logic high (e.g., 1.1 to 1.3V), thereby enabling the induction amplifier latches 1920 and 2022 inside WSA0 and WSA1.

[0213] Under these conditions, the inductive amplifier latch 1920 amplifies the difference between the differential voltages wUP_E and wDOWN_E, causing the inductive amplifier latch 1920 to store a data value representing the data value D0 received on the data bus DATAQ_A1. For example, if the wUP_E voltage is less than the wDOWN_E voltage, the latch 1920 pulls the wUP_E voltage low to ground and pulls the wDOWN_E voltage high to the voltage of the wCOMP2 signal (1.1 to 1.3 V). Conversely, if the wUP_E voltage is greater than the wDOWN_E voltage, the latch 1920 pulls the wDOWN_E voltage low to ground and pulls the wUP_E voltage high to the voltage of the wCOMP2 signal (1.1 to 1.3 V). The wUP_O and wDOWN_O signals are generated in WSA1 in a similar manner in response to the wUP_O and wDOWN_O signals.

[0214] The voltages wUP_E and wDOWN_E are applied to the gates of n-channel transistors 1907 and 1908, respectively. As described above, when the inductive amplifier latch 1920 is enabled, the wUP_E or wDOWN_E voltage is pulled up to 1.1 to 1.3V, thereby turning on the corresponding n-channel transistors 1907 or 1908, respectively. The wUP_O and wDOWN_O signals control the corresponding n-channel transistors 2007 and 2008 within WSA1 in a similar manner.

[0215] Just before time T5, the write input control signal wIN is driven from ground (0V) to a slightly boosted 350 mV voltage. Therefore, if the wDOWN_E voltage rises to 1.1 to 1.3V, the corresponding n-channel transistor 1908 will turn on, coupling the global input / output line GIO0 to ground. In this way, the data value D0 (D0 = 0) is driven onto the global input / output line GIO0 starting at time T5. Note that the ground voltage applied to GIO0 turns on the p-channel transistor 1914 within the inverter 1960, causing the Vdd supply voltage (1.1 to 1.3 V) to be applied to the gate of the p-channel transistor 1915, thus turning off transistor 1915. Therefore, when a logic low write data value is driven onto the global input / output line GIO0, the protection circuit formed by the inverter 1960 and the p-channel transistor will be turned off.

[0216] Conversely, if the wUP_E voltage rises to 1.1 to 1.3V, the corresponding transistor 1907 is turned on, thereby coupling the global input / output line GIO0 to a wIN voltage of 350 mV. In this way, the data value D0 (D0 = 1) is driven onto the global input / output line GIO0 starting at time T5. Note that the logic high voltage (350 mV) applied to GIO0 turns on the p-channel transistor 1909 in the inverter 1960, causing the ground voltage to be applied to the gate of the p-channel transistor 1915, thereby turning on this transistor 1915. The turned-on p-channel transistor 1915 maintains the voltage on the global input / output line GIO0 at the wIN voltage of 350 mV. Thus, when a logic high data value is driven onto the global input / output line GIO0, the protection circuit formed by the inverter 1960 and the p-channel transistor will be activated.

[0217] Within WSA1, the n-channel transistors 2007-2008, inverter 2060, and p-channel transistor 2015 operate as described above to drive the data value D1 onto the global input / output line GIO1 starting from time T5.

[0218] At time T7, the wCOMP2 signal is deactivated (grounded), effectively disabling the inductive amplifier latches 1920 and 2020 in WSA0 and WSA1, respectively. Shortly after time T7, the wPRE signal is activated, pre-charging the inductive amplifier latches 1920 and 2020 to ground before the next write operation. However, the data values ​​D0 and D1 remain on their respective global input / output lines GIO0 and GIO1 until time T10. Specifically, the global input / output lines GIO0 and GIO1, which are actively pulled to ground between times T5 and T7, will remain grounded until time T10 because there is no mechanism within WSA0 or WSA1 to pull the global input / output lines GIO0 and GIO1 from ground (and the capacitors associated with the global input / output lines GIO0 and GIO1, as well as the global bit line GBL, will suppress any sudden voltage changes on these global input / output lines).

[0219] Global input / output lines GIO0 and GIO1, which are actively pulled to a positive wIN voltage (350 mV) between times T5 and T7, will be maintained at this positive wIN voltage by the corresponding protection circuit until time T10. For example, if global input / output line GIO0 is actively pulled to wIN voltage (350 mV) between times T5 and T7, then the n-channel transistor 1909 and p-channel transistor 1915 of inverter 1960 will be turned on as described above. When the n-channel transistor 1907 is turned off in response to the wUP_E signal pre-charged to ground shortly after time T7, global input / output line GIO0 continues to be maintained at wIN voltage (350 mV) through the turned-on p-channel transistor 1915. Note that the small transistors (1909 and 1914) used to implement inverter 1960 allow inverter 1960 to be easily overdriven in response to the next received write data value.

[0220] In the illustrated embodiment, the period between time T0 and time T2 (i.e., the period during which data value D0 is driven to DATA_A1[0]) is 0.5 ns, corresponding to a 2 GHz input data rate on data bus DATA_A1, and the period between time T5 and time T10 is 1 ns, corresponding to a 1 GHz input data rate on global input / output lines GIO0 and GIO1.

[0221] At time T5, the above process begins again. At time T5, the next write data value D2 on the data bus DATA_A1[0] is stored in capacitor 1950 of WSA0 in response to the wSAMPLE_E signal initiated at time T6. At time T7, the next write data value D3 on the data bus DATA_A1[0] is stored in capacitor 2030 of WSA1 in response to the wSAMPLE_O signal initiated at time T8. From time T10 to time T13, write data values ​​D2 and D3 are driven to global input / output lines GIO0 and GIO1, respectively.

[0222] Although Figures 19-21 illustrate the transmission of write input data from the DATA_A1[0] signal line (TSV) to the corresponding global input / output lines GIO0 and GIO1, it is understood that the write input data is transmitted in parallel from all DATA_A1[0:35] signal lines to the corresponding global input / output lines GIO0~GIO71. In this way, 36 bits of write data can be provided at a frequency of 2 GHz on the DATA_A1[0:35] signal lines, and 72 bits of write data can be provided at a frequency of 1 GHz on the global input / output lines GIO0~GIO71. Furthermore, it can be understood that if a write operation is also performed on the DATA_B1 channel, the write input data will also be transmitted in parallel from the DATA_B1[0:35] signal lines to the corresponding global input / output lines GIO72~GIO143, thereby providing 36-bit write data at a frequency of 2 GHz on the DATA_B1[0:35] signal lines and 72-bit write input data at a frequency of 1 GHz on the global input / output lines GIO72~GIO143.

[0223] The 36-bit write data value received at 2 GHz on the DATA_A1[0:71] signal line (and / or DATA_B1[0:71] signal line) is demultiplexed onto the 72-bit global input / output lines GIO0~GIO71 (and / or GIO72~GIO143) operating at 1 GHz, which advantageously reduces the number of silicon vias required to implement the unit stack US1, while maintaining a relatively low data transmission frequency on these silicon vias.

[0224] The control signals used for operating the read and write operations of the secondary inductive amplifier are generated by the secondary inductive amplifier driver circuit SSAD1,1 (as shown in Figure 6). The secondary inductive amplifier driver circuit SSAD1,1 generates the control signals required to control the read operation of the secondary inductive amplifier (i.e., SAMPLE_E, SAMPLE_O, COMP1_E, COMP1_O, COMP2_E, COMP2_E, PRE_E, PRE_O, OUT_EVEN, and OUT_ODD) in response to the signals specified on the receive command bus INST1 for reading and accessing the unit cell UC1,1 (e.g., RW = 0, UC[3:0] = 0001, CLK). Similarly, the secondary inductive amplifier driver circuit SSAD1,1 generates the control signals required to control the writing to the secondary inductive amplifier (i.e., wSAMPLE_E, wSAMPLE_O, wCOMP1, wCOMP2, wPRE, and wIN) in response to the signals specified on the receive command bus INST1 for writing access to cell UC1,1 (e.g., RW = 1, UC[3:0] = 0001, CLK). As described above in conjunction with Figure 6, in one embodiment, the secondary inductive amplifier driver circuit SSAD1,1 is located at the center inside the secondary inductive amplifier circuit SSA1,1. In one embodiment, the secondary inductive amplifier driving circuits SSAD1,1 control the secondary inductive amplifier segments SSA(1,1)A and SSA(1,1)B respectively. The secondary inductive amplifier segment SSA(1,1)A is activated only when accessing one of the subarray columns CoSA0 to CoSA3, while the secondary inductive amplifier segment SSA(1,1)B is activated only when accessing one of the subarray columns CoSA4 to CoSA7.

[0225] [, Addressing , ] [, / , ] [, Data path , ] The following details the signals included on the instruction bus INST1 for accessing the unit cells UC1,1, UC2,1, UC3,1, and UC4,1 of the unit stack US1, and the access modes that can be implemented within the unit stack US1. It should be understood that any combination (including all) of the unit stacks US1 to US2048 in the MTDRAM system 100 can be accessed simultaneously and independently in parallel using the addressing implementation described below, thereby advantageously providing high data bandwidth within the MDRAM system 100.

[0226] Figure 22 illustrates the format of an instruction 2200 for accessing a unit stack US1 according to an embodiment of the present invention. The unit stack access instruction 2200 is routed to each unit cell UC1,1, UC2,1, UC3,1 and UC4,1 on the dedicated instruction bus INST1, as shown in Figure 4.

[0227] Instruction 2200 includes the unit cell address field UC[3:0], the stripe address field STRIP[15:0] shared by data channels DATA_A1 and DATA_B1, the main word line address field MWL[11:0] shared by data channels DATA_A1 and DATA_B1, the subarray column address field CoSAA[3:0] associated with data channel DATA_A1, the subarray column address field CoSAB[3:0] associated with data channel DATA_B1, the subword line address field SWLA[7:0] associated with data channel DATA_A1, the subword line address field SWLB[7:0] associated with data channel DATA_B1, the Y column address field Y-DEC[7:0] shared by data channels DATA_A1 and DATA_B1, and the read / write signal field RW shared by data channels DATA_A1 and DATA_B1.

[0228] The cell address field UC[3:0] specifies the cell to be accessed according to the instruction (cells UC1,1, UC2,1, UC3,1, and UC4,1). The signal in the cell address field UC[3:0] is fully pre-decoded, so when the signals UC[3], UC[2], UC[1], and UC[0] are activated, they specify access to cells UC1,1, UC2,1, UC3,1, and UC4,1, respectively. The cell address UC[3:0] can specify at most one cell for access. For example, access to cell UC1,1 is specified by the UC[3:0] value "0001", and access to cell UC3,1 is specified by the UC[3:0] value "0100".

[0229] The stripe address field STRIP[15:0] specifies which of the 16 stripes in the selected cell should be accessed. In the embodiment described, the stripe address value STRIP[15:0] specifies a single stripe. At startup, the pre-decoding stripe address bits STRIP

[15] to STRIP[0] of instruction 2200 specify the stripes S(x,1)15 to S(x,1)0 (where x = 1 to 4) inside the addressed cell UCx,1, respectively. Therefore, the access to stripe S(1,1)14 of cell UC1,1 is specified by the cell address value UC[3:0] "0001" and the stripe address value STRIP[15:0] "0100 0000 0000 0000". Similarly, the access to the stripe S(2,1)1 of cell UC2,1 is specified by the cell address UC[3:0] "0010" and the stripe address STRIP[15:0] "0000 0000 0000 0010".

[0230] The Master Word Line Address field MWL[11:0] specifies which of the 32 Master Word Lines in the specified stripe should be activated. The signals in the Master Word Line Address field MWL[11:0] are partially pre-decoded, where the signals MWL[11:0] are used to select one of the 32 Master Word Lines within the selected stripe. In one embodiment, eight Master Word Line Address signals MWL[4:11] are used to select one of eight groups of four Master Word Lines, and four Master Word Line signals MWL[0:3] are used to select one of the four Master Word Lines in the selected group.

[0231] Figure 23 illustrates, according to one embodiment, the main word line decoder circuit MWD0 associated with stripe S(1,1)0 of unit cell UC1,1. The main word line decoder circuit MWD0 includes 3-input AND gates AND0~AND32, connected as shown in the figure. If the received instruction specifies access to stripe S(1,1)0 of unit cell UC1,1 (i.e., UC[0] = 1 and STRIP[0] = 1), then AND gate AND32 provides a logic high output signal to each of the 32 AND gates AND0~AND31 of the main word line decoder circuit MWD0. Each of the 8 main word line address signals MWL[4:11] is provided to a corresponding set of 4 AND gates. Specifically, MWL[4] is provided to AND gates AND0~AND3, MWL[5] is provided to AND gates AND4~AND7, ..., and MWL

[11] is provided to AND gates AND28~AND31. During a single access, only one of the signals MWL[4:11] is activated.

[0232] Each of the four main word line address signals MWL[3:0] is provided to each of the eight AND gates. Specifically, signals MWL[0]~MWL[3] are provided to AND gates AND0~AND3, AND gates AND4~AND7, ..., and AND gates AND28~AND31, respectively. In a single access, only one of the signals MWL[3:0] is activated. Thus, in a single access to stripe S(1,1)0 of unit cell UC1,1, one of the 32 main word lines MWL0~MWL31 is activated. Since only two main word line address signals MWL[11:0] are activated during a single access, energy saving is achieved within the unit stack US1. Although a specific decoding circuit for activating the signals required to activate the main word lines MWL0~MWL32 has been described, it should be understood that other decoding circuits are possible and will be apparent to those skilled in the art.

[0233] Please note that each unit cell UC1,1, UC2,1, UC3,1, and UC4,1 includes a corresponding centrally located master word line decoder circuit, which has the same circuitry as the master word line decoder circuit MWD0, as shown in Figure 6. Each master word line decoder circuit operates according to the corresponding stripe address bits and the corresponding unit cell address bits. The timing of the master word line address signals MWL[0:11] is controlled to provide the required timing for the master word line signal MWL0. This timing is detailed in U.S. Patent Application No. 18 / 399,579, the entire contents of which are incorporated herein by reference.

[0234] The fully pre-decoded subarray column address field CoSAA[3:0] specifies one of the four subarray columns CoSA0~CoSA3 associated with data channel DATA_A1 (or may not specify), and the fully pre-decoded subarray column address field CoSAB[3:0] specifies one of the four subarray columns CoSA4~CoSA7 associated with data channel DATA_B1 (or may not specify). For example, a value of "0001" for subarray column address CoSAA[3:0] indicates that subarray column COSA0 is selected for access on data channel DATA_A1, and a value of "0010" for subarray column address CoSAB[3:0] indicates that subarray column CoSA5 is selected for access on data channel DATA_B1.

[0235] The subarray column address signals CoSAA[3:0] and CoSAB[3:0] are used in conjunction with the unit cell signal UC[3:0] and the strip address signal STRIP[15:0] to generate subarray column address signals (e.g., EN_SUBA0,0) to allow the sub-word line drive circuits and primary induction amplifier sub-circuits in the subarray to be accessed.

[0236] Figure 24 illustrates, according to one embodiment, a subarray decoder circuit 2400 associated with stripe S(1,1)0 of unit cell UC1,1. In this embodiment, the subarray decoder circuit 2400 is located centrally within stripe S(1,1)0, adjacent to the corresponding main character line decoder circuit MWD0. It is understood that each stripe of the unit stack US1 has a corresponding subarray decoder circuit similar to the subarray decoder circuit 2400, wherein each subarray decoder circuit operates based on the corresponding stripe address bits and the corresponding unit cell address bits.

[0237] The subarray decoder circuit 2400 includes eight NAND gates 2410-2417, as shown in the figure. Each of these NAND gates 2410-2417 is coupled to the output of the NAND gate NAND32 (Figure 23). Therefore, when the corresponding character line decoder circuit MWD0 is activated, the subarray decoder circuit 2400 is also activated. NAND gates 2410 to 2413 are also coupled to receive subarray column address signals CoSAA[0] to CoSAA[3], respectively. NAND gates 2414 to 2417 are also coupled to receive subarray column address signals CoSAB[0] to CoSAB[3], respectively. The outputs of NAND gates 2410 to 2417 provide subarray enable signals EN_SUBA0,0 to EN_SUBA0,7, respectively. As described above in conjunction with Figure 7, subarray enable signals EN_SUBA0,7 to EN_SUBA0,7 are provided to enable the sub-word line drive circuits in subarrays SUBA0,0 to SUBA0,7, respectively. In this embodiment, the subarray enable signals EN_SUBA0,0 to EN_SUBA0,7 are activated as low voltage (i.e., the corresponding sub-word line drive circuit is enabled when a logic low voltage is present), consistent with the manner described in U.S. Patent Application No. 18 / 399,579.

[0238] At most one subarray column address signal CoSAA[3:0] is activated high, therefore in any given access, only one (or none) of the signals EN_SUBA0,0,EN_SUBA0,1,EN_SUBA0,2, andEN_SUBA0,3 is activated low. Similarly, at most one subarray column address signal CoSAA[3:0] is activated high, therefore in any given access, only one (or none) of the signals EN_SUBA0,4,EN_SUBA0,5,EN_SUBA0,6, andEN_SUBA0,7 is activated low.

[0239] For example, when the subarray column address signal CoSAA[3:0] has a value of "0001", the EN_SUBA0,0 signal is activated, thereby activating the sub-word line driver in subarray SUBA0,0 (see Figure 7). When the subarray column address signal CoSAB[3:0] has a value of "0010", the EN_SUBA0,5 signal is activated, thereby activating the sub-word line driver in subarray SUBA0,5. If the subarray column address signal CoSAA[3:0] has a value of "0000", then subarrays SUBA0,0, SUBA0,1, SUBA0,2, or SUBA0,3 will not be activated (i.e., no data is read on the corresponding data channel DATA_A1). Similarly, when the subarray column address signal CoSAB[3:0] has a value of "0000", no data will be read on the corresponding data channel DATA_B1. The timing of the subarray column address signals CoSAA[3:0] and CoSAB[3:0] is controlled to provide the required timing for the subarray enable signals EN_SUBA0,0 to EN_SUBA0,7. This timing is described in detail in U.S. Patent Application No. 18 / 399,579, the entire contents of which are incorporated herein by reference.

[0240] As described above in conjunction with Figure 7, each main word line is coupled to eight corresponding sub-word lines. For example, the main word line MWL0 is connected to eight corresponding sub-word lines SWL0,0 to SWL7,0 via sub-word line driver circuits SWD0,0 to SWD7,0. The sub-word line address values ​​SWLA[7:0] include eight pre-decoded sub-word line address signals, each associated with one of the eight sub-word lines associated with the activated main word line of the data channel DATA_A1. For example, if instruction 2200 specifies the main word line MWL0 of stripe S(1,1)0 of subarray SUBA0,0, the activated sub-word line address signal SWLA[x] is used to activate the sub-word line SWLx,0 associated with the activated main word line MWL0. In this embodiment, the sub-word line address signals SWLA[7:0] and SWLB[7:0] are in a logic low state when "activated". In detail, the sub-word line address value SWLA[7:0] with the value "1111 1110" (i.e., SWLA[0] is enabled) is used to enable the sub-word line SML0,0 associated with the enabled main word line MWL0.

[0241] Each sub-word line address value SWLAA[7:0] is provided to the corresponding sub-word line driver circuit associated with the corresponding sub-word line. For example, in Figure 7, each sub-word line address value SWLAA[x] is provided to the corresponding sub-word line driver circuit SWDx,0 (where x = 0 to 7).

[0242] When the sub-word line driver circuit receives the enabled subarray signal EN_SUBA, the enabled master word line signal, and the enabled sub-word line address signal, the sub-word line driver circuit drives the corresponding sub-word line to a high state to access the bits coupled to the sub-word line. For example, if instruction 2200 specifies the master word line MWL0 of strip S(1,1)0 of subarray SUBA0,0 in unit cell UC1,1, and the sub-word line address value SWLA[7:0] specifies the sub-word line SWL0,0 associated with the enabled master word line MWL0, then MWL0, EN_SUBA0,0 and SWLA[0] signals will all be enabled, thereby enabling the sub-word line driver SWD0,0 to enable the sub-word line SWL0,0, thereby accessing bits bc0,0 to bc0,575. In one embodiment, the enabled sub-word line address value SWLA[0] is controlled to transition to a logic high state, and then transitions to a boost logic high state during access to sub-word line SWL0,0. This process is described in detail in U.S. Patent Application Serial No. 18 / 399,579, the entire contents of which are incorporated herein by reference.

[0243] As described above in conjunction with Figures 7 and 8, in response to the activated EN_SUBA0,0 signal, the data read from bits bc0,0~bc0,575 is latched into the corresponding primary induction amplifier subcircuits PSA0,0 and PSA1,0.

[0244] Similarly, the sub-word line address value SWLB[7:0] is a pre-decoding address value that specifies one of the eight sub-word lines associated with the activated master word line in data channel DATA_B1. In the embodiment described, the sub-word line address value SWLB[7:0] is independent of the sub-word line address value SWLA[7:0], thus allowing access to different sub-word lines in data channels DATA_A1 and DATA_B1. This advantageously provides flexibility for addressing subarrays within these two data channels. In an alternative embodiment, a single sub-word line address value SWL[7:0] is used to select the sub-word line in both data channels DATA_A1 and DATA_B1. This embodiment advantageously reduces the number of silicon vias required to implement the unit stack US1 by eight.

[0245] As described above in conjunction with Figures 8-10, instruction 2200 further includes a pre-decoded Y address value Y-DEC[7:0], which selects one of the eight 72-bit data values ​​stored in the primary induction amplifier sub-circuit during access.

[0246] Instruction 2200 further includes a read / write control bit (RW), which indicates whether the corresponding access is a read operation or a write operation.

[0247] Therefore, the pre-decoding instruction 2200 requires 65 TSVs in the corresponding TSV region of the unit cell. Adding the 72 TSVs required to implement the two 36-bit data buses DATA_A1 and DATA_B1, and the vias required to provide the clock signal CLK, the entire unit stack US1 requires a total of 138 TSVs. In an alternative embodiment where the two data channels DATA_A1 and DATA_B1 share a single sub-word line address, the unit stack US1 requires only a total of 130 TSVs.

[0248] The following describes the dimensions of cell UC1,1 and the via layout of cell UC1,1.

[0249] [, Unit cell height , ] According to the above embodiment, the vertical height of each MTDRAM bit cell (e.g., bit cell bc0,0 in Figure 7) along the Y-axis in unit cell UC1,1 is 0.0243 micrometers (µm). In the embodiment of Figure 8, each subarray of unit cell UC1,1 includes 576 columns of bit cells, and each stripe includes 8 subarrays. In this embodiment, the required Y-axis height of the bit cell is approximately 112 micrometers (0.0243 micrometers x 576 bit cells / subarray x 8 subarrays / strip).

[0250] In the embodiment shown in Figure 8, each unit cell UC1,1 includes eight sub-word line driver circuits and one main word line driver circuit along the Y-axis. Assuming that the height of each sub-word line driver circuit along the Y-axis is approximately 1.86 micrometers and the height of the main word line driver circuit along the Y-axis is approximately 7 micrometers, the required Y-axis height for the sub-word line driver circuit and the main word line driver circuit is approximately 22 micrometers (1.855 micrometers x 8 + 7 micrometers).

[0251] Therefore, the total height of cell UC1,1 along the Y-axis is approximately 134 micrometers (112+22). Assuming a via spacing of 2 micrometers, a row of vias extending along the height of cell UC1,1 can contain a maximum of approximately 67 vias.

[0252] Figure 25 illustrates the layout of the 137 silicon vias required for cell UC1,1 in the manner described above. It is noteworthy that cells UC2,1, UC3,1, and UC4,1 have the same silicon via pattern as cell UC1,1 to facilitate the connections required for the corresponding unit stack US1. The silicon via pattern in Figure 25 utilizes three rows of silicon vias adjacent to the secondary inductive amplifier SSA1,1. Each row of silicon vias contains 44 or fewer silicon vias, thus easily allowing this silicon via pattern to be set within a 134-micron height of cell UC1,1.

[0253] In the embodiment shown in Figure 25, the 12 vias carrying the main word line address MWL[11:0] are located in the center (below the main word line driver circuit MWD). Six of these vias are located in the open space between the secondary inductive amplifier circuits SSA(1,1)A and SSA(1,1)B, and / or in the open space between the multiplexer circuits MUX(1,1)A and MUX(1,1)B, as shown in the figure. The remaining six vias are located in the three rows of vias below the secondary inductive amplifiers SSA1,1, as shown in the figure.

[0254] The shaded circles in Figure 25 illustrate the 36 silicon vias required to implement the DATA_A1[35:0] bus. Note that these silicon vias are evenly distributed along the width of the secondary inductive amplifier circuit SSA(1,1)A, with the 9 bits of the DATA_A1[35:0] bus located on each of the four subarray columns CoSA0~CoSA3, thereby minimizing signal delay and power consumption.

[0255] The black circles in Figure 25 illustrate the 36 silicon vias required to implement the DATA_B1[35:0] bus. Note that these silicon vias are evenly distributed along the width of the second-stage inductive amplifier circuit SSA(1,1)B, where the 9 bits of the DATA_B1[35:0] bus are located on each of the four subarray columns CoSA4~CoSA7.

[0256] The via distribution required to implement the UC[3:0] address value, STRIP[15:0] address value, CoSAA[3:0] and CoSAB[3:0] address values, SWLA[7:0] and SWLB[7:0] address values, Y-DEC[7:0] address value, RW value and CLK signal is shown in Figure 25.

[0257] According to one embodiment, the via pattern is selected such that most of the vias are located at the center of the unit cell UC1,1 (along the Y-axis). That is, the via pattern is sparsely distributed along the outer edge of the Y-axis (i.e., below subarray columns CoSA0~CoSA1 and CoSA6~CoSA7). As detailed below, these sparsely distributed via regions advantageously provide space for routing structures extending along the X-axis on the underlying processor block 1051.

[0258] Once the via configuration of unit cell UC1,1 is determined, the width of unit cell UC1,1 along the X-axis can be determined.

[0259] [, Unit grid width , ] According to the above embodiment, the width of each MTDRAM bit cell (e.g., bit cell bc0,0 in Figure 7) of unit cell UC1,1 along the X-axis is 0.0383 micrometers. In the embodiment of Figure 8, each strip of unit cell UC1,1 includes 256 columns of bit cells, for a total of 16 stripes. In this embodiment, the required X-axis width of the bit cell is approximately 156.88 micrometers (0.0383 micrometers x 256 bit cells / strip x 16 stripes / unit cell).

[0260] In the embodiment shown in Figure 6, the unit cell UC1,1 includes 17 primary induction amplifier circuits PSA0 to PSA16. Assuming that the width of each primary induction amplifier circuit along the X-axis is approximately 2.65 micrometers, the required width of these primary induction amplifier circuits along the X-axis is approximately 45.05 micrometers (2.65 micrometers x 17).

[0261] In the embodiment of Figure 6, the unit cell UC1,1 further includes a multiplexer MUX1,1 and a secondary inductive amplifier circuit SSA0,0. In one embodiment, the width of the multiplexer MUX1,1 and the secondary inductive amplifier circuit SSA0,0 along the X-axis is approximately 10 micrometers (based on the circuits of Figures 14-20).

[0262] According to the embodiment in Figure 25, the unit cell UC1,1 requires three rows of silicon vias with a spacing of 2 micrometers. Therefore, the required width of the silicon via group TSV1,1 along the X-axis is approximately 6 micrometers.

[0263] Therefore, in the embodiment described, the required total width of the unit cell UC1,1 along the X-axis is approximately 222 micrometers (156.88 micrometers + 45.05 micrometers + 10 micrometers + 4 micrometers + 6 micrometers).

[0264] Since the MTDRAM chip 101 comprises 64 rows and 32 columns of unit cells UC1,1 to UC1,2048 (Figure 2), the total width required along the X-axis of the chip 101 is approximately 7.1 mm (32 × 222 μm), and the total height required along the Y-axis is approximately 8.6 mm (64 x 134 μm). Therefore, the MTDRAM chip 101 has an advantageous size compared to conventional manufacturing practices. This is because the ASIC controller chip 105 performs a large amount of signal pre-decoding to access all four MTDRAM chips 101 to 104. Furthermore, obsolete functions, such as self-refresh and other area-consuming functions typically included in conventional DRAM, are either completely removed or implemented on the ASIC controller chip 105.

[0265] In alternative embodiments of the invention, the number of subarrays per stripe and the number of stripes per unit cell can be modified as needed to make the unit cell size larger or smaller. In a "tiny cell" embodiment, the number of subarrays per stripe is reduced from 8 to 4, and the number of stripes per unit cell is reduced from 16 to 8. This "tiny cell" configuration can increase the number of unit cells per die from 2048 to 8192, thereby significantly increasing the addressable locations within the MTDRAM system.

[0266] The random access cycle time for the same stripe is 4 ns, while the random access cycle time for a "legitimate" stripe (i.e., a stripe not subject to the aforementioned precharge conditions) is 1 ns. Therefore, for 72-bit data, the near-random access rate of the MTDRAM system 100 is 1 GHz / channel x 2 channels / unit stack x 2048 unit stacks = 4.096E+12. This near-random access rate is approximately 12,800 times the 3.2E+08 semi-random addressing rate achieved by conventional HBM3 memory.

[0267] The MTDRAM system employing the "micro-lattice" implementation will exhibit near-random access speeds, i.e., 1 GHz / channel x 2 channels / unit stack x 8192 unit stacks = 1.6384E+13, which is approximately 51,200 times the semi-random addressing speed of 3.2E+08 achievable by conventional HBM3 memory.

[0268] As described above, the data rate of the DATA_A1 and DATA_B1 channels implemented on the silicon via is 2 Gb / sec / pin. This data rate is advantageously lower than the 5.2 Gb / sec / pin data rate of conventional HBM3 memory, thereby significantly saving power.

[0269] As described above, each unit stack of the MTDRAM system 100 contains 72 silicon vias to carry data signals. Since the MTDRAM system 100 contains 2048 unit stacks, there are a total of 147,456 silicon vias available for carrying data in the MTDRAM system 100. Since the data transfer rate on each silicon via is 2 Gb / s, the total data rate of the MTDRAM system 100 is 147,456 x 2 Gb / s = 294,912 Gb / s. This total data rate is approximately 55 times that of a conventional HBM3 memory system, which has a total data rate of approximately 5,325 Gb / s. This total data rate is also approximately 16 times that of a conventional HBM3E memory system, which has a total data rate of approximately 18,842 Gb / s.

[0270] The MTDRAM system employing the "micro-grid" embodiment will consist of 8,192 stacked units, with a total of 589,824 silicon vias available for carrying data. Since the data transfer rate on each silicon via is 2 Gb / s, the total data rate of the MTDRAM system employing the "micro-grid" embodiment is 589,824 x 2 Gb / s = 1,179,648 Gb / s.

[0271] According to other embodiments of the present invention, the single-ended inductive amplifier included in the primary inductive amplifier circuit may have a configuration other than that described above in conjunction with Figures 8, 11A and 11B.

[0272] Figure 26 is a circuit diagram of single-ended inductor amplifiers SA'0,1 and SA'0,3 of the primary inductor amplifier circuit PAS1,0 according to an embodiment of the present invention. The single-ended inductor amplifiers SA'0,1 and SA'0,3 are similar to those in Figure 8, but with the following differences: The single-ended inductor amplifiers SA'0,1 and SA'0,3 do not include the jumper capacitors 821-824 of the single-ended inductor amplifiers SA0,1 and SA0,3. Furthermore, the single-ended inductor amplifiers SA'0,1 and SA'0,3 do not require an NCOM control signal (which is coupled to the n-channel transistors N1-N4 of the single-ended inductor amplifiers SA0,1 and SA0,3). Instead, in the single-ended inductor amplifiers SA'0,1 and SA'0,3, the sources of the n-channel transistors N1-N4 are simply connected to ground (0V). Advantageously, the primary induction amplifier drive circuit PSAD1,0 in Figure 26 does not require the generation of a jump voltage signal Vk or NCOM signal as described above in conjunction with Figures 11A-11B.

[0273] According to this embodiment, the sources of the pre-charged n-channel transistors N12 and N14 are coupled to receive the reference voltage signal Vref. As detailed below, the pre-charged n-channel transistors N12 and N14 are controlled to apply the reference voltage signal Vref to the internal nodes INT0# and INT2#, respectively. Note that in this embodiment, the primary induction amplifier driver circuit PSAD1,0 of FIG26 generates the reference voltage signal Vref.

[0274] Before describing the operation of single-ended sense amplifiers SA'0,1 and SA'0,3, the operating characteristics of a conventional dual-ended sense amplifier are described for comparison. A conventional dual-ended sense amplifier is coupled to the bit line of the cell being read and also to a dummy bit line. This bit line and the dummy bit line are pre-charged to an intermediate voltage, which is half the logic "1" voltage of the cell being written. For example, if the logic "1" voltage of the cell being written is 1.1 volts, the pre-charge voltage of the bit line is 550 mV. DRAM cells lose charge over time and therefore must be refreshed periodically. In one example, the refresh interval of a DRAM cell is 32 milliseconds, where the voltage of the "1" bit stored in the cell drops by approximately 14% at the end of the 32-millisecond refresh interval. In the example described herein, the DRAM cell is refreshed when the logic "1" bit voltage reaches 0.95 V.

[0275] During a read operation, the change in bit line voltage (ΔV) is defined by the following formula: ΔV = (Vbitcell – VBLP) / (1+ CB / CS), Where Vbitcell is the DRAM bit cell voltage stored during a read operation (e.g., 1.1 to 0.95 V), VBLP is the precharge voltage of the bit line (e.g., 0.55 V), CB is the capacitance of the bit line, and CS is the capacitance of the DRAM bit cell. Common values ​​for CB / CS are 4, 6, and 8. Therefore, in a conventional two-ended inductor amplifier, when CB / CS is 4, 6, and 8, ΔV is approximately 80 mV, 57 mV, and 44 mV (at the end of the 32 ms refresh interval), respectively. Note that a bit line read in one direction (e.g., pulled up in response to a logic "1" bit cell) may be adjacent to other bit lines read in the opposite direction (e.g., in response to a logic "0" bit cell). In this case, due to bit line coupling, the voltage of the bit line being read in one direction may be pulled in the other direction. Common bit line coupling estimates include 15%, 25%, and 35%. In the example of the conventional two-ended inductor amplifier described above, the aforementioned ΔV value of 80 / 57 / 44 mV will be reduced to 60 / 43 / 33 mV (for CB / CS values ​​of 4 / 6 / 8 respectively), indicating that the effect of adverse bit line coupling is 25%.

[0276] According to one embodiment, the reference voltage Vref implemented within the single-ended inductor amplifiers SA'0,1 and SA'0,3 of FIG26 is selected to provide an equivalent ΔV relative to the aforementioned dual-ended inductor amplifier. According to this embodiment, the logic "0" cell value is 0 V (e.g., bit line bc0,1 is pulled down to 0 V to write the logic "0" value to the corresponding bit cell bc0,1). Therefore, when a logic "0" value is read from bit cell bc0,1 (or bc0,3), the voltage on the corresponding bit line bc0,1 (or bc0,3) will be equal to 0 V (ignoring poor bit line coupling). To obtain a ΔV value of 60 / 43 / 33 mV (to match the performance of the aforementioned dual-ended inductor amplifier), the Vref rating should be 60 / 43 / 33 mV (corresponding to DRAM systems with CB / CS = 4 / 6 / 8, respectively). At this point, the nominal value of the logic "1" read on bit lines bl0,1 (or bl0,3) should be equal to 120 / 86 / 66 mV (i.e., 60 / 43 / 33 mV + 60 / 43 / 33 mV = 120 / 86 / 66 mV). To achieve a read bit line voltage of 120 / 86 / 66 mV based on CB / CS = 4 / 6 / 8, the corresponding bit cell voltage must be at least 600 / 602 / 594 mV (i.e., 120 / 86 / 66 mV x (1+4) / (1+6) / (1+8) = 600 / 602 / 594 mV). To ensure that the minimum bit cell voltage at the end of the refresh interval is at least 600 / 602 / 594 mV, the DRAM bit cell should initially be written with approximately 14% higher bit cell voltage, i.e., 698 / 700 / 691 mV. At this point, the maximum read bit line voltage (assuming the read operation occurs immediately after the refresh operation) is approximately 140 / 100 / 77 mV (i.e., 698 / 700 / 691 mV divided by (1+4) / (1+6) / (1+8) = 140 / 100 / 77 mV).

[0277] Suppose that the bit line reading logic "0" is affected by 25% bad bit line coupling from the adjacent bit line reading logic "1". The bit line reading logic "0" might be pulled up from 0 V to 35 / 25 / 19 mV (i.e., 140 / 100 / 77 mV x 25% = 35 / 25 / 19 mV). To compensate for this bit line coupling, the value of Vref can be increased to 95 / 68 / 52 mV (because the voltage level of the logic "0" bit line can be pulled up from 0 V to 35 / 25 / 19 mV through bad bit line coupling; the Vref rating is increased from 60 / 43 / 33 mV, providing 95 / 68 / 52 mV by adding 35 / 25 / 19 mV). At this point, the rated value of the logic "1" read on bit lines bl0,1 (or bl0,3) should be adjusted upwards to at least 155 / 111 / 85 mV (i.e., 95 / 68 / 52 mV + 60 / 43 / 33 mV = 155 / 111 / 85 mV) to maintain the specified ΔV value of 60 / 43 / 33 mV. In order to achieve a read bit line voltage of 155 / 111 / 85 mV based on CB / CS = 4 / 6 / 8, the corresponding bit grid voltage must be at least 775 / 777 / 765 mV (i.e., 155 / 111 / 85 mV x (1+4) / (1+6) / (1+8) = 775 / 777 / 765 mV). To ensure that the minimum grid voltage at the end of the refresh interval is at least 775 / 777 / 765 mV, the DRAM grid should initially be written with approximately 14% higher grid voltage, i.e., 901 / 904 / 890 mV. In this case, the maximum read bit line voltage (assuming the read operation occurs immediately after the refresh operation) is approximately 180 / 129 / 99 mV for CB / CS = 4 / 6 / 8 respectively (i.e., 901 / 904 / 890 mV divided by (1+4) / (1+6) / (1+8) = 180 / 129 / 99 mV).

[0278] Assuming a 25% faulty bit line coupling from an adjacent bit line reading a logic "1" value, the bit line reading a logic "0" value might be pulled up from 0 V to 45 / 32 / 25 mV (i.e., 180 / 129 / 99 mV x 25% = 45 / 32 / 25 mV). Similarly, to compensate for this bit line coupling, the value of Vref can be increased to 105 / 75 / 58 mV (i.e., because the voltage level of the logic "0" bit line can be pulled up from 0 V to 45 / 32 / 25 mV through faulty bit line coupling, the value of Vref is adjusted to 60 / 43 / 33 mV + 45 / 32 / 25 mV = 105 / 75 / 58 mV).

[0279] As mentioned above, adjusting the Vref value may require adjusting the nominal voltage of the logic "1" read on the bit line, the logic "1" bit cell voltage, and the bit cell coupling voltage (which in turn requires adjusting the Vref value). After several iterations, these adjustments converge to a final set of values, where the final iteration is selected based on the precision required for the specific application. In this example, after four iterations, the bit line coupling voltage is 49 / 35 / 27 mV, the reference voltage Vref is 109 / 78 / 60 mV, the nominal logic "1" read bit line voltage is 169 / 121 / 93 mV, and the full DRAM bit cell voltage is 983 / 985 / 973 mV (corresponding to CB / CS = 4 / 6 / 8, respectively). Having determined these voltages (to establish an equivalent ΔV to that of a conventional two-ended inductor amplifier), the operation of the single-ended inductor amplifiers SA'0,1 and SA'0,3 is described below.

[0280] In the example below, read access is performed on the bit cells bc0,1 and bc0,3, which are coupled to bit lines bl0,1 and bl0,3 respectively. Bit cell bc0,1 stores the logic "1" bit cell voltage, and bit cell bc0,3 stores the logic "0" bit cell voltage. As shown in the figure, bit cells bc0,1 and bc0,3 are coupled to receive a common sub-word line signal SWL0,0.

[0281] Figure 27 illustrates the signal waveforms related to the read and access of bits bc0,1 and bc0,3.

[0282] At time T0, sub-word lines SWL0,0 are logic low (0V), and the reference voltage signal Vref is grounded (0V). Precharge control voltages PRE0 and PRE1 are activated high (1V), turning on precharge transistors N11-N14. Under these conditions, internal nodes INT0 / INT0# and INT2 / INT2# are pulled down to ground. ISOS0 and ISOS1 signals are deactivated low (0V), isolating single-ended inductors SA0,1 and SA0,3 from bit lines bl0,1 and bl0,3 (and bit lines bl1,1 and bl1,3). The PCOM signal remains logic low (0V), and bit lines bl0,1 and bl0,3 are precharged to ground (0V).

[0283] The read operation begins at time T1. Before time T1, the reference voltage signal Vref is driven to a predetermined positive voltage, thereby pre-charging the voltages on internal nodes INT0# and INT2# to the predetermined reference voltage Vref, i.e., 109 / 78 / 60 mV (corresponding to CB / CS = 4 / 6 / 8 respectively). As detailed below, the read voltages generated on bit lines bl0,1 and bl0,3 are compared with the reference voltage Vref inside the induction amplifier circuits SA'0,1 and SA'0,3 respectively.

[0284] Since there is little or no current flowing on the bit lines reading logic "0" (because the bit lines are pre-charged to 0V and remain near 0V during the read operation), there is no significant undesirable bit line coupling associated with reading logic "1" values. Therefore, when reading a logic "1" value from bit cell bc0,1 (or bc0,3), in order to obtain a ΔV value of 60 / 43 / 33 mV (to match the performance of the aforementioned dual-ended induction amplifier), the voltage generated on the read bit lines should be at least greater than the sum of the Vref reference voltage of 109 / 78 / 60 mV and the ΔV value of 60 / 43 / 33 mV, i.e., 169 / 121 / 93 mV. The logic "1" bit read line voltage of 169 / 121 / 93 mV is converted to a bit grid voltage of 845 / 847 / 837 mV for CB / CS = 4 / 6 / 8 (i.e., 169 / 121 / 93 mV x (1+Cb / Cs) = 845 / 847 / 837 mV). To ensure that the minimum bit grid voltage at the end of the refresh interval is 845 / 847 / 837 mV, the bit grid should initially be written with approximately 14% higher full bit grid voltage, i.e., 983 / 985 / 973 mV (corresponding to CB / CS = 4 / 6 / 8).

[0285] Returning to Figure 27, at time T1, sub-word line SWL0,0 is activated to a high voltage (1.5V). Under these conditions, read voltages are generated on bit lines bl0,1 and bl0,3, which depend on the data value stored in the corresponding bit cell coupled to these bit lines. In the illustrated embodiment, bit line bl0,1 is initially pulled up from the bit line precharge voltage 0V to the voltage level of the logic "1" read bit line (e.g., 169 / 121 / 93 mV or higher as described above). Although bit line bl0,3 should remain at the logic "0" value, i.e., 0V, in the worst case, bit line bl0,3 is surrounded by multiple adjacent bit lines, all of which are pulled up to the logic "1" read voltage potential. In this case, due to poor bit line coupling with the logic "1" read voltage generated on adjacent bit lines bl0,1 and other connected bit lines, bit line bl0,3 initially pulls up slightly from the bit line precharge voltage 0V. As mentioned above, this poor bit line coupling may pull the voltage on bit line bl0,3 up to approximately 49 / 35 / 27 mV (corresponding to CB / CS = 4 / 6 / 8).

[0286] Also at time T1, the precharge control signal PRE0 is deactivated to low voltage (0V), thereby turning off the n-channel transistors N11 and N13, so that the internal nodes INT0 and INT2 no longer actively pull down to ground.

[0287] At time T2 (shortly after time T1), the ISOS0 signal is activated at a high voltage (1.5V), thereby turning on the n-channel transistors 801 and 802. This applies the read voltages generated on bit lines bl0,1 and bl0,3 to internal nodes INT0 and INT2, respectively. Therefore, as shown in Figure 27, the voltage on internal node INT0 begins to increase towards the logic "1" read bit line voltage of 169 / 121 / 93 mV, while due to poor bit line coupling, the voltage on internal node INT2 begins to increase towards 49 / 35 / 27 mV (worst-case).

[0288] The voltages on nodes INT0 and INT2 continue to be generated until time T3. By time T3, the voltages on bit lines bl0,1 and internal node INT0 have reached at least 169 / 121 / 93 mV read bit line voltages (as described above), and due to poor bit line coupling, the voltage on internal node INT2 is as high as 49 / 35 / 27 mV (worst-case). At time T3, the precharge control signal PRE1 is deactivated to a low voltage, thereby turning off transistors N12 and N14, so that internal nodes INT0# and INT2# are no longer actively driven to the reference voltage Vref of 109 / 78 / 60 mV.

[0289] Also at time T3, the ISOS0 signal is deactivated to a low voltage (0V), thus turning off the n-channel transistors 801 and 802, thereby temporarily isolating bit lines bl0,1 and bl0,3 from internal nodes INT0 and INT2, respectively.

[0290] At time T4 (immediately following the deactivation of the precharge control signals PRE1 and ISOS0), the PCOM signal is activated at a logic high-order voltage (983 / 985 / 973 mV), thereby activating the single-ended inductive amplifier circuits SA0,1 and SA0,3. Under these conditions, inductive amplifier circuit SA'0,1 amplifies the voltage difference between the signals at internal nodes INT0 and INT0#, and inductive amplifier circuit SA0,3 amplifies the voltage difference between the signals at internal nodes INT2 and INT2#. In the illustrated example, the voltage at internal node INT0 is at least 169 / 121 / 93 mV, while the reference voltage at node INT0# is 109 / 78 / 60 mV (ΔV is 60 / 43 / 33 mV). In the single-ended inductive amplifier SA'0,1, the relatively low voltage at the internal node INT0# causes transistor P2 to turn on first when the PCOM voltage turns high. This increases the differential voltage between the internal nodes INT0 and INT0# until the voltage at the internal node INT0 becomes high enough to turn on transistor N1.

[0291] As a result, the voltage on internal node INT0 is pulled up to the full PCOM voltage of 983 / 985 / 973 mV, while the voltage on node INT0# is pulled down to ground (0V). Note that balancing the capacitances of internal nodes INT0 and INT0# is crucial during this initial sensing phase. During this initial sensing phase, turning off the isolation transistor 801 temporarily decouples the capacitance of bit line bl0,1 from the internal node INT0, making the capacitance of internal node INT0 closer to that of INT0# during this initial sensing phase.

[0292] Similarly, the inductive amplifier circuit SA0,3 amplifies the voltage difference between the signals at internal nodes INT2 and INT2#. In the illustrated example, due to the worst-case adverse bit-line coupling effect of adjacent logic "1" bit lines, the voltage at internal node INT2 is 49 / 35 / 27 mV, while the reference voltage at internal node INT2# is 109 / 78 / 60 mV (corresponding to ΔV of 60 / 43 / 33 mV). In the single-ended inductive amplifier SA0,3, the relatively low voltage at internal node INT2 causes transistor P3 to turn on first when the PCOM voltage turns high. This increases the differential voltage between internal nodes INT2 and INT2# until the voltage at internal node INT2# becomes high enough to turn on transistor N4. As a result, the voltage at internal node INT2# is pulled up to the full PCOM voltage of 983 / 985 / 973 mV, while the voltage at node INT2 is pulled down to ground (0V).

[0293] At time T5 (after a full signal swing of 983 / 985 / 973 mV is formed on each pair of internal nodes INT0 / INT0# and INT2 / INT2#), the ISOS0 signal is restarted at a high voltage (1.5V), thereby turning on isolation transistors 801 and 802 and recoupled bit lines bl0,1 and bl0,3 to internal nodes INT0 and INT2, respectively. Under these conditions, bit lines bl0,1 and bl0,3 are driven to 983 / 985 / 973 mV and 0V, respectively, thereby refreshing the data values ​​in the corresponding bit cells bc0,1 and bc0,3. Although Figure 27 illustrates that isolation transistors 801 and 802 are restarted after forming a full-signal swing of 983 / 985 / 973 mV on each pair of internal nodes INT0 / INT0# and INT2 / INT2#, in an alternative embodiment, isolation transistors 801 and 802 are restarted when the signal swing on each pair of internal nodes is less than the full-signal swing of 983 / 985 / 973 mV, but large enough to overcome the capacitance introduced by bit lines bl0,1 and bl0,3 during the restart of isolation transistors 801 and 802. Furthermore, at time T5, the reference voltage signal Vref is driven to ground to save power.

[0294] At time T6, sub-word line SWL0,0 is deactivated, thereby shutting down the access transistors of bits bc0,1 and bc0,3 (isolating bit lines bl0,1 and bl0,3 from the unit capacitors of bits bc0,1 and bc0,3). At this point, the data values ​​read from bits bc0,1 and bc0,3 have been restored to those bits.

[0295] At time T7, the PCOM control signal is driven to ground. As a result, the voltages INT0 and INT2# are also driven to ground. At this time, the INT0 node is still coupled to bit line bl0,1 (through the isolation transistor 801), so the voltage on bit line bl0,1 is also driven to ground. During this period, bit line bl0,3 remains grounded, so that both bit lines bl0,1 and bl0,3 are pre-charged to ground.

[0296] At time T8, the ISOS0 voltage is driven to ground, shutting down isolation transistors 801 and 802 and isolating primary induction amplifiers SA'0,1 and SA'0,3 from bit lines bl0,1 and bl0,3. At time T9, precharge control voltages PRE0 and PRE1 are driven from ground to 1V to precharge induction amplifiers SA'0,1 and SA'0,3, where INT0, INT0#, INT2, and INT2# are actively pulled to ground by transistors N11, N12, N13, and N14, respectively.

[0297] Compared to conventional dual-ended inductor amplifiers, the single-ended inductor amplifier in Figure 27 saves at least approximately 20% of the bit line CV2f power when reading a logic "1" value. That is, the bit line CV2f power of the single-ended inductor amplifier in Figure 27 divided by the CV2f power of the dual-ended inductor amplifier is at least equal to (0.985 x 0.985) / (1.1 x 1.1), or 0.80. Compared to conventional dual-ended inductor amplifiers, the single-ended inductor amplifier shown in Figure 27 saves 100% of the power consumption when reading a logic "0" value (because the bit line being read remains grounded or nearly grounded throughout the read operation, so it consumes little to no power). Assuming the read operation typically contains half logic "1" values ​​and half logic "0" values, the single-ended inductor amplifier in Figure 27 saves an average of approximately 60% of the power consumption compared to a conventional dual-ended inductor amplifier (100% x 50 + 20% x 50 = 60%), which is approximately a 2.5-fold reduction in power consumption.

[0298] Please note that in the embodiment illustrated in FIG27, the isolation transistors 801-802 (and the transistors driving the sub-word lines SWL0,0) must be overdriveable thick oxide transistors so that the read voltage generated on the bit lines can be provided to the sense amplifier latch, and the all-positive voltage generated by the sense amplifier latch can be driven onto the bit lines. The embodiments described below advantageously do not require the thick oxide transistors of the embodiment in FIG27.

[0299] [, First Alternative Embodiment , ] In a first alternative embodiment, the n-channel transistors N1-N4 and p-channel transistors P1-P4 are manufactured according to the MST technology, which includes superlattice channels extending between the source and drain regions of these transistors. This technology is described in more detail in the applicant's U.S. Patents Nos. 10,109,342 and 10,107,854 and U.S. Patent Application No. 18 / 311,465, the entire contents of which are incorporated herein by reference. Manufacturing transistors N1-N4 and P1-P4 using the MST technology advantageously allows these transistors to exhibit more precisely defined threshold voltages. Therefore, inductive amplifiers implementing transistors manufactured using the MST technology (hereinafter referred to as "MST inductive amplifiers") can more reliably detect specific bit lattice voltages. Consequently, MST inductive amplifiers SA'0,1 and SA'0,3 can reliably sense a significant reduction (e.g., about half) in the ΔV value variation. Therefore, while a non-MST inductor amplifier (such as the inductor amplifier described above in conjunction with the embodiment of Figure 27) may exhibit a ΔV value of 60 / 43 / 33 mV, an MST inductor amplifier (such as the inductor amplifier described below in conjunction with the embodiment of Figure 28) can advantageously exhibit an improved ΔV value range of approximately 30 / 21 / 16 mV (corresponding to CB / CS = 4 / 6 / 8, respectively). In other words, the MST inductor amplifier can reliably operate within a ΔV value range (approximately half the ΔV value range of the non-MST inductor amplifier).

[0300] Figure 28 illustrates the signal waveforms related to the read access of bit lattices bc0,1 and bc0,3 in the first alternative embodiment, wherein the n-channel transistors N1~N4 and the p-channel transistors P1~P4 are all manufactured as superlattice channels incorporating MST technology, i.e., the induction amplifiers SA'0,1 and SA'0,3 are MST induction amplifiers.

[0301] The waveform diagram in Figure 28 is similar to that in Figure 27, but the differences are described below. Since the waveform diagram in Figure 28 corresponds to an MST induction amplifier using a ΔV value of 30 / 21 / 16 mV, the initial Vref rating should be 30 / 21 / 16 mV. Assuming a 25% defective bit line coupling effect when adjacent bit lines are pulled high to the logic "1" voltage level, the Vref adjustment can be calculated as 54 / 38 / 29 mV (using the method described above, after three iterations). Specifically, through 25% defective bit line coupling, the logic "0" read bit line voltage level can be pulled high from 0 V to 24 / 17 / 13 mV, so the Vref adjustment equals 30 / 21 / 16 mV + 24 / 17 / 13 mV, or 54 / 38 / 29 mV (corresponding to CB / CS = 4 / 6 / 8 respectively).

[0302] When reading a logic "1" value from bit cell bc0,1 (or bc0,3), in order to obtain a ΔV value of 30 / 21 / 16 mV, the voltage generated on the read bit line at the end of the refresh interval should be at least greater than the Vref reference voltage of 54 / 38 / 29 mV plus the ΔV value of 30 / 21 / 16 mV, i.e., 84 / 59 / 45 mV.

[0303] The logic "1" read bit line voltage of 84 / 59 / 45 mV is converted to a bit grid voltage of 420 / 413 / 405 mV with CB / CS = 4 / 6 / 8 (i.e., 84 / 59 / 45 mV x (1+Cb / Cs) = 420 / 413 / 405 mV). To ensure that the minimum bit grid voltage at the end of the refresh interval is 420 / 413 / 405 mV, the bit grid should initially be written with approximately 14% higher bit grid voltage, i.e., 488 / 480 / 471 mV. Since the logic "1" bit grid voltage is only 488 / 480 / 471 mV, the isolation transistors 801~802 (and the transistors driving the sub-word line voltages SWL0,0) can be implemented using conventional logic transistors, without the need for thick oxide transistors (as required in the embodiment of Figure 27). Furthermore, the sub-word line voltage SWL0,0 (and ISOS0 and ISOS1 voltages) can be reduced to 1V or lower. Specifically, the sub-word line voltage SWL0,0 (and ISOS0 and ISOS1 voltages) only needs to be high enough to ensure that the 488 / 480 / 471 mV logic "1" bit cell voltage is written back to that bit cell.

[0304] Figure 28 shows the adjusted reference voltage Vref 54 / 38 / 29mV, adjusted worst-case bit line coupling voltage 24 / 17 / 13mV, logic "1" read bit line voltage 84 / 59 / 45mV, and logic "1" bit grid voltage 488 / 480 / 471mV achieved by using the MST inductive amplifier. The timing of all signals is the same as that described above in conjunction with the waveform diagram in Figure 27.

[0305] Compared to conventional dual-ended inductor amplifiers, the single-ended inductor amplifier in Figure 28 saves approximately 80% of the bit line CV2f power when reading a logic "1" value. That is, the bit line CV2f power of the single-ended inductor amplifier in Figure 28 divided by the CV2f power of the dual-ended inductor amplifier equals at least (0.488 x 0.488) / (1.1 x 1.1), or 0.20. Compared to conventional dual-ended inductor amplifiers, the single-ended inductor amplifier in Figure 28 saves 100% of the power consumption when reading a logic "0" value (because the bit line being read remains grounded or nearly grounded throughout the read operation, so it consumes little to no power). Assuming the read operation typically contains half logic "1" values ​​and half logic "0" values, the single-ended inductor amplifier in Figure 28 saves an average of 90% of the power consumption compared to conventional dual-ended inductor amplifiers (100% x 50 + 80% x 50 = 90%), which is approximately a 10-fold reduction in power consumption.

[0306] [, Second Alternative Embodiment , ] Figure 29 illustrates the circuit diagrams of single-ended MST inductor amplifiers SA''0,1 and SA''0,3 according to a second alternative embodiment of the present invention. The single-ended MST inductor amplifiers SA''0,1 and SA''0,3 are similar to those in Figure 26, but differ as described below. In the single-ended MST inductor amplifiers SA''0,1 and SA''0,3, the n-channel transistors N1~N4 and the p-channel transistors P1~P4 are manufactured according to MST technology (i.e., superlattice channels extend between the source and drain regions of these transistors), causing the single-ended MST inductor amplifiers SA''0,1 and SA''0,3 to exhibit a ΔV value range of 30 / 21 / 16 mV (as described above in conjunction with Figure 28). In addition, the single-ended MST inductive amplifiers SA''0,1 and SA''0,3 include jumper capacitors 821, 822, 823 and 824, which are coupled to bit lines bl0,1,bl0,3,bl1,1 andbl1,3, respectively.

[0307] Figure 30 illustrates the signal waveforms related to the read access of the mid-cells bc0,1 and bc0,3 of the single-ended MST inductive amplifiers SA''0,1 and SA''0,3, according to a second alternative embodiment of the present invention. The waveforms in Figure 30 are similar to those in Figure 28, but the differences are described below.

[0308] Since the waveform in Figure 28 corresponds to an MST inductive amplifier using a ΔV value of 30 / 21 / 16 mV, the initial Vref rating should be 30 / 21 / 16 mV. Assuming that 25% of the poor bit line coupling from adjacent bit lines is pulled high to the logic "1" voltage level, the adjusted Vref value can be calculated as 54 / 38 / 29 mV (using the method described above, after three iterations). Specifically, through 25% of the poor bit line coupling, the voltage level of the logic "0" read bit line can be pulled high from 0 V to 24 / 17 / 13 mV, making the adjusted Vref value equal to 30 / 21 / 16 mV + 24 / 17 / 13 mV, or 54 / 38 / 29 mV (corresponding to CB / CS = 4 / 6 / 8 respectively).

[0309] Furthermore, in the embodiments of Figures 29-30, each jumper capacitor 821-824 is designed to reduce the voltage on the relevant bit lines to half of the adjusted Vref reference voltage of 54 / 38 / 29 mV during read operations. Specifically, during read accesses of bits bc0,1 and bc0,3, jumper capacitors 821 and 822 are selected to kick down the voltage on bit lines b10,1 and b10,3 by -27 / -19 / -14.5 mV, respectively. In this way, the reference voltage Vref required by the single-ended MST inductive amplifiers SA''0,1 and SA''0,3 is similarly reduced from 54 / 38 / 29 mV to 27 / 19 / 14.5 mV (i.e., 54 / 38 / 29 mV - 27 / 19 / 14.5 mV = 27 / 19 / 14.5 mV). In the embodiments of Figures 29-30, the jumper capacitor is controlled to reduce the voltage on bit lines bl0,1 and bl0,3 between time T2 and time T3 (i.e., at time T2.5). In one embodiment, the jumper capacitor is turned on as close as possible to time T3.

[0310] Given a reference voltage Vref of 27 / 19 / 14.5 mV, the required logic "1" bit line read voltages for the single-ended MST induction amplifiers SA''0,1 and SA''0,3 are 57 / 40 / 30.5 mV (i.e., 30 / 21 / 16 mV + 27 / 19 / 14.5 mV = 57 / 40 / 30.5 mV) to obtain a ΔV value range of 30 / 21 / 16 mV. These logic "1" bit line read voltages are shown in Figure 30. Note that these logic "1" bit line read voltages provide the appropriate ΔV value of 30 / 21 / 16 mV compared to the reference voltage Vref of 27 / 19 / 14.5 mV.

[0311] Corresponding to CB / CS = 4 / 6 / 8, the logic "1" bit line write voltage of 57 / 40 / 30.5 mV is converted to a bit cell voltage of 285 / 280 / 275 mV (i.e., 57 / 40 / 30.5 mV x (1+Cb / Cs) = 285 / 280 / 275 mV). To ensure that the minimum bit cell voltage at the end of the refresh interval is 285 / 280 / 275 mV, the bit cell should initially be written with approximately 14% higher bit cell voltage, i.e., 331 / 326 / 320 mV. Since the logic "1" bit cell voltage is only 331 / 326 / 320 mV, the isolation transistors 801~802 (and the transistors driving the sub-word line voltages SWL0,0) can be implemented using conventional logic transistors, without the need for thick oxide transistors (as required in the embodiment of Figure 27). Furthermore, the sub-word line voltages SWL0,0 (and ISOS0 and ISOS1 voltages) can be reduced to 1V or lower. Specifically, the sub-word line voltages SWL0,0 (and ISOS0 and ISOS1 voltages) only need to be high enough to ensure that a logic "1" bit voltage of 331 / 326 / 320 mV is written to that bit.

[0312] As described above, due to poor 25% bit line coupling, the voltage level of the logic "0" bit line (e.g., bit line bl0,3 in Figure 29) can be pulled up from 0 V to 24 / 17 / 13 mV. Because the jumper capacitor 822 reduces the voltage on bit line bl0,3 by -27 / 19 / 14.5 mV during read access to bit cell bc0,3, the logic "0" bit line read voltage is adjusted to -3 / -2 / -1.5 mV (i.e., 24 / 17 / 13 mV - 27 / 19 / 14.5 mV = -3 / -2 / -1.5 mV). These logic "0" bit line read voltages are shown in Figure 30. Note that these logic "0" bit line read voltages provide an appropriate ΔV value of 30 / 21 / 16 mV compared to the reference voltage Vref of 27 / 19 / 14.5 mV. Since there is little or no current flowing on the bit line for reading logic "0" (because the bit line is precharged to 0V and remains near 0V during the read operation), there is no significant undesirable bit line coupling associated with reading logic "1" on the bit line.

[0313] Compared to conventional two-ended inductor amplifiers, the single-ended inductor amplifiers of Figures 29-30 save at least approximately 91% of the bit line CV2f power when reading logic "1" values. That is, the bit line CV2f power of the single-ended inductor amplifier in Figure 30 divided by the CV2f power of the two-ended inductor amplifier equals at least (0.331 x 0.331) / (1.1 x 1.1), or 0.091. Compared to conventional two-ended inductor amplifiers, the single-ended inductor amplifier in Figure 30 saves 100% of the power consumption when reading logic "0" values ​​(because the bit line being read remains close to ground throughout the read operation, consuming little to no power). Assuming the read operation typically consists of half logic "1" values ​​and half logic "0" values, the single-ended inductor amplifier in Figure 30 saves an average of 95.5% of the power consumption compared to conventional two-ended inductor amplifiers (100% x 50 + 91% x 50 = 95.5%), which is approximately a 22-fold reduction in power consumption.

[0314] Please note that the control methods of the single-ended inductor amplifiers SA''0,1 and SA''0,3 in Figures 29-30 are similar to those in Figures 26-28. That is, the timing sequence of the SWL0,0, Vref, PRE0, ISOS0, PRE1, and PCOM signals remains consistent throughout the entire operation of these single-ended inductor amplifiers.

[0315] [, Third Alternative Embodiment , ] Figure 31 illustrates the circuit diagram of single-ended MST inductive amplifiers SA'''0,1 and SA'''0,3 according to a third alternative embodiment of the present invention. The single-ended MST inductive amplifiers SA'''0,1 and SA'''0,3 are similar to the single-ended inductive amplifiers SA'0,1 and SA'0,3 (Figure 26), and their similarities and differences are described below.

[0316] In the single-ended MST inductive amplifiers SA'''0,1 and SA'''0,3, the n-channel transistors N1~N4 and p-channel transistors P1~P4 are manufactured according to MST technology (including superlattice channels extending between the source and drain regions of these transistors), so that the single-ended MST inductive amplifiers SA'''0,1 and SA'''0,3 exhibit a ΔV value range of 30 / 21 / 16 mV (corresponding to CB / CS = 4 / 6 / 8, respectively).

[0317] In single-ended induction amplifiers SA'''0,1 and SA'''0,3, the reference voltage Vref is set to ground (0V), and the sources of n-channel transistors N1~N4 are coupled to receive the NCOM control signal from the primary induction amplifier driver PSAD1,0 (instead of ground). Furthermore, the logic "0" byte voltage is set to -200 mV (instead of 0V). As shown in Figure 32, a logic "0" byte voltage of -200 mV can be achieved by pulling the NCOM control signal low to -200 mV during sensing operation.

[0318] Figure 32 illustrates the signal waveforms related to the read access of the mid-cells bc0,1 and bc0,3 of the single-ended MST inductive amplifiers SA'''0,1 and SA'''0,3 according to a third alternative embodiment of the present invention. The waveforms in Figure 32 are similar to those in Figure 28, but the differences are described below.

[0319] With a nominal "0" bit voltage of -200 mV, and CB / CS values ​​of 4 / 6 / 8, the nominal logic "0" read bit line voltage is -40 / -29 / -22 mV (i.e. -200 mV). (1 + CB / CS) = -40 / -29 / -22 mV, corresponding to CB / CS = 4 / 6 / 8). Assuming the bit line reading logic "0" is affected by 25% bad bit line coupling from a plurality of adjacent bit lines reading logic "1", the bit line reading logic "0" may be pulled high by 10 / 7 / 6 mV (i.e., 40 / 29 / 22 mV x 25). That is, the logic "0" read bit line voltage will be pulled high to -30 / -22 / -16 mV. Note that when the reference voltage Vref is set to 0 V, the logic "0" read bit line voltage is -30 / -22 / -16 mV, satisfying the specified ΔV values ​​for single-ended induction amplifiers SA'''0,1 and SA'''0,3 (i.e., ΔV = 30 / 21 / 16 mV).

[0320] As described above, in this embodiment, the reference voltage Vref is set to ground. To obtain the ΔV value of 30 / 21 / 16 mV for the logic "1" read data value, the rated value of the logic "1" read on bit line bl0,1 (or bl0,3) should be at least equal to 30 / 21 / 16 mV (i.e., 0 mV + 30 / 21 / 16 mV = 30 / 21 / 16 mV). Assuming that 25% of the adjacent bit lines are poorly coupled and pulled down to the logic "0" read value (i.e., a negative voltage level), the rated value of the logic "1" read on bit line bl0,1 (or bl0,3) should be adjusted to 40 / 28 / 21 mV (i.e., 30 / 21 / 16 mV divided by 0.75 = 40 / 28 / 21 mV) to compensate for this poor bit line coupling. Corresponding to CB / CS = 4 / 6 / 8, the logic "1" bit line voltage of 40 / 28 / 21 mV is converted to a bit grid voltage of 200 / 196 / 189 mV (i.e., 40 / 28 / 21 mV x (1+Cb / Cs) = 200 / 196 / 189 mV). To ensure that the minimum bit grid voltage at the end of the refresh interval is 200 / 196 / 189 mV, the bit grid should initially be written with approximately 14% higher bit grid voltage, i.e., 233 / 228 / 220 mV. Since the logic "1" bit grid voltage is only 233 / 228 / 220 mV, the isolation transistors 801~802 (and the transistors driving the sub-word line voltages SWL0,0) can be implemented using conventional logic transistors, without the need for thick oxide transistors. In detail, the sub-word line voltages SWL0,0 (and ISOS0 and ISOS1 voltages) only need to be high enough to ensure that the logic "1" bit voltage of 233 / 228 / 220 mV is written to the bit cell.

[0321] Compared to conventional dual-ended inductor amplifiers, the single-ended inductor amplifiers specified in Figures 31-32 can save approximately 95.5% of the bit line CV2f power when reading a logic "1" value. That is, the power of the logic "1" bit line CV2f of the single-ended inductor amplifier in Figure 30 divided by the power of the logic "1" bit line CV2f of the dual-ended inductor amplifier is equal to (0.233 x 0.233) / (1.1 x 1.1), which is 0.045.

[0322] Compared to conventional dual-ended inductor amplifiers, the single-ended inductor amplifiers specified in Figures 31-32 can save approximately 96.7% of the bit line CV2f power when reading a logic "0" value. That is, the logic "0" bit line CV2f power of the single-ended inductor amplifier in Figure 30 divided by the logic "0" bit line CV2f power of the dual-ended inductor amplifier is equal to (-0.200 x -0.200) / (1.1 x 1.1), which is 0.033.

[0323] Assuming that the read operation contains an average of half logic "1" values ​​and half logic "0" values, the single-ended induction amplifier specified in Figure 31 saves an average power consumption of 96.1% (95.5% x 50 + 96.7% x 50 = 96.1%) compared to a conventional double-ended induction amplifier, which is about 26 times less power consumption.

[0324] Please note that the control methods of the single-ended inductor amplifiers SA'''0,1 and SA'''0,3 in Figures 30-31 are similar to those in Figures 26-28. That is, the timing of the SWL0,0, PRE0, ISOS0, PRE1, and PCOM signals is consistent throughout the operation of these single-ended inductor amplifiers. Note that when the single-ended inductor amplifiers SA'''0,1 and SA'''0,3 are enabled at time T4 (i.e., when the PCOM signal is driven from 0V to 233 / 228 / 220 mV), the NCOM signal is driven down from 0V to a negative voltage of -200 mV. This advantageously allows the INT2 node and bit line bl0,3 to be driven to -200 mV to correctly refresh the bit cell voltage of bit cell bc0,3.

[0325] [, Fourth Alternative Embodiment , ] Figure 33 illustrates the circuit diagram of single-ended MST inductive amplifiers SA''''0,1 and SA''''0,3 according to the fourth alternative embodiment of the present invention. The single-ended MST inductive amplifiers SA''''0,1 and SA''''0,3 are similar to the single-ended inductive amplifiers SA'0,1 and SA'0,3 (Figure 31), and their similarities and differences are described below.

[0326] In the single-ended MST inductive amplifiers SA''''0,1 and SA''''0,3, the n-channel transistors N1~N4 and p-channel transistors P1~P4 are manufactured according to MST technology (including superlattice channels extending between the source and drain regions of these transistors), so that the single-ended MST inductive amplifiers SA''''0,1 and SA''''0,3 exhibit a ΔV value range of 30 / 21 / 16 mV.

[0327] Inside the single-ended induction amplifiers SA''''0,1 and SA''''0,3, the reference voltage Vref is set to ground (0V), and the NCOM control signal is pulled down to -100 mV (instead of -200 mV) to activate the single-ended induction amplifiers SA''''0,1 and SA''''0,3. Thus, the logic "0" bit voltage is set to -100 mV (instead of -200 mV).

[0328] Furthermore, the single-ended MST inductive amplifiers SA''''0,1 and SA''''0,3 include snap-on capacitors 821, 822, 823, and 824, which are coupled to bit lines bl0,1,bl0,3,bl1,1, andbl1,3, respectively. As detailed below, each snap-on capacitor 821-824 is designed to reduce the voltage on the relevant bit line during read operations.

[0329] Figure 34 illustrates the signal waveforms related to the read access of the mid-cells bc0,1 and bc0,3 of the single-ended MST inductive amplifiers SA''''0,1 and SA''''0,3 according to a fourth alternative embodiment of the present invention. The waveforms in Figure 34 are similar to those in Figure 32, but the differences are described below.

[0330] With a nominal "0" bit voltage of -100 mV, when CB / CS = 4 / 6 / 8, the nominal logic "0" read bit line voltage is -20 / -14 / -11 mV (i.e. -100 mV). (1 + CB / CS) = -20 / -14 / -11 mV, corresponding to CB / CS = 4 / 6 / 8). Assuming the bit line reading logic "0" is affected by 25% bad bit line coupling from a plurality of adjacent bit lines reading logic "1", the bit line reading logic "0" might be pulled high by 5 / 4 / 3 mV (i.e., 20 / 14 / 11 mV x 25). That is, the logic "0" read bit line voltage will be pulled high to -15 / -10 / -8 mV. Note that when the reference voltage Vref is equal to 0 V, these logic "0" read bit line voltages do not satisfy the specified ΔV values ​​(i.e., ΔV = 30 / 21 / 16 mV) for the single-ended induction amplifiers SA''''0,1 and SA''''0,3. To obtain the required ΔV value of 30 / 21 / 16 mV for reading the data value of logic "0", the switched snap capacitors 821-822 are activated to pull down the voltage on the corresponding bit lines bl0,1 and bl0,3 by -15 / -11 / -8 mV, respectively, corresponding to CB / CS = 4 / 6 / 8. As a result, the voltage on the logic "0" bit line drops from -15 / -10 / -8 mV to -30 / -21 / -16 mV (i.e., -15 / -10 / -8 mV – 15 / 11 / 8 mV = -30 / -21 / -16 mV), thus satisfying the specified ΔV value (i.e., ΔV = 30 / 21 / 16 mV) for the single-ended induction amplifiers SA''''0,1 and SA''''0,3. In the embodiments shown in Figures 33-34, jumper capacitors 821-822 are controlled to reduce the voltage on bit lines bl0,1 and bl0,3 between time T2 and time T3 (i.e., at time T2.5). In one embodiment, the jumper capacitors are turned on as close as possible to time T3.

[0331] As described above, in this embodiment, the reference voltage Vref is set to ground. To obtain the ΔV value of 30 / 21 / 16 mV for the logic "1" read data value, the rated value of the logic "1" read on bit line bl0,1 (or bl0,3) should be at least equal to 30 / 21 / 16 mV (i.e., 0 mV + 30 / 21 / 16 mV = 30 / 21 / 16 mV). Assuming that 25% of the adjacent bit lines are poorly coupled and pulled down to the logic "0" read value (i.e., a negative voltage level), the rated value of the logic "1" read on bit line bl0,1 (or bl0,3) should be adjusted to 40 / 28 / 21 mV (i.e., 30 / 21 / 16 mV divided by 0.75 = 40 / 28 / 21 mV) to compensate for this poor bit line coupling. The rated value of the logic "1" read on bit lines bl0,1 (or bl0,3) should also be increased by 15 / 11 / 8 mV to compensate for the jump voltage applied by jump capacitors 821-822. Specifically, the rated value of the logic "1" read on bit lines bl0,1 (or bl0,3) should be adjusted to 55 / 39 / 29 mV (i.e., 40 / 28 / 21 mV + 15 / 11 / 8 mV = 55 / 39 / 29 mV) to compensate for the jump capacitor voltage.

[0332] When CB / CS = 4 / 6 / 8, the logic "1" bit line voltage of 55 / 39 / 29 mV is converted to a bit grid voltage of 275 / 273 / 261 mV (i.e., 55 / 39 / 29 mV x (1+Cb / Cs) = 275 / 273 / 261 mV). To ensure that the minimum bit grid voltage at the end of the refresh interval is 275 / 273 / 261 mV, the bit grid should initially be written with approximately 14% higher bit grid voltage, i.e., 320 / 317 / 304 mV. Since the logic "1" bit grid voltage is only 320 / 317 / 304 mV, the isolation transistors 801~802 (and the transistors driving the sub-word line voltages SWL0,0) can be implemented using conventional logic transistors, without the need for thick oxide transistors. In detail, the sub-word line voltages SWL0,0 (and ISOS0 and ISOS1 voltages) only need to be high enough to ensure that the 320 / 317 / 304 mV logic "1" bit cell voltage is written to that bit cell.

[0333] Compared to conventional dual-ended inductor amplifiers, the single-ended inductor amplifiers in Figures 33-34 can save approximately 91.5% of the bit line CV2f power when reading a logic "1" value. That is, the power of the logic "1" bit line CV2f of the single-ended inductor amplifier in Figure 30 divided by the power of the logic "1" bit line CV2f of the dual-ended inductor amplifier equals (0.320 x 0.320) / (1.1 x 1.1), which is 0.085.

[0334] Compared to conventional dual-ended inductor amplifiers, the single-ended inductor amplifiers specified in Figures 31-32 can save approximately 99.2% of the bit line CV2f power when reading a logic "0" value. That is, the logic "0" bit line CV2f power of the single-ended inductor amplifier in Figure 30 divided by the logic "0" bit line CV2f power of the dual-ended inductor amplifier is equal to (-0.100 x -0.100) / (1.1 x 1.1), which is 0.008.

[0335] Assuming that the read operation contains an average of half logic "1" values ​​and half logic "0" values, the single-ended induction amplifier specified in Figure 31 saves an average power consumption of 95.4% (91.5% x 50 + 99.2% x 50 = 95.4%) compared to a conventional double-ended induction amplifier, which is about 22 times less power consumption.

[0336] Please note that the control methods of the single-ended inductor amplifiers SA''''0,1 and SA''''0,3 in Figures 33-34 are similar to those in Figures 29-30. That is, the timing of the SWL0,0, PRE0, ISOS0, PRE1, and PCOM signals is consistent throughout the operation of these single-ended inductor amplifiers. Note that when the single-ended inductor amplifiers SA''''0,1 and SA''''0,3 are enabled at time T4 (i.e., when the PCOM signal is driven from 0V to 320 / 317 / 304 mV), the NCOM signal is driven down from 0V to a negative voltage of -100 mV. This advantageously allows the INT2 node and bit line bl0,3 to be driven to -100 mV to correctly refresh the bit cell voltage of bit cell bc0,3.

[0337] In the above embodiments, the voltage (i.e., Vplate) applied to the capacitor plates of DRAM bit cells bc0,1 and bc0,3 needs to be significantly reduced because the logic "1" bit cell voltage is drastically reduced. In the above embodiments, the bit cell voltage is reduced from 1.1V (corresponding to a conventional two-ended induction amplifier) ​​to approximately 985 mV (corresponding to a single-ended induction amplifier in Figures 26-27), approximately 488 mV (corresponding to a single-ended induction amplifier in Figure 28), approximately 331 mV (corresponding to a single-ended induction amplifier in Figures 29-30), approximately 233 mV (corresponding to a single-ended induction amplifier in Figures 31-32), and approximately 320 mV (corresponding to a single-ended induction amplifier in Figures 33-34). Assuming that the capacitor plate voltage Vplate is half of the bit cell voltage, the capacitor plate voltage can be reduced from 550 mV (corresponding to a conventional two-ended induction amplifier) ​​to approximately 493 mV, 244 mV, 166 mV, 117 mV, and 160 mV (corresponding to a single-ended induction amplifier in the above embodiments). The reduced voltage across the DRAM grid capacitors facilitates the use of different capacitor materials / structures within the DRAM grid. Furthermore, since no virtual bit lines pass through the grid array / sensor amplifier region, the aforementioned single-ended inductive amplifier can be manufactured with a DRAM grid area of ​​4F² units.

[0338] Although several embodiments have been presented to illustrate the invention, it should be understood that the invention is not limited to the embodiments disclosed herein, but is capable of various modifications, which will be apparent to those skilled in the art. Therefore, the scope of the invention should be defined by the claims.

[0339] 111~114:TSVC 201: Local Vertical Transmission Controller 100: MTDRAM processor system 101~104: MTDRAM chips 1010~1040: MTDRAM unit grid 105: ASIC controller chip 1050: Processor Array 1051~1052048: Processor Blocks 801~804: High-voltage NMOS transistors 821~824: Bit line voltage jump capacitor 1601~1608, 1701~1708, 1740, 1901~1909, 1940, 2001~2009, N1~N4, N11~N14, N20, N22: n-channel transistors 1610~1613, 1710~1713, 1910~1915, 2010~2015, P1~P4: p-channel transistors 1620, 1720, 1920, 2020: Induction Amplifier Latch 1630, 1631, 1730, 1731, 1750, 1930, 1931, 1950, 2030, 2031: Capacitors 1960, 2060: Inverters 2200: Instruction 2400: Subarray Decoder Circuit 2410~2417: NAND gate AND0~AND32: AND gate bc0,0~bc7,575: Bit cell bl0,0~bl1,575、bl2,0~bl2,7: Bit lines C0: Cell capacitor CoSA0~CoSA7: Subarray columns COMP1_E, COMP1_O, COMP2_E, COMP2_O: Comparator enable signal D0~D3: Data values DATA_A1, DATA_A2, DATA_B1, DATA_B2: Data bus / data channel EN_SUBA0,0, EN_SUBA1,0: Subarray enable signal G0: Bit-level transmission thyristor GBL0~GBL575: Global Bit Line GIO0~GIO143: Global Input / Output Lines IN_E: Input signal INST1, INST2: Instruction bus INT0, INT0#, INT2, INT2#: Internal induction amplifier nodes ISOS0, ISOS1: Isolation control signals ML0~ML7: Metal wire MUX1,1,MUX1,2,MUX2,1,MUX2,2,MUX3,1,MUX3,2,MUX4,1,MUX4,2,MUXA0~MUXA7: Multiplexers MUX(1,1)A: First multiplexer circuit / Multiplexer section MUX(1,1)B: Second multiplexer circuit / Multiplexer section MWD0~MWD15: Main character line drive circuit MWL0: Main character line OUT_ODD, OUT_EVEN: Output control signals PRE0, PRE1: Precharge signals PRE_O, PRE_E: Control signals PSA0~PSA16: Primary Induction Amplifier Circuit PSA0,0~PSA16,7: Primary induction amplifier sub-circuit PSAD0,0, PSAD1,0: Primary induction amplifier driver circuit PSAR0~PSAR16: Central Area REF_E: Reference signal RSA0~RSA71: Read the secondary inductive amplifier circuit S(1,1)0~S(1,1)15、S(1,2)0~S(1,2)15、S(2,1)0~S(2,1)15、S(3,1)0~S(3,1)15、S(4,1)0~S(4,1)15、S(2,2)0~S(2,2)15、S(3,2)0~S(3,2)15、S(4,2)0~S(4,2)15: stripes SA0,0~SA0,575、SA1,0~SA1,7: Single-ended inductive amplifiers SA'0,1, SA'0,3, SA''0,1, SA''0,3, SA'''0,1, SA'''0,3, SA''''0,1, SA''''0,3: Single-ended MST sense amplifier SAMPLE_E, SAMPLE_O: Control signals SSA1,1, SSA2,1, SSA3,1, SSA4,1, SSA1,2, SSA2,2, SSA3,2, SSA4,2, SSAEVEN: Second-stage inductive amplifier circuit SSA(1,1)A: First and second stage inductive amplifier section SSA(1,1)B: Second-stage inductive amplifier section SSAD1,1: Second-stage inductive amplifier driver circuit SUBA0,0~SUBA15,7: Subarrays SWD0,0~SWD7,0: Sub-character line drive circuit SWL0,0~SWL7,0: Sub-character lines TSV1,1, TSV1,2, TSV2,1, TSV2,2, TSV3,1, TSV3,2, TSV4,1, TSV4,2: Silicon through-hole group TSVR1,0~TSVR1,15: Main TSV areas UC1,1~UC1,2048, UC2,1~UC2,2048, UC3,1~UC3,2048, UC4,1~UC4,2048: MTDRAM unit cells US1~US2048: Unit Stacking Vk: Trigger control signal VREF: Reference Voltage wIN_E, wIN_O: Write input signal WSA0~WSA71: Write to the secondary induction amplifier circuit wSAMPLE_E: Write sampling signal

Claims

1. A method for operating a single-ended inductive amplifier, comprising: Precharge one bit to ground; A first internal node of a latch circuit is coupled to ground, and a second internal node of the latch circuit is coupled to a reference voltage; a word line voltage is activated by applying a voltage to the gate of the access transistor of a DRAM bit cell, thereby coupling the bit cell capacitor of the DRAM bit cell to the bit line, thereby generating a read voltage on the bit line, wherein the bit line is isolated from the latch circuit when the word line voltage is initially activated; the first internal node of the latch circuit is decoupled from ground; then the bit line is coupled to the first internal node of the latch circuit, wherein the read voltage generated on the bit line is applied to the first internal node of the latch circuit; then the second internal node of the latch circuit is decoupled from the reference voltage, and the bit line is isolated from the first internal node of the latch circuit; then the latch circuit is activated, wherein the activated latch circuit amplifies the voltage difference between the read voltage on the first internal node of the latch circuit and the reference voltage on the second internal node of the latch circuit, causing a read data voltage to be stored on the first internal node of the latch circuit.

2. The method of claim 1, wherein the latching circuit comprises: A first transistor, having its source coupled to a first voltage supply node, its gate coupled to the first internal node, and its drain coupled to the second internal node; a second transistor, having its source coupled to the first voltage supply node, its gate coupled to the second internal node, and its drain coupled to the first internal node; a third transistor, having its source coupled to a second voltage supply node, its gate coupled to the first internal node, and its drain coupled to the second internal node; and a fourth transistor, having its source coupled to the second voltage supply node, its gate coupled to the second internal node, and its drain coupled to the first internal node, wherein activating the latch circuit includes increasing the voltage applied to the first voltage supply node from ground to a positive qubit voltage.

3. The method of claim 2 further includes keeping the second voltage supply node grounded.

4. The method of claim 1, further comprising applying a control voltage to the second voltage supply node, wherein the control voltage switches between ground and a negative voltage.

5. The method of request item 1, wherein the reference voltage is a positive voltage.

6. The method of request item 5, wherein the reference voltage is less than or equal to 109 mV.

7. The method of request item 5, wherein the reference voltage is less than or equal to 54 mV.

8. The method of request item 5, wherein the reference voltage is less than or equal to 27 mV.

9. The method of claim 5, further comprising applying a negative jump voltage to the bit line after coupling the bit line to a first internal node of the latch circuit, but before activating the latch circuit.

10. The method of request item 1, wherein the reference voltage is grounded.

11. The method of claim 10, further comprising applying a negative jump voltage to the bit line after coupling the bit line to a first internal node of the latch circuit, but before activating the latch circuit.

12. The method of claim 1, wherein the data reading voltage is a positive voltage less than or equal to 985 mV.

13. The method of claim 1, wherein the data reading voltage is a positive voltage less than or equal to 488 mV.

14. The method of claim 1, wherein the data reading voltage is a positive voltage less than or equal to 331 mV.

15. The method of claim 1, wherein the logic low-order cell voltage of the DRAM bit cell is 0 volts, and the read voltage generated on the bit line has a maximum logic low voltage, the maximum logic low voltage being specified by the logic low-order cell voltage of 0 volts plus a positive voltage coupled to one or more adjacent bit lines when the DRAM bit cell has a logic low-order cell voltage, and wherein the reference voltage is selected such that when the first internal node is at the maximum logic low voltage and the second internal node is at the reference voltage, the latch circuit can reliably pull the first internal node to ground.

16. The method of claim 15, wherein the difference between the maximum logic low voltage and the reference voltage is equal to a first voltage difference, wherein the logic high cell voltage of the DRAM bit cell corresponds to the read data voltage, wherein the read data voltage is selected such that the minimum logic high voltage of the read voltage generated on the bit line is equal to or greater than the reference voltage plus the first voltage difference when the DRAM bit cell has a logic high cell voltage, wherein the latch circuit can reliably pull the first internal node to the read data voltage when the first internal node is at the minimum logic high voltage and the second internal node is at the reference voltage.

17. The method of request item 3, wherein the reference voltage is a positive voltage.

18. The method of request item 4, wherein the reference voltage is grounded.

19. The method of claim 4, wherein the negative voltage is in the range of -100 mV to -200 mV.

20. The method of claim 10, wherein the DRAM bit cell has a logic low cell voltage equal to a negative voltage, and when the DRAM bit cell has a logic low cell voltage, the maximum logic low voltage of the read voltage generated on the bit line is determined by the negative logic low cell voltage plus the positive coupling voltage between the bit line and one or more adjacent bit lines, and wherein the maximum logic low voltage is selected such that when the first internal node is at the maximum logic low voltage and the second internal node is at the reference voltage grounded, the latch circuit can reliably pull the first internal node to the negative voltage.

21. The method of claim 20, wherein the difference between the maximum logic low voltage and the reference voltage grounded is equal to a first voltage difference, wherein the logic high cell voltage of the DRAM cell corresponds to the read data voltage, wherein the read data voltage is selected such that the minimum logic high voltage of the read voltage generated on the bit line is equal to or greater than the reference voltage grounded plus the first voltage difference when the DRAM cell has a logic high cell voltage, wherein the latch circuit reliably pulls the first internal node to the read data voltage when the first internal node is at the maximum logic high voltage and the second internal node is at the reference voltage grounded.

22. The method of claim 1, further comprising, after activating the latch circuit, recoupled the bit line to a first internal node of the latch circuit, wherein a read data voltage on the first internal node of the latch circuit is applied to the bit line.

23. The method of claim 22, wherein the reference voltage is a positive voltage, the method further comprising driving the reference voltage from the positive voltage to ground when the bit line is recoupled to the first internal node of the latch circuit.

24. The method of claim 1, wherein when a read voltage is applied to a first internal node of the latch circuit, the bit line is the only bit line coupled to the latch circuit.

25. The method of claim 1, further comprising, after activating the latch circuit, coupling the first internal node to a global bit line, wherein a read data voltage on the first internal node is applied to the global bit line.

26. The method of claim 1, wherein the bit line has a capacitor CB and the DRAM bit cell has a capacitor CS, wherein the value of CB / CS is in the range of 4 to 8.

27. The method of claim 1, wherein when the first internal node of the latch circuit is coupled to ground, the first internal node is pulled low to ground, and when the second internal node of the latch circuit is coupled to the reference voltage, the second internal node is precharged to the reference voltage.

28. The method of claim 27, wherein when the first internal node of the latch circuit is decoupled from ground, the first internal node is no longer actively pulled to ground, and when the second internal node of the latch circuit is decoupled from the reference voltage, the second internal node is no longer actively driven to the reference voltage.

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