Semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes: a substrate, a dielectric layer, a gate structure, a lightly doped region, a first spacer wall, and a heavily doped region. The dielectric layer is located on the substrate and includes a first segment having a first thickness and a second segment having a second thickness, the first thickness being greater than the second thickness, and the second segment surrounding the first segment. The gate structure covers a portion of the first segment. The lightly doped region is formed in the substrate and adjacent to the gate structure. The first spacer wall is located outside the sidewall of the gate structure and covers another portion of the first segment. The heavily doped region is located within the lightly doped region and adjacent to the second segment.

Claims

1. A semiconductor device, comprising: a substrate; a dielectric layer disposed on the substrate and including a first segment having a first thickness and a second segment having a second thickness, the first thickness being greater than the second thickness, and the second segment surrounding the first segment; a gate structure covering a portion of the first segment; a lightly doped region disposed in the substrate and adjacent to the gate structure; a first spacer wall adjacent to a sidewall of the gate structure and covering another portion of the first segment, wherein at least a portion of the lightly doped region is located below both an outer edge of the first spacer wall and the sidewall of the gate structure; a heavily doped region disposed in the lightly doped region and adjacent to the second segment; and an insulating structure disposed in the substrate, outside the heavily doped region, wherein an upper surface of the second segment is lower than an upper surface of the insulating structure.

2. The semiconductor device as claimed in claim 1, wherein the first segment and the second segment together form a stepped structure.

3. The semiconductor device as claimed in claim 1, wherein the dielectric layer comprises silicon oxide; and the gate structure comprises: a high-k dielectric layer on the first segment of the portion; a work function barrier layer on the high-k dielectric layer; and a metal gate on the work function barrier layer.

4. The semiconductor device as claimed in claim 1, wherein the heavily doped region extends below one end of the second segment away from the sidewall.

5. The semiconductor element as claimed in claim 1 further includes a second spacer wall located outside the outer edge of the first spacer wall and covering another portion of the first segment.

6. The semiconductor device as claimed in claim 5, wherein the second spacer wall comprises silicon nitride; and the first spacer wall comprises silicon oxide.

7. The semiconductor element as claimed in claim 5, wherein an outer edge of the second spacer wall is aligned with an outer edge sidewall of the first segment.

8. A method of manufacturing a semiconductor device, comprising: providing a substrate; forming an insulating structure therein to define an active region; forming a dielectric layer on the active region; forming a gate structure on the dielectric layer; forming a lightly doped region in the active region adjacent to the gate structure; thinning the dielectric layer such that the dielectric layer includes a first segment having a first thickness and a second segment having a second thickness, the first thickness being greater than the second thickness, and the second segment surrounding the first segment; an upper surface of the second segment being lower than an upper surface of the insulating structure; forming a first spacer wall on the outer side of a sidewall of the gate structure, adjacent to the sidewall and covering a portion of the first segment, such that at least a portion of the lightly doped region is located below both an outer edge of the first spacer wall and the sidewall of the gate structure; and forming a heavily doped region in the lightly doped region adjacent to the second segment.

9. A method for manufacturing a semiconductor device as claimed in claim 8, wherein the step of thinning the dielectric layer comprises: forming a patterned photoresist layer covering the gate structure and a portion of the dielectric layer surrounding the gate structure; performing a dry etching process to thin another portion of the dielectric layer not covered by the patterned photoresist layer; stripping the patterned photoresist layer to form the first spacer wall; and performing a cleaning / etch-back process to remove the other portion of the dielectric layer not covered by the patterned photoresist layer and thin the portion of the dielectric layer not covered by the gate structure and the first spacer wall.

10. A method for manufacturing a semiconductor device as claimed in claim 8, wherein the step of forming the gate structure includes: forming a patterned high-dielectric-coefficient dielectric layer on the dielectric layer; forming a work function barrier layer on the patterned high-dielectric-coefficient dielectric layer; and forming a silicon gate electrode on the work function barrier layer.

11. The method of manufacturing a semiconductor device as described in claim 10 further includes replacing the silicon gate electrode with a metal gate electrode.

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