Methods of compensating display panel for reducing luminance discrepancy

Abstract

A method for compensating a display panel includes: providing a refresh control signal to configure a first region and a second region of the display panel; and providing an initial signal to the display panel. The initial signal includes a first initial voltage for initializing the first region before a first data operation, and a second initial voltage for setting the second region without performing any data operation.

Description

Display panel compensation method for reducing brightness differences The present invention relates to display technology, and in particular to a display panel compensation method for reducing brightness differences. A light-emitting diode (LED) display is a flat-panel display that uses a pixel array composed of LEDs. Each pixel is initialized by an initial voltage Vinit before displaying. In related technologies, LED displays use multi-area frame rate (MAFR) technology, which uses different refresh rates for the video area and text area on the screen. For example, the refresh rate of the video area may be higher than that of the text area. If the screen displays the video area and the text area at the same time, the lower refresh rate of the text area may cause the brightness of the text area to be higher than that of the video area over time, resulting in uneven brightness between different areas on the screen, affecting the user experience. According to one embodiment of the present invention, a method for compensating a display panel includes providing a refresh control signal to configure a first region and a second region of the display panel; and providing an initial signal to the display panel. The initial signal includes a first initial voltage for setting the first region before a data operation is performed, and a second initial voltage for setting the second region when no data operation is performed. According to another embodiment of the present invention, a method for compensating a display panel includes providing a refresh control signal to configure a first region and a second region of the display panel; and providing a ground voltage signal. The ground voltage signal includes a first ground voltage for operating the first region and a second ground voltage for operating the second region. The first region is refreshed, while the second region is not refreshed. FIG1 is a block diagram of a display device 1 according to an embodiment of the present invention. Display device 1 may include a display panel 10 and a control circuit 12 coupled to display panel 10. Control circuit 12 may receive image data and control data from a host device to display images on display panel 10. Display panel 10 may be an organic light-emitting diode (OLED) panel, and control circuit 12 may be implemented as a standalone integrated circuit. The display panel 10 may include a pixel array 100 and gate on array (GOA) drivers 102a and 102b. The GOA drivers 102a and 102b are coupled to the pixel array 100. The pixel array 100 may include (N×M) pixels PX, source lines SL(1) to SL(N) and gate lines GL(1) to G(M), where N and M are positive integers. The pixels PX may be arranged in N rows and M columns, and each pixel PX may be a red (R) pixel, a green (G) pixel or a blue (B) pixel. The N rows of pixels PX may be coupled to the control circuit 12 via the source lines SL(1) to SL(N) to receive data signals VD(1) to VD(N) to display an image. The data signals VD(1) to VD(N) may be voltage signals. M columns of pixels PX can be coupled to GOA drivers 102a and 102b via gate lines GL(1) to G(M) to receive gate line voltages G(1) to G(M). Each pixel PX can be coupled to a corresponding gate line and a corresponding source line. The pixel PX can be enabled by a gate signal on the corresponding gate line and can load pixel data on the corresponding source line. For example, if N=1920 and M=1080, the pixel array 100 will include (1920×1080) pixels PX coupled to source lines SL(1) to SL(1920) and gate lines GL(1) to G(1080). The display device 1 can utilize a multi-area refresh rate (MAFR) architecture to divide the pixel array 100 into multiple areas that update at different refresh rates. The refresh rate configuration can be dynamically adjusted based on the image content, allowing for more efficient use of resources and power. The MAFR architecture can reduce power consumption by lowering the refresh rate of low refresh rate areas while maintaining high image quality in high refresh rate areas. Figure 2 is a schematic diagram of the MAFR architecture used by the display device 1. The pixel array 100 is divided into a high refresh rate area 20 and a low refresh rate area 22. The high refresh rate area 20 can display dynamic content that requires frequent updates, while the low refresh rate area 22 can display static content that requires less frequent updates. For example, the high refresh rate area 20 can display video content or game images at a higher refresh rate (typically 120Hz) to ensure smooth movement and reduce motion blur. Conversely, the low refresh rate area 22 can display background elements or user interface elements at 10Hz to reduce power consumption and simultaneously conserve computing resources. The MAFR architecture can adopt an efficient update ratio between the high refresh rate area 20 and the low refresh rate area 22. Every time the high refresh rate area 20 updates data 12 times, the low refresh rate area 22 may only be updated once, which significantly saves power while maintaining appropriate display quality. Therefore, in every 12 frames, only one frame is a fully refreshed frame, which contains pixel data for all pixels PX in the pixel array 100. The other 11 frames are partially refreshed frames, which only contain pixel data for pixels PX in the high refresh rate area 20 and do not contain pixel data for the low refresh rate area 22. That is, in the partially refreshed frame, the pixels PX in the high refresh rate area 20 are refreshed, while the pixels PX in the low refresh rate area 22 are not refreshed. In Figure 2, the pixel array 100 receives a partially refreshed frame, including a vertical back porch interval (VBP), a refreshed area, an unrefreshed area, and a vertical front porch interval (VFP). The contrasting refresh rates result in different brightness levels between the high refresh rate region 20 and the low refresh rate region 22 . In an OLED panel, each pixel PX includes a data storage capacitor. The first terminal of this data storage capacitor can be connected to the supply voltage VDD, and the second terminal receives a target data voltage during each data update, as shown by capacitor Cpx in Figures 5 and 6. In the high refresh rate region 20, frequent updates cause the voltage at the second terminal of the data storage capacitor to approach the target data voltage because the data storage capacitor is charged during each data update. This is known as the resistor-capacitor (RC) loading effect. As a result, the voltage on the data storage capacitor tends to decrease over time, causing the brightness level of the pixels PX in the high refresh rate region 20 to gradually decrease. Conversely, in the low refresh rate region 22, the refresh frequency of pixels PX is lower. Between refreshes, the voltage on the second terminal of the data storage capacitor tends to decay due to current leakage. This decay occurs because the data storage capacitor of pixels PX in the low refresh rate region 22 is only charged once during a few consecutive data updates (e.g., 12 data updates) in the high refresh rate region 20. Therefore, the voltage on the data storage capacitor of pixels PX in the low refresh rate region 22 tends to increase over time, resulting in an increase in brightness level. The difference in brightness levels between high refresh rate regions 20 and low refresh rate regions 22 may result in noticeable differences in brightness levels across pixel array 100. High refresh rate regions 20 may appear brighter than low refresh rate regions 22. These brightness variations may affect the overall visual consistency and quality of the displayed image, posing a challenge to providing uniform brightness across pixel array 100. In order to resolve the brightness difference between the high refresh rate area 20 and the low refresh rate area 22, the display panel 10 can adopt the initial signal Sini from the control circuit 12. The initial signal Sini can be a voltage signal, which is used to initialize the pixel PX before each data update operation (data operation) to ensure that the pixel PX is ready to load data. The initial signal Sini can include different voltage levels tailored for the high refresh rate area 20 and the low refresh rate area 22. By providing different voltage levels in the initial signal Sini, the display panel 10 can compensate for the larger voltage drop of the pixel PX in the high refresh rate area 20 and the smaller voltage drop of the pixel PX in the low refresh rate area 22, ensuring that consistent brightness can be maintained on the pixel array 100 regardless of the refresh rate changes, thereby improving visual quality. In some embodiments, the control circuit 12 can further adjust the supply voltage signal VGH and / or the ground voltage signal VGL for the display panel 10 to compensate for refresh rate variations in the high refresh rate region 20 and the low refresh rate region 22. The supply voltage signal VGH can include different voltage levels for the high refresh rate region 20 and the low refresh rate region 22. Similarly, the ground voltage signal VGL can include different voltage levels for the high refresh rate region 20 and the low refresh rate region 22. The voltage level adjustment of the supply voltage signal VGH and / or the ground voltage signal VGL will be further discussed in subsequent paragraphs. In FIG1 , the control circuit 12 may include a power generator 120, a clock generator (CG) 121, a data driver 122, a timing generator (TG) 123, a data channel circuit 124, an oscillator (OSC) 125, a command decoder 126, and an interface circuit 127. The interface circuit 127 may be coupled to the command decoder 126. The command decoder 126 and the oscillator 125 may be coupled to the timing generator 123. The timing generator 123 may be coupled to the power generator 120, the clock generator 121, and the data channel circuit 124. The data channel circuit 124 may be coupled to the data driver 122. The power generator 120, the clock generator 121, and the data driver 122 may be coupled to the display panel 10. Interface circuit 127 can receive image data and control data from a host device and pass the image data and control data to command decoder 126. Interface circuit 127 can be a mobile industry processor interface (MIPI), a serial peripheral interface (SPI), a display serial interface (DSI), an embedded display port (EDP), a low-voltage differential signaling (LVDS), or other display interface. The host device can be a graphics card, a smartphone, or an embedded system. Image data can include visual content to be displayed on pixel array 100. Control data can be commands for managing the display, such as brightness adjustment or pixel refresh. Command decoder 126 can interpret the control data to generate specific commands for the display, such as refreshing pixels PX, adjusting contrast, or changing display mode. Command decoder 126 can transmit the commands and image data to timing generator 123. The oscillator 125 can generate a system clock and transmit the system clock to the timing generator 123. The timing generator 123 can generate a vertical synchronization (Vsync) signal, a horizontal synchronization (Hsync) signal, and other image control signals based on the system clock, image data, and commands, and transmit the Vsync signal, Hsync signal, and other image control signals to the power generator 120, the clock generator 121, the data channel circuit 124, and the display panel 10. The power generator 120 can use the supply voltage signal VGH, the ground voltage signal VGL, and the initial signal Sini to supply the display panel 10 based on various image control signals used to perform data operations. Therefore, the power generator 120 can generate different voltage levels in the supply voltage signal VGH, the ground voltage signal VGL, and / or the initial signal Sini to compensate for the brightness difference between the high refresh rate area 20 and the low refresh rate area 22 caused by the refresh rate change. The clock generator 121 can generate and supply a start vertical signal STV, a clock signal GCK, a reset signal RST and a refresh control signal MAFR to the display panel 10. The start vertical signal STV indicates the beginning of the pixel data in a frame to facilitate display synchronization. The clock signal GCK can be used to selectively sample pixel data, thereby reducing power consumption. The reset signal RST can be used to reset the GOA drivers 102a and 102b. The refresh control signal MAFR can be used to specify the positions of the high refresh rate area 20 and the low refresh rate area 22. The data channel circuit 124 can process the image data to generate pixel data. The pixel data is then fed to the data driver 122 to generate data signals VD(1) to VD(N). The GOA drivers 102 a and 102 b may receive a start vertical signal STV, a clock signal GCK, a reset signal RST, a refresh control signal MAFR, a power supply voltage signal VGH, a ground voltage signal VGL, and an initialization signal Sini to control data operations of the pixel PX. FIG3 is a flow chart of method 3 for compensating pixel array 100 using initial signal Sini. Method 3 includes steps S302 and S304, which adjust the voltage level of initial signal Sini to reduce or eliminate brightness variations, thereby providing uniform brightness across pixel array 100. Any reasonable variations or adjustments to these steps are within the scope of this disclosure. Details of steps S302 and S304 are as follows: Step S302: The control circuit 12 provides a refresh control signal MAFR to configure the first area and the second area of ​​the display panel 10; and Step S304 : The control circuit 12 provides an initial signal Sini to the display panel 10 . The initial signal Sini includes a first initial voltage for initializing the first region before the first data operation and a second initial voltage for initializing the second region without performing the second data operation. In step S302, the control circuit 12 generates a refresh control signal MAFR to set the boundary between the first and second regions. The first region may be referred to as the refreshed (scanned) region, and pixels PX located in the first region may be refreshed. The second region may be referred to as the unrefreshed (unscanned) region, and pixels PX in the second region may remain unrefreshed. In step S304, the control circuit 12 provides two different initial voltages to the display panel 10 via the initial signal Sini. The first initial voltage is applied to the pixels PX in the first region to prepare them for a first data operation (e.g., a data update operation). Simultaneously, the control circuit 12 provides a second initial voltage to the second region to compensate for any brightness differences resulting from the lack of the second data operation (e.g., a data update operation), thereby maintaining consistent display performance between the first and second regions in the pixel array 100. The second initial voltage is different from the first initial voltage. In this way, the control circuit 12 can adjust the initial signal Sini to balance the visual brightness of the entire pixel array 100. Step 302 can be explained with reference to FIG4. FIG4 is a circuit diagram of the GOA driver 102a / 102b and the pixel array 100. The first region can be a high refresh rate region 20, the second region can be a low refresh rate region 22, and the refresh control signal MAFR can define a boundary Bd. The refresh control signal MAFR can be a voltage signal, including a low voltage level VL for defining the high refresh rate region 20 and a high voltage level VH for defining the low refresh rate region 22. The GOA driver 102a / 102b can include OR gates OR(1) to OR(M). Each OR gate OR(m) includes a first input terminal configured to receive the refresh control signal MAFR, a second input terminal configured to receive the gate enable signal GE(m), and an output terminal coupled to the mth column of pixels PX through a gate line GL(m), where m is an integer from 1 to M. The OR gate OR(m) generates the gate line signal G(m) by performing an OR operation on the refresh control signal MAFR and the gate enable signal GE(m), and transmits the gate line signal G(m) to the m-th row of pixels PX. If the refresh control signal MAFR is at a low voltage level VL, the gate enable signal GE(m) generates the gate line signal G(m) through the OR gate OR(m). In other words, the pulse in the gate enable signal GE(m) appears in the gate line signal G(m), allowing the m-th row of pixels PX to load their respective data voltages. If the refresh control signal MAFR is at a high voltage level VH, the OR gate OR(m) blocks the gate enable signal GE(m), setting the gate line signal G(m) to a high voltage level VH. In other words, the gate line signal G(m) remains at the high voltage level VH regardless of the voltage of the gate enable signal GE(m), preventing the m-th row of pixels PX from loading their respective data voltages. FIG4 shows that the first ends of the OR gates OR(1) to OR(Q) receive the low voltage level VL of the refresh control signal MAFR, and the second ends receive pulses from the gate enable signals GE(1) to GE(Q) in sequence, generating pulses in the gate line signals G(1) to G(Q), thereby enabling the pixels PX in the 1st to Qth columns to be loaded with data voltages in a raster order. Q is a positive integer less than M. Therefore, the pixels PX in the 1st to Qth columns are refreshed to form a high refresh rate region 20. The first ends of the OR gates OR(Q+1) to OR(M) receive the high voltage level VH of the refresh control signal MAFR. Therefore, although the second ends of the OR gates OR(Q+1) to OR(M) receive pulses from the gate enable signals GE(Q+1) to GE(M), the gate line signals G(Q+1) to G(M) remain at the high voltage level VH, preventing the pixels PX in the (Q+1)th to Mth columns from being loaded with data voltages. Therefore, the pixels PX in the (Q+1)th to Mth columns that are not refreshed define a low refresh rate region 22 . Step 304 may be explained with reference to FIG. 5 shows a circuit schematic of a GOA driver 102a / 102b and a pixel PX in a pixel array 100 . The GOA driver 102a / 102b may generate a predetermined initial voltage for the initial signals Sini1, Sini2, and Sini3 provided to the refreshed pixel PX based on a first initial voltage. Furthermore, the GOA driver 102a / 102b may selectively generate a compensated initial voltage for the initial signals Sini1 and Sini3 provided to the unrefreshed pixel PX based on a second initial voltage. The timing of the refresh initial voltages Sini1 and Sini3 remains the same for refreshed pixels PX and unrefreshed pixels PX. The initial signal of unrefreshed pixel PX Sini2 can remain unrefreshed. In some embodiments, the GOA driver 102a / 102b may stop generating an initial signal Sini2 that does not refresh pixel PX or set these signals to a preset voltage (e.g., 0V). GOA drivers 102a / 102b may include driver circuits 50 to 54 to control the operation of pixel PX in pixel array 100 . In some embodiments, driver circuits 50 to 54 may be implemented as integrated circuits located outside the display panel 10 . The pixel PX may include transistors T1 to T8, a capacitor Cpx, and a light-emitting diode (LED) Dpx. Transistors T1 to T8 may be, but are not limited to, P-type thin film transistors, and light-emitting diodes Dpx may be, but are not limited to, organic light-emitting diodes. Capacitor Cpx includes a first terminal and a second terminal coupled to a power supply terminal. The power supply terminal can provide a supply voltage VDD, for example, 8V. Transistor T1 (also known as a light-emitting control transistor) includes a control terminal coupled to the driver circuit 50 to receive a control signal EM, a first terminal coupled to the power supply terminal, and a second terminal. Transistor T2 (also known as a driver transistor) includes a control terminal coupled to the second terminal of capacitor Cpx, a first terminal coupled to the second terminal of transistor T1, and a second terminal. Transistor T3 includes a control terminal coupled to the driver circuit 54 to receive a control signal GN, a first terminal coupled to the control terminal of transistor T2, and a second terminal coupled to the second terminal of transistor T2. Transistor T4 (also known as a light-emitting control transistor) includes a control terminal coupled to the driver circuit 50 to receive a control signal EM, a first terminal coupled to the second terminal of transistor T2, and a second terminal. Light-emitting diode Dpx includes a first terminal (anode) coupled to the second terminal of transistor T4 and a second terminal (cathode) coupled to ground. The ground terminal can provide a ground voltage VSS, for example, 0V. Transistor T5 includes a control terminal coupled to the drive circuit 51 to receive the control signal RH, a first terminal coupled to the second terminal of transistor T1, and a second terminal configured to receive the initial signal Sini1. Transistor T6 (also known as a switching transistor) includes a control terminal coupled to the drive circuit 52 to receive the control signal GP, a first terminal coupled to the second terminal of transistor T1, and a second terminal configured to receive the data signal VD. Transistor T7 includes a control terminal coupled to the drive circuit 53 to receive the control signal RP, a first terminal coupled to the second terminal of transistor T2, and a second terminal configured to receive the initial signal Sini2. Transistor T8 includes a control terminal coupled to the drive circuit 51 to receive the control signal RH, a first terminal coupled to the second terminal of transistor T4, and a second terminal configured to receive the initial signal Sini3. The light-emitting diode Dpx can adjust the brightness of the pixel PX according to the driving current provided by the transistor T2. The transistor T2 can control the amount of driving current according to the voltage of the node N1. The capacitor Cpx can store the voltage of the node N1. The transistors T1 and T4 can control the timing of light emission according to the control signal EM. The transistor T3 can use the initial signal Sini2 to reset the voltage of the node N1 through the transistor T7. The transistor T5 can use the initial signal Sini1 to set the voltage of the node N2, thereby achieving fine-tuning control of the brightness of the pixel PX. The transistor T6 can transmit the data signal VD to the node N2. The transistor T7 can use the initial signal Sini2 to set the voltage of the node N3, and can reset the voltage on the capacitor Cpx through the transistor T3. The transistor T8 can use the initial signal Sini3 to set the voltage of the node N4, thereby achieving coarse-tuning control of the brightness of the pixel PX. In some embodiments, during a data update operation, transistors T3, T7, and T6 may be turned on sequentially, followed by transistor T3 being turned off, and then transistors T5 and T8 being turned on. The timing of the transistors is not limited to the given example. A person skilled in the art will recognize that the transistors of pixel PX may be turned on in other orders to meet specific requirements without departing from the principles of the present invention. The GOA drivers 102a / 102b can generate start signals EM_STV, RH_STV, GP_STV, RP_STV, and GN_STV in response to a start vertical signal STV. Upon receiving a pulse in the start vertical signal STV, the GOA drivers 102a / 102b can generate phase-shifted pulses in the signals EM_STV, RH_STV, GP_STV, RP_STV, and GN_STV. The GOA drivers 102a / 102b can generate phase-shifted clock signals EM_CKB, RH_CK / RH_CKB, GP_CK / GP_CKB, RP_CK / RP_CKB, and GN_CK / GN_CKB based on a clock signal GCK. The clock signals RH_CKB, GP_CKB, RP_CKB, and GN_CKB are inverses of the clock signals RH_CK, GP_CK, RP_CK, and GN_CK, respectively. GOA drivers 102 a / 102 b can generate signals EM_MAFR, RH_MAFR, GP_MAFR, RP_MAFR, and GN_MAFR with different phases according to a refresh control signal MAFR. Furthermore, GOA drivers 102 a / 102 b can generate initial signals Sini1, Sini2, and Sini3 according to an initial signal Sini. GOA drivers 102 a / 102 b can be operated by a supply voltage signal VGH / a ground voltage signal VGL, for example, to generate control signals EM, RH, GP, RP, and GN. The driving circuit 50 can generate a control signal EM based on a start signal EM_STV and a clock signal EM_CK. The driving circuit 51 can generate a control signal RH based on a start signal RH_STV, clock signals RH_CK / RH_CKB, and a signal RH_MAFR. The driving circuit 52 can generate a control signal GP based on a start signal GP_STV, clock signals GP_CK / GP_CKB, and a signal GP_MAFR. The driving circuit 53 can generate a control signal RP based on a start signal RP_STV, clock signals RP_CK / RP_CKB, and a signal RP_MAFR. The driving circuit 54 can receive a control signal GN generated based on a start signal GN_STV, clock signals GN_CK / GN_CKB, and a signal GN_MAFR. The signals RH_MAFR, GP_MAFR, RP_MAFR, and GN_MAFR can be used to control the timing of the control signals RH, GP, RP, and GN to control the brightness of the pixel PX. In some embodiments, the pixel PX may be located in a refreshed area or an unrefreshed area. The voltage levels of the initial signals Sini1, Sini2, and Sini3 may be set according to the location of the pixel PX. For the pixel PX located in the refreshed area, the pixel PX operates under normal conditions. In this case, the initial signals Sini1, Sini2, and Sini3 are set to a predetermined initial voltage to ensure optimal performance during the data update operation. On the other hand, the pixel PX located in the unrefreshed area needs to be compensated. Therefore, the initial signals Sini1 and / or Sini3 can be selectively adjusted. Each selected initial signal is set to a compensated initial voltage, which is different from the corresponding predetermined initial voltage used in the refreshed area, thereby compensating for the brightness difference between the refreshed area and the unrefreshed area. In some embodiments, the initial signal Sini1 can be adjusted to compensate for the brightness of the pixels PX in the unrefreshed area, while the initial signals Sini2 and Sini3 can maintain the same fixed voltage level as those pixels PX in the refreshed area. Therefore, the selective adjustment of the initial signal Sini1 can achieve fine-tuning compensation for brightness variations, ensuring uniform brightness across the entire pixel array 100. The initial signals Sini2 and Sini3 maintain a consistent voltage level regardless of the position of the pixel PX, simplifying the overall compensation mechanism while still allowing effective brightness correction. The initial signal Sini1 can be set to a first initial voltage or a second initial voltage depending on the position of the pixel PX. The compensation mechanism may include the driver circuit 51 turning on the transistor T1 of the unrefreshed pixel PX to provide the first initial voltage to the node N2 of the unrefreshed pixel PX, and turning on the transistor T1 of the refreshed pixel PX to provide the second initial voltage to the node N2 of the refreshed pixel PX. In other embodiments, the initial signals Sini1 and Sini3 can be adjusted to compensate for the brightness of the pixels PX in the unrefreshed area, while the initial signal Sini2 can maintain the same fixed voltage level as those pixels PX in the refreshed area. Therefore, the selective adjustment of the initial signals Sini1 and Sini3 can achieve fine-tuning compensation and coarse-tuning compensation for brightness changes, while maintaining the same voltage level of the initial signal Sini2 in the refreshed area and the unrefreshed area simplifies the compensation mechanism. The initial signal Sini1 can be set to a first initial voltage or a second initial voltage according to the position of the pixel PX, and the initial signal Sini3 can be set to a third initial voltage or a fourth initial voltage according to the position of the pixel PX. The compensation mechanism may include the driving circuit 51 turning on the transistor T1 of the unrefreshed pixel PX to provide a first initial voltage to the node N2 of the unrefreshed pixel PX, turning on the transistor T1 of the refreshed pixel PX to provide a second initial voltage to the node N2 of the refreshed pixel PX, turning on the transistor T8 of the unrefreshed pixel PX to provide a third initial voltage to the node N4 of the unrefreshed pixel PX, and turning on the transistor T8 of the refreshed pixel PX to provide a fourth initial voltage to the node N4 of the refreshed pixel PX. In other embodiments, the initial signal Sini3 can be adjusted to compensate for the brightness of the pixels PX in the unrefreshed area, while the initial signals Sini1 and Sini2 can maintain the same fixed voltage level as those pixels PX in the refreshed area. Therefore, the selective adjustment of the initial signal Sini3 can achieve coarse compensation for brightness variations, ensuring uniform brightness across the entire pixel array 100. The initial signals Sini1 and Sini2 maintain a consistent voltage level regardless of the position of the pixel PX, simplifying the overall compensation mechanism while still allowing effective brightness correction. The initial signal Sini3 can be set to a first initial voltage or a second initial voltage depending on the position of the pixel PX. The compensation mechanism may include the driver circuit 51 turning on the transistor T8 of the unrefreshed pixel PX to provide the first initial voltage to the node N4 of the unrefreshed pixel PX, and turning on the transistor T8 of the refreshed pixel PX to provide the second initial voltage to the node N4 of the refreshed pixel PX. FIG6 is a circuit diagram of a GOA driver 602a / 602b and a pixel PX6 in the pixel array 100 according to another embodiment of the present invention. The GOA drivers 602a / 602b can replace the GOA drivers 102a / 102b, and the pixel PX6 can replace the pixel PX in FIG5. The GOA drivers 602a / 602b can generate predetermined initial voltages for the initial signals Sini2 and Sini3 provided to the refreshed pixel PX6 based on a first initial voltage. Furthermore, the GOA drivers 602a / 602b can selectively generate compensated initial voltages for the initial signals Sini2 and Sini3 provided to the unrefreshed pixel PX6 based on a second initial voltage. GOA drivers 602a / 602b may include drivers 60 and 61 to control the operation of pixel PX6. In some embodiments, driver circuits 60 and 61 may be implemented as integrated circuits located outside the display panel 10 . Pixel PX6 may include transistors T1 to T4, transistors T6 to T8, capacitors Cpx and light-emitting diodes (LEDs) Dpx. Transistors T1 to T4 and T6 to T8 may, but are not limited to, P-type thin film transistors, and light-emitting diodes Dpx may, but are not limited to, organic light-emitting diodes. The capacitor Cpx includes the first and second terminals coupled to the power supply terminal. Supply voltage VDD, such as 8V, can be provided at the power supply end. The transistor T1 (also referred to as the light-emitting control transistor) includes a control terminal coupled to the driver circuit 61 to receive the control signal EM, a first and second terminals coupled to the power supply terminal. Transistor T2 (also called a driver transistor) includes a control terminal coupled to the second terminal of the capacitor Cpx, a first and second terminal coupled to the second terminal of the transistor T1. The transistor T3 includes a control terminal coupled to the driver circuit 60 to receive the control signal GP, a first terminal coupled to the control terminal of the transistor T2 and a second terminal coupled to the second terminal of the transistor T2. Transistor T4 (also referred to as light-emitting control transistor) includes a control terminal coupled to driver circuit 61 to receive the control signal EM, a first terminal coupled to a second terminal of transistor T2 and a second terminal. The light-emitting diode Dpx includes a first terminal (anode) coupled to the second terminal of transistor T4 and a second terminal (cathode) coupled to the ground terminal. The ground terminal may provide a ground voltage VSS, such as 0V. Transistor T6 (also referred to as switching transistor) includes a control terminal coupled to driver circuit 60 to receive the control signal GP, a first terminal coupled to a second terminal of transistor T1 and a second terminal configured to receive a data signal VD. Transistor T7 includes a control terminal coupled to driver circuit 60 to receive the control signal RP, a first terminal coupled to a second terminal of the capacitor Cpx and a second terminal configured to receive the initial signal Sini2. Transistor T8 includes a control terminal coupled to driver circuit 60 to receive a control signal RH, a first terminal coupled to a second terminal of transistor T4 and a second terminal configured to receive an initial signal Sini3. The operation of transistors T1 to T4 and T6 to T8 can be similar to that in Fig. 5. For brevity, the explanation is not repeated here. GOA drivers 602a / 602b can generate phase-shifted clock signals CK1, CK2, CK3, and CK4 based on the clock signal GCK. Furthermore, GOA drivers 602a / 602b can generate initial signals Sini2 and Sini3 based on the initial signal Sini. GOA drivers 602a / 602b can be operated by the supply voltage signal VGH / ground voltage signal VGL, for example, to generate control signals EM, GP, RH, and RP. Driver circuit 60 can generate control signals GP, RH, and RP based on the start vertical signal STV, the refresh control signal MAFR, and the clock signals CK1, CK2, CK3, and CK4. Driver circuit 61 can generate control signal EM based on the start vertical signal STV, the refresh control signal MAFR, and the clock signals CK1, CK2, CK3, and CK4. The voltage levels of the initial signals Sini2 and Sini3 can be selectively compensated according to the position of the pixel PX6. In other embodiments, the initial signal Sini3 can be adjusted to compensate for the brightness of the pixels PX6 in the unrefreshed area, while the initial signal Sini2 can maintain the same fixed voltage level as those pixels PX in the refreshed area. Therefore, the selective adjustment of the initial signal Sini3 can achieve fine-tuned brightness compensation while maintaining a consistent voltage level for the initial signal Sini2, simplifying the overall compensation mechanism regardless of the position of the pixel PX6. The initial signal Sini3 can be set to a first initial voltage or a second initial voltage depending on the position of the pixel PX6. The compensation mechanism may include the driving circuit 60 turning on the transistor T8 of the unrefreshed pixel PX6 to provide the first initial voltage to the node N4 of the unrefreshed pixel PX6, and turning on the transistor T8 of the refreshed pixel PX6 to provide the second initial voltage to the node N4 of the refreshed pixel PX6. In other embodiments, the initial signals Sini2 and Sini3 can be adjusted to compensate for the brightness of the pixel PX6 in the unrefreshed area. The initial signal Sini3 can be set to a first initial voltage or a second initial voltage according to the position of the pixel PX6, and the initial signal Sini2 can be set to a third initial voltage or a fourth initial voltage according to the position of the pixel PX6. The compensation mechanism may include the driver circuit 60 turning on the transistor T8 of the unrefreshed pixel PX6 to provide the first initial voltage to the node N4 of the unrefreshed pixel PX6, and turning on the transistor T8 of the refreshed pixel PX6 to provide the second initial voltage to the node N4 of the refreshed pixel PX6, and the driver circuit 53 turning on the transistor T7 of the unrefreshed pixel PX6 to provide the third initial voltage to the second end of the capacitor Cpx in the unrefreshed pixel PX6, and turning on the transistor T7 of the refreshed pixel PX6 to provide the fourth initial voltage to the second end of the capacitor Cpx in the refreshed pixel PX6. In other embodiments, the initial signal Sini2 can be adjusted to compensate for the brightness of the pixels PX6 in the unrefreshed area, while the initial signal Sini3 can maintain the same fixed voltage level as those pixels PX in the refreshed area. The initial signal Sini2 can be set to a first initial voltage or a second initial voltage depending on the position of the pixel PX6. The compensation mechanism can include the driver circuit 60 turning on the transistor T7 of the unrefreshed pixel PX6 to provide the first initial voltage to the second end of the capacitor Cpx in the unrefreshed pixel PX6, and turning on the transistor T7 of the refreshed pixel PX6 to provide the second initial voltage to the second end of the capacitor Cpx in the refreshed pixel PX6. FIG7 is a schematic diagram of a MAFR architecture used in a display device 1 according to another embodiment of the present invention. Pixel array 100 is divided into active areas 71 through 73. Active areas 71 and 73 can display textual content that requires less frequent updates (e.g., 10 Hz), while active area 72 can display video content that requires more frequent updates (e.g., 120 Hz). While FIG7 illustrates a specific refresh rate, those skilled in the art will recognize that active areas 71 through 73 can be updated at other refresh rates depending on the displayed content. Figures 8A and 8B are timing diagrams of the display device 1 according to the MAFR architecture shown in Figure 7. Figures 8A and 8B illustrate a partially refreshed frame including the vertical back porch interval (VBP), active areas 71 to 73, and the vertical front porch interval (VFP). The initialization signal Sini can switch between initial voltages VinitA and VinitB based on a line or a clock. For line-based switching, the switching of the initialization signal Sini occurs simultaneously with the switching of the refresh control signal MAFR, which configures the active areas 71 to 73. In Figure 8A, the partially refreshed frame starts at pulse V81 of the Vsync signal and ends at pulse V82. Active regions 71 and 73 are not refreshed, as indicated by the high logic level of the refresh control signal MAFR, and the initial signal Sini is set to the initial voltage VinitA to perform brightness compensation and reduce flickering. In contrast, the active region 72 is refreshed, as indicated by the low logic level of the refresh control signal MAFR, and the initial signal Sini is set to the initial voltage VinitB to perform the data update operation. The initial signal Sini may be set to, but not limited to, the initial voltage VinitA during the refresh of the vertical hind shoulder spacer VBP and the vertical front shoulder spacer VFP. In that example, the falling edge transition T81 of the refresh control signal MAFR is aligned with the switch T82 from the initial voltage VinitA to the initial voltage VinitB in the initial signal Sini. The rising edge transition T83 of the refresh control signal MAFR is aligned with the switch T84 from the initial voltage VinitB to the initial voltage VinitA in the initial signal Sini. The initial voltage VinitA may be, but is not limited to, 3.1V, and the initial voltage VinitB may be, but not limited to, 3V. In Figure 8B , a partially refreshed frame starts at pulse V83 of the Vsync signal and ends at pulse V84. Active regions 71 and 73 are refreshed, as indicated by the low logic level of the refresh control signal MAFR, and the initial signal Sini is set to the initial voltage VinitB to perform the data update operation. In contrast, the active region 72 is not refreshed, as indicated by the high logic level of the refresh control signal MAFR, and the initial signal Sini is set to the initial voltage VinitA for brightness compensation. The initial signal Sini is set to the initial voltage VinitA during the refresh of the vertical posterior shoulder spacing VBP and the vertical front shoulder spacing VFP. In that example, the rising edge switch T85 of the refresh control signal MAFR is aligned with the switch T86 from the initial voltage VinitB to the initial voltage VinitA in the initial signal Sini. The falling edge switch T87 of the refresh control signal MAFR is aligned with the switch T88 from the initial voltage VinitA to the initial voltage VinitB in the initial signal Sini. Figures 9A and 9B are timing diagrams of a display device 1 according to the MAFR architecture of Figure 7, according to another embodiment of the present invention. Figures 9A and 9B are similar to Figure 8B, except that the switching of the initial signal Sini precedes the switching of the refresh control signal MAFR that configures the active areas 71 to 73 in Figure 9A, and the switching of the initial signal Sini lags behind the switching of the refresh control signal MAFR that configures the active areas 71 to 73 in Figure 9B. Figures 9A and 9B address the issue of clock-based switching of the initial signal Sini, the potential misalignment of the switching of the refresh control signal MAFR, and the switching of the initial signal Sini. For example, the control circuit 12 can operate with a system clock CLK having a clock period Tck, and the duration of one line can be equal to 90 clock periods Tck. In Figure 9A, the partial refresh frame begins with pulse V91 of the Vsync signal and ends with pulse V92. Switching of initial voltage Sini (T91) can occur 200 lines (=18,000 clock cycles Tck) before switching of refresh control signal MAFR (T92). Therefore, GOA drivers 102a and 102b have sufficient time to respond to the switching of initial voltage Sini and generate compensated initial voltages for initial signals Sini1, Sini2, and / or Sini3. In FIG9B , the partial refresh frame begins with pulse V93 of the Vsync signal and ends with pulse V94. Switching of initial voltage Sini (T93) can occur 200 lines (=18,000 clock cycles Tck) after switching of refresh control signal MAFR (T94). Figure 10 shows a waveform diagram of the initial signal Sini switching from initial voltage VinitA to initial voltage VinitB. The horizontal axis represents time, and the vertical axis represents initial signal Sini in volts (V). The switching of initial signal Sini can be step-wise. Initial signal Sini can be set to initial voltage VinitB at time t0 and gradually increase from initial voltage VinitB before time t1 to initial voltage VinitA after time t4, passing through three intermediate voltage levels. This step-wise switching can reduce undesirable noise in display device 1. Figure 11 is a schematic diagram of initialization signals Sini1 / Sini2 / Sini3 for refreshed pixels PX in the Nth line according to another embodiment of the present invention, where the horizontal axis represents time. Each pulse in the horizontal synchronization (Hsync) signal represents the beginning of a line. For example, the (N-5)th line begins with pulse H1 of the Hsync signal and ends with pulse H2 of the Hsync signal, while the Nth line begins with pulse H3 of the Hsync signal and ends with pulse H4 of the Hsync signal. In pixel PX, nodes N2 and / or N4 can be initialized using initialization signals Sinit1 and / or Vinit3 for three lines, then node N3 can be initialized using initialization signal Sinit2 for two lines, and then node N2 can receive pixel data Data N for one line. Therefore, pixel PX requires six lines to complete the data refresh operation. In some embodiments, nodes N2 and / or N4 can be initialized from the (N-5)th line to the (N-3)th line by the initial signals Sinit1 and / or Vinit3, and node N3 can be initialized from the (N-3)th line to the (N-1)th line by the initial signal Sinit2. Then, node N2 can be set by the pixel data Data N during the Nth line, completing the initialization before feeding the pixel data Data N. Figure 12 is a timing diagram of a display panel in the related art, where the horizontal axis represents time and the vertical axis represents various signals in volts (V). Signal GN_MAFR controls the state of control signal GN(m). Supply voltage signal VGH sets the high voltage level of control signal GN(m), while ground voltage signal VGL sets the low voltage level of control signal GN(m). When signal GN_MAFR switches from a high logic level to a low logic level, both supply voltage signal VGH and ground voltage signal VGL may experience different load conditions, causing the voltage levels of supply voltage signal VGH and ground voltage signal VGL to change, respectively. At time t1, the control signal EM(m) switches from a low logic level to a high logic level. The signal GN_MAFR is set to a logic high level, generating a high load condition from the perspective of the power supply voltage signal VGH and the ground voltage signal VGL. At time t2, the control signal GN(m) switches from a low voltage level L0 to a high voltage level L1, preventing the pixel PX from being refreshed. The low voltage level L0 can be set by the first ground voltage of the ground voltage signal VGL. The high voltage level L1 can be set by the first supply voltage of the supply voltage signal VGH. At time point t3, the signal GN_MAFR switches from a high logic level to a low logic level, preparing to control the signal GN(m) to switch from a high state to a low state. Once the signal GN_MAFR switches to a low state, the supply voltage signal VGH and the ground voltage signal VGL may experience a light load condition. Therefore, due to the light load condition, the supply voltage signal VGH may become higher, while the ground voltage signal VGL may become lower. In an embodiment, under the light load condition, the supply voltage signal VGH may increase from a high voltage level L1 to a high voltage level L2, while the ground voltage signal VGL may decrease from a low voltage level L3 to a low voltage level L4. The high voltage level L1 may be +8V, the high voltage level L2 may be +9V, the low voltage level L3 may be -8V, and the low voltage level L4 may be -9V. Between time point t3 and time point t4 , the control signal GN(m) is set to a high logic level L2 because the voltage level of the power supply voltage signal VGH increases. After time point t4 , the control signal GN(m) is set to a low logic level L4 because the voltage level of the ground voltage signal VGL decreases. At time point t5 , the control signal EM(m) transitions from a high logic level to a low logic level. Therefore, the voltage difference between the high voltage level and the low voltage level of the control signal GN(m) increases under light load conditions, generating greater capacitive coupling under light load conditions than under heavy load conditions, affecting the voltage on the capacitor Cpx, and causing severe flicker effects on the pixel array 100. FIG13 is a flow chart of method 13 for compensating a display panel using the supply voltage signal VGH and / or the ground voltage signal VGL. Method 13 includes steps S1302 through S1306 to reduce flicker effects on pixel array 100. Any reasonable variations or adjustments to these steps are within the scope of this disclosure. Details of steps S1302 through S1306 are as follows: Step S1302 : The control circuit 12 provides a refresh control signal MAFR to configure the first area and the second area of ​​the display panel 10 ; Step S1304: the control circuit 12 provides a ground voltage signal VGL, wherein the ground voltage signal VGL includes a first ground voltage for operating in the first region and a second ground voltage for operating in the second region; and Step S1306 : The control circuit 12 provides a power supply voltage signal VGH, and the power supply voltage signal VGH includes a first power supply voltage for operating the first region and a second power supply voltage for operating the second region. In step S1302, the first region may be referred to as a refreshed (scanned) region, and the pixels PX in the first region may be refreshed. The second region may be referred to as an unrefreshed (unscanned) region, and the pixels PX in the second region may remain unrefreshed. In step S1304, the control circuit 12 provides two different ground voltages to the display panel 10 via the ground voltage signal VGL. The first ground voltage can be lower than the second ground voltage to compensate for the flicker effect. In some embodiments, the control circuit 12 can determine the first ground voltage based on the ratio of the first area to the fully enabled area of ​​the pixel array 100. The switching of the ground voltage signal VGL can occur simultaneously with the switching of the refresh control signal MAFR that configures the second area. In some embodiments, the switching of the ground voltage signal VGL can precede the switching of the refresh control signal that configures the second area, providing sufficient time for the GOA driver 102a / 102b to use the updated ground voltage in the ground voltage signal VGL to generate a signal. In some embodiments, the switching of the ground voltage signal VGL can lag behind the switching of the refresh control signal that configures the second area. Similarly, in step S1306, the control circuit 12 provides two different supply voltages to the display panel 10 via the supply voltage signal VGH. The first supply voltage may be higher than the second supply voltage to compensate for the flicker effect. In some embodiments, the control circuit 12 may determine the first supply voltage based on the ratio of the first area to the fully enabled area of ​​the pixel array 100. The switching of the supply voltage signal VGH may occur simultaneously with the switching of the refresh control signal MAFR that configures the second area. In some embodiments, the switching of the supply voltage signal VGH may precede the switching of the refresh control signal that configures the second area, providing sufficient time for the GOA driver 102a / 102b to use the updated ground voltage in the supply voltage signal VGH to generate a signal. In some embodiments, the switching of the supply voltage signal VGH may lag behind the switching of the refresh control signal that configures the second area. The first ground voltage and the first power supply voltage are applied to the pixels PX in the first area, and the second ground voltage and the second power supply voltage are applied to the pixels PX in the second area, thereby reducing a flicker effect. Display device 1 can use methods 3 and 13 independently or together. Figures 14A and 14B are timing diagrams of display device 1 using methods 3 and 13 based on the MAFR architecture in Figure 7. Figures 14A and 14B show a partially refreshed frame including vertical back porch interval VBP, active areas 71 to 73, and vertical front porch interval VFP. Initial signal Sini can switch between initial voltages VinitA and VinitB. Supply voltage signal VGH can switch between supply voltages VGHA and VGHB. Ground voltage signal VGL can switch between ground voltages VGLA and VGLB. In FIG14A , the partially refreshed frame begins with pulse V141 of the Vsync signal and ends with pulse V142 . Active areas 71 and 73 are refreshed, as indicated by a low logic level of the refresh control signal MAFR. Initial signal Sini is set to initial voltage VinitB, supply voltage signal VGH is set to supply voltage VGHB, and ground voltage signal VGL is set to ground voltage VGLB to perform a data refresh operation. Conversely, active area 72 is not refreshed, as indicated by a high logic level of the refresh control signal MAFR. Initial signal Sini is set to initial voltage VinitA for brightness compensation, supply voltage signal VGH is set to supply voltage VGHA, and ground voltage signal VGL is set to ground voltage VGLA to reduce flicker. During the refresh period of the vertical back porch interval VBP and the vertical front porch interval VFP, the initial signal Sini may be set to, but not limited to, the initial voltage VinitA, the supply voltage signal VGH may be set to, but not limited to, the supply voltage VGHA, and the ground voltage signal VGL may be set to, but not limited to, the ground voltage VGLA. The switching of the refresh control signal MAFR may be aligned with the switching of the initial signal Sini, the supply voltage signal VGH, and the ground voltage signal VGL. FIG14B shows a partially refreshed frame starting with pulse V143 of the Vsync signal and ending with pulse V144. Active areas 71 and 73 are not refreshed, as indicated by the high logic level of the refresh control signal MAFR. The initialization signal Sini is set to the initialization voltage VinitA for brightness compensation, the supply voltage signal VGH is set to the supply voltage VGHA, and the ground voltage signal VGL is set to the ground voltage VGLA to reduce flicker. During the refresh of the vertical back porch interval VBP and the vertical front porch interval VFP, the initialization signal Sini may be set to, but not limited to, the initial voltage VinitA, the supply voltage signal VGH may be set to, but not limited to, the supply voltage VGHA, and the ground voltage signal VGL may be set to, but not limited to, the ground voltage VGLA. The switching of the refresh control signal MAFR may be aligned with the switching of the initialization signal Sini, the supply voltage signal VGH, and the ground voltage signal VGL. For different brightness levels in the pixel array 100, the control circuit 12 can output different voltages, Vinit, for refreshed and unrefreshed areas. For example, for a brightness of 100 nits, the control circuit 12 can output initial voltages, VinitB and VinitA, for refreshed and unrefreshed frames, respectively. For a brightness of 2 nits, the control circuit 12 can output initial voltages, VinitB2 and VinitA2, for refreshed and unrefreshed frames, respectively. The values ​​of the initial voltages, VinitA and VinitA2, can be different, and the values ​​of the initial voltages, VinitB and VinitB2, can also be different. The control circuit 12 can store a voltage lookup table for determining the appropriate initial voltage for a given brightness level. Figures 15A to 15C are timing diagrams of a display device 1 using methods 3 and 14 according to another embodiment of the present invention. Figures 15A to 15C illustrate a partially refreshed frame including a vertical back porch interval VBP, active areas 71 to 73, and a vertical front porch interval VFP. In Figure 15A, the partially refreshed frame begins with pulse V151 of the Vsync signal and ends with pulse V152. In Figure 15B, the partially refreshed frame begins with pulse V153 of the Vsync signal and ends with pulse V154. In Figure 15C, the partially refreshed frame begins with pulse V155 of the Vsync signal and ends with pulse V156. The initialization signal Sini can switch between any two of the initialization voltages VinitA to VinitD. The supply voltage signal VGH can switch between any two of the supply voltages VGHA to VGHD. The ground voltage signal VGL can switch between any two of the ground voltages VGLA to VGLD. In some embodiments, the initial voltage can be provided to the pixel array 100 based on the ratio of the unrefreshed area to the fully enabled area of ​​the pixel array 100, as shown in Figures 15A to 15C. For example, if the control circuit 12 needs to refresh the entire screen, the initial voltage VinitC and the high voltage levels VGHC / VGLC are used. If the control circuit 12 does not refresh the entire screen, the initial voltage VinitD and the high voltage levels VGHD / VGLD are used. If the unrefreshed area occupies 80% of the entire screen, the initial voltage VinitA-1 (not shown) and the high voltage levels VGH-A1 / VGL-A1 (not shown) are used. If the unrefreshed area occupies 5% of the entire screen, the initial voltage VinitA-2 (not shown) and the high voltage levels VGH-A2 / VGL-A2 (not shown) are used. The control circuit 12 can store a voltage lookup table for determining the appropriate initial voltage for a given ratio. Embodiments of the present invention provide a method for compensating a display panel by adjusting the initial voltage signal, the supply voltage signal, and the ground voltage signal, thereby eliminating brightness variations and mitigating flicker effects. The foregoing description is merely a preferred embodiment of the present invention. All equivalent variations and modifications made within the scope of the present invention are intended to be covered by the present invention. 1: Display device 3, 13: Method 12: Control circuit 10: Display panel 20: High refresh rate area 22: Low refresh rate area 50 to 54, 60, 61: Driving circuit 71 to 73: Active area 100: Pixel array 102a, 102b, 602a, 602b: GOA driver 120: Power generator 121: Clock generator 122: Data driver 123: Timing generator 124: Data channel circuit 125: Oscillator 126: Command decoder 127: Interface circuit Bd: Boundary CK1, CK2, CK3, CK4: Clock signal Cpx: Capacitor Data N: Pixel data Dpx: Light emitting diode EM, EM(m): Control signal EM_STV: Start signal EM_CKB: Clock signal GE(1) to GE(M), GE(Q), GE(Q+1): Gate enable signal GL(1) to GL(M), GL(Q), GL(Q+1), G(1) to G(M): Gate line GCK: Clock signal GP: Control signal GN, GN(m): Control signal GP_STV: Start signal GP_CK: Clock signal GP_MAFR: Signal GN_STV: Start signal GN_CK: Clock signal GN_MAFR: Signal Hsync: Horizontal synchronization signal H1, H2, H3, H4: Pulse L0, L3, L4: Low voltage level L1, L2: High voltage level MAFR: Refresh control signal N1, N2, N3, N4: Nodes PX, PX6, PX(1,1) to PX(N,M): Pixels OR(1) to OR(M), OR(Q), OR(Q+1): OR gate RST: Reset signal RH: Control signal RP: Control signal RH_STV: Start signal RH_CK: Clock signal RH_CKB: Clock signal RH_MAFR: Signal RP_STV: Start signal RP_CK: Clock signal RP_MAFR: Signals S302, S304, S1302, S1304, S1306: STV: Starting vertical signal Sini, Sini1, Sini2, Sini3: Initial signal SL(1) to SL(N): Source line T1 to T8: Transistor T81, T87: Falling edge switching T82, T84, T86, T88, T91, T92, T93, T94: Switching T83, T85: Rising edge switching t0, t1, t2, t3, t4, t5: Time points V81 to V84, V91 to V94, V141 to V144, V151 to V156: Pulse VBP: vertical back porch interval VDD: power supply voltage VD(1) to VD(N), VD(1:N): data signal VFP: vertical front porch interval VinitA, VinitB, VinitC, VinitD: initial voltage VGH: power supply voltage signal VGHA, VGHB, VGHC, VGHD: power supply voltage VGL: ground voltage signal VGLA, VGLB, VGLC, VGLD: ground voltage VH: high voltage level VL: low voltage level VSS: ground voltage, Figure 1 is a block diagram of a display device according to an embodiment of the present invention. Figure 2 is a schematic diagram of a MAFR structure in the display device of Figure 1 according to an embodiment of the present invention. Figure 3 is a flow chart of a method for compensating a display panel using the initial voltage signal of Figure 1 according to an embodiment of the present invention. Figure 4 is a schematic diagram of the circuitry of the GOA driver and pixel array of Figure 1 according to an embodiment of the present invention. Figure 5 is a schematic diagram of the circuitry of the GOA driver and pixel PX in the pixel array of Figure 1 according to another embodiment of the present invention. Figure 6 is a schematic diagram of the circuitry of the GOA driver and pixel PX in the pixel array of Figure 1 according to another embodiment of the present invention. Figure 7 is a schematic diagram of the MAFR structure used in the display device of Figure 1 according to another embodiment of the present invention. Figures 8A and 8B are timing diagrams of the display device of the MAFR structure of Figure 7. Figures 9A and 9B are timing diagrams of the display device of the MAFR structure of Figure 7 according to another embodiment of the present invention. Figure 10 is a waveform diagram of the initial signal of Figure 1. Figure 11 is a schematic diagram of the initial signal for refreshing pixel PX of Figure 5. Figure 12 is a timing diagram of a display panel in the related art. FIG13 is a flow chart of a method for compensating a display panel using a supply voltage signal and / or a ground voltage signal according to one embodiment of the present invention. FIG14A and FIG14B are timing diagrams of a display device according to another embodiment of the present invention. FIG15A, FIG15B, and FIG15C are timing diagrams of a display device according to another embodiment of the present invention. 3: Method S302, S304: Steps

Claims

1. A method for compensating a display panel, comprising: Provide a refresh control signal to configure a first area and a second area of ​​the display panel; It also provides an initial signal to the display panel, the initial signal including a first initial voltage for setting the first area before a data operation, and a second initial voltage for setting the second area without performing any data operation.

2. The method as described in request 1, wherein the switching of the initial signal and the switching of the refresh control signal occur simultaneously to configure the first region.

3. The method as described in claim 1, wherein the switching of the initial signal precedes the switching of the refresh control signal to configure the first region.

4. The method as described in claim 1, wherein the initial signal is switched in a step manner.

5. The method as described in claim 1, further comprising: A power supply voltage signal is provided, the power supply voltage signal including a first power supply voltage for operating the first region and a second power supply voltage for operating the second region.

6. The method described in claim 5 further includes: The first power supply voltage is determined based on the ratio of the first region to a fully active region of the display panel.

7. The method as described in claim 5, wherein the first supply voltage is higher than the second supply voltage.

8. The method as described in claim 1, further comprising: A ground voltage signal is provided, the ground voltage signal including a first ground voltage for operating the first region and a second ground voltage for operating the second region.

9. The method described in claim 8 further includes: The first ground voltage is determined based on the ratio of the first region to a fully enabled region of the display panel.

10. The method as described in claim 8, wherein the first ground voltage is lower than the second ground voltage.

11. The method of claim 1, wherein the display panel includes a driving circuit and a pixel array comprising a plurality of pixels, each pixel comprising: A capacitor includes a first terminal and a second terminal coupled to a power supply terminal; a first transistor includes a control terminal, a first terminal coupled to the power supply terminal, and a second terminal; a second transistor includes a control terminal coupled to the second terminal of the capacitor, a first terminal coupled to the second terminal of the first transistor, and a second terminal; a third transistor includes a control terminal, a first terminal coupled to the second terminal of the capacitor, and a second terminal coupled to the second terminal of the second transistor; a fourth transistor includes a control terminal, a first terminal coupled to the second terminal of the second transistor, and a second terminal; a light-emitting diode includes a first terminal coupled to the second terminal of the fourth transistor and a second terminal coupled to a ground terminal; a fifth transistor includes a control terminal coupled to the driving circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal. A sixth transistor includes a control terminal coupled to the driving circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal configured to receive a data signal; a seventh transistor includes a control terminal coupled to the driving circuit, a first terminal coupled to the second terminal of the second transistor, and a second terminal; and an eighth transistor includes a control terminal coupled to the driving circuit, a first terminal coupled to the second terminal of the fourth transistor, and a second terminal.

12. The method as described in claim 11, further comprising: The driving circuit turns on the fifth transistor of a pixel in the first region to provide the first initial voltage to the second terminal of the first transistor of the pixel in the first region; and the driving circuit turns on the fifth transistor of a pixel in the second region to provide the second initial voltage to the second terminal of the first transistor of the pixel in the second region.

13. The method as described in claim 12, further comprising: The driving circuit turns on the eighth transistor of the pixel in the first region to provide a third initial voltage to the second terminal of the fourth transistor of the pixel in the first region; and the driving circuit turns on the eighth transistor of the pixel in the second region to provide a fourth initial voltage to the second terminal of the fourth transistor of the pixel in the second region.

14. The method as described in claim 11, further comprising: The driving circuit turns on the eighth transistor of a pixel in the first region to provide the first initial voltage to the second terminal of the fourth transistor of the pixel in the first region; and the driving circuit turns on the eighth transistor of a pixel in the second region to provide the second initial voltage to the second terminal of the fourth transistor of the pixel in the second region.

15. The method of claim 1, wherein the display panel includes a driving circuit and a pixel array comprising a plurality of pixels, each pixel comprising: A capacitor includes a first terminal and a second terminal coupled to a power supply terminal; a first transistor includes a control terminal, a first terminal coupled to the power supply terminal, and a second terminal; a second transistor includes a control terminal coupled to the second terminal of the capacitor, a first terminal coupled to the second terminal of the first transistor, and a second terminal; a third transistor includes a control terminal, a first terminal coupled to the second terminal of the capacitor, and a second terminal coupled to the second terminal of the second transistor; a fourth transistor includes a control terminal, a first terminal coupled to the second terminal of the second transistor, and a second terminal; a light-emitting diode includes a first terminal coupled to the second terminal of the fourth transistor and a second terminal coupled to a ground terminal; a fifth transistor includes a control terminal coupled to the driving circuit, a first terminal coupled to the second terminal of the capacitor, and a second terminal. A sixth transistor includes a control terminal coupled to the driving circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal configured to receive a data signal; and a seventh transistor includes a control terminal coupled to the driving circuit, a first terminal coupled to the second terminal of the fourth transistor, and a second terminal.

16. The method as described in claim 15, further comprising: The driving circuit turns on the seventh transistor of a pixel in the first region to provide the first initial voltage to the second terminal of the fourth transistor of the pixel in the first region; and the driving circuit turns on the seventh transistor of a pixel in the second region to provide the second initial voltage to the second terminal of the fourth transistor of the pixel in the second region.

17. The method as described in claim 16, further comprising: The driving circuit turns on the fifth transistor of the pixel in the first region to provide a third initial voltage to the second terminal of the capacitor of the pixel in the first region; and the driving circuit turns on the fifth transistor of the pixel in the second region to provide a fourth initial voltage to the second terminal of the capacitor of the pixel in the second region.

18. The method as described in claim 15, further comprising: The driving circuit turns on the fifth transistor of a pixel in the first region to provide the first initial voltage to the second terminal of the capacitor of the pixel in the first region; and the driving circuit turns on the fifth transistor of a pixel in the second region to provide the second initial voltage to the second terminal of the capacitor of the pixel in the second region.

19. A method for compensating a display panel, the method comprising: Provide a refresh control signal to configure a first area and a second area of ​​the display panel; It also provides a ground voltage signal, the ground voltage signal including a first ground voltage for operating the first region and a second ground voltage for operating the second region; wherein the first region is refreshed, while the second region is not refreshed.

20. The method of claim 19, further comprising: The first ground voltage is determined based on the ratio of the first region to a fully enabled region of the display panel.

21. The method as described in claim 19, wherein the first ground voltage is lower than the second ground voltage.

22. The method as described in claim 19, wherein the switching of the ground voltage signal and the switching of the refresh control signal occur simultaneously to configure the second region.

23. The method of claim 19, wherein the switching of the ground voltage signal precedes the switching of the refresh control signal to configure the second region.

24. The method as described in claim 19, further comprising: A power supply voltage signal is provided, the power supply voltage signal including a first power supply voltage for operating the first region and a second power supply voltage for operating the second region.

25. The method as described in claim 24, further comprising: The first power supply voltage is determined based on the ratio of the first region to a fully active region of the display panel.

26. The method as described in claim 24, wherein the first supply voltage is higher than the second supply voltage.

27. The method as described in claim 24, wherein the switching of the power supply voltage signal and the switching of the refresh control signal occur simultaneously to configure the second region.

28. The method as described in claim 24, wherein the switching of the power supply voltage signal precedes the switching of the refresh control signal to configure the second region.

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