Cell region and method of manufacturing the same

Abstract

The cell region of this embodiment includes: a transistor element layer comprising a first feedthrough via (FTA); a first metallization layer above the transistor element layer, including a first front segment, the first front segment including first and second front power grid (FPG) segments, and one or more front routing (FRTE) segments, including the first FRTE segment; and a first buried metallization layer below the transistor element layer, including a first back segment, the first back segment including first and second back power grid (BPG) segments, and one or more back routing (BRTE) segments, including the first BRTE segment. The first FTA couples the first FRTE segment to the first BRTE segment. The first BPG segment has a first groove relative to a first direction and a second direction perpendicular to the first direction, the groove portion being occupied by at least a first portion of the first BRTE segment.

Description

Prior Technology

[0001] The integrated circuit (IC) industry manufactures various analog and digital devices to solve problems in multiple different fields. Advances in semiconductor manufacturing technology nodes have progressively reduced component size and spacing, leading to a gradual increase in transistor density. ICs have become smaller. Simple Explanation of the Diagram

[0002] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 is a block diagram according to some embodiments. Figures 2A-2I are corresponding layout diagrams according to some embodiments. Figures 3A-3E are corresponding layout diagrams according to some embodiments. Figures 4A-4C are corresponding layout diagrams according to some embodiments. Figures 5A-5B are corresponding cross-sections according to some embodiments. Figures 6A-6D are corresponding block diagrams according to some embodiments. Figure 6E is a tree diagram according to some embodiments. Figures 7A-7B are corresponding method flowcharts according to some embodiments. Figure 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Figure 9 is a block diagram of an integrated circuit (IC) manufacturing system and its related IC manufacturing process according to some embodiments. Implementation

[0003] The following disclosure reveals many different embodiments or examples to achieve different features of the subject matter. Examples of elements, materials, values, steps, operations, arrangements, or the like are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Other elements, values, operations, materials, arrangements, or the like are also contemplated. For example, in the following description, the formation of a first feature over or on a second feature includes embodiments in which the first and second features are in direct contact, and further includes embodiments in which an additional feature is formed between the first and second features such that the first and second features are in indirect contact. Furthermore, reference numerals and / or letters are repeated in various examples throughout this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, spatial relative terms such as "below," "lower," "lower," "upper," and "higher" are used herein to facilitate the description of the relationship of one component or feature relative to another component or feature shown in the figure. These spatial relative terms are intended to cover different orientations of the device in use or operation, other than those depicted in the figure. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein are interpreted accordingly. In some embodiments, the term "standard cell structure" refers to a standardized building block contained in various standard cell structure libraries. In some embodiments, various standard cell structures are selected from the library and used as elements in layout diagrams representing circuits.

[0005] In some embodiments, the cell region includes: a transistor element layer comprising a first feedthrough via (FTA); a first metallization layer above the transistor element layer and comprising a first front-side segment extending along a first direction (e.g., parallel to the X-axis), the first front-side segment comprising first and second front power grid (FPG) segments and one or more front wiring (FRTE) segments comprising a first front FRTE segment; and a first buried metallization layer below the transistor element layer and comprising a first back-side segment extending along the first direction, the first back-side segment comprising first and second back power grid (BPG) segments and one or more back wiring (BRTE) segments comprising a first BRTE segment. The first FTA couples the first FRTE segment to the first BRTE segment. The first BPG segment has a first recess partially occupied by at least a first portion of the first BRTE segment relative to the first direction and a second direction perpendicular to the first direction. In some embodiments, the cell region is referred to as a functional circuit cell region or a functional circuit region (FNCR). In some embodiments, the FTA is contained within a feedthrough via cell region (FTCR), such that the FTCR is described as being embedded in the FNCR.

[0006] According to another approach, the counterpart of FNCR 204 does not include routing segments in any of the metallization layers on the back side. Instead, the FNCR counterpart of this other approach uses only the back metallization layer for the power grid. In terms of signal routing, the FNCR counterpart of this other approach suffers from congestion in the front metallization layer. In contrast, according to some embodiments, embedding the FTCR within the FNCR facilitates the use of the back metallization layer for both signal routing and the power grid, which reduces front-side signal routing congestion compared to the other approach.

[0007] Figure 1 is a block diagram of an apparatus 100 according to some embodiments.

[0008] Device 100 is an example of an integrated circuit (IC). In some embodiments, device 100 is referred to as a semiconductor device. Device 100 includes a macro region 102. In some embodiments, macro region 102 comprises one or more functional regions, such as circuit regions or similar regions. In some embodiments, macro region 102 includes one or more memories, power grids, cells or multiple cells, inverters, latches, buffers, drivers, analog devices such as digital-to-analog converters (DACs) or analog-to-digital converters (ADCs) or similar devices, clock trees, phase-locked loops (PLLs), interfaces, and / or any other type of circuit arrangement. Examples of memories include static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM, magnetoresistive RAM (MRAM), read-only memory (ROM), or similar memories.

[0009] Macro region 102 can be represented digitally in a standard cell library. In some embodiments, macro region 102 can be understood herein as an analogy to the architectural hierarchy of modular programming, where subroutines / programs are called by a main program (or other subroutines) to perform a given computational function. In this document, device 100 uses macro region 102 to perform one or more given functions. Therefore, in this document and in terms of architectural hierarchy, device 100 is analogous to a main program, and macro region 102 is analogous to a subroutine / program. In some embodiments, macro region 102 is a soft macro. In some embodiments, macro region 102 is a hard macro. In some embodiments, macro region 102 is a soft macro described digitally in register-transfer level (RTL) code. In some embodiments, composition, placement, and routing have not yet been performed on macro region 102, therefore the soft macro can be composed, placed, and routed for various process technology nodes. In some embodiments, the macro 102 is a hard macro digitally described in a binary file format (e.g., Graphic Database System II (GDSII) streaming format), wherein the binary file format represents the planar geometry, text labels, other information, etc., of one or more layouts of the macro 102 in a hierarchical manner. In some embodiments, the binary file format is referred to as a non-text file format. In some embodiments, composition, placement, and routing have been performed on the macro 102, therefore the hard macro is specific to a particular process technology node.

[0010] In Figure 1, the large region 102 includes a functional circuit region 104. The functional circuit region 104 includes at least one active device, such as a transistor or similar device. In some embodiments, the functional circuit region 104 includes one or more logic gates. In some embodiments, the functional circuit region 104 is or includes a buffer, driver, inverter, or similar device. Examples of logic gates / circuits include circuits configured to perform logic functions AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), or similar functions. Other examples of functional circuits include multiplexers (MUX), flip-flops, buffers, drivers (DRV), latches, delays, clocks, memory, or similar circuitry.

[0011] The functional circuit region 104 includes a feedthrough unit region 106 (see Figures 2A-2D, 3A-3E, 4A-4C). In some embodiments, the functional circuit region 104 is described as overlapping with the feedthrough unit region 106. In some embodiments, the feedthrough unit region 106 is described as being embedded in the functional circuit region 104.

[0012] The functional circuit region 104 and the feedthrough unit region 106 each include corresponding segments in one or more metallization layers. In some embodiments, in even-numbered metallization layers, the major and minor axes of the segments extend in first and second perpendicular directions (e.g., parallel to the X and Y axes), respectively; in these embodiments, in odd-numbered metallization layers, the major and minor axes of the segments extend in second and first directions (e.g., parallel to the Y and X axes), respectively. In these embodiments, the boundaries of the overlapping functional circuit region 104 and feedthrough unit region 106 are described in the first and second directions, such that the boundary of the feedthrough unit region 106 lies within the boundary of the functional circuit region 104 relative to the first and second directions.

[0013] Regarding Figure 1, in some embodiments, the feedthrough unit region 106 is a standalone unit in a standard cell library. In some embodiments, the feedthrough unit region 106 does not include active devices, such as transistors or similar devices. In some embodiments, the feedthrough unit region 106 does not include functional circuit components, such as buffers, drivers, inverters, or similar devices. In some embodiments, the feedthrough unit region 106 does not include logic gates.

[0014] In some embodiments, functional circuit region 104 corresponds to a transistor layer (see FIG. 5A) having circuit elements (e.g., transistors), which is formed in front-end process (FEOL) fabrication. In functional circuit region 104, various metal layers (see FIGS. 5A-5B) and corresponding interconnect layers are staggered and stacked above and / or below insulating layers in back-end process (BEOL) fabrication, above and / or below the active region layer. BEOL fabrication provides power networks and / or wiring for the circuitry of device 100, including giant region 102 and functional circuit region 104.

[0015] In some embodiments, the functional circuit region 104 includes one or more active devices, passive devices, or similar devices. Examples of active devices or active components include, but are not limited to, transistors, diodes, or similar devices. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, resistors, or similar elements.

[0016] In Figure 1, the feedthrough unit region 106 includes a feedthrough via (FTA) 108 (see Figure 5A). The FTA 108 is an arrangement containing feedthrough vias (FTVs) (see Figure 5A). The FTA 108 passes through the transistor layer (see transistor element layer 536 in Figure 5A) and electrically couples a section of the metallization layer on the front side of the transistor layer (e.g., the first metallization layer) and a section of the back side metallization layer on the back side of the transistor layer (e.g., the first back side metallization layer), with the back side of the transistor layer facing the front side of the transistor layer.

[0017] Figures 2A-2B are layout diagrams of the front 208A and back 210B corresponding to the functional circuit region 204(1) according to some embodiments.

[0018] Functional circuit region (FNCR) 204(1) is an example of a first functional unit region, such as functional unit region 104 of FIG1. ​​In some embodiments, FNCR 204(1) includes a first macro cell region, wherein the first macro cell region includes a first device. In some embodiments, the first macro cell region and the first device correspond to examples of macro region (macro cell region) 102 and device 100 of FIG1, respectively. FNCR 204(1) includes feedthrough unit region (FTCR) 206(1). FNCR 204(1) is an example of a first feedthrough unit region, such as FTCR 106 of FIG1. ​​In some embodiments, FTCR 206(1) is described as embedded in FNCR 204(1). To simplify the illustration in FIG2A-2B, FNCR 204(1) and some of its structures are truncated by line 234 relative to the X-axis.

[0019] Using the illustration of FNCR 204(1), the front 208A and back 210B layouts of Figures 2A-2B respectively represent a transistor-based device. The structures within the device are represented by patterns (also called shapes) in the layouts. For the sake of simplicity, components in the front 208A and back 210B layouts of Figures 2A-2B (as well as components in other layouts disclosed herein) will be referred to as structures rather than patterns. For example, an instance of component 214 in Figure 2A represents an instance of a wiring segment in the first metallization layer. In the following discussion, instances of component 214 are referred to as instances of wiring segments 214, not instances of wiring patterns. In Figures 2A-2B, section lines 5A-5A' extend parallel to the X-axis. In some embodiments, section lines 5A-5A' of Figures 2A-2B correspond to section 509A of Figure 5A.

[0020] In Figures 2A-2B and other layout diagrams disclosed herein, an orthogonal Cartesian coordinate system is assumed, where the first, second, and third directions are parallel to the X-axis, Y-axis, and Z-axis, respectively. The layout diagram is a top view. The shapes in the layout diagram are two-dimensional relative to the X-axis and Y-axis, while the represented devices are three-dimensional. Therefore, the shapes in these layout diagrams are described as having width / length relative to the X-axis and height relative to the Y-axis. For example, the bottom / back face of the first element represented in the layout diagram is stacked relative to the Z-axis on the top / front face of the second element device represented in the layout diagram, or the top / front face of the first element is stacked relative to the Z-axis below the bottom / back face of the second element. In some embodiments, the first to third directions correspond to directions other than the X-axis, Y-axis, and Z-axis.

[0021] Typically, the device is organized as a stack of layers relative to the Z-axis, with corresponding structures, i.e., the layers to which the corresponding structures belong. Each shape in the layout diagram more specifically represents an element in the corresponding layer of the device. Furthermore, the layout diagram typically represents the relative depth of a shape and its corresponding layer, i.e., its position along the Z-axis, by superimposing a second shape on top of a first shape such that the second shape at least partially overlaps the first shape. For simplicity, some structures in the device that have a first stacking order along the Z-axis are represented in the layout diagram using a second stacking order along the Z-axis, i.e., a different / changed stacking order; see, for example, Figure 2I.

[0022] Layout diagrams vary in the amount of detail they represent. In some cases, such as for simplification, selected layers in a layout diagram are combined / simplified to a single layer. Or, in some cases, such as for simplification, not all layers of the corresponding device are shown, i.e., selected layers in the layout diagram are omitted. Or, in some cases, such as for simplification, not all components of a given depicted layer of the corresponding device are shown, i.e., selected components of a given depicted layer in the layout diagram are omitted. Figure 2A and other layout diagrams disclosed herein are examples of layout diagrams where selected layers and / or selected components depicting a given layer are omitted.

[0023] The front layout 208A of Figure 2A includes a first metallization layer on the transistor element layer (see, for example, transistor element layer 536 in Figure 5A). The back layout 208B of Figure 2B includes a first buried metallization layer under the transistor element layer (see, for example, transistor element layer 536 in Figure 5A). Both the first metallization layer and the first buried metallization layer include conductive segments. In some embodiments, depending on the numbering convention of the corresponding process technology node in manufacturing the device, the first metallization layer is metal layer zero (MET0) or metal layer one (MET1), and correspondingly, the first interconnect layer located on the first metallization layer is interconnect layer zero (VIA0) or interconnect layer one (VIA1). In these embodiments, again depending on the numbering convention of the corresponding process technology node, the first buried metallization layer is buried metal layer zero (BMET0) or buried metal layer one (BMET1), and correspondingly, the first buried interconnect layer located under the first metallization layer is interconnect layer zero (VIA0) or interconnect layer one (VIA1).

[0024] In Figure 2A and other figures disclosed herein, the following nomenclature is used: The first metallization layer is assumed to be MET0; the first interconnect layer is assumed to be VIA0; the second metallization layer is assumed to be MET1; the second interconnect layer is assumed to be VIA1; and the third metallization layer is assumed to be MET2. The metallized segment in the MET0 layer is called the M0 segment. The via structure in the VIA0 layer is called the V0 structure. The metallized segment in the MET1 layer is called the M1 segment. The via structure in the VIA1 layer is called the V1 structure. The metallized segment in the MET2 layer is called the M2 segment.

[0025] In Figure 2B and other figures disclosed herein, the following nomenclature is used: The first embedded metallization layer is assumed to be BMET0; the first embedded interconnect layer is assumed to be BVIA0; the second embedded metallization layer is assumed to be BMET1; the second embedded interconnect layer is assumed to be BVIA1; and the third embedded metallization layer is assumed to be BMET2. The metallized segment in the BMET0 layer is called the embedded M0 segment. The via structure in the BVIA0 layer is called the BV0 structure. The metallized segment in the BMET1 layer is called the BM1 segment. The via structure in the BVIA1 layer is called the BV1 structure. The metallized segment in the BMET2 layer is called the BM2 segment.

[0026] In Figures 2A-2B and some other figures disclosed herein, the layout diagrams assume that the corresponding process technology node will use a dual-stacking lithography process. Therefore, in Figures 2A-2B and some other figures disclosed herein, alternating segments in a given metallization layer (e.g., metallization layer METO and embedded metallization layer BMETO) are displayed with different border line styles, different fill patterns, or similar arrangements relative to the Y-axis. In some embodiments, other lithography processes besides dual-stacking lithography are used for the corresponding process technology node.

[0027] Returning to Figure 2A, the M0 segment extends parallel to the X-axis. The M0 segment includes: M0 power grid (PG) segments 212(1) and 212(2); and instances of M0 wiring (M0_rte) segments 214(1)-214(3); and M0_rte segments 216(1)-216(3).

[0028] Relative to the Y-axis: the top boundaries of FNCR 204(1) and FTCR 206(1) are substantially aligned with the center line of M0_PG segment 212(1); the bottom boundaries of FNCR 204(1) and FTCR 206(1) are substantially aligned with the center line of M0_PG segment 212(2); corresponding instances of M0_rte segments 214(1), 214(2) and 214(3) are collinear; M0_rte segments 216(1), 216(2) and 216(3) are collinear;

[0029] Relative to the X-axis: Instances of M0_rte segment 214(2) lie between corresponding instances of M0_rte segments 214(1) and 214(3); M0_rte segment 216(2) lies between M0_rte segments 216(1) and 216(3); instances of M0_rte segment 214(2) and corresponding instances of M0_rte segment 214(1) are separated by a gap at the left boundary of the corresponding FTCR 206(1); instances of M0_rte segment 216(2) and M0_rte segment 216(1) are separated by a gap at the left boundary of the corresponding FTCR 206(1); instances of M0_rte segment 214(2) and corresponding instances of M0_rte segment 214(3) are separated by a gap at the left boundary of the corresponding FTCR 206(1). 206(1) is separated by a gap at the right boundary; M0_rte segment 216(2) and M0_rte segment 216(3) are separated by a gap at the right boundary of the corresponding FTCR 206(1); instances of M0_rte segment 216(1) and M0_rte segment 214(1) are located to the left of FTCR 206(1) 232(1); instances of M0_rte segment 216(3) and M0_rte segment 214(2) are located to the right of FTCR 206(1) 232(1);

[0030] Relative to the Y-axis: M0_PG segments 212(1) and 212(2) each have a width (size) W1; each instance of M0_rte segments 216(1)-216(3) and M0_rte segments 214(1)-214(3) each has a width W2. Width W2 is less than width W1, such that W2 < W1. Widths W1 and W2 are determined according to the scale of the relevant semiconductor process technology node and the corresponding design rules.

[0031] Regarding Figure 2A, the gap dimensions determined according to the scale of the relevant semiconductor process technology node and the corresponding design rules include the following: relative to the Y-axis, the gap width between M0_PG segments 212(1) and 212(2) and the adjacent M0_rte segment; relative to the Y-axis, the gap width between adjacent M0_rte segments; and relative to the X-axis, the gap width separating adjacent M0_rte segments.

[0032] In Figure 2B, the BM0 segment extends parallel to the X-axis. The BM0 segment includes: BM0 power grid (PG) (BM0_PG) segments 218(1) and 218(2); and BM0 wiring (BM0_rte) segment 220(1).

[0033] Relative to the Y-axis: the top boundaries of FNCR 204(1) and FTCR 206(1) are substantially aligned with the center line of BM0_PG segment 218(1), respectively; the bottom boundaries of FNCR 204(1) and FTCR 206(1) are substantially aligned with the center line of BM0_PG segment 218(2), respectively.

[0034] A groove 221(1) is formed in segment 218(2) of BM0_PG. The groove 221(1) has a bottom surface 224(1), a left side 226(1) and a right side 227(1). The groove 221(2) has a bottom surface 224(2), a left side 226(2) and a right side 227(2).

[0035] Relative to the Y-axis: the top boundary of FTCR 206(1) is substantially aligned with the bottom surface 224(1) of groove 222(1); the bottom boundary of FTCR 206(1) is substantially aligned with the bottom surface 224(2) of groove 222(2); BM0_PG segments 218(1) and 218(2) each have a width (dimension) W3; BM0_rte segment 220(1) has a width W4.

[0036] Relative to the X-axis: the left boundary of FTCR 206(1) is substantially aligned with the left side 226(1) of groove 222(1) and the left side 226(2) of groove 222(2); the right boundary of FTCR 206(1) is substantially aligned with the right side 227(1) of groove 222(1) and the right side 227(2) of groove 222(2).

[0037] Relative to the X-axis: Segment 228(1) of segment 218(1) and segment 228(3) of segment 218(2) of BM0_PG are respectively located to the left of FTCR 206(1), with a width (size) W3; Segment 228(2) of segment 218(1) and segment 228(4) of segment 218(2) of BM0_PG are respectively located to the right of FTCR 206(1), with a width W3; Segment 230(1) of BM0_PG 218(1) is located between segments 228(1) and 228(2), with a width of approximately (½*W3); Segment 230(2) of BM0_PG 218(2) is located between segments 228(3) and 228(4), with a width of approximately (½*W3); BM0_PG The segment 228(1) of 218(1) and the segment 228(3) of BM0_PG 218(2) are separated by a gap with a width of W5; the segment 228(2) of BM0_PG 218(1) and the segment 228(4) of BM0_PG 218(2) are separated by a gap with a width of W5; the segment 230(1) of BM0_PG 218(1) and the segment 220(2) of BM0_rte are separated by a gap with a width of approximately W6; the segment 230(2) of BM0_PG 218(2) and the segment 220(2) of BM0_rte are separated by a gap with a width of approximately W6.

[0038] In some embodiments, segments 228(1)-228(2) of segment 218(1) and segments 228(3)-228(4) of segment 218(2) of segment BM0_PG are referred to as half-width segments. In some embodiments, segments 230(1) of segment 218(1) and segments 230(2) of segment 218(2) of segment BM0_PG are referred to as full-width segments.

[0039] In some embodiments, the width W6 is approximately equal to or less than the width W4, such that W6 ≈ ≤ W4. The width W3 is also determined based on the scale of the relevant semiconductor process technology node and the corresponding design rules.

[0040] Figure 2B assumes that the width W4 is equal to or greater than the minimum width of the BM0_rte segment, denoted as Wy_BM0_rte_min, which is relative to the Y-axis. W4 and Wy_BM0_rte_min are each determined according to the scale of the relevant semiconductor process technology node and the corresponding design rules. Width W4 is less than width W3, such that W4 < W3. Furthermore, width W1 is less than width W4, such that W1 < W4.

[0041] Figure 2B also assumes that the width W4 is approximately equal to (½ * W3), such that W4 ≈ (½ * W3). In some embodiments, the value of the width W4 differs substantially from (½ * W3), although W4 < W3. Figure 2B assumes that the width W5 is equal to or greater than the minimum height of the gap between adjacent BMO segments, denoted as H_BM0_gap, which is relative to the Y-axis, where W5 and H_BM0_gap are each determined according to the scale of the relevant semiconductor process technology node and the corresponding design rules. In Figure 2B, the width W5 is less than the width W4, such that W5 < W4.

[0042] Relative to the X-axis, the BM0_rte segment 220(1) has a length (size) L1. Figure 2B assumes that the length L1 is equal to or greater than the minimum length of the BM0_rte segment, called Lx_BM0_rte_min, which is relative to the X-axis such that Lx_BM0_rte_min ≤ L1, where L_BM0_rte_min is determined according to the scale of the relevant semiconductor process technology node and the corresponding design rules.

[0043] In Figure 2B, relative to the X-axis: the left boundary of BM0_rte segment 220(1) and FTCR 206(1) is separated by a gap of size W7, that is, the segment 228(1) of BM0_rte segment 220(1) and the segment 228(3) of BM0_PG segment 218(1) are each separated by a gap of approximately size W7; and the right boundary of BM0_rte segment 220(1) and FTCR 206(1) is separated by a gap of size W7, that is, the segment 228(2) of BM0_rte segment 220(1) and the segment 228(4) of BM0_PG segment 218(2) are each separated by a gap of approximately size W7.

[0044] Figure 2B assumes that the length W7 is equal to or greater than the minimum length of the gap between BM0 segments, called Wx_BM0_gap_min, which is relative to the X-axis such that Wx_BM0_gap_min ≤ W7. Wx_BM0_gap_min and W7 are determined according to the scale of the relevant semiconductor process technology node and the corresponding design rules.

[0045] Relative to the X-axis, Figure 2B assumes that segment 220(1) of BM0_rte is substantially centered between segments 228(1) and 228(2) of BM0_PG segment 218(1), and between segments 228(3) and 228(4) of BM0_PG segment 218(2). That is, relative to the X-axis, Figure 2B assumes that segment 220(1) of BM0_rte is substantially centered between the left and right boundaries of FTCR 206(1).

[0046] Relative to the X-axis, FTCR 206(1) has a width called W_FTCR_206(1). In some embodiments, when the width W_FTCR_206(1) is substantially greater than Lx_BM0_rte_min plus twice Wx_BM0_gap_min, such that Lx_BM0_rte_min + 2*Wx_BM0_gap_min < W_FTCR_206(1), BM0_rte segment 220(1) is not necessarily substantially located at the center between segment 228(1) of BM0_PG segment 218(1) and segment 228(2) of BM0_PG segment 218(1), and at the center between segment 228(3) of BM0_PG segment 218(2) and segment 228(4) of BM0_PG segment 218(2). However, in these embodiments, relative to the X-axis: the segments 220(1) of M0_rte and 228(1) of BMO_PG and 218(2) of BMO_PG are each separated by a first gap having a size at least equal to or greater than Wx_BM0_gap_min; and the segments 228(2) of BMO_rte and 218(1) of BMO_PG and 218(2) of BMO_PG are each separated by a second gap having a size at least equal to or greater than Wx_BM0_gap_min.

[0047] Relative to the Y-axis, Figure 2B assumes that BM0_rte segment 220(1) is substantially located between segment 230(1) of BM0_PG segment 218(1) and segment 230(2) of BM0_PG segment 218(2).

[0048] In other words, relative to the Y-axis, Figure 2B assumes that BM0_rte segment 220(1) is actually located at the center between the upper and lower boundaries of FTCR 206(1).

[0049] Relative to the Y-axis, FTCR 206(1) has a height called H_FTCR_206(1). In some embodiments, when the height H_FTCR_206(1) is substantially greater than Wy_BM0_rte_min plus twice H_BM0_min, such that Wy_BM0_rte_min + 2* H_BM0_gap < H_FTCR_206(1), BM0_rte segment 220(1) is not necessarily substantially located at the center between segment 230(1) of BM0_PG segment 218(1) and segment 230(2) of BM0_PG segment 218(2). However, in these embodiments, relative to the X-axis: the segments 230(1) of BM0_rte segment 220(1) and 230(2) of BM0_PG segment 218(1) are each separated by a gap having a size at least equal to or greater than H_BM0_min.

[0050] According to another method, the corresponding portion of FNCR 204(1) does not include wiring segments in any metallization layer on the back side, i.e., there are no wiring segments in metallization layer BMETO or any metallization layer below it. Conversely, the portion of FNCR 204(1) corresponding to the other method uses only the back metallization layer as the power grid. In terms of signal routing, the portion of FNCR 204(1) corresponding to the other method suffers from congestion in the front metallization layer. In contrast, according to some embodiments, embedding feedthrough unit regions (e.g., FTCR 206(1)) in the functional circuit region (e.g., FNCR 204(1)) facilitates the use of the back metallization layer for both signal routing and power grid, which reduces front signal routing congestion compared to the other method.

[0051] Recall that section line 5A-5A' in Figures 2A-2B corresponds to the section in Figure 5A, the discussion will turn to Figure 5A and then back to Figures 2A-2B.

[0052] Figure 5A is a cross-sectional view 509A of an apparatus according to some embodiments.

[0053] More specifically, section 509A is a section of the second FTCR in the second FNCR, wherein the second FNCR includes a second macrocell region, and the second macrocell region includes a second device. In some embodiments, the second FTCR is an example of FTCR 206(1) in FIG. 2A-2B, the second FNCR is an example of FNCR 204(1) in FIG. 2A-2B, and the second macrocell region and the second device are corresponding examples of macrocell region 102 and device 100 in FIG. 1, respectively. That is, in some embodiments, section 509A corresponds to section lines 5A-5A' in FIG. 2A-2B.

[0054] In Figure 5A, the front and back sides of section 509A are defined relative to reference line 535. Transistor element layer 536 extends from the front side across reference line 535 to the back side of section 509.

[0055] Section 509A includes: in the BMET0 layer, BM0_rte 520(1) is an example of BM0_rte segment 220(1) in FIG2B; in the transistor element layer 536, feedthrough arrangement (FTA) 508(1) is on BM0_rte segment 520(1); and in the MET0 layer, M0_rte segment 516(2) is on FTA 508(1) and is an example of M0_rte segment 216(2) in FIG2B.

[0056] FTA 508(1) includes: a feedthrough via (FTV) 546(1) on BMO_rte segment 520(1); a metal-to-source / drain (MD) contact 544(1) on FTV 546(1); and a via-to-MD (VD) contact on MD contact 544(1) and below BMO_rte segment 516(2). MD contact 544(1), VDR 542(1) and BMO_rte segment 516(2) are on the front side of section 509. FTV 546(1) and BMO_rte segment 520(1) are on the back side of section 509.

[0057] An active region (AR) layer 548 is contained within a transistor element layer 536 below a reference line 535. An active region (not shown) is formed in the AR layer 548. An FTV 546(1) extends through the AR layer 548 and downward beyond the AR layer 548.

[0058] Now let's return to Figures 2A-2B for discussion.

[0059] For the sake of simplicity, the structure in the transistor element layer is omitted in Figures 2A-2B (see, for example, transistor element layer 536 in Figure 5A). However, Figures 2A-2B assume that an FTA (for example, FTA 508(1) in Figure 5A) is coupled between M0_rte segment 216(2) in Figure 2A and BM0_rte segment 220(1) in Figure 2B.

[0060] Figure 2C is a rear 210C layout diagram of FNCR 204(2) according to some embodiments.

[0061] The layout of the reverse side 210C in Figure 2C is similar to the layout of the reverse side 210B in Figure 2B. For the sake of simplicity, the discussion will focus on the differences between the layout of the reverse side 210C and the layout of the reverse side 210B, rather than their similarities.

[0062] The back 210C layout of Figure 2C includes: FNCR 204(2); FTCR 206(2); BM0_PG segment and BM0_rte segment embedded in the metallization layer BET0; embedded via (BV0) structure embedded in the interconnect layer BVIA0; BM1_PG segment and BM1_rte segment embedded in the metallization layer BMET1; and track lines extending parallel to the Y-axis.

[0063] The BM0_PG segment is configured with a groove. A portion of the BM0_rte segment is located within the groove of the BM0_PG segment. In Figure 2C, the BM1_PG segment, the BM1_rte segment, and the BV0 structure are aligned with their corresponding track lines.

[0064] To ensure compliance with design guidelines for relevant semiconductor process technology nodes, the positions of the two selected BV0 structures are shifted relative to the Y-axis. For example, these two selected BV0 structures are shifted to improve the overlap between the BV0 structure and the corresponding portion of the BMO segment.

[0065] Figure 2D is a rear 210D layout diagram of FNCR 204(3) according to some embodiments.

[0066] The rear 210D layout in Figure 2D is similar to the rear 210C layout in Figure 2C. For simplicity, the discussion will focus on the differences between the rear 210D and rear 210C layouts, rather than their similarities. For example, the rear 210D layout does not include the BM1 segment and does not have track lines.

[0067] Relative to the Y-axis: the top boundary of FTCR 206(3) is substantially aligned with the corresponding center line c_line of the upper M0_PG segment; while the bottom boundary of FTCR 206(3) is substantially aligned with the corresponding center line c_line of the lower M0_PG segment.

[0068] In Figure 2D, to ensure compliance with the design rules of the relevant semiconductor process technology node, the positions of the four selected BVO structures are shifted relative to the Y-axis. For example, the first, second, and third of the four selected BVO structures are shifted parallel to the Y-axis to improve the overlap between the BVO structure and the corresponding portion of the BMO_PG segment, and to ensure that the first, second, and third shifted BVO structures are located at the minimum offset DR_gap1 from the edge of the corresponding portion of the BMO_PG segment. For example, the fourth of the four selected BVO structures is shifted parallel to the X-axis to improve the overlap between the BVO structure and the corresponding portion of the BMO_PG segment, and to ensure that the fourth shifted BVO structure is located at the minimum offset DR_gap2 from the edge of the corresponding portion of the BMO_PG segment. In some embodiments, one or more BVO structures are shifted relative to both the X-axis and the Y-axis.

[0069] Figures 2E-2H are corresponding rear layout diagrams according to some embodiments.

[0070] The rear layout diagrams of Figures 2E-2H are similar to excerpts of the rear layout diagram 210D of Figure 2D. For the sake of brevity, the discussion will focus on the differences between the rear layout diagrams of Figures 2E-2E and the rear layout diagram 210D of Figure 2D, rather than their similarities.

[0071] In Figure 2E-2H, relative to the Y-axis, the narrower portion of segment BM0 has a width of W11, and the wider portion has a width of W12, where W11 < W12. Figure 2E-2H shows different starting positions of the BV0 structure relative to segment BM0. It is assumed that the layout diagram in Figure 2E-2H will be checked for compliance with design rules, including those relating to DR_gap1 and DR_gap2E in Figure 2D, and adjusted accordingly if necessary.

[0072] Figure 2I is a layout diagram of macro cell region 202(1) according to some embodiments.

[0073] Macro cell region 202(1) includes associated means. In some embodiments, macro cell region 202(1) and associated means are corresponding examples of macro region (macro cell region) 102 and means 100 in FIG1, respectively. In some embodiments, macro cell region 202(1) is an example of macro cell region in FIG6A.

[0074] Regarding Figure 2I, for the sake of simplification, some structures in the relevant device that have a first stacking order along the Z-axis are represented in the layout diagram Figure 2I by a second stacking order along the Z-axis, i.e., a different / changed stacking order.

[0075] Figure 2I includes offset section lines 5B-5B', which extend partially parallel to the X-axis and partially parallel to the Y-axis. In some embodiments, section lines 5B-5B' of Figure 2I correspond to the section of Figure 5B.

[0076] Macro unit region 202(1) includes FNCR 204(4) and FNCR 204(5). FNCR 204(4) includes FTCR 204(4). FNCR 204(5) includes FTCR 204(5).

[0077] For simplicity, the structure in the transistor layer is omitted in Figure 2I (see, for example, transistor element layer 536 in Figure 5B). However, Figure 2I assumes that in FTCR 206(4) and FTCR 206(5), the first and second FTAs ​​(for example, FTAs ​​508(2) and 508(3) in Figure 5B) are coupled between the corresponding M0_rte segment and BMO_rte segment.

[0078] Offset profile lines 5B-5B' represent a signal path consisting of the following segments: the first segment F21 is located on the front side and above the transistor layer, including the structure of FNCR 204(4) in the MET2, VIA1, MET1, VIA0, and MET0 layers; the second segment F22 is located in the transistor layer, including the first FTA of FNCR 204(4) in the transistor layer; the third segment F23 is located on the back side and below the transistor layer, including the structure of FNCR 204(4) in the BMET0, BVIA0, BMET1, BVIA1, and BMET2 layers; the fourth segment F24 is located on the back side and below the transistor layer, including a portion of the BM2_ret segment in the BMET2 layer between FNCR 204(4) and FNCR 204(5); the fifth segment F25 is located on the back side and below the transistor layer, including FNCR 204(4) and FNCR 204(5). 204(5) in the structure of BMET0, BVIA0, BMET1, BVIA1 and BMET2 layers; the sixth segment F26 is located on the front and above the transistor layer, including the second FTA of FNCR 204(5) in the transistor layer; the seventh segment F27 is located on the front and above the transistor layer, including the structure of FNCR 204(5) in the structure of MET2, VIA1, MET1, VIA0 and MET0 layers.

[0079] We will now continue the discussion according to the drawing numbers.

[0080] Figures 3A-3B are layout diagrams of the corresponding front 308A and back 310B of the functional circuit region 304(1) according to some embodiments.

[0081] The front layout 308A and the back layout 310B correspond to the front layout 208A and the back layout 210B of Figures 2A-2B, respectively. For the sake of brevity, the discussion will focus on the differences between the front layout 308A and the back layout 310B and the front layout 208A and the back layout 210B of Figures 2A-2B, rather than their similarities.

[0082] Relative to the Y-axis: the top boundaries of FNCR 304(1) and FTCR 306(1) are substantially aligned with the center lines of M0_PG segment 312(1) and groove BM0_PG segment 318(1), respectively; the bottom boundary of FTCR 306(1) is substantially aligned with the center lines of M0_PG segment 312(2) and groove BM0_PG segment 318(2); the bottom boundary of FNCR 304(1) is substantially aligned with the center lines of M0_PG segment 312(2) and grooveless BM0_PG segment 318(3).

[0083] In Figure 3B, to ensure compliance with the design rules of the relevant semiconductor process technology node, the position of a selected BV0 structure relative to the Y-axis is shifted. For example, the selected BV0 structure is shifted to improve the overlap between the BV0 structure and the corresponding part of BMO segment 318(1).

[0084] In Figure 3B, FNCR 304(1) is an example of a BUFFD4 cell region. In some embodiments, BUFFDx is an alphanumeric literal string used as an adjective to indicate that the corresponding cell region is a buffer cell region, where the drive strength of the cell region is DX, and X is a multiple of the unit drive strength D. In FNCR 304(1), x=4, so the drive strength is D4.

[0085] Figure 3C is a rear 310C layout diagram of FNCR 304(2) according to some embodiments.

[0086] The layout of the back side 310C is similar to that of the back side 310B in Figure 3B. For the sake of brevity, the discussion will focus on the differences between the layout of the back side 310C and the layout of the back side 310B in Figure 3B, rather than their similarities. FNCR 304(2) is an extended version of FNCR 304(1) in Figure 3B.

[0087] In Figure 3C, to ensure compliance with the design rules of the relevant semiconductor process technology node, the position of a selected BV0 structure relative to the Y-axis is shifted. For example, the selected BV0 structure is shifted to improve the overlap between the BV0 structure and the corresponding portion of BMO segment 318(2). In Figure 3C, FNCR 304(2) is an example of a potential converter cell region.

[0088] Figures 3D-3E are layout diagrams of the front 308D and back 310E of FNCR 304(3) according to some embodiments.

[0089] The rear layout diagram 310E is similar to the rear layout diagram 310B of Figure 3B. For the sake of brevity, the discussion will focus on the differences between the rear layout diagram 310E and the rear layout diagram 310B of Figure 2B, rather than their similarities. Layout diagram 310E is an extended version of layout diagram 310B in Figure 3B.

[0090] In Figure 3E, to ensure compliance with the design rules of the relevant semiconductor process technology nodes, the positions of some selected BV0 structures relative to the Y-axis are shifted. For example, the selected BV0 structures are shifted to improve the overlap between the BV0 structures and the corresponding portions of the BMO segments.

[0091] In Figures 3D-3E, FNCR 304(3) is an example of a CK_BUFFD32 cell region. In some embodiments, CK_BUFFDx is an alphanumeric literal string used as an adjective to indicate that the corresponding cell region is a clock buffer cell region. The drive strength of the cell region is DX, where X is a multiple of the unit drive strength D. In FNCR 304(3), x=32, therefore the drive strength is D32.

[0092] Figures 4A-4B are layout diagrams of the front 408A and back 410B corresponding to the functional circuit region 404(1) according to some embodiments.

[0093] The front layout 408A and the back layout 410B are similar to the front layout 208A in Figure 2A and the back layout 310B in Figure 3B, respectively. For the sake of brevity, the discussion will focus on the differences between the front layout 408A and the back layout 410B and the front layout 208A in Figure 2A and the back layout 310B in Figure 3B, rather than their similarities.

[0094] In Figure 4A, segment M0 extends parallel to the X-axis and includes segments M0_PG 412(1)-412(2). Relative to the Y-axis: the top boundaries of FNCR 404(1) and FTCR 406(1) are substantially aligned with the centerline of segment M0_PG 412(1); the bottom boundaries of FNCR 404(1) and FTCR 406(1) are substantially aligned with the centerline of segment M0_PG 412(2); and segments M0_PG 412(3)-414(5) are collinear.

[0095] Relative to the X-axis: M0_PG segment 412(4) is located between M0_PG segments 416(3) and 414(5); M0_PG segment 412(4) and M0_PG segment 412(3) are separated by a first gap corresponding to the left boundary of FTCR 406(1); and M0_PG segment 412(4) and M0_PG segment 412(5) are separated by a second gap corresponding to the right boundary of FTCR 406(1).

[0096] Relative to the Y-axis: each of the segments 412(1)-412(5) of M0_PG has a width of W41; each of the first and second gaps has a width of W42; and some adjacent segments of M0_PG 412(1)-412(5) are separated from each other by a third gap having a width of W43.

[0097] Each of the widths W41-W43 is determined according to the scale of the relevant semiconductor process technology node and the corresponding design rules. In some embodiments, one or both of the first and second gaps have a width different from W42.

[0098] In Figure 4B, segment BM0 extends parallel to the X-axis and includes segments BM0_PG 212(1)-212(2).

[0099] Relative to the Y-axis: the top boundaries of FNCR 404(1) and FTCR 406(1) are substantially aligned with the center line of BM0_PG segment 418(1); and the bottom boundaries of FNCR 404(1) and FTCR 406(1) are substantially aligned with the center line of BM0_PG segment 418(2); and BM0_PG segments 418(3)-414(4) and BM0_rte segment 420(1) are collinear.

[0100] Relative to the X-axis: BM0_rte segment 420(1) is located between BM0_PG segments 418(3) and 418(4); BM0_rte segment 420(1) and BM0_PG segment 418(3) are separated by a fourth gap corresponding to the left boundary of FTCR 406(1); and BM0_rte segment 420(1) and BM0_PG segment 418(5) are separated by a fifth gap corresponding to the right boundary of FTCR 406(1). In some embodiments, BM0_PG segments 418(3) and 418(4) together with BM0_rte segment 420(1) represent a first instance of segmented BM0 segments.

[0101] Relative to the Y-axis: BM0_rte segment 420(1) has a width of W44; each of BM0_PG segments 418(1)-418(4) has a width of W45; each of the fourth and fifth gaps has a width of W46; some adjacent segments of BM0_PG segments 418(1)-418(4) are separated from each other by a sixth gap with a width of W47; and each of BM0_rte segment 420(1) and BM0_PG segments 418(1)-418(2) is separated by a seventh gap with a width of W48.

[0102] Each of the widths W41-W48 is determined according to the scale of the relevant semiconductor process technology node and the corresponding design rules. In some embodiments, one or both of the fourth and fifth gaps have a width different from W42. In Figure 4B, the width W44 is less than the width W45, such that W44 < W45. In Figures 4A-4B, the width W41 is less than the width W44, such that W41 < W44. Each of the BMO_PG segments 418(1)-418(2) has no groove, i.e., no groove, while the corresponding BMO_PG segments 318(1)-318(2) in Figure 3B have grooves. Relative to the Y-axis, FNCR 404(1) has a height h_404(1), as follows: h_404(1) = W44 + 2*W48 + 2*(W45 / 2).

[0103] According to another approach, the counterpart of FNCR 404(1) does not include routing segments in any metallization layer on the back side, i.e., no routing segments are present in metallization layer BMETO or any metallization layer below it. Instead, the counterpart of FNCR 404(1) in this alternative approach uses only the back metallization layer for the power grid. In terms of signal routing, the counterpart of FNCR 404(1) in this alternative approach suffers from congestion in the front metallization layer. In contrast, according to some embodiments, embedding feedthrough unit regions (e.g., FTCR 406(1)) within functional circuit regions (e.g., FNCR 404(1)) facilitates signal routing and power grid utilization using the back metallization layer, which reduces front-side signal routing congestion compared to the alternative approach.

[0104] Figure 4C is a rear view 410C layout diagram of the functional circuit region 304(1) according to some embodiments.

[0105] The layout of the back side 410C is similar to that of the back side 410B in Figure 4B. For the sake of brevity, the discussion will focus on the differences between the layout of the back side 410C and the back side 410B in Figure 4B, rather than their similarities. The FNCR 404(2) in Figure 4C is an extended version of the FNCR 404(1) in Figure 4B.

[0106] In Figure 4C, FNCR 404(2) includes three M0_rte segments, corresponding to the first separation BM0 segment 460(1), the second separation BM0 segment 460(2), and the third separation BM0 segment 460(3). Relative to the Y-axis, FNCR 404(2) has a height h_404(2), which is four times the height of FNCR 404(1) in Figure 4C, such that h_404(2) = 4 * h_404(1).

[0107] Figure 5B is a cross-section 509B of an apparatus according to some embodiments.

[0108] More specifically, section 509B corresponds to the third and fourth FTCRs in the third and fourth FNCRs, where the third and fourth FNCRs constitute a third macrocell region, and the third macrocell region constitutes a third device. In some embodiments, the third and fourth FTCRs are examples of FTCR 206(4) and FTCR 206(5) of FIG. 2I, the third and fourth FNCRs are examples of FNCR 204(4) and FNCR 204(5) of FIG. 2I, the third macrocell region is an example of macrocell region 202(1) of FIG. 2I, and the third device is an example of device 100 of FIG. 1. That is, in some embodiments, section 509B corresponds to the offset section line 5B-5B' of FIG. 2I.

[0109] Section 509B of Figure 5B is similar to section 509A of Figure 5A. For the sake of brevity, the discussion will focus on the differences between section 509B of Figure 5B and section 509A of Figure 5A, rather than their similarities.

[0110] Compared to section 509A of Figure 5A, section 509B of Figure 5B additionally includes the corresponding structures in the BMET1, BVIA1, BMET2, MET1, VIA1, and MET2 layers. Section 509B includes FTAs ​​508(2) and 508(3), which correspond to the first and second FTAs ​​of Figure 2I. Section 509B represents the signal path consisting of segments F51-F57, corresponding to signal path segments F21-F27 of Figure 2I.

[0111] Figures 6A-6D are block diagrams of corresponding macro unit regions 602A-602D according to some embodiments.

[0112] In Figure 6A, macro cell region 602A includes FNCR 604(1) and FNCR 604(2). FNCR 604(1) has a front input and a back output. FNCR 604(2) has a back input and a front output. The back output of FNCR 604(1) is coupled to the back input of FNCR 604(2). In some embodiments, FNCR 604(1) and FNCR 604(2) represent corresponding buffers, drivers, or similar elements.

[0113] FNCR 604(1) includes FTCR 606(1). The signal path between the front input and the rear output of FNCR 604(1) includes FTCR 606(1). FNCR 604(2) includes FTCR 606(2). The signal path between the rear input and the front output of FNCR 604(2) includes FTCR 606(2).

[0114] In Figure 6B, macro cell region 602B includes FNCR 604(3) and FNCR 604(4). FNCR 604(3) has a back-side input and a back-side output. FNCR 604(4) has a back-side input and a back-side output. The back-side output of FNCR 604(3) is coupled to the back-side input of FNCR 604(4). In some embodiments, FNCR 604(1) and FNCR 604(2) represent corresponding buffers, drivers, or similar elements.

[0115] The FNCR 604(3) includes the FTCR 606(3) and the FTCR 606(4). The signal path between the rear input and the rear output of the FNCR 604(3) includes the FTCR 606(3) and the FTCR 606(4).

[0116] Regarding Figure 6C, macro cell region 606C is similar to macro cell region 606A in Figure 6A. For the sake of brevity, the discussion will focus on the differences between macro cell region 606C and macro cell region 606A in Figure 6A, rather than their similarities.

[0117] In FIG6C, macro cell region 602C includes FNCR 604(2) and FNCR 604(5) of FIG6A. FNCR 604(5) has a front input and a back output. The back output of FNCR 604(5) is coupled to the back input of FNCR 604(2). In some embodiments, FNCR 604(5) represents a buffer, driver or similar element.

[0118] The FNCR 604(5) includes FTCR 606(7), FTCR 606(8), and FTCR 606(9). The signal path between the front input and the rear output of the FNCR 604(5) includes one or more of FTCR 606(7), FTCR 606(8), or FTCR 606(9).

[0119] In FIG6D, macro cell region 602D includes FNCR 604(3), FNCR 604(7), and FNCR 604(8) of FIG6B. In some embodiments, macro cell region 602D replaces FNCR 604(3) with FNCR 604(4) of FIG6B. FNCR 604(7) has a front input and a back output. FNCR 604(8) has a back input and a front output.

[0120] The rear output of FNCR 604(7) is coupled to the rear input of FNCR 604(3). The rear output of FNCR 604(3) is coupled to the rear input of FNCR 604(8). In some embodiments, FNCR 604(7) and FNCR 604(8) represent corresponding buffers, drivers or similar elements.

[0121] The FNCR 604(7) includes the FTCR 606(11). The signal path between the front input and the rear output of the FNCR 604(7) includes the FTCR 606(11).

[0122] The FNCR 604(8) includes the FTCR 606(12). The signal path between the rear input and the front output of the FNCR 604(8) includes the FTCR 606(12).

[0123] Figure 6E is a tree diagram of a device 600E according to some embodiments.

[0124] In some embodiments, device 600 is an example of device 100 in FIG1. ​​The tree diagram in FIG6E is an example of an H-tree architecture for clock tree synthesis.

[0125] The device 600 includes: a macro cell region 602E(1) representing a clock port at the root of the tree; a macro cell region 602E(2) representing a trunk driver; a macro cell region 602E(3) representing a tap driver; and a macro cell region 602(4) representing a local subtree driver.

[0126] Macro cell region 602E(1) includes one or more instances of FNCR 650, which have inputs on the front and outputs on the back. An example of FNCR 650 is FNCR 604(1) or a similar element in FIG. 6A. Macro cell region 602E(2) includes one or more instances of FNCR 652, which have inputs on the back and outputs on the back. An example of FNCR 652 is FNCR 604(3) or a similar element in FIG. 6B. Macro cell region 602E(3) includes one or more instances of FNCR 654, which have inputs on the back and outputs on the front. An example of FNCR 654 is FNCR 604(2) or a similar element in FIG. 6A. Macro cell region 602E(4) includes: one or more instances of FNCR 656, which have inputs on the back and outputs on the front; an integrated clock gating (ICG) cell region; and one or more instances of convergence cell regions representing leaves.

[0127] Figure 7A is a flowchart of a method 700A for manufacturing a system or apparatus according to some embodiments.

[0128] According to some embodiments, method 700A can be implemented, for example, using EDA system 800 (Figure 8, discussed below) and IC manufacturing system 900 (Figure 9, discussed below). Examples of FNCRs with embedded FTCRs that can be manufactured according to method 700A include the FNCRs with embedded FTCRs or similar elements disclosed herein.

[0129] In Figure 7A, the method of flowchart 700A includes blocks 702-704. In block 702, a layout diagram is generated, which includes one or more layout diagrams corresponding to one or more FNCRs or similar elements embedded with FTCRs disclosed herein. According to some embodiments, block 702 may be implemented, for example, using EDA system 800 (Figure 8, discussed below). From block 702, the process proceeds to block 704.

[0130] At block 704, based on the layout diagram, at least (A) one or more lithography exposures, (B) the fabrication of one or more photomasks, or (C) the fabrication of one or more components in a layer of the apparatus, such as the fabrication apparatus. See the discussion of IC fabrication system 900 in Figure 9 below.

[0131] Figure 7B is a flowchart 700B of a method of manufacturing apparatus according to some embodiments.

[0132] Flowchart 700B is an example of block 704 (see Figure 7A discussed above). According to some embodiments, the method of flowchart 700B can be implemented, for example, using IC manufacturing system 900 (see Figure 9 discussed below). Examples of devices that can be manufactured according to the method of flowchart 700B include devices incorporating an FNCR or similar element with an embedded FTCR disclosed herein. Flowchart 700B includes blocks 710-722.

[0133] In block 710, a device is formed in a transistor layer (e.g., transistor element layer 536), including a first FTA (e.g., 508(1) or 508(2)). In some embodiments, block 710 includes forming a second FTA (e.g., 508(3)).

[0134] At block 710, the process proceeds to block 712.

[0135] In block 712, a first front segment is formed in the first metallization layer (e.g., METO), including a first (e.g., 212(1)) and a second (e.g., 212(2)) front power grid (FPG) segment and a front routing (FRTE) segment (e.g., 216(2), 516(2)). Within block 712, the process proceeds to block 714.

[0136] In block 714, the first FRTE segment (e.g., 216(2), 516(2)) is coupled to the FTA (e.g., 508(1)). From block 714, the process leaves block 712 and proceeds to block 716.

[0137] In block 716, a first backside segment is formed in the first embedded metallization layer (e.g., BMET0), including a first (e.g., 218(1)) and a second (e.g., 218(2)) backside power grid (BPG) segment and a first backside routing (BRTE) segment (e.g., 220(1), 520(1)). From block 718, the process proceeds to block 720.

[0138] In block 720, portions of the first BRTE segment (e.g., 220(1), 520(1)) are located in the first (e.g., 218(1)) and second (e.g., 222(1)) and second (e.g., 222(2)) grooves of the first (e.g., 218(1)) and second (e.g., 218(2)) BPG segments, respectively. From block 720, the process proceeds to block 722.

[0139] In block 722, the first BRTE segment (e.g., 220(1), 520(1)) is coupled to the FTA (e.g., 508(1)). From block 722, the process leaves block 716.

[0140] Figure 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0141] In some embodiments, EDA system 800 includes an Automatic Placement and Routing (APR) system. In some embodiments, EDA system 800 is a general-purpose computing device including a hardware processor 802 and a non-transitory computer-readable medium 804. Among other functions, storage medium 804 is encoded with (i.e., stored) computer program code (instructions 806), i.e., a set of executable instructions. Hardware processor 802 executes instructions 806 to represent (at least partially) implementing some or all of the EDA tools, such as one or more methods, or similar methods (hereinafter referred to as the processes and / or methods), according to one or more embodiments, to generate a layout diagram corresponding to the layout diagram disclosed herein.

[0142] In addition to other functions, storage media 804 stores layout diagram 811, such as the layout diagram disclosed herein or other similar layout diagrams.

[0143] Processor 802 is electrically coupled to computer-readable media 804 via bus 808. Processor 802 is also electrically coupled to input / output interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and computer-readable media 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code (instructions 806) encoded in computer-readable media 804 to enable EDA system 800 to perform some or all of the said processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0144] In one or more embodiments, the computer-readable media 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable media 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable media 804 includes a read-only optical disc (CD-ROM), a read-write optical disc (CD-R / W), and / or a digital video disc (DVD).

[0145] In one or more embodiments, storage medium 804 stores computer program code (instructions 806) configured to enable EDA system 800 (whose execution representation (at least part) of EDA tools) to perform some or all of the said processes and / or methods. In one or more embodiments, storage medium 804 also stores information facilitating the execution of some or all of the said processes and / or methods. In one or more embodiments, storage medium 804 stores a standard cell library 807 comprising standard cells corresponding to the layout diagrams disclosed herein. Storage medium 804 stores one or more layout diagrams 816, such as one or more layout diagrams corresponding to the layout diagrams disclosed herein or similar layout diagrams. It also includes an executed DCIM macro 817.

[0146] EDA system 800 includes an input / output interface 810. The input / output interface 810 is coupled to external circuitry. In one or more embodiments, the input / output interface 810 includes a keyboard, numeric keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and instructions to processor 802.

[0147] EDA system 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows EDA system 800 to communicate with a network 814 connected to one or more other computer systems. Network interface 812 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more EDA systems 800.

[0148] EDA system 800 is configured to receive information via input / output interface 810. The information received via input / output interface 810 includes one or more instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. This information is transmitted to processor 802 via bus 808. EDA system 800 is also configured to receive user interface (UI) related information via input / output interface 810. This information is stored as UI 842 on computer-readable media 804.

[0149] In some embodiments, some or all of the processes and / or methods are implemented as standalone software applications for processor execution. In some embodiments, some or all of the processes and / or methods are implemented as part of an additional software application. In some embodiments, some or all of the processes and / or methods are implemented as add-ons to the software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application part of an EDA tool. In some embodiments, some or all of the processes and / or methods are implemented as software applications used by EDA system 800. In some embodiments, the layout including standard cells is generated using VIRTUOSO® or other suitable layout generation tools provided by CADENCE DESIGN SYSTEMS.

[0150] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical discs, like DVDs; magnetic disks, like hard disks; semiconductor memory, such as ROM, RAM, memory cards, etc.

[0151] Figure 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and its associated IC manufacturing process according to some embodiments.

[0152] In some embodiments, based on the layout diagram generated from block 702 of FIG7, the IC manufacturing system 900 implements block 704 of FIG7, wherein the manufacturing system 900 manufactures at least one of (A) one or more semiconductor photomasks or (B) at least one element in a layer of an unfinished semiconductor integrated circuit. In some embodiments, the IC manufacturing system 900 implements the flowchart of FIG5 or a similar process.

[0153] In Figure 9, the IC manufacturing system 900 includes entities such as a design company 920, a photomask fab 930, and an IC manufacturer / wafer fab (“fab”) 950, which interact with each other in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC components 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design company 920, photomask fab 930, and IC wafer fab 950 are owned by a larger company. In some embodiments, two or more of the design company 920, photomask fab 930, and IC wafer fab 950 coexist in the same facility and use shared resources.

[0154] Design firm (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometries designed for IC component 960. These geometries correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of IC component 960. The layers combine to form various IC features. For example, a portion of IC design layout 922 includes various IC features such as active regions, gate terminals, sources and drains, interconnecting metal lines or vias, and openings for bonding pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Depending on the context, source / drain regions may refer individually or collectively as sources or drains. Design firm 920 implements appropriate design procedures to form IC design layout 922. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 922 is presented as one or more data files containing geometric information. For example, IC design layout 922 is represented in GDSII or DFII file format.

[0155] Photomask fabrication 930 includes data preparation 932 and photomask fabrication 934. Photomask fabrication 930 uses an IC design layout 922 to fabricate one or more photomasks 935 for fabricating layers of an IC component 960 according to the IC design layout 922. Photomask fabrication 930 performs photomask data preparation 932, in which the IC design layout 922 is converted into a representative data file ("RDF"). Photomask data preparation 932 provides the RDF to photomask fabrication 934. Photomask fabrication 934 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate, such as a photomask (mask) or a semiconductor wafer. The design layout is operated by photomask data preparation 932 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC wafer fab 950. In Figure 9, photomask data preparation 932, photomask fabrication 934, and photomask 935 are depicted as separate components. In some embodiments, photomask data preparation 932 and photomask fabrication 934 are collectively referred to as photomask data preparation.

[0156] In some embodiments, mask data preparation 932 includes optical approximation correction (OPC), which uses lithography techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution adjustment features, phase-shifting masks, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography (ILT) is further used, which treats OPC as a reverse imaging problem.

[0157] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that checks the IC design layout processed by OPC using a set of mask fabrication rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 934, which may undo some modifications performed by OPC to comply with the mask fabrication rules.

[0158] In some embodiments, photomask data preparation 932 includes lithography process inspection (LPC), which simulates the process that an IC wafer fab 950 will be used to manufacture IC component 960. The LPC simulates this process based on IC design layout 922 to manufacture simulated manufactured components, such as IC component 960. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), photomask error enhancement factor (“MEEF”), other appropriate factors, and combinations thereof. In some embodiments, after the LPC manufactures the simulated component, if the shape of the simulated component is not close enough to meet design rules, OPC and / or MRC are repeated to further optimize the IC design layout 922.

[0159] The description of the photomask data preparation 932 has been simplified for clarity. In some embodiments, photomask data preparation 932 includes additional features, such as logical operations (LOPs), to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0160] After photomask data preparation 932 and during photomask fabrication 934, a photomask 935 or a set of photomasks 935 is fabricated based on the modified IC design layout. In some embodiments, a pattern is formed on the photomask (or mask) based on the modified IC design layout using an electron beam (e-beam) or multiple electron beam mechanism. The photomask is formed using various techniques. In some embodiments, the photomask is formed using a binary technique. In some embodiments, the photomask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary photomask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the photomask. In another example, the photomask is formed using a phase-shifting technique. In a phase-shifting photomask (PSM), various features in the pattern formed on the photomask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shifting photomask is an attenuated PSM or an alternating PSM. The photomasks produced by 934 are used in various processes. For example, such photomasks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or for other suitable processes.

[0161] Integrated circuit wafer fab 950 is an integrated circuit manufacturing business that includes one or more manufacturing facilities for manufacturing various integrated circuit products. In some embodiments, integrated circuit wafer fab 950 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple integrated circuit products, while a second manufacturing facility may provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging integrated circuit products, and a third manufacturing facility may provide other services for the foundry business.

[0162] Integrated circuit wafer fab 950 uses a photomask (or photomask) 935 fabricated by photomask fab 930 to manufacture integrated circuit device 960 using manufacturing tool 952. Therefore, integrated circuit wafer fab 950 at least indirectly uses IC design layout 922 to manufacture integrated circuit device 960. In some embodiments, integrated circuit wafer fab 950 uses a photomask (or photomask) 935 to manufacture semiconductor wafer 953 to form integrated circuit device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate with material layers formed thereon. The semiconductor wafer also includes one or more various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0163] In some embodiments, the cell region includes a transistor element layer, a first metallization layer, and a first buried metallization layer. The transistor element layer includes a first feedthrough via (FTA). The first metallization layer is located above the transistor element layer and includes a first front-side segment extending along a first direction. The first front-side segment includes: first and second front power grid (FPG) segments; and one or more front routing (FRTE) segments, including the first FRTE segment. The first buried metallization layer is located below the transistor element layer and includes a first back-side segment extending along the first direction. The first back-side segment includes: first and second back power grid (BPG) segments; and one or more back routing (BRTE) segments, including the first BRTE segment. The first FTA couples the first FRTE segment to the first BRTE segment; and the first BPG segment has a first groove relative to the first direction and in a second direction perpendicular to the first direction, the first groove being partially occupied by at least a first portion of the first BRTE segment.

[0164] In some embodiments, wherein: the first BRTE segment is located between the first and second BPG segments relative to the second direction; and the second BPG segment has a second groove, the second groove being partially occupied by at least a second portion of the first BRTE segment.

[0165] In some embodiments, the top and bottom boundaries of the unit region extend along the first direction; the first FPG segment and the first BPG segment each overlap with the top boundary; and the second FPG segment and the second BPG segment each overlap with the bottom boundary.

[0166] In some embodiments, wherein: the top and bottom boundaries of the unit region extend along the first direction; the first back side segment further includes: a third BPG segment; the second BPG segment is located between the first BPG segment and the third BPG segment relative to the second direction; the first FPG segment and the first BPG segment respectively overlap with the top boundary; and the second FPG segment and the third BPG segment respectively overlap with the bottom boundary.

[0167] In some embodiments, the method further includes: a first embedded interconnect layer located below the transistor element layer and including a first back-side via; and wherein: the first back-side via overlaps with the first back-side segment accordingly; some of the first back-side vias near the first recess are adjacent embedded vias; each adjacent embedded via is separated from the first recess by a corresponding first embedded via offset distance relative to the first direction or by a corresponding second embedded via offset distance relative to the second direction; each first embedded via offset distance is equal to or greater than a first reference distance; and each second embedded via offset distance is equal to or greater than a second reference distance.

[0168] In some embodiments, wherein: relative to the centerline extending through the first BPG segment in the first direction, and further relative to the centerline extending correspondingly through the first back-side guide hole including the adjacent embedded via in the first direction, and relative to the second direction, the respective centerlines of the one or more selected adjacent embedded vias are displaced relative to the centerline of the first BPG segment.

[0169] In some embodiments, wherein: the corresponding centerline of the first back-side guide hole is substantially collinear with the corresponding centerline of the first BPG segment or the second BPG segment, except for the one or more selected adjacent embedded vias, and with respect to the second direction.

[0170] In some embodiments, wherein: the cell region represents a functional circuit including: an input pin configured to receive an input signal; and an output pin configured to provide an output signal, the input pin and the output pin being located on the front or back of the cell region; and a signal path coupling the input pin to the output pin including the first FTA.

[0171] In some embodiments, wherein: the transistor element layer further includes a second FTA; the transistor element layer further includes a second FTA; an input pin configured to receive an input signal; and an output pin configured to provide an output signal, the input pin and the output pin being located on the front or back side of the cell region; and the signal path coupling the input pin to the output pin includes the first FTA and the second FTA.

[0172] In some embodiments, wherein: relative to the second direction, excluding the portion of the first BPG segment having the first groove, the width of the first BRTE segment is smaller than the width of each of the first BPG segment and the second BPG segment.

[0173] In some embodiments, the width of the first BRTE segment is greater than the width of both the first FPG segment and the second FPG segment relative to the second direction.

[0174] In some embodiments, the cell region includes a transistor element layer, a first metallization layer, and a first buried metallization layer. The transistor element layer includes a first feedthrough via (FTA). The first metallization layer is located above the transistor element layer and includes a first front-side segment extending along a first direction. The first front-side segment includes: first and second front power grid (FPG) segments; and one or more front routing (FRTE) segments, including the first FRTE segment. The first buried metallization layer is located below the transistor element layer and includes a first back-side segment extending along the first direction. The first back-side segment includes: first, second, and third back power grid (BPG) segments; and one or more back routing (BRTE) segments, including the first BRTE segment. The first FTA couples the first FRTE segment to the first BRTE segment; the second and third BPG segments and the first FRTE segment are substantially collinear; and the first BRTE segment is located between the second and third BPG segments.

[0175] In some embodiments, wherein: the first front segment further includes a third FPG segment and a fourth FPG segment; the third and fourth FPG segments are located between the first FPG segment and the second FPG segment; the third FPG segment and the fourth FPG segment and the first RTE segment are substantially collinear; and the first RTE segment is located between the third FPG segment and the fourth FPG segment.

[0176] In some embodiments, wherein: the first back side segment further includes a fourth BPG segment; the second BPG segment and the third BPG segment are located between the first BPG segment and the fourth BPG segment relative to a second direction perpendicular to the first direction; the first FPG segment and the first BPG segment each correspondingly overlap with the top boundary of the cell region; and the second FPG segment and the fourth BPG segment each correspondingly overlap with the bottom boundary of the cell region.

[0177] In some embodiments, the width of the first BRTE segment is smaller than the width of each of the first, second, third, and fourth BPG segments relative to a second direction perpendicular to the first direction.

[0178] In some embodiments, wherein: relative to a second direction perpendicular to the first direction, the width of the first BRTE segment is greater than the width of each of the first and second FPG segments.

[0179] In some embodiments, the method (for manufacturing the cell region) includes: forming an element in a transistor element layer including a first feedthrough via (FTA); forming a first front segment extending in a first direction in a first metallization layer above the transistor element layer, including: first and second front power grid (FPG) segments; and one or more front wiring (FRTE) segments, including the first FRTE segment; and forming a first back segment extending in the first direction in a first buried metallization layer below the transistor element layer, including: first and second back power grid (BPG) segments; and one or more back wiring (BRTE) segments, including the first BRTE segment; the forming of the first front segment includes: coupling the first FRTE segment to the first FTA; and the forming of the first back segment includes: forming a first groove in the first BPG segment relative to the first direction and a second direction perpendicular to the first direction; positioning the first BRTE segment such that at least a first portion of the first BRTE segment partially occupies the first groove; and coupling the first BRTE segment to the first FTA.

[0180] In some embodiments, the formation of the first back section further includes: positioning the first BRTE section between the first and second BPG sections relative to the second direction; forming a second groove in the second BPG section relative to the first and second directions; and positioning the first BRTE section such that at least a second portion of the first BRTE section partially occupies the second groove.

[0181] In some embodiments, the method further includes: forming a first back-side via in a first embedded interconnect layer below the first embedded metallization layer; and wherein: forming the first back-side via includes: positioning the first back-side via to overlap with the first back-side segment accordingly; and some of the first back-side vias near the first recess are adjacent embedded vias; forming the first back-side via further includes: separating each of the adjacent embedded vias from the first recess by an offset distance relative to a corresponding first embedded via in the first direction or an offset distance relative to a corresponding second embedded via in the second direction; the offset distance of each first embedded via is equal to or greater than a first reference distance; and the offset distance of each second embedded via is equal to or greater than a second reference distance.

[0182] In some embodiments, the formation of the first back-side guide hole further includes: displacing the center lines of one or more selected adjacent embedded vias from the center line of the first BPG segment relative to a center line extending through the first back-side guide hole (including the adjacent embedded via) along the first direction, and relative to the second direction.

[0183] In some embodiments, wherein: relative to a centerline extending through the second BPG segment along the first direction, and in addition to the one or more selected adjacent embedded vias, and relative to the second direction, forming the first back-side via further includes substantially collinearly aligning the corresponding centerline of the first back-side via with the corresponding centerline of the first BPG segment or the second BPG segment.

[0184] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

[0185] 5A-5A: Section lines 5B-5B: Offset Profile Line 100, 600E: device 102: Mega Zone 104, 204, 304, 404: Functional circuit area 106, 206: Feedthrough via unit area 108: Feedthrough hole arrangement 202, 602, 602E: Macro cell regions 204, 304, 404, 604, 650, 652, 654, 656: FNCR 206, 306, 406, 606: FTCR 208A, 308A, 408A: Front 210B, 210C, 210D, 310B, 310C, 410B, 410C: Layout Diagram 212, 218: Power grid segment 214, 216, 220: Wiring segments 222: Groove 224: Bottom 226, 227, 232: Side Sections 228 and 230 234: Ellipsis 509, 509A, 509B: Sections 535: Reference Line 536: Transistor element layer 546:FTV 548: Active Layer 700A: Method 700A, 700B: Flowchart Blocks 702 and 704 800, 900: System 802: Processor 804: Computer-readable media 806: Instruction 807: Standard Cell Library 808: Busbar 810: Input / Output Interface 812: Network Interface 814: Internet 816: Layout Diagram 817: Executed DCIM Macro 920: Design Company 922: Integrated Circuit Design Layout 930: Photomask Factory 932: Photomask Data Preparation 934: Photomask Creation 935: Photomask 950: Integrated Circuit Wafer Fab 952: Manufacturing Tools 953: Semiconductor wafer 960: Integrated circuit device F21, F22, F23, F24, F25, F26, F27, F51-F57: Excerpts L1: Length W1, W2, W3, W4, W5, W6, W7, W11, W12, W2, W4, W41, W42, W43, W44, W45, W46, W47, W48: Width

Claims

1. A unit region, comprising: Transistor element layer, including a first feedthrough via (FTA); A first metallization layer, located above the transistor element layer, includes a first front segment extending along a first direction, the first front segment including: first and second front power grid (FPG) segments; and one or more front routing (FRTE) segments, including the first FRTE segment; and a first buried metallization layer, located below the transistor element layer, includes a first back segment extending along the first direction, the first back segment including: first and second back power grid (BPG) segments; and one or more back routing (BRTE) segments, including the first BRTE segment; the first FTA couples the first FRTE segment to the first BRTE segment; and the first BPG segment has a first groove relative to the first direction and in a second direction perpendicular to the first direction, the first groove being occupied by at least a first portion of the first BRTE segment.

2. The cell region as described in claim 1, wherein: Relative to the second direction, the first BRTE segment is located between the first and second BPG segments; The second BPG segment has a second groove, which is occupied by at least a second portion of the first BRTE segment.

3. The unit region as described in claim 1, further comprising: A first embedded interconnect layer is located below the transistor element layer and includes a first back-side via. And wherein: the first back guide hole overlaps with the first back segment accordingly; some of the first back guide holes near the first groove are adjacent embedded through holes; each of the adjacent embedded through holes is separated from the first groove by a corresponding first embedded through hole offset distance relative to the first direction or separated by a corresponding second embedded through hole offset distance relative to the second direction; each first embedded through hole offset distance is equal to or greater than a first reference distance; and each second embedded through hole offset distance is equal to or greater than a second reference distance.

4. The cell region as described in claim 1, wherein: The cell region represents a functional circuit, which includes: an input pin configured to receive an input signal; and an output pin configured to provide an output signal, wherein the input pin is located on one of the front or back sides of the cell region, and the output pin is located on the other of the front or back sides of the cell region; and the signal path coupling the input pin to the output pin includes the first FTA.

5. The cell region as described in claim 1, wherein: The transistor element layer further includes a second FTA; the cell region represents a functional circuit, which includes: an input pin configured to receive an input signal; and an output pin configured to provide an output signal, wherein the input pin and the output pin are both located on the front or back of the cell region; and the signal path coupling the input pin to the output pin includes the first FTA and the second FTA.

6. The cell region as described in claim 1, wherein: Relative to the second direction, excluding the portion of the first BPG segment with the first groove, the width of the first BRTE segment is smaller than the width of both the first BPG segment and the second BPG segment.

7. A unit region, comprising: Transistor element layer, including a first feedthrough via (FTA); A first metallization layer, located above the transistor element layer, includes a first front segment extending along a first direction, the first front segment including: first and second front power grid (FPG) segments; and one or more front routing (FRTE) segments, including the first FRTE segment; and a first buried metallization layer, located below the transistor element layer, includes a first back segment extending along the first direction, the first back segment including: first, second, and third back power grid (BPG) segments; and one or more back routing (BRTE) segments, including the first BRTE segment; the first FTA couples the first FRTE segment to the first BRTE segment; the second BPG segment and the third BPG segment and the first FRTE segment are substantially collinear; and the first BRTE segment is located between the second BPG segment and the third BPG segment.

8. The cell region as described in claim 7, wherein: The first front segment further includes a third FPG segment and a fourth FPG segment; the third FPG segment and the fourth FPG segment are located between the first FPG segment and the second FPG segment; the third FPG segment and the fourth FPG segment and the first FRTE segment are substantially collinear; and the first FRTE segment is located between the third FPG segment and the fourth FPG segment.

9. A method for manufacturing a cell region, comprising: A device is formed in a transistor element layer including a first feedthrough via (FTA); In a first metallization layer above the transistor element layer, a first front segment extending along a first direction is formed, the first front segment including: first and second front power grid (FPG) segments; and one or more front wiring (FRTE) segments, including the first FRTE segment; and in a first buried metallization layer below the transistor element layer, a first back segment extending along the first direction is formed, the first back segment including: first and second back power grid (BPG) segments; and one or more back wiring (BRTE) segments, including the first BRTE segment; forming the first front segment includes: coupling the first FRTE segment to the first FTA; and forming the first back segment includes: forming a first groove in the first BPG segment relative to the first direction and a second direction perpendicular to the first direction; positioning the first BRTE segment such that at least a first portion of the first BRTE segment partially occupies the first groove; and coupling the first BRTE segment to the first FTA.

10. The method of claim 9, wherein forming the first back face segment further comprises: The first BRTE segment is positioned between the first and second BPG segments relative to the second direction; A second groove is formed in the second BPG segment relative to the first direction and the second direction; and the first BRTE segment is positioned such that at least a second portion of the first BRTE segment occupies the second groove.

Images