Integrated circuit and method of fabricating integrated circuit

Abstract

This disclosure provides an integrated circuit and a method of manufacturing the integrated circuit. The integrated circuit includes a first cell region, a first transistor assembly containing a clock circuit, and a second cell region adjacent to the first cell region along a first boundary. The second cell region includes a feed via extending from the front side of a substrate to the back side and is configured to electrically couple components on the front and back sides together. The feed via includes a first conductor on the back side of the substrate, a second conductor on a first layer and above the first conductor, a first contact on a second layer and above the first conductor, and a first via on a third layer and above the first conductor.

Description

Prior Technology

[0001] The integrated circuit (IC) industry has produced a wide variety of digital devices to address problems in many different fields. Among these digital devices, some, such as memory macros, are configured to store data. As ICs become smaller and more complex, the resistance of the conductive lines within these digital devices changes, affecting their operating voltage and overall IC performance. Simple Explanation of the Diagram

[0002] The best understanding of all aspects of this disclosure can be obtained from the detailed description below when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is an integrated circuit diagram according to some embodiments. Figures 2A-2H are corresponding integrated circuit diagrams based on some embodiments. Figures 3A-3C are integrated circuit diagrams according to some embodiments. Figure 4 is an integrated circuit diagram according to some embodiments. Figure 5A is a top view of an integrated circuit according to some embodiments. Figures 5B-5C are cross-sectional views of integrated circuits according to some embodiments. Figure 6A is a top view of an integrated circuit according to some embodiments. Figures 6B-6C are cross-sectional views of integrated circuits according to some embodiments. Figure 7A is a top view of an integrated circuit according to some embodiments. Figure 7B is a top view of an integrated circuit according to some embodiments. Figure 8A is a top view of an integrated circuit according to some embodiments. Figure 8B is a top view of an integrated circuit portion according to some embodiments. Figure 9A is a top view of an integrated circuit according to some embodiments. Figure 9B is a top view of an integrated circuit portion according to some embodiments. Figure 10A is a top view of an integrated circuit according to some embodiments. Figure 10B is a top view of an integrated circuit portion according to some embodiments. Figure 11A is a top view of an integrated circuit portion according to some embodiments. Figure 11B is a top view of an integrated circuit portion according to some embodiments. Figure 11C is a top view of an integrated circuit portion according to some embodiments. Figure 12A is a top view of an integrated circuit portion according to some embodiments. Figure 12B is a top view of an integrated circuit portion according to some embodiments. Figure 12C is a top view of an integrated circuit portion according to some embodiments. Figure 13A is a top view of an integrated circuit portion according to some embodiments. Figure 13B is a top view of an integrated circuit portion according to some embodiments. Figure 13C is a top view of an integrated circuit portion according to some embodiments. Figures 14A-14B are functional flowcharts of methods for manufacturing IC devices according to some embodiments. Figure 15 is a flowchart of a method for forming or manufacturing an integrated circuit according to some embodiments. Figure 16 is a flowchart of a method for generating integrated circuit layout design according to some embodiments. Figure 17 is a schematic diagram of an IC layout design and IC circuit system manufacturing based on some embodiments. Figure 18 is a block diagram of an integrated circuit (IC) manufacturing system and an associated IC manufacturing process according to at least one embodiment of the present disclosure. Implementation

[0003] The following disclosure provides various embodiments or examples for implementing the provided subject matter features. Specific examples of elements, materials, values, steps, arrangements, or the like are described below to simplify this disclosure. Of course, these are merely examples and not limiting. Other elements, materials, values, steps, arrangements, or the like are conceivable. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0005] According to some embodiments, the integrated circuit includes a first cell region extending in a first direction and having a first height in a second direction different from the first direction.

[0006] In some embodiments, the first unit region includes a first transistor set of a clock circuit.

[0007] In some embodiments, the integrated circuit further includes a second cell region extending in a first direction and having a second height in a second direction. In some embodiments, the second height is different from the first height. In some embodiments, the second cell region is adjacent to the first cell region along a first boundary. In some embodiments, the first boundary extends in the first direction.

[0008] In some embodiments, the second unit region includes a feed via extending from the front side of the substrate to the back side. In some embodiments, the feed via is configured to electrically couple elements on the front and back sides together.

[0009] In some embodiments, the feed through-hole includes a first conductor located on the back side of the substrate and extending in a first direction.

[0010] In some embodiments, the feed perforation further includes a second conductor extending in a first direction, located on a first level, and above the first conductor.

[0011] In some embodiments, the feed-through via (FTV) further includes a first contact extending at least in a first or second direction, located on a second level different from the first level, and located above the first conductor.

[0012] In some embodiments, the feed through-hole further includes a first through-hole extending in a first direction, located on a third level different from the first and second levels, and located above the first conductor.

[0013] In some embodiments, the integrated circuit is configured to provide a cell-to-feed via electrical connection between the feed via and the first cell region. In some embodiments, by electrically connecting the feed via and the first cell region together, the feed via is configured to send / receive an output signal to / from the first cell region while being located outside the first cell region and not occupying an area within the first cell region.

[0014] In some embodiments, by electrically connecting the feed via and the first cell region together, the feed via is configured to send / receive an output signal to / from the first cell region while reducing the resistance and / or capacitance of the feed via, thereby reducing the resistance and / or capacitance of the clock tree by using backside wiring compared to other methods.

[0015] In some embodiments, by reducing the resistance and / or capacitance of the clock tree, the integrated circuit has less clock cell delay than other methods, thereby improving the performance of the clock cells and / or clock tree of the integrated circuit compared to other methods.

[0016] Figure 1 is a circuit diagram of an integrated circuit 100 according to some embodiments.

[0017] In some embodiments, the integrated circuit 100 is a clock tree circuit. In some embodiments, the clock tree circuit is configured to transmit the clock signal CLK to each leaf unit LC1, LC2, LC3 or LC4 in a balanced timing sequence.

[0018] The integrated circuit 100 includes a clock source 102, inverters I1, I2 and I3, buffers B1, B2, B3, B4 and B5, and leaf units LC1, LC2, LC3 and LC4.

[0019] Clock source 102 is coupled to the input of buffer B1. In some embodiments, clock source 102 is configured to generate clock signal CLK.

[0020] In some embodiments, one or more of buffers B1, B2, B3, B4, or B5 are configured to buffer or delay the clock signal CLK.

[0021] The output of buffer B1 is coupled to the input of buffer B2 and the input of inverter I1. Buffer B1 is configured to receive the clock signal CLK. The output of buffer B1 is configured to output the clock signal CLK.

[0022] Buffer B2 is coupled to the inputs of buffer B3 and buffer B4. Buffer B2 is configured to receive the clock signal CLK. The output of buffer B2 is configured to output the clock signal CLK to the inputs of buffer B3 and buffer B4.

[0023] Buffer B3 is coupled to the input of inverter I2. Buffer B3 is configured to receive the clock signal CLK. The output of buffer B3 is configured to output the clock signal CLK to the input of inverter I2.

[0024] Buffer B4 is coupled to the input of the corresponding leaf unit LC1. Buffer B4 is configured to receive the clock signal CLK. The output of buffer B4 is configured to output the clock signal CLK to the input of leaf unit LC1.

[0025] Leaf unit LC1 is configured to receive clock signal CLK. In some embodiments, one or more of leaf units LC1, LC2, LC3, or LC4 include one or more elements of memory, macro, or standard cell.

[0026] Inverter I2 is coupled to the input of the corresponding leaf unit LC2. Inverter I2 is configured to receive the clock signal CLK. The output of inverter I2 is configured to output the inverted clock signal CLK2 to the input of leaf unit LC2. In some embodiments, the inverted clock signal CLK2 is inverted compared to the clock signal CLK, and vice versa.

[0027] Leaf unit LC2 is configured to receive inverted clock signal CLK2.

[0028] Inverter I1 is coupled to the input of buffer B5 and the input of inverter I3. Inverter I1 is configured to generate an inverted clock signal CLK1. In some embodiments, the inverted clock signal CLK1 is the inverse of the clock signal CLK, and vice versa. Inverter I1 is configured to receive the clock signal CLK. The output of inverter I1 is configured to output the inverted clock signal CLK1 to the input of buffer B5 and the input of inverter I3.

[0029] Buffer B5 is coupled to the input of the corresponding leaf unit LC3. Buffer B5 is configured to receive the inverted clock signal CLK1. The output of buffer B5 is configured to output the inverted clock signal CLK1 to the input of leaf unit LC3.

[0030] Leaf unit LC3 is configured to receive the inverted clock signal CLK1.

[0031] Inverter I3 is coupled to the input of the corresponding leaf unit LC4. Inverter I3 is configured to receive the inverted clock signal CLK1. The output of inverter I3 is configured to output the clock signal CLK3 to the input of leaf unit LC4. In some embodiments, the clock signal CLK3 is inverted compared to the inverted clock signal CLK1, and vice versa. In some embodiments, the clock signal CLK3 is a delayed version of the clock signal CLK.

[0032] Leaf unit LC4 is configured to receive the inverted clock signal CLK3.

[0033] In some embodiments, one or more of leaf units LC1, LC2, LC3 or LC4 are single leaf units.

[0034] Other numbers of inverters I1, I2, or I3, buffers B1, B2, B3, B4, or B5, or leaf units LC1, LC2, LC3, or LC4 are within the scope of this disclosure. In some embodiments, other numbers of circuit branches of the integrated circuit 100 are within the scope of this disclosure.

[0035] Figures 2A-2H are corresponding diagrams of integrated circuits 200A-200H, based on some embodiments.

[0036] In some embodiments, Figures 2A-2H are corresponding plan views of integrated circuits 200A-200H according to some embodiments.

[0037] Figure 2A is a diagram of integrated circuit 200A, based on some embodiments.

[0038] The integrated circuit 200A includes unit 202a and unit 204a.

[0039] In some embodiments, unit 202a is a region of a clock circuit, and the clock circuit includes one or more buffers or inverters. In some embodiments, unit 202a is an integrated circuit 100. In some embodiments, unit 202a includes one or more buffers, inverters, or leaf units of the integrated circuit 100.

[0040] In some embodiments, unit 204a is a region for feeding through-via (FTV) circuitry. In some embodiments, the FTV circuitry extends from the front side of the substrate to the back side of the substrate, and vice versa. In some embodiments, the FTV circuitry is configured to route signals from the front side of the substrate to the back side of the substrate, and vice versa.

[0041] In some embodiments, unit 204a is referred to as an FTV-Output (FTV-O) unit. In some embodiments, the FTV-O unit is configured to receive output signals from other clock units (e.g., unit 202a).

[0042] Units 202a and 204a are configured to share a common boundary 201a. Boundary 201a extends in a first direction X. In some embodiments, units 202a and 204a are adjacent or directly adjacent along boundary 201a.

[0043] Unit 202a has a height H1 in the second direction Y. In some embodiments, the second direction Y is different from the first direction X.

[0044] Unit 204a has a height H2 in the second direction Y.

[0045] In some embodiments, height H2 is different from height H1. In some embodiments, height H2 is less than height H1.

[0046] In some embodiments, the width of unit 204a in the first direction X is at least 80% of the width of unit 202a in the first direction X. In some embodiments, the width of unit 202a in the first direction X is greater than the height H1. In some embodiments, the width of unit 204a in the first direction X is greater than the height H2.

[0047] In some embodiments, at least one of units 202a, 204a, 204b, 204c, 206a, 206b, or 206c is a single-height unit. In some embodiments, at least one of units 202a, 204a, 204b, 204c, 206a, 206b, or 206c is a dual-height unit.

[0048] Other configurations in the integrated circuit 200A, arrangements at other levels, or other quantities of units 202a or 204a also fall within the scope of this disclosure.

[0049] Figure 2B is a schematic diagram of an integrated circuit 200B according to some embodiments.

[0050] The integrated circuit 200B includes unit 202a and unit 206a.

[0051] Integrated circuit 200B is a variant of integrated circuit 200A, therefore a similar detailed description is omitted. Compared to integrated circuit 200A, unit 206a replaces unit 204a in integrated circuit 200B, therefore a similar detailed description is omitted.

[0052] In some embodiments, unit 206a is referred to as an FTV-Input (FTV-I) unit. In some embodiments, the FTV-I unit is configured to output an input signal to other clock units (e.g., unit 202a).

[0053] Units 202a and 206a are configured to share a common boundary 201a. In some embodiments, units 202a and 206a are adjacent or directly adjacent along the boundary 201a.

[0054] Unit 206a has a height H3 in the Y direction.

[0055] In some embodiments, height H3 is different from height H1. In some embodiments, height H3 is less than height H1.

[0056] In some embodiments, the width of unit 206a in the X direction is at least 80% of the width of unit 202a in the X direction. In some embodiments, the width of unit 202a in the X direction is greater than the height H1. In some embodiments, the width of unit 206a in the X direction is greater than the height H3.

[0057] Other configurations, arrangements or quantities of units 202a or 206a in integrated circuit 200B at other levels are also within the scope of this disclosure.

[0058] Figure 2C is a schematic diagram of an integrated circuit 200C according to some embodiments.

[0059] The integrated circuit 200C includes unit 202a, unit 204a and unit 204b.

[0060] Integrated circuit 200C is a variant of integrated circuit 200A, therefore a similar detailed description is omitted. Compared to integrated circuit 200A, integrated circuit 200C also includes unit 204b, therefore a similar detailed description is omitted.

[0061] In some embodiments, unit 204b is similar to unit 204a, therefore a similar detailed description is omitted.

[0062] In some embodiments, units 204a and 204b are referred to as FTV-O units, and at least one of units 204a or 204b is configured to receive an output signal from another clock unit (e.g., unit 202a).

[0063] Units 202a and 204b are configured to share a common boundary 201b. Boundary 201b extends in a first direction X. In some embodiments, units 202a and 204b are adjacent or directly adjacent along boundary 201b.

[0064] Unit 204b has a height H2 in the second direction Y.

[0065] In some embodiments, the height of unit 204b is different from the height of unit 204a.

[0066] In some embodiments, the width of unit 204b in the first direction X is at least 80% of the width of unit 202a in the first direction X. In some embodiments, the width of unit 204b in the first direction X is greater than the height H1.

[0067] Other configurations in the integrated circuit 200C, arrangements at other levels, or other numbers of units 202a, 204a, or 204b are also within the scope of this disclosure.

[0068] Figure 2D is a diagram of an integrated circuit 200D according to some embodiments.

[0069] The integrated circuit 200D includes unit 202a, unit 206a and unit 204b.

[0070] Integrated circuit 200D is a variant of integrated circuits 200B and 200C, therefore a similar detailed description is omitted. Compared to integrated circuit 200B, integrated circuit 200D also includes unit 204b, therefore a similar detailed description is omitted. Compared to integrated circuit 200C, unit 206a of integrated circuit 200D replaces unit 204a of integrated circuit 200C, therefore a similar detailed description is omitted.

[0071] In some embodiments, units 206a and 204b are referred to as FTV-O units, and at least one of units 206a or 204b is configured to receive an output signal from another clock unit (e.g., unit 202a).

[0072] In some embodiments, unit 206a is referred to as FTV-I unit.

[0073] In some embodiments, unit 204b is referred to as FTV-O unit.

[0074] In some embodiments, unit 206a is replaced by unit 204a, and unit 204b is replaced by a unit similar to unit 206a, so a similar detailed description is omitted.

[0075] Other configurations in the integrated circuit 200D, arrangements at other levels, or other quantities of units 202a, 206a, or 204b are also within the scope of this disclosure.

[0076] Figure 2E is a diagram of an integrated circuit 200E according to some embodiments.

[0077] The integrated circuit 200E includes unit 202a and unit 204a.

[0078] Integrated circuit 200E is a variant of integrated circuit 200A, therefore a similar detailed description is omitted. Compared to integrated circuit 200A, the width W2 of cell 204a in integrated circuit 200E is greater than the width W1 of cell 202a in integrated circuit 200A, therefore a similar detailed description is omitted.

[0079] In some embodiments, the width W2 of unit 204a in the first direction X is greater than the width W1 of unit 202a in the first direction X. In some embodiments, the width W1 of unit 202a in the first direction X is greater than the height H1. In some embodiments, the width W2 of unit 204a in the first direction X is greater than the height H2.

[0080] In some embodiments, unit 204a is replaced by unit 206a, therefore a similar detailed description is omitted.

[0081] Other configurations in the integrated circuit 200E, arrangements at other levels, or other quantities of units 202a or 204a are also within the scope of this disclosure.

[0082] Figure 2F is a diagram of an integrated circuit 200F according to some embodiments.

[0083] The integrated circuit 200F includes unit 202a and unit 204a.

[0084] Integrated circuit 200F is a variant of integrated circuit 200B, therefore a similar detailed description is omitted. Compared to integrated circuit 200B, the width W3 of cell 204a in integrated circuit 200F is smaller than the width W1 of cell 202a in integrated circuit 200B, therefore a similar detailed description is omitted.

[0085] In some embodiments, the width W3 of unit 204a in the first direction X is smaller than the width W1 of unit 202a in the first direction X.

[0086] In some embodiments, unit 204a is replaced by unit 206a, therefore a similar detailed description is omitted.

[0087] Other configurations in the integrated circuit 200F, arrangements at other levels, or other quantities of units 202a or 204a also fall within the scope of this disclosure.

[0088] Figure 2G is a diagram of an integrated circuit 200G according to some embodiments.

[0089] The integrated circuit 200G includes unit 202a, unit 204a and unit 204c.

[0090] Integrated circuit 200G is a variant of integrated circuit 200A, therefore a similar detailed description is omitted. Compared with integrated circuit 200A, integrated circuit 200G also includes unit 204c, therefore a similar detailed description is omitted.

[0091] In some embodiments, unit 204c is similar to unit 204a, therefore a similar detailed description is omitted.

[0092] In some embodiments, units 204a and 204c are referred to as FTV-O units, and at least one of units 204a or 204c is configured to receive an output signal from another clock unit (e.g., unit 202a).

[0093] Units 202a, 204a, and 204c are configured to share a common boundary 201a. In some embodiments, units 202a, 204a, and 204c are adjacent to each other or directly adjacent to each other along the boundary 201a.

[0094] In some embodiments, units 204a and 204c are adjacent to each other or directly adjacent in the second direction Y.

[0095] Units 204c and 204a have a height H2 in the second direction Y.

[0096] Units 204a and 204c have a width W4 in the second direction Y.

[0097] In some embodiments, the width W4 of unit 204a or 204c in the first direction X is smaller than the width W1 of unit 202a in the first direction X.

[0098] In some embodiments, the width W4 is equal to 50% of the width W1.

[0099] In some embodiments, unit 204a is replaced by a unit similar to unit 204a disposed along boundary 201b, and unit 204c is replaced by a unit similar to unit 204c disposed along boundary 201b; therefore, similar detailed descriptions are omitted.

[0100] Other configurations in the integrated circuit 200G, arrangements at other levels, or other numbers of units 202a, 204a, or 204c are also within the scope of this disclosure.

[0101] Figure 2H is a schematic diagram of an integrated circuit 200H according to some embodiments.

[0102] The integrated circuit 200H includes unit 202a, unit 206a and unit 206c.

[0103] Integrated circuit 200H is a variant of integrated circuit 200B, therefore a similar detailed description is omitted. Compared to integrated circuit 200B, integrated circuit 200H also includes unit 206c, therefore a similar detailed description is omitted.

[0104] In some embodiments, unit 206c is similar to unit 206a, therefore a similar detailed description is omitted.

[0105] In some embodiments, units 206a and 206c are referred to as FTV-I units, and at least one of units 206a or 206c is configured to output an input signal to another clock unit (e.g., unit 202a).

[0106] Units 202a, 206a, and 206c are configured to share a common boundary 201a. In some embodiments, units 202a, 206a, and 206c are adjacent to each other or directly adjacent to each other along the boundary 201a.

[0107] In some embodiments, units 206a and 206c are adjacent to each other or directly adjacent in the Y direction.

[0108] Units 206c and 206a have a height H3 in the Y direction.

[0109] Units 206a and 206c have a width W5 in the Y direction.

[0110] In some embodiments, the width W5 of unit 206a or 206c in the X direction is smaller than the width W1 of unit 202a in the X direction.

[0111] In some embodiments, the width W5 is equal to 50% of the width W1.

[0112] In some embodiments, unit 206a is replaced by a unit similar to unit 206a along boundary 201b, and unit 206c is replaced by a unit similar to unit 206c along boundary 201b, so similar detailed descriptions are omitted.

[0113] In some embodiments, unit 206a or 206c is replaced by corresponding unit 204a or 204c along boundary 201a, so a similar detailed description is omitted.

[0114] Other configurations in the integrated circuit 200H, arrangements at other levels, or the number of units 202a, 206a, or 206c are also within the scope of this disclosure.

[0115] In some embodiments, at least one of the integrated circuits 200A-200H is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0116] Figures 3A-3C are schematic diagrams of an integrated circuit 300 according to some embodiments.

[0117] The integrated circuit 300 is an embodiment of at least one of units 204a, 204b, 204c, 206a, 206b or 206c, and similar detailed descriptions are omitted.

[0118] Figure 3A is a top view of an integrated circuit 300 according to some embodiments.

[0119] Figures 3B-3C are corresponding cross-sectional views of an integrated circuit 300 according to some embodiments.

[0120] Figure 3B is a cross-sectional view of the integrated circuit 300 intersecting with plane A-A' according to some embodiments. Figure 3C is a cross-sectional view of the integrated circuit 300 intersecting with plane B-B' according to some embodiments.

[0121] In some embodiments, the integrated circuit 300 is at least one of units 204a, 204b, 204c, 206a, 206b or 206c, and similar details will not be described for the sake of brevity.

[0122] In some embodiments, the integrated circuit 300 is manufactured based on a corresponding layout design similar to that of the integrated circuit 300.

[0123] For the sake of brevity, Figures 3A-6C and 8A-13C are described as corresponding integrated circuits 300-600 and 800-1300. However, in some embodiments, Figures 3A-6C and 8A-13C also correspond to layout designs, and the structural elements of integrated circuits 300-600 and 800-1300 also correspond to layout patterns. The structural relationships of the corresponding layout designs of integrated circuits 300-600 and 800-1300 include alignment, length, and width, as well as configuration and hierarchy. These relationships and configurations are similar to those of integrated circuits 300-600 and 800-1300, and for the sake of brevity, such detailed descriptions will not be repeated.

[0124] For ease of illustration, some components marked in one or more of Figures 3A-6C and 8A-13C are not marked in one or more of Figures 3A-6C and 8A-13C. In some embodiments, at least one or more of the integrated circuits 300-600 and 800-1300 include additional components not shown in Figures 3A-6C and 8A-13C.

[0125] The integrated circuit 300 includes one or more features such as an oxide diffusion (OD) layer or active layer, a gate (POLY) layer, a metal overdiffusion (MD) layer, a back metal 0 (BMO) layer, a feed through-hole (FTC) layer, and a via to the MD power rail (VDR) layer.

[0126] The integrated circuit 300 includes cells 301. Cell 301 has cell boundaries 301a and 301b extending in a first direction X, and cell boundaries 301c and 301d extending in a second direction Y. In some embodiments, the second direction Y is different from the first direction X. In some embodiments, the integrated circuit 300 is adjacent to other cell layout designs (not shown) along cell boundaries 301c and 301d. In some embodiments, the integrated circuit 300 is adjacent to other cell layout designs (not shown) along cell boundaries 301a and 301b extending in the first direction X. In some embodiments, the integrated circuit 300 is a single-height standard cell. In some embodiments, the integrated circuit 300 is a double-height standard cell. Other standard cell heights of the integrated circuit 300 are also within the scope of this disclosure.

[0127] In some embodiments, cell 301 is a standard cell, and the integrated circuit 300 corresponds to the layout of the standard cell defined by cell boundaries 301a, 301b, 301c, and 301d. In some embodiments, cell 301 is a predefined portion of the integrated circuit 300 containing one or more transistors for performing one or more circuit functions and electrically connected. In some embodiments, cell 301 is surrounded by cell boundaries 301a, 301b, 301c, and 301d, and therefore corresponds to a region of functional circuit elements or means that is a portion of the standard cell.

[0128] In some embodiments, such as those depicted in Figures 3A-6C and 8A-13C discussed below, a given cell has cell boundaries 301c and 301d that are overlapped by corresponding gates 304a and 304e. In some embodiments, cell boundaries 301c and 301d of cell 301 are identified by gates 304a and 304f.

[0129] The unit is therefore configured as one or more standard units, custom units, engineering change instruction (ECO) units, logic gate units, memory units, custom units, physical device units, or other types of units or combinations of units that can be defined in the IC layout diagram, similar to integrated circuits 300-600 and 800-1300. In some embodiments, at least one of units 301, 802, 803, 902, 903, 1002, 1003, 1102, 1104, 1106, 1202, 1204, 1206, 1302, or 1304 is a standard unit of a logic gate unit. In some embodiments, the logic gate unit includes AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, positive / negative, BUFF, latch, delay, or clock units. In some embodiments, one or more of integrated circuits 300-600 and 800-1300 represent a layout design for memory cells. In some embodiments, the memory cells include static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), or read-only memory (ROM). In some embodiments, one or more of integrated circuits 300-600 and 800-1300 include one or more active or passive elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field-effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), FinFETs, wafer transistors, nanowire transistors, complementary FETs (CFETs), and planar MOS transistors with raised source / drain. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors.In some embodiments, at least integrated circuits 300-600 and 800-1300 are standard cells. In some embodiments, one or more of integrated circuits 300-600 and 800-1300 are logic gate cells.

[0130] In some embodiments, one or more of integrated circuits 300-600 and 800-1300 are clock trees, such as integrated circuit 100. In some embodiments, one or more of integrated circuits 300-600 are feed-through vias (FTVs).

[0131] The integrated circuit 300 also includes a substrate 390. The substrate 390 has a front side 390a and a back side 390b opposite to the front side. The substrate 390 includes a well 305.

[0132] In some embodiments, well 305 includes a first doping type impurity. In some embodiments, the first doping type is a p-type doping impurity, and well 305 is referred to as a p-type well.

[0133] In some embodiments, the first doping type is an n-type doped impurity, and well 305 is referred to as an N-type well.

[0134] The integrated circuit 300 also includes one or more active regions 302a or 302b extending along the first direction X (collectively referred to as "active region set 302").

[0135] The active region 302 is embedded in the substrate 390 or well 305.

[0136] The active region 302a is embedded in the substrate 390, and the active region 302b is embedded in the well 305.

[0137] In some embodiments, the active region 302b is an n-type doped impurity, the first well is a P-well, and the active region 302b corresponds to an N-type transistor, while the active region 302a corresponds to a P-type transistor.

[0138] In some embodiments, the active region 302b is a p-type doped impurity, the first well is an N-well, and the active region 302b corresponds to a p-type transistor, while the active region 302a corresponds to an N-type transistor.

[0139] The active regions 302a and 302b of the active region set 302 are separated from each other in the second direction Y. In some embodiments, the active region set 302 is located on the front side 390a of at least the integrated circuits 300-600 and 800-1300.

[0140] In some embodiments, the active region set 302 is manufactured by an active region set layout pattern similar to that of the active region set 302, and such descriptions will not be elaborated for the sake of brevity. In some embodiments, the active regions 302a and 302b of the active region set 302 are manufactured by corresponding active region layout patterns, which are similar to the active regions 302a and 302b of the active region set 302 of the integrated circuits 300-600 and 800-1300.

[0141] In some embodiments, the active region set 302 is referred to as the oxide diffusion (OD) region, which defines the source or drain diffusion regions of at least integrated circuits 300-600 and 800-1300.

[0142] In some embodiments, the active region 302a is the source and drain regions of the PMOS transistors of the integrated circuits 300-600 and 800-1300, and the active region 302b is the source and drain regions of the NMOS transistors of the integrated circuits 300-600 and 800-1300.

[0143] In some embodiments, the active region 302a is the source and drain regions of the NMOS transistors of the integrated circuits 300-600 and 800-1300, and the active region 302b is the source and drain regions of the PMOS transistors of the integrated circuits 300-600 and 800-1300.

[0144] In some embodiments, the active region set 302 is located at a first level. In some embodiments, the first level corresponds to the active level or OD level of one or more of the integrated circuits 300-600 and 800-1300.

[0145] In some embodiments, the active region 302a is the source and drain regions of one or more n-type CFETs, n-type fin field-effect transistors (FinFETs), n-type nanosheet transistors, or n-type nanowire transistors, and the active region layout pattern 302b is the source and drain regions of one or more p-type CFETs, p-type fin field-effect transistors (FinFETs), p-type nanosheet transistors, or p-type nanowire transistors.

[0146] In some embodiments, the active region 302a is the source and drain regions of one or more p-type CFETs, p-type fin field-effect transistors (FinFETs), p-type nanosheet transistors, or p-type nanowire transistors, and the active region layout pattern 302b is the source and drain regions of one or more n-type CFETs, n-type fin field-effect transistors (FinFETs), n-type nanosheet transistors, or n-type nanowire transistors.

[0147] Other active regions in active region set 302 are also within the scope of this disclosure.

[0148] Other configurations in the active area set 302, other arrangements at other levels, or other numbers of patterns are also within the scope of this disclosure.

[0149] The integrated circuit 300 also includes an insulating region 303.

[0150] Insulating region 303 is configured to electrically isolate one or more elements from each other in active region assembly 302, gate assembly 304, and contact assembly 306. In some embodiments, insulating region 303 includes a plurality of insulating regions deposited at different times during methods 1400-1500 (FIGs 14A-15). In some embodiments, the insulating region is a dielectric material. In some embodiments, the dielectric material includes silicon dioxide, silicon oxynitride, or the like.

[0151] Other configurations in insulating region 303, other arrangements at other layout levels, or other numbers of portions are also within the scope of this disclosure.

[0152] The integrated circuit 300 also includes one or more gates 304a, 304b1, 304b2, 304c1, 304c2, 304d1, 304d2 or 304e (collectively referred to as the "gate set 304") extending in the second direction Y. Each gate in the gate set 304 is separated from the adjacent gates in the gate set 304 by a first spacing (unmarked) in the first direction X.

[0153] The gate set 304 overlaps with the active region set 302.

[0154] Gate set 304 is manufactured from a set of corresponding gate patterns similar to gate set 304. For the sake of brevity, similar detailed descriptions will not be repeated. In some embodiments, each gate 304a, 304b1, 304b2, 304c1, 304c2, 304d1, 304d2 or 304e of gate set 304 is manufactured from a corresponding gate pattern similar to the corresponding gate 304a, 304b1, 304b2, 304c1, 304c2, 304d1, 304d2 or 304e. For the sake of brevity, similar detailed descriptions will not be repeated.

[0155] In some embodiments, at least gate 304b1, 304c1 or 304d1 is the corresponding gate of the corresponding NMOS transistor, and at least gate 304b2, 304c2 or 304d2 is the corresponding gate of the corresponding PMOS transistor.

[0156] In some embodiments, at least gate 304b1, 304c1 or 304d1 is a corresponding gate of a PMOS transistor, and at least gate 304b2, 304c2 or 304d2 is a corresponding gate of an NMOS transistor.

[0157] In some embodiments, at least one of gates 304a or 304e is a corresponding dummy gate. In some embodiments, the dummy gate is also referred to as continuous poly over diffusion edge (CPODE). In some embodiments, at least gate 304a or 304e corresponds to a dummy gate. In some embodiments, the dummy gate is the gate of a non-functional transistor.

[0158] In some embodiments, at least one of the gates 304a, 304b1, 304b2, 304c1, 304c2, 304d1, 304d2 or 304e corresponds to a pseudo gate.

[0159] Gate set 304 is located above active region set 302. Gate set 304 is located on a second level different from the first level. In some embodiments, the second level is different from the first level. In some embodiments, the second level corresponds to one or more POLY levels of integrated circuits 300-600 and 800-1300.

[0160] In some embodiments, the POLY level is above the OD level.

[0161] Other configurations, other arrangements at other levels, or other numbers of patterns in gate set 304 are also within the scope of this disclosure.

[0162] The integrated circuit 300 also includes one or more contacts 306a or 306b extending along the second direction Y (collectively referred to as "contact assembly 306").

[0163] Each contact in the contact set 306 is separated from the pattern of its adjacent contact in the first direction X. In some embodiments, the contact set 306 is referred to as a "slit contact set" or a "slit MD set".

[0164] The contact set 306 is manufactured from a set of corresponding contact patterns similar to the contact set 306; for the sake of brevity, a similar detailed description will not be provided. In some embodiments, each contact 306a or 306b in the contact set 306 is manufactured from a corresponding contact pattern similar to the corresponding contact 306a or 306b in the contact set 306; for the sake of brevity, a similar detailed description will not be provided.

[0165] In some embodiments, the contact assembly 306 is also referred to as the metal diffusion layer (MD) conductor assembly.

[0166] In some embodiments, at least one of the contacts 306a or 306b in the contact set 306 is the corresponding source or drain terminal of one of the NMOS or PMOS transistors of the integrated circuits 300-600 and 800-1300.

[0167] In some embodiments, the contact set 306 overlaps with the active region set 302. The contact set is located at a third level. In some embodiments, the third level corresponds to one or more contact levels or MD levels of integrated circuits 300-600 and 800-1300. In some embodiments, the third level is the same as the second level. In some embodiments, the third level is different from the first level.

[0168] Other configurations, arrangements at other levels, or the number of patterns in contact assembly 306 are also within the scope of this disclosure.

[0169] The integrated circuit 300 also includes one or more conductors 320a (collectively referred to as "conductor assembly 320") extending in at least a first direction X.

[0170] In some embodiments, each conductor 320a in the conductor set 320 is separated from each other in at least the second direction Y.

[0171] In some embodiments, conductor assembly 320 is located on the back side 390b of integrated circuit 300.

[0172] Although conductor 320a is shown as a continuous structure, in some embodiments, conductor 320a is separated to form one or more discontinuous structures.

[0173] The conductor set 320 is manufactured from a set of corresponding conductive feature patterns similar to the conductor set 320, and such details will not be described further for the sake of brevity. In some embodiments, conductor 320a is manufactured from a set of corresponding conductive feature patterns similar to conductor 320a in the conductor set 320, and such details will not be described further for the sake of brevity.

[0174] In some embodiments, conductor set 320 is configured to transmit or receive one or more signals. In some embodiments, conductor set 320 is configured to transmit or receive one or more clock signals, such as at least one of clock signals CLK or CLK3 in FIG. 1, or at least one of inverted clock signals CLK2 in FIG. 1. In some embodiments, conductor set 320 is configured to transmit or receive one or more supply voltages or reference supply voltages.

[0175] In some embodiments, conductor set 320 is overlapped by one or more active region sets 302, gate sets 304, contact sets 306, conductor set 322 (discussed in Figures 8A-8B) or conductor set 330 (discussed in Figures 8A-8B).

[0176] In some embodiments, conductor assembly 320 is located on a fourth layer. In some embodiments, the fourth layer differs from the first, second, and third layers. In some embodiments, the fourth layer corresponds to the BMO layer of one or more integrated circuits 300-600 and 800-1300. In some embodiments, the BMO layer is located below one or more active region layers, polysilicon layers, metal diffusion layers, feed via layers, vertical diffusion resistor layers, metal O (M0) layers, via O (V0) layers, or metal I (M1) layers.

[0177] In some embodiments, the conductor assembly 320 is located on other metal layers (e.g., back metal 1 (BM1), back metal 2 (BM2), etc.).

[0178] Each conductor in conductor set 320 is separated from its adjacent conductor in conductor set 320 by a spacing (unmarked) in the second direction Y.

[0179] In some embodiments, conductor set 320 corresponds to a BMO wiring trace. In some embodiments, conductor set 320 corresponds to one BMO wiring trace. Other numbers of BMO wiring traces are also within the scope of this disclosure.

[0180] Other configurations in conductor assembly 320, other arrangements at other levels, or other numbers of patterns also fall within the scope of this disclosure.

[0181] The integrated circuit 300 also includes one or more conductors 322a (collectively referred to as "conductor assembly 322") extending in at least a first direction X.

[0182] In some embodiments, each conductor 322a in the conductor set 322 is separated from each other in at least the second direction Y.

[0183] In some embodiments, conductor assembly 322 is also referred to as feed through assembly or contact assembly.

[0184] In some embodiments, conductor set 322 overlaps with conductor set 320. In some embodiments, conductor set 322 and conductor set 320 are electrically coupled.

[0185] In some embodiments, the conductor assembly 322 is embedded in the substrate 390. In some embodiments, the conductor assembly 322 is embedded in an opening (not marked) in the substrate 390.

[0186] Although conductor 322a is shown as a continuous structure, in some embodiments, conductor 322a is separated to form one or more discontinuous structures.

[0187] The conductor set 322 is manufactured from a set of corresponding conductive feature patterns similar to the conductor set 322; detailed descriptions of similarity are omitted for brevity. In some embodiments, conductor 322a is manufactured from a set of corresponding conductive feature patterns similar to conductor 322a in the conductor set 322; detailed descriptions of similarity are omitted for brevity.

[0188] In some embodiments, conductor set 322 is configured to transmit or receive one or more signals. In some embodiments, conductor set 322 is configured to transmit or receive one or more clock signals, such as at least one of clock signals CLK or CLK3 in FIG. 1, or at least one of inverted clock signals CLK2 in FIG. 1. In some embodiments, conductor set 322 is configured to transmit or receive one or more supply voltages or reference supply voltages.

[0189] In some embodiments, conductor set 322 is overlapped by one or more of gate set 304, contact set 306, conductor set 322 (discussed in Figures 8A-8B) or conductor set 330 (discussed in Figures 8A-8B).

[0190] In some embodiments, conductor assembly 322 is located on a fifth layer. In some embodiments, the fifth layer differs from the first, second, third, and fourth layers. In some embodiments, the fifth layer corresponds to a feed via (FTC) layer of one or more of integrated circuits 300-600 and 800-1300. In some embodiments, the feed via layer is located below one or more of a polysilicon layer, a metal diffusion layer, a vertical diffusion resistor layer, an MO layer, a VO layer, or an M1 layer. In some embodiments, the feed via layer is located above a BMO layer.

[0191] In some embodiments, conductor assembly 322 is located on other layers.

[0192] Each conductor in conductor set 322 is separated from its adjacent conductor in conductor set 322 by a spacing (not marked) in the second direction Y.

[0193] Other configurations, other arrangements at other levels, or other numbers of patterns in conductor set 322 are also within the scope of this disclosure.

[0194] The integrated circuit 300 also includes one or more conductors 330a (collectively referred to as "conductor assembly 330") extending at least in the first direction X.

[0195] In some embodiments, each conductor 330a in the conductor set 330 is separated from each other in at least the second direction Y.

[0196] In some embodiments, conductor assembly 330 is also referred to as via assembly or via-to-metal diffusion layer track assembly.

[0197] In some embodiments, conductor assembly 330 overlaps with contact assembly 306, conductor assembly 320, and conductor assembly 322. In some embodiments, conductor assembly 330 is electrically coupled to contact assembly 306, conductor assembly 320, and conductor assembly 322.

[0198] In some embodiments, the contact assembly 306 is located between the conductor assembly 330 and the conductor assembly 322. In some embodiments, the width of the conductor assembly 330 in the first direction X is greater than the width of the contact assembly 306 in the first direction X.

[0199] In some embodiments, the gate set 304 is located between the conductor set 330 and the conductor set 322.

[0200] In some embodiments, conductor assembly 330 is electrically coupled to contact assembly 306, contact assembly 306 is electrically coupled to conductor assembly 322, and conductor assembly 322 is electrically coupled to conductor assembly 320.

[0201] Although conductor 330a is shown as a continuous structure, in some embodiments, conductor 330a is separated to form one or more discontinuous structures.

[0202] The conductor set 330 is manufactured from a corresponding set of conductive feature patterns, which is similar to the conductor set 330 and will not be described in detail for the sake of simplicity. In some embodiments, the conductor 330a is manufactured from a corresponding conductive feature pattern, which is similar to the conductor 330a of the conductor set 330 and will not be described in detail for the sake of simplicity.

[0203] In some embodiments, conductor set 330 is configured to transmit or receive one or more signals. In some embodiments, conductor set 330 is configured to transmit or receive one or more clock signals, such as at least one of clock signals CLK or CLK3 of FIG. 1, or at least one of the inverted clock signals CLK2 of FIG. 1. In some embodiments, conductor set 330 is configured to transmit or receive one or more supply voltages or reference supply voltages.

[0204] In some embodiments, conductor set 330 overlaps with one or more of gate set 304, contact set 306, conductor set 320, or conductor set 322.

[0205] In some embodiments, conductor assembly 330 is located on a sixth layer. In some embodiments, the sixth layer differs from the first, second, third, fourth, and fifth layers. In some embodiments, the sixth layer corresponds to a vertically diffused resistor layer of one or more of integrated circuits 300-600 and 800-1300. In some embodiments, the vertically diffused resistor layer is located above one or more bottom metal layers, feed via layers, polysilicon layers, or metal diffusion layers. In some embodiments, the vertically diffused resistor layer is located below one or more metal-0 layers, via-0 layers, or metal-1 layers.

[0206] In some embodiments, conductor assembly 330 is located on other layers.

[0207] Each conductor in conductor set 330 is separated from its adjacent conductors in conductor set 330 by a spacing (unmarked) in the second direction Y.

[0208] Other configurations, other arrangements at other levels, or other numbers of patterns in conductor set 330 also fall within the scope of this disclosure.

[0209] In some embodiments, at least one gate in gate set 304 or 804 is formed using doped or undoped polycrystalline silicon. In some embodiments, at least one gate in gate set 304 or 804 comprises a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0210] In some embodiments, at least one contact from the contact set 306, 406, 506, 806, or at least one conductor from the conductor set 320, 322, 330, 840, 850, 1116, 1118, 1150, 1152, 1250, or 1350, or at least one via from the via set 842, comprises one or more layers of conductive material, metal, metal compound, or doped semiconductor. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, or the like, or combinations thereof. In some embodiments, the metal comprises at least Cu (copper), Co, W, Ru, Al, or the like. In some embodiments, the metal compound comprises at least AlCu, W-TiN, TiSix, NiSix, TiN, TaN, or the like. In some embodiments, the doped semiconductor comprises at least doped silicon or the like.

[0211] In some embodiments, contact assembly 306, conductor assembly 320 and conductor assembly 322 are referred to as feed through-hole (FTV) 391.

[0212] In some embodiments, the FTV 391 extends from the front side 390a of the substrate 390 to the back side 390b of the substrate 390, and vice versa. In some embodiments, the FTV 391 is configured to transmit signals from the front side 390a of the substrate 390 to the back side 390b of the substrate 390, and vice versa.

[0213] In some embodiments, FTV 391 is referred to as FTV-O unit, and FTV 391 is configured to receive output signals from other clock units, such as unit 202a in FIG2A.

[0214] In some embodiments, FTV 391 is referred to as FTV-I unit, and FTV 391 is configured to output input signals to other clock units, such as unit 202a in FIG2B.

[0215] In some embodiments, FTV 391 is configured to send one or more signals to adjacent units. In some embodiments, FTV 391 is configured to receive one or more signals from adjacent units, such as unit 202a in FIG. 2A. In some embodiments, FTV 391 is configured to send or receive one or more clock signals to a unit, such as at least one of clock signals CLK or CLK3 in FIG. 1, or at least one of inverted clock signals CLK2 in FIG. 1, such as unit 202a in FIG. 2B. In some embodiments, FTV 391 is configured to send or receive one or more supply voltages or reference supply voltages.

[0216] In some embodiments, the integrated circuit 300 is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0217] Other configurations, arrangements at other levels, or other numbers of elements in the integrated circuit 300 are also within the scope of this disclosure.

[0218] Figure 4 is a diagram of an integrated circuit 400 according to some embodiments.

[0219] The integrated circuit 400 is an embodiment of at least one of units 204a, 204b, 204c, 206a, 206b or 206c, and similar detailed descriptions are omitted.

[0220] Figure 4 is a top view of an integrated circuit 400 according to some embodiments.

[0221] Integrated circuit 400 is manufactured by a corresponding layout design similar to integrated circuit 400.

[0222] Integrated circuit 400 is a variant of integrated circuit 300 (Figures 3A-3C). Compared to integrated circuit 300 in Figures 3A-3C, integrated circuit 400 replaces contact set 306 with contact set 406; therefore, a similar detailed description is omitted. Compared to integrated circuit 300 in Figures 3A-3C, integrated circuit 400 replaces feed via 391 with feed via 491; therefore, a similar detailed description is omitted.

[0223] The integrated circuit 400 includes at least unit 301, substrate 390, active region assembly 302, well 305, insulating region 303, gate assembly 304, contact assembly 406, conductor assembly 320, conductor assembly 322 and conductor assembly 330.

[0224] Contact assembly 406 includes at least contact 406a or 406b. Compared to the integrated circuit 300 of Figures 3A-3C, contact 406a or 406b of contact assembly 406 replaces the corresponding contact 306a or 306b of contact assembly 306, therefore a similar detailed description is omitted.

[0225] Contact element set 406 overlaps with active region 302a. Contact elements 406a and 406b of contact element set 406 overlap with active region 302a.

[0226] The contact assembly 406 extends at least to the cell boundary 301a in the second direction. In some embodiments, contacts 406a and 406b of the contact assembly 406 extend at least to the cell boundary 301a in the second direction.

[0227] In some embodiments, the contact assembly 406 overlaps with the cell boundary 301a to adjacent cells. In some embodiments, by overlapping with the cell boundary 301a to adjacent cells, the contact assembly 406 is configured to receive an output signal from the adjacent cell (e.g., as shown in Figures 9A-9B and 12A-12C).

[0228] In some embodiments, contacts 406a and 406b of contact set 406 overlap with cell boundary 301a to adjacent cells. In some embodiments, by overlapping with cell boundary 301a to adjacent cells, contacts 406a and 406b of contact set 406 are configured to receive one or more output signals from adjacent cells (e.g., as shown in Figures 9A-9B and 12A-12C).

[0229] In some embodiments, the contact assembly 406 overlaps with the cell boundary 301b to another adjacent cell. In some embodiments, the contact assembly 406 overlaps with the cell boundaries 301a and 301b to the respective adjacent cells.

[0230] Other configurations, arrangements at other levels, or the number of patterns in contact set 406 are also within the scope of this disclosure.

[0231] The feed perforation 491 includes a contact assembly 406, a conductor assembly 320, and a conductor assembly 322.

[0232] In some embodiments, the feed via 491 extends from the front side 390a of the substrate 390 to the back side 390b of the substrate 390, and vice versa. In some embodiments, the feed via 491 is configured to route a signal from the front side 390a of the substrate 390 to the back side 390b of the substrate 390, and vice versa.

[0233] In some embodiments, feed via 491 is referred to as FTV-O unit, and feed via 491 is configured to receive output signals from other clock units, such as unit 202a in FIG2A.

[0234] In some embodiments, feed via 491 is configured to receive one or more signals from adjacent cells, such as cell 202a in FIG. 2A. In some embodiments, feed via 491 is configured to receive one or more clock signals, such as at least one of clock signals CLK or CLK3 in FIG. 1, or at least one of inverted clock signals CLK2 in FIG. 1, such as cell 202a in FIG. 2A. In some embodiments, feed via 491 is configured to receive one or more supply voltages or reference supply voltages.

[0235] In some embodiments, the integrated circuit 400 is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0236] Other configurations, arrangements at other levels, or the number of components in the integrated circuit 400 are also within the scope of this disclosure.

[0237] Figure 5A is a top view of an integrated circuit 500 according to some embodiments.

[0238] Figures 5B-5C are corresponding cross-sectional views of an integrated circuit 500 according to some embodiments.

[0239] Figure 5B is a cross-sectional view of an integrated circuit 500 with surfaces C-C' intersecting according to some embodiments. Figure 5C is a cross-sectional view of an integrated circuit 500 with surfaces D-D' intersecting according to some embodiments.

[0240] The integrated circuit 500 is an embodiment of at least one of units 204a, 204b, 204c, 206a, 206b or 206c, and similar detailed descriptions are omitted.

[0241] Figure 5 is a top view of an integrated circuit 500 according to some embodiments.

[0242] Integrated circuit 500 is manufactured using a similar layout design.

[0243] Integrated circuit 500 is a variant of integrated circuit 300 (Figures 3A-3C). Compared to integrated circuit 300 of Figures 3A-3C, integrated circuit 500 replaces contact set 306 with contact set 506; therefore, a similar detailed description is omitted. Compared to integrated circuit 300 of Figures 3A-3C, integrated circuit 500 replaces feed via 391 with feed via 591; therefore, a similar detailed description is omitted.

[0244] The integrated circuit 500 includes at least unit 301, substrate 390, active area assembly 302, well 305, insulating area 303, gate assembly 304, contact assembly 506, conductor assembly 320, conductor assembly 322 and conductor assembly 330.

[0245] Compared to the integrated circuit 300 in Figures 3A-3C, contacts 306a and 306b of contact set 306 are combined into a single contact (e.g., contact 506a of contact set 506), so a similar detailed description is omitted.

[0246] Contact assembly 506 includes at least contact 506a. Compared to the integrated circuit 300 of Figures 3A-3C, contact 506a of contact assembly 506 replaces contacts 306a and 306b of contact assembly 306, therefore a similar detailed description is omitted.

[0247] Contact assembly 506 overlaps with conductor assemblies 322 and 320. Contact 506a of contact assembly 506 overlaps with conductor assemblies 322 and 320.

[0248] The contact assembly 506 extends at least in the X or Y direction.

[0249] In some embodiments, the width of the contact 506a in the X direction is less than at least one of the width of the conductor 320a in the X direction or the width of the conductor 330a in the X direction.

[0250] In some embodiments, the width of contact 506a in the X direction is substantially equal to about 60% to about 80% of at least one of the width of conductor 322a in the X direction or the width of conductor 330a in the X direction.

[0251] In some embodiments, if the difference between two or more elements is less than 5%, then the elements are substantially equal.

[0252] In some embodiments, the width of the contact 506a in the X direction is greater than or equal to at least one of the width of the conductor 320a in the X direction or the width of the conductor 330a in the X direction.

[0253] In some embodiments, contact 506a is located between gates 304c1 and 304c2.

[0254] Other configurations, arrangements at other levels, or the number of patterns in contact assembly 506 are also within the scope of this disclosure.

[0255] The feed perforation 591 includes a contact assembly 506, a conductor assembly 320, and a conductor assembly 322.

[0256] In some embodiments, the feed via 591 extends from the front side 390a of the substrate 390 to the back side 390b of the substrate 390, and vice versa. In some embodiments, the feed via 591 is configured to route signals from the front side 390a of the substrate 390 to the back side 390b of the substrate 390, and vice versa.

[0257] In some embodiments, feed via 591 is referred to as FTV-O unit, and feed via 591 is configured to receive output signals from other clock units, such as unit 202a in FIG2A.

[0258] In some embodiments, feed through-hole 591 is referred to as FTV-I unit, and feed through-hole 591 is configured to output input signals to other clock units, such as unit 202a in FIG2B.

[0259] In some embodiments, feed via 591 is configured to transmit one or more signals to adjacent cells. In some embodiments, feed via 591 is configured to receive one or more signals from adjacent cells, such as cell 202a in FIG. 2A. In some embodiments, feed via 591 is configured to transmit or receive one or more clock signals, such as at least one of clock signals CLK or CLK3 in FIG. 1, or at least one of inverted clock signals CLK2 in FIG. 1, such as cell 202a in FIG. 2B. In some embodiments, feed via 591 is configured to transmit or receive one or more supply voltages or reference supply voltages.

[0260] In some embodiments, by combining contacts 306a and 306b into a single contact (e.g., contact 506a), the contact set 506 has an increased area and / or volume, thereby reducing the resistance of the contact set 506 compared to other methods.

[0261] In some embodiments, by combining contacts 306a and 306b into a single contact (e.g., contact 506a), the contact set 506 has an increased area and / or volume, thereby increasing the capacitance of the contact set 506 compared to other methods.

[0262] In some embodiments, the integrated circuit 500 is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0263] Other configurations, arrangements at other levels, or other numbers of elements in the integrated circuit 500 are also within the scope of this disclosure.

[0264] Figure 6A is a top view of an integrated circuit 600 according to some embodiments.

[0265] Figures 6B-6C are corresponding cross-sectional views of an integrated circuit 600 according to some embodiments.

[0266] Figure 6B is a cross-sectional view of an integrated circuit 600 intersecting plane E-E' according to some embodiments. Figure 6C is a cross-sectional view of an integrated circuit 600 intersecting plane F-F' according to some embodiments.

[0267] The integrated circuit 600 is an embodiment of at least one of units 204a, 204b, 204c, 206a, 206b or 206c, and similar detailed descriptions are omitted.

[0268] Figure 6 is a top view of an integrated circuit 600 according to some embodiments.

[0269] Integrated circuit 600 is fabricated from a corresponding layout design similar to integrated circuit 600.

[0270] Integrated circuit 600 is a variant of integrated circuit 300 (Figures 3A-3C). Compared to integrated circuit 300 in Figures 3A-3C, integrated circuit 600 has a gate set 604 replacing the gate set 304; therefore, a similar detailed description is omitted. Compared to integrated circuit 300 in Figures 3A-3C, integrated circuit 600 has a feed via 691 replacing the feed via 391; therefore, a similar detailed description is omitted.

[0271] The integrated circuit 600 includes at least a unit 301, a substrate 390, an active region assembly 302, a well 305, an insulating region 303, a gate assembly 604, a contact assembly 306, a conductor assembly 320, a conductor assembly 322, and a conductor assembly 330.

[0272] Gate set 604 includes at least gates 304a, 604b, 604c, 604d, or 304e. Compared to the integrated circuit 300 of Figures 3A-3C, gate 604b of gate set 604 replaces gates 304b1 and 304b2 of gate set 304, gate 604c of gate set 604 replaces gates 304c1 and 304c2 of gate set 304, and gate 604d of gate set 604 replaces gates 304d1 and 304d2 of gate set 304; therefore, a similar detailed description is omitted.

[0273] Compared to the integrated circuit 300 in Figures 3A-3C, gates 304b1 and 304b2 of gate set 304 are combined into a single gate (e.g., gate 604b of gate set 604), gates 304c1 and 304c2 of gate set 304 are combined into a single gate (e.g., gate 604c of gate set 604), and gates 304d1 and 304d2 of gate set 304 are combined into a single gate (e.g., gate 604d of gate set 604). Therefore, a similar detailed description is omitted.

[0274] In some embodiments, at least one of gates 604b, 604c, or 604d overlaps with at least one of active region 302a, active region 302b, conductor 322a, or conductor 320a. In some embodiments, conductor 330a overlaps with at least one of gates 604b, 604c, or 604d.

[0275] In some embodiments, at least one of the gates 604b, 604c, or 604d is located between conductors 322a and 330a.

[0276] In some embodiments, at least one of the gates 604b, 604c, or 604d is alternately arranged with at least one of the contacts 306a or 306b in the X direction.

[0277] In some embodiments, the gate set 604 extends in the Y direction to at least the cell boundary 301a or 301b. In some embodiments, gates 604b, 604c, and 604d of the gate set 604 extend in the Y direction to at least the cell boundary 301a or 301b.

[0278] In some embodiments, the gate set 604 overlaps with the cell boundary 301a or 301b to the corresponding adjacent cell. In some embodiments, by overlapping with the cell boundary 301a or 301b to the corresponding adjacent cell, the gate set 604 is configured to receive an output signal from the feed through-hole 691 (e.g., as shown in FIG10A-10B) and is configured to output the output signal to the corresponding adjacent cell (e.g., as shown in FIG10A-10B).

[0279] In some embodiments, gates 604b, 604c, and 604d of gate set 604 overlap with cell boundary 301a or 301b to the corresponding adjacent cell. In some embodiments, by overlapping with cell boundary 301a or 301b to the adjacent cell, gates 604b, 604c, and 604d of gate set 604 are configured to receive one or more output signals from feed via 691 (e.g., as shown in FIG10A-10B) and are configured to output the output signals to the adjacent cell (e.g., as shown in FIG10A-10B).

[0280] In some embodiments, the gate set 604 overlaps with cell boundary 301b to another adjacent cell. In some embodiments, the gate set 604 overlaps with cell boundaries 301a and 301b to the corresponding adjacent cells.

[0281] In some embodiments, at least one of the gate sets 304 or 604 has a height H7 in the Y direction. In some embodiments, at least one of the contact sets 306, 406, or 506 has a height H6 in the Y direction. In some embodiments, as shown in FIG. 6B, the height H6 is greater than the height H7. In some embodiments, when the height H6 is greater than the height H7 as shown in FIG. 6B, the bottom surface 330a1 of the conductor 330a is substantially uniform in the X direction. In some embodiments, when the height H6 is equal to the height H7, the bottom surface 330a1 of the conductor 330a is not substantially uniform in the X direction, and the conductor 330a includes one or more conductive protrusions 330b extending in the Y direction. In some embodiments, the one or more conductive protrusions 330b extending in the Y direction are in direct contact with the contact set 306, thereby providing an electrical connection between the conductor 330a and the contact set 306. In some embodiments, an insulating region 303 is located between at least the top surface of the gate of the gate set 604 and the bottom surface 330a1 of the conductor 330a.

[0282] Other configurations, other arrangements at other levels, or other numbers of patterns in gate set 604 are also within the scope of this disclosure.

[0283] The feed perforation 691 includes a contact assembly 306, a conductor assembly 320, and a conductor assembly 322.

[0284] In some embodiments, the feed via 691 extends from the front side 390a of the substrate 390 to the back side 390b of the substrate 390, and vice versa. In some embodiments, the feed via 691 is configured to transmit a signal from the front side 390a of the substrate 390 to the back side 390b of the substrate 390, and vice versa.

[0285] In some embodiments, the feed through-hole 691 is referred to as an FTV-I unit, and the feed through-hole 691 is configured to output an input signal to other clock units, such as unit 202a in FIG2B.

[0286] In some embodiments, feed via 691 is configured to send one or more signals to adjacent cells. In some embodiments, feed via 691 is configured to send one or more clock signals to a cell (e.g., cell 202a in FIG. 2B), such as at least one of clock signals CLK or CLK3 in FIG. 1, or at least one of inverted clock signals CLK2 in FIG. 1. In some embodiments, feed via 691 is configured to send one or more supply voltages or reference supply voltages.

[0287] Other configurations in the integrated circuit 600, other arrangements at other levels, or other numbers of elements are also within the scope of this disclosure.

[0288] Integrated circuit 600D is a variation of integrated circuit 600 (Figures 6A-6C). Compared to integrated circuit 600 in Figures 6A-6C, the height H6 of contact assembly 306 is equal to the height H7 of gate assembly 604, therefore a similar detailed description is omitted.

[0289] In some embodiments, when height H6 is equal to height H7, the bottom surface 330a1 of conductor 330a is not substantially uniform in the first direction X, and conductor 330a includes one or more conductive protrusions 330b extending in the second direction Y. In some embodiments, the one or more conductive protrusions 330b extending in the second direction Y are in direct contact with contact assembly 306, thereby providing an electrical connection between conductor 330a and contact assembly 306. In some embodiments, insulating region 303 is located between the top surface of the gate of gate assembly 604 and the bottom surface 330a1 of conductor 330a.

[0290] Other configurations in the integrated circuit 600D, other arrangements at other levels, or other numbers of elements are also within the scope of this disclosure.

[0291] Figure 7A is a top view of the integrated circuit 700A, based on some embodiments.

[0292] In some embodiments, the integrated circuit 700A is an embodiment of at least one of buffers B1, B2, B3, B4 or B5 in FIG1, and similar detailed descriptions are omitted.

[0293] In some embodiments, integrated circuit 700A is an embodiment of unit 202a, and similar detailed descriptions are omitted.

[0294] The integrated circuit 700A includes inverter 702 and inverter 704.

[0295] In some embodiments, the integrated circuit 700A includes an even number of inverters, such as inverters 702 and 704.

[0296] Inverter 702 is configured to generate an inverted signal S1B in response to signal S1. In some embodiments, signal S1 is derived by inverting the inverted signal S1B. The input of inverter 702 is configured to receive signal S1. The output of inverter 702 is coupled to the input of inverter 704 and configured to output the inverted signal S1B.

[0297] Inverter 704 is configured to generate signal S2 in response to inverted signal S1B. In some embodiments, inverted signal S1B is derived from the inverted signal S2. The input of inverter 704 is coupled to the output of inverter 702 and configured to receive inverted signal S1B. The output of inverter 704 is configured to output signal S2.

[0298] In some embodiments, signal S2 is a delayed version of signal S1.

[0299] Other configurations, other circuit elements, or the number of inverters in the integrated circuit 700A are within the scope of this disclosure.

[0300] Figure 7B is a top view of an integrated circuit 700B according to some embodiments.

[0301] In some embodiments, the integrated circuit 700B is an embodiment of at least one of the inverters I1, I2 or I3 in FIG1, and similar detailed descriptions are omitted.

[0302] In some embodiments, integrated circuit 700A is an embodiment of unit 202a, and similar detailed descriptions are omitted.

[0303] The integrated circuit 700A includes an inverter 706.

[0304] Inverter 706 is configured to generate an inverted signal S1B in response to signal S1. The input of inverter 706 is configured to receive signal S1. The output of inverter 706 is configured to output the inverted signal S1B.

[0305] Other configurations, other circuit elements, or the number of inverters in the integrated circuit 700B are within the scope of this disclosure.

[0306] Figure 8A is a top view of an integrated circuit 800 according to some embodiments.

[0307] Figure 8B is a top view of a portion 800B of an integrated circuit 800 according to some embodiments.

[0308] The integrated circuit 800 includes one or more features of the OD level, POLY level, MD level, BMO level, FTC level, VDR level, M0 level, V0 level and M1 level.

[0309] Part of 800B includes one or more features of the MD level, M0 level, V0 level and M1 level of integrated circuit 800.

[0310] In some embodiments, integrated circuit 800 is an embodiment of at least one of integrated circuit 200A or 200B, and therefore a similar detailed description is omitted.

[0311] The integrated circuit 800 includes unit 802 and unit 803.

[0312] In some embodiments, unit 802 is an embodiment of at least one of units 204a or 206a, and therefore a similar detailed description is omitted.

[0313] In some embodiments, unit 802 is the integrated circuit 300 of Figures 3A-3C, therefore a similar detailed description is omitted.

[0314] In some embodiments, unit 803 is an embodiment of unit 202a, and therefore a similar detailed description is omitted.

[0315] In some embodiments, unit 803 is an embodiment of one or more buffer circuits, such as integrated circuit 700A of FIG. 7A, or an embodiment of one or more inverters, such as integrated circuit 700B of FIG. 7B, and therefore similar detailed descriptions are omitted.

[0316] Units 802 and 803 are adjacent to each other along unit boundary 201a.

[0317] Unit 803 includes one or more active regions 802a or 802b (collectively referred to as the "set of active regions 802") extending in the first direction X.

[0318] The active region 802 is embedded in the substrate 390 or the well 805.

[0319] The substrate 390 also includes a set of wells 805. In some embodiments, the set of wells 805 is similar to the set of wells 305, so a similar detailed description is omitted.

[0320] The set of wells 805 includes well 805a. In some embodiments, well 805a of the set of wells 805 is similar to well 305a of the set of wells 305, therefore a similar detailed description is omitted.

[0321] In some embodiments, the active region 802 set is similar to the active region 302 set, therefore a similar detailed description is omitted.

[0322] Active region 802a is embedded in substrate 390, while active region 802b is embedded in well 805a.

[0323] In some embodiments, the active region 802b is an n-type dopant, the well 805 is a p-type well, and the active region 802b corresponds to an n-type transistor, while the active region 802a corresponds to a p-type transistor.

[0324] In some embodiments, the active region 802b is a p-type dopant, the well 805 is an N-type well, and the active region 802b corresponds to a p-type transistor, while the active region 802a corresponds to an N-type transistor.

[0325] The active regions 802a and 802b of the active region 802 set are separated from each other in the Y direction. In some embodiments, the active region 802 set is located on the front side 390a of at least integrated circuits 300-600 and 800-1300.

[0326] In some embodiments, the active region 802 set is manufactured from an active region layout pattern set similar to the active region 802 set; for the sake of brevity, such descriptions will not be elaborated further. In some embodiments, the active regions 802a and 802b of the active region 802 set are manufactured from corresponding active region layout patterns of the active regions 802a and 802b of the active region 802 set similar to those of integrated circuits 300-600 and 800-1300.

[0327] In some embodiments, the active region 802a is the source and drain regions of the PMOS transistors in the integrated circuits 300-600 and 800-1300, while the active region 802b is the source and drain regions of the NMOS transistors in the integrated circuits 300-600 and 800-1300.

[0328] In some embodiments, the active region 802a is the source and drain regions of the NMOS transistors of the integrated circuits 300-600 and 800-1300, while the active region 802b is the source and drain regions of the PMOS transistors of the integrated circuits 300-600 and 800-1300.

[0329] In some embodiments, the active region 802 set is located on the first level.

[0330] In some embodiments, the active region 802a is the source and drain regions of one or more n-type CFETs, n-type finFETs, n-type nanosheet transistors, or n-type nanowire transistors, while the active region layout pattern 802b is the source and drain regions of one or more p-type CFETs, p-type finFETs, p-type nanosheet transistors, or p-type nanowire transistors.

[0331] In some embodiments, the active region 802a is the source and drain regions of one or more p-type CFETs, p-type finFETs, p-type nanosheet transistors, or p-type nanowire transistors, while the active region layout pattern 802b is the source and drain regions of one or more n-type CFETs, n-type finFETs, n-type nanosheet transistors, or n-type nanowire transistors.

[0332] Other active regions in the active region set 802 are also within the scope of this disclosure.

[0333] Other configurations, other arrangements at other levels, or other numbers of patterns in the active area 802 set are also included within the scope of this disclosure.

[0334] Unit 803 also includes an insulating region 303 (as described above).

[0335] Other configurations, other arrangements at other layout levels, or other numbers of portions in insulating regions 303 are also included within the scope of this disclosure.

[0336] Unit 803 further includes one or more gates 804a, 804b, 804c, 804e or 804e (collectively referred to as "gate set 804") extending in the second direction Y. Each gate in gate set 804 is separated from its adjacent gate in gate set 804 by a first spacing (not shown) in the first direction X.

[0337] In some embodiments, gate set 804 is similar to gate set 304, therefore a similar detailed description is omitted.

[0338] The gate set 804 overlaps with the active region set 802.

[0339] Gate set 804 is manufactured from a set of corresponding gate patterns similar to gate set 804; for the sake of brevity, similar detailed descriptions will not be described further. In some embodiments, each gate 804a, 804b, 804c, 804e, or 804e in gate set 804 is manufactured from a corresponding gate pattern similar to the corresponding gate 804a, 804b, 804c, 804e, or 804e; for the sake of brevity, similar detailed descriptions will not be described further.

[0340] In some embodiments, at least gates 804b, 804c, or 804d are the corresponding gates of the corresponding NMOS transistor and the corresponding PMOS transistor.

[0341] In some embodiments, at least one of gates 804a or 804e is a corresponding dummy gate or CPODE. In some embodiments, at least gate 804a or 804e corresponds to a dummy gate.

[0342] In some embodiments, at least one of gates 804a, 804b, 804c, 804e or 804e corresponds to a dummy gate.

[0343] Gate set 804 is located above active region set 802. Gate set 804 is located in the second level.

[0344] In some embodiments, the polycrystalline silicon layer is located above the active region layer.

[0345] Other configurations, other arrangements at other levels, or other numbers of patterns in the gate set 804 are also included within the scope of this disclosure.

[0346] Unit 803 also includes one or more contacts 806a, 806b, 806c or 806d (collectively referred to as "contact set 806") extending in the Y direction.

[0347] In some embodiments, contact set 806 is similar to contact set 306, therefore a similar detailed description is omitted.

[0348] Each contact in the contact set 806 is separated from the adjacent contact pattern in the contact set 806 in the X direction.

[0349] The contact set 806 is manufactured from a set of corresponding contact patterns similar to the contact set 806; for the sake of brevity, a similar detailed description will not be described. In some embodiments, each contact 806a, 806b, 806c, or 806d in the contact set 806 is manufactured from a corresponding contact pattern similar to the corresponding contact 806a, 806b, 806c, or 806d in the contact set 806; for the sake of brevity, a similar detailed description will not be described.

[0350] In some embodiments, the contact assembly 806 is also referred to as the MD conductor assembly.

[0351] In some embodiments, at least one of contacts 806a, 806b, 806c or 806d in the contact set 806 is a corresponding source or drain terminal of one of the NMOS or PMOS transistors of the integrated circuits 300-600 and 800-1300.

[0352] In some embodiments, the contact set 806 overlaps with the active area set 802. The contact set is located at the third level.

[0353] Other configurations, arrangements at other levels, or the number of patterns in contact assembly 806 are also within the scope of this disclosure.

[0354] In some embodiments, unit 802 is the integrated circuit 300 of Figures 3A-3C, and similar detailed descriptions are omitted.

[0355] Unit 802 includes the feed through-hole 391 of FIG3A, and similar detailed descriptions are omitted.

[0356] The integrated circuit 800 also includes one or more conductors 840a, 840b, 840c (collectively referred to as "conductor assembly 840") extending in the first direction X.

[0357] Each conductor in conductor set 840 is separated from another conductor in conductor set 840 in the second direction Y.

[0358] The conductor set 840 overlaps with at least one of the active region set 802, conductor set 330, conductor set 322, conductor set 320, contact set 306, contact set 806, or gate set 804.

[0359] Conductor 840a overlaps with at least one of conductor set 330, conductor set 322, conductor set 320 or contact set 306.

[0360] Conductor 840b overlaps with at least one of active region 802a, contact 806a, contact 806b, gate 804b, gate 804c, or gate 804d.

[0361] Conductor 840c overlaps with at least one of active region 802b, contact 806c, contact 806d, gate 804b, gate 804c, or gate 804d.

[0362] In some embodiments, conductor set 840 is manufactured from a set of corresponding conductive feature patterns similar to conductor set 840.

[0363] In some embodiments, conductors 840a, 840b, and 840c are manufactured from corresponding conductive feature patterns similar to those of the corresponding conductors 840a, 840b, and 840c.

[0364] In some embodiments, at least one conductor in the conductor set 840 is located on the front side 303a of the integrated circuits 300-600 and 800-1300.

[0365] In some embodiments, conductor assembly 840 is located on a seventh level. In some embodiments, the seventh level differs from at least one of the first, second, third, fourth, fifth, or sixth levels. In some embodiments, the seventh level corresponds to the M0 level of integrated circuit 800 or one or more of integrated circuits 300-600 and 800-1300. In some embodiments, the M0 level is above the OD level, POLY level, MD level, VDR level, BMO level, or FTC level. In some embodiments, the M0 level is below one or more of the V0 level or M1 level.

[0366] In some embodiments, conductor set 840 corresponds to 3 M0 wiring tracks. Other numbers of M0 wiring tracks are within the scope of this disclosure.

[0367] Other configurations in conductor set 840, other arrangements at other levels, or other numbers of conductors are also within the scope of this disclosure.

[0368] Other M0 orbital assignments also fall within the scope of this disclosure.

[0369] The integrated circuit 800 also includes one or more conductors 850a, 850b (collectively referred to as "conductor assembly 850") extending in the second direction Y.

[0370] Each conductor in conductor set 850 is separated from another conductor in conductor set 850 in the first direction X.

[0371] The conductor set 850 overlaps with at least one of the following: conductor set 840, through hole set 842, active zone set 302, active zone set 802, conductor set 330, conductor set 322, conductor set 320, contact set 306, or contact set 806.

[0372] In some embodiments, conductor set 850 is manufactured from a set of corresponding conductive feature patterns similar to conductor set 850.

[0373] In some embodiments, conductors 850a and 850b are manufactured from corresponding conductive feature patterns similar to those of the corresponding conductors 850a and 850b.

[0374] In some embodiments, at least one conductor in the conductor set 850 is located on the front side 303a of the integrated circuits 300-600 and 800-1300.

[0375] In some embodiments, conductor assembly 850 is located on an eighth layer. In some embodiments, the eighth layer differs from at least one of the first, second, third, fourth, fifth, sixth, or seventh layers. In some embodiments, the eighth layer corresponds to the M1 layer of one or more integrated circuits 800 or 1100-1300. In some embodiments, the M1 layer is located above the OD layer, POLY layer, MD layer, VDR layer, BMO layer, FTC layer, M0 layer, or V0 layer.

[0376] In some embodiments, conductor set 850 corresponds to two M1 wiring tracks. Other numbers of M1 wiring tracks are within the scope of this disclosure.

[0377] In some embodiments, conductor set 850 overlaps with cell boundary 301a of cell 803. In some embodiments, by overlapping with cell boundary 301a of cell 803, conductor set 850 is configured to send / receive output signals to / from cell 803 and is referred to as a set of M1 local interconnects (M1-LIs).

[0378] In some embodiments, conductors 850a and 850b of conductor set 850 overlap with cell boundary 301a of cell 803. In some embodiments, by overlapping with cell boundary 301a of cell 803, conductors 850a and 850b of conductor set 850 are configured to send / receive one or more output signals to / from cell 803.

[0379] In some embodiments, the conductor set 850 overlaps with the cell boundary 201b of another adjacent cell.

[0380] In some embodiments, the number of M1 forks or tracks in the conductor set 850 is determined based on the ratio R1 in Formula 1.

[0381] The ratio R1 of the number of M1 forks to the number of CPPs is expressed in Formula 1. R1 = Number of M1 finger forks / Number of CPPs (1)

[0382] The number of M1 forks is the number of metal 1 forks or tracks in the integrated circuit 800, while the number of CPPs is the number of center polysilicon pitches (CPPs) in the integrated circuit 800.

[0383] In some embodiments, the ratio R1 is less than or equal to 10% and greater than or equal to 35%, as expressed in Formula 2. 10% ≤ R1 ≤ 35% (2)

[0384] Other ranges or values ​​of ratio R1 are within the scope of this disclosure.

[0385] In some embodiments, the number of M0 forks or tracks in the conductor set 840 is determined based on the ratio R2 in Formula 3. R2 = Number of M0 finger forks / Clock unit height (3)

[0386] The number of M0 finger forks or tracks is the number of metal 0 finger forks or tracks in the integrated circuit 800, while the clock unit height is the height of the clock unit in the Y direction in the integrated circuit 800.

[0387] In some embodiments, the ratio R2 is greater than or equal to 1, as expressed in Formula 4. R² ≥ 1 (4)

[0388] Other ranges or values ​​of the ratio R2 are within the scope of this disclosure.

[0389] For example, Formula 2 indicates that the ratio of the number of M0 finger forks to the clock unit height should be greater than or equal to 1.

[0390] In some embodiments, the height of a single-height clock unit is 1. In some embodiments, the height of a single-height clock unit is 2. In some embodiments, the height of a triple-height clock unit is 3.

[0391] In some embodiments, if the ratio R1 is greater than or equal to 10% and less than or equal to 35%, the resistance of the gate 304 assembly and / or the resistance of the gate 804 assembly will not cause an increase in the resistance of one or more feed vias (e.g., feed via 391), and therefore will not increase the resistance of the clock tree or increase the clock cell delay, and will not degrade the performance of the clock cell and clock tree compared to other methods.

[0392] In some embodiments, if the ratio R1 is less than 10% or greater than 35%, the resistance of the gate 304 assembly and / or the gate 804 assembly will cause an increase in the resistance of one or more feed vias (e.g., feed via 391), thus increasing the resistance of the clock tree or increasing the clock cell delay, and degrading the performance of the clock cell and clock tree compared to other methods.

[0393] In some embodiments, if the ratio R2 is greater than or equal to 1, the resistance of the gate 304 assembly and / or the resistance of the gate 804 assembly will not cause an increase in the resistance of one or more feed vias (e.g., feed via 391), and therefore will not increase the resistance of the clock tree or increase the clock cell delay, and will not degrade the performance of the clock cell and clock tree compared to other methods.

[0394] In some embodiments, if the ratio R2 is less than 1, the resistance of the gate 304 assembly and / or the gate 804 assembly will cause an increase in the resistance of one or more feed vias (e.g., feed via 391), thus increasing the resistance of the clock tree or increasing the clock cell delay, and degrading the performance of the clock cell and clock tree compared to other methods.

[0395] In some embodiments, the number of conductors in the conductor set 850 is specified by satisfying Formulas 1 and 2, while ensuring that the gate resistance of the gate set 304 or the gate set 804 does not become too large, thereby reducing the performance of the integrated circuit 800.

[0396] In some embodiments, the number of conductors in the conductor set 840 is specified by satisfying Formulas 3 and 4, while ensuring that the gate resistance of the gate set 304 or the gate set 804 does not become too large, thereby reducing the performance of the integrated circuit 800.

[0397] Other configurations in the conductor 850 set, arrangements at other levels, or other quantities of conductors also fall within the scope of this disclosure.

[0398] The integrated circuit 800 also includes one or more vias 842a, 842b, 842c, 842d, 842e, and 842f (collectively referred to as the "via 842 set").

[0399] In some embodiments, the via 842 set is manufactured from a corresponding via pattern set similar to the via 842 set.

[0400] In some embodiments, the vias 842a, 842b, 842c, 842d, 842e, and 842f of the via set 842 are manufactured from corresponding via patterns similar to the vias 842a, 842b, 842c, 842d, 842e, and 842f of the via set 842.

[0401] In some embodiments, the via 842 assembly is located between the conductor 840 assembly and the conductor 850 assembly.

[0402] In some embodiments, the via 842 assembly electrically couples the conductor 840 assembly and the conductor 850 assembly together.

[0403] Through hole 842a is located between conductor 840a and conductor 850a.

[0404] Through hole 842b is located between conductor 840a and conductor 850b.

[0405] Through hole 842c is located between conductor 840b and conductor 850a.

[0406] Through hole 842d is located between conductor 840b and conductor 850b.

[0407] Through hole 842e is located between conductor 840c and conductor 850a.

[0408] Through hole 842f is located between conductor 840c and conductor 850b.

[0409] The via 842 assembly is located above a via (V0) level of one or more metal 0 layers in integrated circuits 800 or 1100-1300. In some embodiments, the V0 level is located above the active region layer, polysilicon layer, metal diffusion layer, vertical diffusion resistor layer, bottom metal 0 layer, feed via layer, metal 0 layer, or V0 layer. In some embodiments, the V0 level is located below a metal 1 layer. In some embodiments, the V0 level is located between the metal 0 layer and the metal 1 layer. In some embodiments, the V0 level is located between the seventh and eighth levels. Other levels are within the scope of this disclosure.

[0410] In at least the set of 842 vias, other configurations, arrangements or numbers of vias at other levels are within the scope of this disclosure.

[0411] In some embodiments, at least one of the conductor set 840, conductor set 850, or via set 842 is part of at least one of unit 802 or unit 803.

[0412] In some embodiments, unit 802 includes a feed perforation 391.

[0413] In some embodiments, feed through-hole 391 is referred to as FTV-O unit, and feed through-hole 391 is configured to receive an output signal from a clock unit (e.g., unit 803).

[0414] In some embodiments, feed through-hole 391 is referred to as FTV-I unit, and feed through-hole 391 is configured to output an input signal to a clock unit (e.g., unit 803).

[0415] In some embodiments, the feed through-hole 391 is configured to send one or more signals to the unit 803.

[0416] In some embodiments, the feed through-hole 391 is configured to receive one or more signals from unit 803.

[0417] In some embodiments, the feed through-hole 391 is configured to send one or more clock signals to the unit 803, such as at least one of the clock signals CLK or CLK3 in FIG1, or at least one of the inverted clock signals CLK2 in FIG1.

[0418] In some embodiments, the feed through-hole 391 is configured to receive one or more clock signals from unit 803, such as at least one of clock signals CLK or CLK3 in FIG. 1, or at least one of the inverted clock signals CLK2 in FIG. 1.

[0419] In some embodiments, the sets of conductors 840 and 850 and the set of vias 842 are configured to provide an electrical connection between the feed via 391 and the cell 803. In some embodiments, by electrically connecting the feed via 391 and the cell 803 together, the feed via 391 is configured to send / receive output signals to the cell 803 while being located outside the cell 803 and therefore not occupying internal area of ​​the cell 803.

[0420] In some embodiments, by electrically connecting the feed via 391 and the unit 803 together, the feed via 391 is configured to send / receive an output signal to / from the unit 803 while reducing the resistance and / or capacitance of the feed via, thereby reducing the resistance and / or capacitance of the clock tree by using backside wiring compared to other methods.

[0421] In some embodiments, by reducing the resistance and / or capacitance of the clock tree (e.g., integrated circuit 800), the integrated circuit 800 has a smaller clock cell delay than other methods, thereby improving the performance of the clock cells and / or clock tree of the integrated circuit 800 compared to other methods.

[0422] Other configurations in the integrated circuit 800, arrangements at other levels, or other numbers of elements are also within the scope of this disclosure.

[0423] Figure 9A is a top view of integrated circuit 900, according to some embodiments.

[0424] Figure 9B is a top view of a portion 900B of an integrated circuit 900, according to some embodiments.

[0425] The integrated circuit 900 includes one or more features of the OD level, POLY level, MD level, BMO level, FTC level and VDR level.

[0426] Part 900B includes one or more features of the OD level and MD level of the integrated circuit 900.

[0427] In some embodiments, integrated circuit 900 is an embodiment of at least one of integrated circuit 200A or 200B, and therefore a similar detailed description is omitted.

[0428] Integrated circuit 900 is a variant of integrated circuit 800 (Figures 8A-8B). Compared with integrated circuit 800 of Figures 8A-8B, the contact set 406 of integrated circuit 900 replaces the contact sets 306 and 806, therefore a similar detailed description is omitted.

[0429] Compared to the integrated circuit 800 in Figures 8A-8B, the integrated circuit 900 does not include the conductor 840 set, the via 842 set, and the conductor 850 set, therefore a similar detailed description is omitted.

[0430] Compared to the integrated circuit 800 in Figures 8A-8B, the feed via 491 of the integrated circuit 900 replaces the feed via 391 in Figures 8A-8B, therefore a similar detailed description is omitted.

[0431] The integrated circuit 900 includes unit 902 and unit 903.

[0432] In some embodiments, unit 902 is an embodiment of at least one of units 204a or 206a, and therefore a similar detailed description is omitted.

[0433] In some embodiments, unit 902 is the integrated circuit 400 of FIG4, therefore a similar detailed description is omitted.

[0434] In some embodiments, unit 903 is similar to unit 803 of FIG8A, therefore a similar detailed description is omitted.

[0435] In some embodiments, unit 903 is an embodiment of unit 202a, and therefore a similar detailed description is omitted. In some embodiments, unit 903 is an embodiment of one or more buffer circuits, such as integrated circuit 700A of FIG. 7A, or an embodiment of one or more inverters, such as integrated circuit 700B of FIG. 7B, and therefore a similar detailed description is omitted.

[0436] Units 902 and 903 are adjacent to each other along unit boundary 201a.

[0437] Unit 903 includes active area assembly 802, insulation area 303, gate assembly 804, and well assembly 805.

[0438] Unit 902 includes active area assembly 302, insulation area 303, gate assembly 304, contact assembly 406, well assembly 305, conductor assembly 320, conductor assembly 322 and conductor assembly 330.

[0439] In some embodiments, contact assembly 406, conductor assembly 320, and conductor assembly 322 are part of feed through-hole 491.

[0440] The contact assembly 406 includes at least contact 406a or 406b.

[0441] Contact element set 406 overlaps with active regions 302b, 802a, and 802b. Contact elements 406a and 406b of contact element set 406 overlap with active regions 302b, 802a, and 802b.

[0442] In some embodiments, contacts 406a and 406b of contact assembly 406 are electrically coupled to at least one of active regions 302b, 802a, or 802b. In some embodiments, feed through-hole 491 is configured to receive an output signal from at least one of active regions 802a or 802b via contacts 406a and 406b.

[0443] In some embodiments, the contact set 406 overlaps with the cell boundary 201a into the cell 903. In some embodiments, by overlapping with the cell boundary 201a into the cell 903, the contact set 406 is configured to receive output signals from the cell 903 and is referred to as a set of metal diffused local interconnects (MD-LIs).

[0444] In some embodiments, contacts 406a and 406b of contact set 406 overlap with cell boundary 201a into cell 903. In some embodiments, by overlapping with cell boundary 201a into cell 903, contacts 406a and 406b of contact set 406 are configured to receive one or more output signals from cell 903 and are referred to as a set of metal diffused local interconnects (MD-LIs).

[0445] In some embodiments, the contact assembly 406 overlaps with another unit boundary (unmarked) onto another adjacent unit.

[0446] Other configurations, arrangements at other levels, or other numbers of patterns in contact set 406 are also included within the scope of this disclosure.

[0447] Other configurations, arrangements at other levels, or other numbers of elements in at least one of units 802 or 803 are also included in the scope of this disclosure.

[0448] In some embodiments, unit 902 includes a feed perforation 491.

[0449] In some embodiments, feed via 491 is referred to as FTV-O unit, and feed via 491 is configured to receive output signals from other clock units, such as unit 903.

[0450] In some embodiments, feed through-hole 491 is configured to receive one or more signals from adjacent cells, such as cell 903.

[0451] In some embodiments, the feed through-hole 491 is configured to receive one or more signals from unit 903.

[0452] In some embodiments, the feed through-hole 491 is configured to receive one or more clock signals, such as at least one of the clock signals CLK or CLK3 in FIG. 1, or at least one of the inverted clock signals CLK2 in FIG. 1, which originate from unit 903.

[0453] In some embodiments, contact assembly 406 is configured to provide an electrical connection between the unit and the feed through-hole 491 and the unit 903. In some embodiments, by electrically connecting the feed through-hole 491 and the unit 903 together, the feed through-hole 491 is configured to receive an output signal from the unit 903, while being located outside the unit 903, thus not occupying area within the unit 903.

[0454] In some embodiments, by electrically connecting feed via 491 and unit 903 together, feed via 491 is configured to receive an output signal from unit 903 while reducing the resistance and / or capacitance of the feed via, thereby reducing the resistance and / or capacitance of the clock tree by using backside wiring compared to other methods.

[0455] In some embodiments, by reducing the resistance and / or capacitance of the clock tree (e.g., integrated circuit 900), the integrated circuit 900 has less clock cell delay than other methods, thereby improving the performance of the clock cells and / or clock tree of the integrated circuit 900 compared to other methods.

[0456] Other configurations in the integrated circuit 900, arrangements at other levels, or other numbers of elements are also within the scope of this disclosure.

[0457] Figure 10A is a top view of the integrated circuit 1000, according to some embodiments.

[0458] Figure 10B is a top view of a portion 1000B of the integrated circuit 1000, according to some embodiments.

[0459] The integrated circuit 1000 includes one or more features of the OD level, POLY level, MD level, BMO level, FTC level and VDR level.

[0460] Part 1000B includes one or more features of the OD level and POLY level of the integrated circuit 1000.

[0461] In some embodiments, integrated circuit 1000 is an embodiment of at least one of integrated circuit 200A or 200B, and similar detailed descriptions are omitted here.

[0462] Integrated circuit 1000 is a variant of integrated circuit 800 (Figures 8A-8B). Compared with integrated circuit 800 of Figures 8A-8B, gate set 604 of integrated circuit 1000 replaces gate sets 304 and 804, so similar detailed descriptions are omitted here.

[0463] Compared to the integrated circuit 800 in Figures 8A-8B, the integrated circuit 1000 does not include the conductor assembly 840, the via assembly 842, and the conductor assembly 850; therefore, similar detailed descriptions are omitted here.

[0464] Compared to the integrated circuit 800 in Figures 8A-8B, the feed via 691 of the integrated circuit 1000 replaces the feed via 391 in Figures 8A-8B, so a similar detailed description is omitted here.

[0465] The integrated circuit 1000 includes unit 1002 and unit 1003.

[0466] In some embodiments, unit 1002 is an embodiment of at least one of units 204a or 206a, and similar detailed descriptions are omitted here.

[0467] In some embodiments, unit 1002 is the integrated circuit 600 of Figures 6A-6C, and similar detailed descriptions are omitted here.

[0468] In some embodiments, unit 1003 is similar to unit 803 of FIG8A, and similar detailed descriptions are omitted here.

[0469] In some embodiments, unit 1003 is an embodiment of unit 202a, and similar detailed descriptions are omitted here. In some embodiments, unit 1003 is an embodiment of one or more buffer circuits, such as integrated circuit 700A of FIG. 7A, or an embodiment of one or more inverters, such as integrated circuit 700B of FIG. 7B, and similar detailed descriptions are omitted here.

[0470] Units 1002 and 1003 are adjacent to each other along unit boundary 201a.

[0471] Unit 1003 includes an active area assembly 802, an insulating area 303, gates 804a and 804b, a contact assembly 806, and a well assembly 805.

[0472] Unit 1002 includes active area assembly 302, insulation area 303, gate assembly 604, contact assembly 306, well assembly 305, conductor assembly 320, conductor assembly 322 and conductor assembly 330.

[0473] In some embodiments, contact assembly 306, conductor assembly 320, and conductor assembly 322 are part of feed through-hole 691.

[0474] The gate set 604 includes at least one of gates 304a, 604b, 604c, 604d or 304e.

[0475] In some embodiments, at least one of gates 604b, 604c, or 604d overlaps with at least one of active regions 302b, 802a, or 802b.

[0476] In some embodiments, the feed via 691 is electrically coupled to one or more transistors in unit 1003 through at least one of gates 604b, 604c, or 604d.

[0477] In some embodiments, the gate set 604 extends across cell boundary 201a into cell 1003. In some embodiments, by extending across cell boundary 201a into cell 1003, the gate set 604 is configured to receive an output signal from feed via 691 and is configured to output the output signal to cell 1003, and is referred to as a polysilicon local interconnect set (POLY-LIs).

[0478] In some embodiments, gates 604b, 604c, and 604d of gate set 604 extend across cell boundary 201a into cell 1003. In some embodiments, by extending across cell boundary 201a or 301b into cell 1003, gates 604b, 604c, and 604d of gate set 604 are configured to receive one or more output signals from feed via 691 and are configured to output the output signals to cell 1003, and are referred to as polysilicon local interconnect set.

[0479] In some embodiments, the gate assembly 604 extends across another cell boundary (unmarked) to another adjacent cell.

[0480] Other configurations in gate set 604, other arrangements at other levels, or other numbers of gates also fall within the scope of this disclosure.

[0481] Other configurations of at least one of units 802 or 803, other arrangements at other levels, or other numbers of elements are also within the scope of this disclosure.

[0482] In some embodiments, unit 1002 includes a feed perforation 691.

[0483] In some embodiments, feed through-hole 691 is referred to as FTV-I unit, and feed through-hole 691 is configured to send / output input signals to other clock units (e.g., unit 1003).

[0484] In some embodiments, the feed through-hole 691 is configured to send one or more signals to an adjacent cell (e.g., cell 1003).

[0485] In some embodiments, feed through-hole 691 is configured to send one or more signals to unit 1003.

[0486] In some embodiments, the feed through-hole 691 is configured to send one or more clock signals to the unit 1003, such as at least one of the clock signals CLK or CLK3 of FIG. 1, or at least one of the inverted clock signals CLK2 of FIG. 1.

[0487] In some embodiments, gate assembly 604 is configured to provide an electrical connection from a cell to a feed via, the connection being located between feed via 691 and cell 1003. In some embodiments, by electrically connecting feed via 691 and cell 1003 together, feed via 691 is configured to output an input signal to cell 1003, while being located outside cell 1003 and thus not occupying area within cell 1003.

[0488] In some embodiments, by electrically connecting the feed via 691 and the unit 1003 together, the feed via 691 is configured to output an input signal to the unit 1003, while reducing the resistance and / or capacitance of the feed via, thereby reducing the resistance and / or capacitance of the clock tree by using backside wiring compared to other methods.

[0489] In some embodiments, by reducing the resistance and / or capacitance of the clock tree (e.g., integrated circuit 1000), the integrated circuit 1000 has less clock cell delay than other methods, thereby improving the performance of the clock cells and / or clock tree of the integrated circuit 1000 compared to other methods.

[0490] Other configurations in the integrated circuit 1000, arrangements at other levels, or other numbers of elements are also within the scope of this disclosure.

[0491] Figure 11A is a top view of a portion 1100A of integrated circuit 1100, according to some embodiments.

[0492] Figure 11B is a top view of a portion of integrated circuit 1100B, according to some embodiments.

[0493] Figure 11C is a top view of a portion of integrated circuit 1100C, according to some embodiments.

[0494] The integrated circuit 1100 includes one or more features of the OD level, POLY level, MD level, BMO level, FTC level, VDR level, M0 level, V0 level and M1 level.

[0495] Part 1100A includes one or more features of the MD level, V0 level and M1 level of the integrated circuit 1100.

[0496] Part 1100B includes one or more features of the MD level, M0 level, V0 level and M1 level of the integrated circuit 1100.

[0497] Part 1100C includes one or more features of the POLY level and MD level of the integrated circuit 1100.

[0498] In some embodiments, integrated circuit 1100 is a part of at least one of integrated circuit 200G or 200H, and similar detailed descriptions are omitted.

[0499] In some embodiments, the integrated circuit 1100 is an example of a plurality of FTV cells (e.g., FTV cell sets 1191 and 1192) along cell boundaries 201a and 201b.

[0500] Integrated circuit 1100 is a variation of integrated circuit 800 (Figures 8A-8B). Compared to integrated circuit 800 in Figures 8A-8B, the feed via sets 1191 and 1192 of integrated circuit 1100 replace feed via 391, therefore a similar detailed description is omitted.

[0501] In some embodiments, each feed via in the feed via set 1191 or 1192 of the integrated circuit 1100 is similar to feed via 391 in Figures 8A-8B, and therefore a similar detailed description is omitted.

[0502] The integrated circuit 1100 includes cell set 1102, cell set 1104 and cell set 1106.

[0503] In some embodiments, unit 1102 is similar to unit 803 of Figures 8A-8C, and similar detailed descriptions are omitted.

[0504] Element 1102 and element set 1104 are adjacent to each other along element boundary 201a.

[0505] Element 1102 and element set 1106 are adjacent to each other along element boundary 201b.

[0506] Unit sets 1104 and 1106 have a height H3 in the Y direction. In some embodiments, at least one of unit sets 1104 or 1106 is a single-height unit.

[0507] Unit 1102 has a height H4 in the Y direction. In some embodiments, unit 1102 is a dual-height unit.

[0508] In some embodiments, the width of unit sets 1104 and 1104 in the X direction is greater than the width of unit 1102 in the X direction.

[0509] The set of elements 1104 includes one or more elements 1104a, 1104b, ..., 1104d or 1104e.

[0510] In some embodiments, each unit 1104a, 1104b, ..., 1104d or 1104e in the unit set 1104 is similar to unit 802 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0511] In some embodiments, each cell 1104a, 1104b, ..., 1104d or 1104e in cell set 1104 is an alternating sequence of feed via-O and feed via-I cells similar to cells 204a or 206a in Figures 2A-2B, and similar detailed descriptions are omitted.

[0512] In some embodiments, each unit 1104a, 1104b, ..., 1104d or 1104e in the unit set 1104 includes a corresponding feed via 1191a, 1191b, ..., 1191d or 1191e in the feed via set 1191, which is similar to feed via 591 in Figures 5A-5C, and similar detailed descriptions are omitted.

[0513] In some embodiments, each feed through hole 1191a, 1191b, ..., 1191d or 1191e in the feed through hole set 1191 includes a corresponding contact 1116a, 1116b, ..., 1116d or 1116e in the contact set 1116, which is similar to contact 506a in the contact set 506 in FIG. 5, and similar detailed descriptions are omitted.

[0514] The set of elements 1106 includes one or more elements 1106a, 1106b, ..., 1106d or 1106e.

[0515] In some embodiments, each of the units 1106a, 1106b, ..., 1106d or 1106e in the unit set 1106 is similar to unit 802 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0516] In some embodiments, each cell 1106a, 1106b, ..., 1106d or 1106e in cell set 1106 is an alternating sequence of feed via-O and feed via-I cells similar to cells 204a or 206a in Figures 2A-2B, and similar detailed descriptions are omitted.

[0517] In some embodiments, each unit 1106a, 1106b, ..., 1106d or 1106e in the unit set 1106 includes a corresponding feed via 1192a, 1192b, ..., 1192d or 1192e in the feed via set 1192, which is similar to feed via 591 in Figures 5A-5C, and similar detailed descriptions are omitted.

[0518] In some embodiments, each feed through hole 1192a, 1192b, ..., 1192d or 1192e in the feed through hole set 1192 includes a corresponding contact 1118a, 1118b, ..., 1118d or 1118e in the contact set 1118, which is similar to contact 506a in the contact set 506 in FIG. 5, and similar detailed descriptions are omitted.

[0519] The integrated circuit 1100 also includes conductor sets 1140, conductor sets 1150 and conductor sets 1152.

[0520] In some embodiments, conductor set 1140 is similar to conductor set 840 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0521] In some embodiments, at least one of the conductor sets 1150 or 1152 is similar to conductor set 850 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0522] The conductor set 1140 includes one or more conductors 1140a or 1140b.

[0523] In some embodiments, each conductor 1140a or 1140b in conductor set 1140 is similar to the corresponding conductor 840a or 840b in conductor set 840 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0524] The conductor assembly 1150 includes one or more conductors 1150a or 1150b.

[0525] In some embodiments, each conductor 1150a or 1150b in conductor set 1150 is similar to the corresponding conductor 850a or 850b in conductor set 850 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0526] In some embodiments, each conductor 1152a or 1152b in conductor set 1152 is similar to the corresponding conductor 850a or 850b in conductor set 850 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0527] In a non-limiting example, Equations 1-4 are applied to integrated circuit 1100. For example, integrated circuit 1100 includes 4 M1 fingers and 2 M0 fingers, and a CPP count equal to 26 CPPs. Furthermore, in this non-limiting example, the height H4 is equal to 2 because cell 1102 is a double-height cell.

[0528] In some embodiments, applying Formula 1 yields a ratio R1 equal to 4 / 26, or 15.3%. In some embodiments, when the ratio R1 is 15.3%, the ratio R1 is between 10% and 35%, thus satisfying Formula 2.

[0529] In some embodiments, applying Formula 3 yields a ratio R2 equal to 2 / 2, which is 1. In some embodiments, when the ratio R2 is 1, then the ratio R2 equals 1, thus satisfying Formula 4.

[0530] In some embodiments, the integrated circuit 1100 is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0531] Other configurations in the integrated circuit 1100, arrangements at other levels, or other numbers of elements are also within the scope of this disclosure.

[0532] Figure 12A is a top view of a portion 1200A of the integrated circuit 1200, according to some embodiments.

[0533] Figure 12B is a top view of a portion 1200B of the integrated circuit 1200, according to some embodiments.

[0534] Figure 12C is a top view of a portion 1200C of the integrated circuit 1200, according to some embodiments.

[0535] The integrated circuit 1200 includes one or more features of the OD level, POLY level, MD level, BMO level, FTC level, VDR level, M0 level, V0 level and M1 level.

[0536] Part 1200A includes one or more features of the MD level, V0 level and M1 level of the integrated circuit 1200.

[0537] Part 1200B includes one or more features of the MD level, M0 level, V0 level and M1 level of the integrated circuit 1200.

[0538] Part 1200C includes one or more features of the POLY level, MD level and VDR level of integrated circuit 1200.

[0539] In some embodiments, integrated circuit 1200 is a portion of at least one of integrated circuits 200G or 200H, and similar detailed descriptions are omitted.

[0540] In some embodiments, the integrated circuit 1200 is an example of an FTV cell (e.g., FTV cells 1291 and 1292) along cell boundaries 201a and 201b.

[0541] Integrated circuit 1200 is a variation of integrated circuit 800 (Figures 8A-8B). Compared to integrated circuit 800 in Figures 8A-8B, feed vias 1291 and 1292 of integrated circuit 1200 replace feed via 391, therefore a similar detailed description is omitted.

[0542] In some embodiments, each feed via in the set of feed vias 1291 or 1292 of the integrated circuit 1200 is similar to feed via 391 in Figures 8A-8B, so similar detailed descriptions are omitted.

[0543] The integrated circuit 1200 includes cell set 1202, cell set 1204 and cell set 1206.

[0544] In some embodiments, unit 1202 is similar to unit 803 of Figures 8A-8C, and similar detailed descriptions are omitted.

[0545] Sets of units 1202 and 1204 are adjacent to each other along unit boundary 201a.

[0546] Sets of cells 1202 and 1206 are adjacent to each other along cell boundary 201b.

[0547] The sets of units 1204 and 1206 have a height H5 in the Y direction. In some embodiments, at least one of the sets of units 1204 or 1206 is a dual-height unit.

[0548] Unit 1202 has a height H4 in the Y direction. In some embodiments, unit 1202 is a dual-height unit.

[0549] In some embodiments, the width of the set of units 1204 and 1206 in the X direction is equal to the width of unit 1202 in the X direction.

[0550] The set of units 1204 includes one or more units 1204a.

[0551] In some embodiments, each unit 1204a in the set of units 1204 is similar to unit 802 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0552] In some embodiments, each unit 1204a in the set of units 1204 includes a corresponding feed through 1291a in the set of feed through 1291, which is similar to feed through 391 in Figures 3A-3C, and similar detailed descriptions are omitted.

[0553] In some embodiments, each feed hole 1291a in the feed hole set 1291 includes a corresponding contact 1216a, 1216b, ..., 1216f or 1216g in the contact set 1216, which is similar to the contacts 306a and 306b in the contact set 306 in FIG. 5, and similar detailed descriptions are omitted.

[0554] The unit set 1206 includes one or more units 1206a.

[0555] In some embodiments, each unit 1206a in the unit set 1206 is similar to unit 802 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0556] In some embodiments, each unit 1206a in the unit set 1206 includes a corresponding feed through 1292a in the feed through 1292 set, which is similar to feed through 391 in Figures 3A-3C, and similar detailed descriptions are omitted.

[0557] In some embodiments, each feed hole 1292a in the feed hole set 1292 includes a corresponding contact 1218a, 1218b, ..., 1218f or 1218g in the contact set 1218, which is similar to the contacts 306a and 306b of the contact set 306 in Figures 3A-3C, and similar detailed descriptions are omitted.

[0558] The integrated circuit 1200 also includes conductor assembly 1240 and conductor assembly 1250.

[0559] In some embodiments, conductor set 1240 is similar to conductor set 840 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0560] In some embodiments, conductor set 1250 is similar to conductor set 850 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0561] The conductor set 1240 includes one or more conductors 1240a or 1240b.

[0562] In some embodiments, each conductor 1240a or 1240b in conductor set 1240 is similar to the corresponding conductor 840a or 840b in conductor set 840 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0563] The conductor assembly 1250 includes one or more conductors 1250a or 1250b.

[0564] In some embodiments, each conductor 1250a or 1250b in conductor set 1250 is similar to the corresponding conductor 850a or 850b in conductor set 850 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0565] In a non-limiting example, Equations 1-4 are applied to integrated circuit 1200. For example, integrated circuit 1200 includes 2 M1 fingers and 2 M0 fingers, and a number of CPPs equal to 9. Furthermore, in this non-limiting example, the height H4 is equal to 2 because cell 1202 is a double-height cell.

[0566] In some embodiments, applying Formula 1 yields a ratio R1 equal to 2 / 9, or 22.2%. In some embodiments, when the ratio R1 is 22.2%, the ratio R1 is between 10% and 35%, thus satisfying Formula 2.

[0567] In some embodiments, applying Formula 3 yields a ratio R2 equal to 2 / 2, which is 1. In some embodiments, when the ratio R2 is 1, the ratio R2 equals 1, thus satisfying Formula 4.

[0568] In some embodiments, the integrated circuit 1200 is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0569] Other configurations in the integrated circuit 1200, arrangements at other levels, or the number of components are all within the scope of this disclosure.

[0570] Figure 13A is a top view of a portion 1300A of the integrated circuit 1300, according to some embodiments.

[0571] Figure 13B is a top view of a portion 1300B of the integrated circuit 1300, according to some embodiments.

[0572] Figure 13C is a top view of a portion 1300C of the integrated circuit 1300, according to some embodiments.

[0573] The integrated circuit 1300 includes one or more features of the OD level, POLY level, MD level, BMO level, FTC level, VDR level, M0 level, V0 level and M1 level.

[0574] Part 1300A includes one or more features of the MD level, V0 level and M1 level of the integrated circuit 1300.

[0575] Part 1300B includes one or more features of the MD level, M0 level, V0 level and M1 level of the integrated circuit 1300.

[0576] Part 1300C includes one or more features of the POLY level, MD level and VDR level of integrated circuit 1300.

[0577] In some embodiments, integrated circuit 1300 is an embodiment of at least one of integrated circuit 200G or 200H, and similar detailed descriptions are omitted here.

[0578] In some embodiments, the integrated circuit 1300 is an example of a feed via cell (e.g., feed via cell 1391) along cell boundary 201a.

[0579] Integrated circuit 1300 is a variant of integrated circuit 800 (Figures 8A-8B). Compared with integrated circuit 800 in Figures 8A-8B, integrated circuit 1300 replaces feed via 391 with feed via 1391, therefore a similar detailed description is omitted.

[0580] In some embodiments, each feed via in the feed via set 1391 of the integrated circuit 1300 is similar to feed via 391 in Figures 8A-8B, so a similar detailed description is omitted.

[0581] The integrated circuit 1300 includes a unit 1302 and a unit set 1304.

[0582] In some embodiments, unit 1302 is similar to unit 803 of Figures 8A-8C, and similar detailed descriptions are omitted.

[0583] Element 1302 and element set 1304 are adjacent to each other along element boundary 201a.

[0584] The unit set 1304 has a height H5 in the Y direction. In some embodiments, at least one unit in the unit set 1304 is a double-height unit.

[0585] Unit 1302 has a height H4 in the Y direction. In some embodiments, unit 1302 is a dual-height unit.

[0586] In some embodiments, the width of the unit set 1304 in the X direction is smaller than the width of the unit 1302 in the X direction.

[0587] The unit set 1304 includes one or more units 1304a.

[0588] In some embodiments, each unit 1304a in the unit set 1304 is similar to unit 802 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0589] In some embodiments, each unit 1304a in the unit set 1304 includes a corresponding feed through 1391a, which belongs to the feed through set 1391, similar to the feed through 391 in Figures 3A-3C, and similar detailed descriptions are omitted.

[0590] In some embodiments, the feed through hole 1391a in the feed through hole set 1391 includes contacts 1316a, 1316b, ..., 1316y, 1316z or 1316za in the contact set 1316, similar to contacts 306a and 306b in the contact set 306 in FIG. 5, and similar detailed descriptions are omitted.

[0591] The integrated circuit 1300 also includes conductor assembly 1340 and conductor assembly 1350.

[0592] In some embodiments, conductor set 1340 is similar to conductor set 840 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0593] In some embodiments, conductor assembly 1350 is similar to conductor assembly 850 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0594] The conductor set 1340 includes one or more conductors 1340a or 1340b.

[0595] In some embodiments, each conductor 1340a or 1340b in conductor set 1340 is similar to the corresponding conductor 840a or 840b in conductor set 840 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0596] The conductor assembly 1350 includes one or more conductors 1350a, 1350b, 1350c, or 1350d.

[0597] In some embodiments, each conductor 1350a, 1350b, 1350c or 1350d in conductor set 1350 is similar to one or more conductors 850a or 850b in conductor set 850 in Figures 8A-8C, and similar detailed descriptions are omitted.

[0598] In a non-limiting example, Equations 1-4 are applied to integrated circuit 1300. For example, integrated circuit 1300 includes 4 M1 fingers and 2 M0 fingers, and a CPP quantity equal to 29 CPPs. Furthermore, in this non-limiting example, the height H4 is equal to 2 because cell 1302 is a double-height cell.

[0599] In some embodiments, applying Formula 1 yields a ratio R1 equal to 4 / 29, or 13.7%. In some embodiments, when the ratio R1 is 13.7%, the ratio R1 is between 10% and 35%, thus satisfying Formula 2.

[0600] In some embodiments, applying Formula 3, the ratio R2 equals 2 / 2, which is 1. In some embodiments, when the ratio R2 is 1, the ratio R2 equals 1, thus satisfying Formula 4.

[0601] In some embodiments, the integrated circuit 1300 is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0602] Other configurations, arrangements at other levels, or other quantities of components in the integrated circuit 1300 also fall within the scope of this disclosure.

[0603] Figures 14A-14B are functional flowcharts of a method 1400 for manufacturing an IC device according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1400 depicted in Figures 14A-14B, and some other processes may only be briefly described herein.

[0604] In some embodiments, the order of other operations of methods 1400-1600 is within the scope of this disclosure. Methods 1400-1600 include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or removed according to the spirit and scope of the disclosed embodiments. In some embodiments, at least one or more operations of methods 1400, 1500, or 1600 are not performed.

[0605] In some embodiments, method 1400 is an embodiment of operation 804 of method 800. In some embodiments, methods 1400-1600 can be used to manufacture or produce at least integrated circuits 100, 200A-200H, 300, 400, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200 or 1300.

[0606] In operation 1402 of method 1400, a first transistor assembly is manufactured in the front side 303a of a semiconductor wafer or substrate 390 in at least the first unit region.

[0607] In some embodiments, the first unit region of method 1400 includes at least one unit selected from units 202a, 803, 903, 1003, 1102, 1202, or 1302.

[0608] In some embodiments, the first transistor set of method 1400 includes one or more transistors in at least the active region set 802. In some embodiments, the first transistor set of method 1400 includes one or more transistors as described herein.

[0609] In some embodiments, the first cell region extends in the first direction X and has a first cell height in the second direction Y.

[0610] In some embodiments, the first transistor set includes at least one of a set of buffer circuits B1, B2, B3, B4 or B5 of a clock circuit, or at least one of a set of inverters I1, I2 or I3 of a clock circuit.

[0611] In some embodiments, the height of the first unit includes at least one of heights H1 or H4.

[0612] In some embodiments, operation 1402 includes fabricating source and drain regions of the transistor assembly in a first well (e.g., wells 303 and 503). In some embodiments, the first well includes a P-type dopant. In some embodiments, the P-type dopant includes boron, aluminum, or other suitable P-type dopant. In some embodiments, the first well includes an epitaxial layer grown on a substrate. In some embodiments, the epitaxial layer is doped by adding a dopant during an epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after formation. In some embodiments, the first well is formed by doping the substrate. In some embodiments, doping is performed by ion implantation. In some embodiments, the first well has a dopant concentration ranging from 1 x 10¹² atoms / cm³ to 1 x 10¹⁴ atoms / cm³.

[0613] In some embodiments, the first well includes an N-type dopant. In some embodiments, the N-type dopant includes phosphorus, arsenic, or other suitable N-type dopant. In some embodiments, the N-type dopant concentration ranges from about 1 x 10¹² atoms / cm³ to about 1 x 10¹⁴ atoms / cm³.

[0614] In some embodiments, the formation of the source / drain feature includes removing a portion of the substrate to form a groove at the edge of the spacer, and then performing a fill process by filling the groove in the substrate. In some embodiments, the groove is etched after the removal of a pad oxide layer or a sacrificial oxide layer, such as by wet etching or dry etching. In some embodiments, the etching process is performed to remove the upper surface portion of the active region adjacent to an insulating region (e.g., an STI region). In some embodiments, the fill process is performed using an epitaxial process. In some embodiments, the groove is filled using a build process concurrent with the etching process, wherein the build rate of the build process is greater than the etch rate of the etching process. In some embodiments, the groove is filled using a combination of a build process and an etching process. For example, a layer of material is built in the groove, and then the built material is subjected to an etching process to remove a portion of the material. A subsequent build process is then performed on the etched material until the material in the groove reaches the desired thickness. In some embodiments, the build process continues until the top of the material extends beyond the top surface of the substrate. In some embodiments, the build process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by an isotropic or anisotropic etching process. The etching process selectively etches the first well, avoiding etching the gate structure and any gaps. In some embodiments, the etching process is performed using reactive ion etching, wet etching, or other suitable techniques. In some embodiments, semiconductor material is deposited in a trench to form source / drain features. In some embodiments, an epitaxial process is performed to deposit semiconductor material in the trench. In some embodiments, the epitaxial process includes selective epitaxy growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epitaxial process uses gaseous and / or liquid precursors that react with the composition of the substrate. In some embodiments, the source / drain features include epitaxially grown silicon (epi Si), silicon carbide, or silicon-germanium. The source / drain features of the integrated circuit device associated with the gate structure are either in-situ doped or undoped during the epitaxial process, and in some instances, the source / drain features are doped in subsequent processes. Subsequent doping processes include ion implantation, plasma-immersion ion implantation, gas and / or solid-state source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, the source / drain features are further subjected to an annealing process after the formation of the source / drain features and / or the subsequent doping process.

[0615] In some embodiments, operation 1402 further includes operation 1402a. In some embodiments, operation 1402a includes forming a first gate region of a first transistor assembly. In some embodiments, the first gate region of the first transistor assembly of method 1400 includes a plurality of gates 804.

[0616] In some embodiments, operation 1402 further includes operation 1402b. In some embodiments, operation 1402b includes forming a second gate region of a second transistor assembly. In some embodiments, the second gate region of the second transistor assembly of method 1400 includes a plurality of gates 304.

[0617] In some embodiments, the first and second gate regions are located between the drain region and the source region. In some embodiments, the first and second gate regions are located on a first well and a substrate. In some embodiments, fabricating the first and second gate regions of operations 1402a and 1402c includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition processes include CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, fabricating the first and second gate regions includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, fabricating the first and second gate regions includes forming a gate electrode or a dummy gate electrode. In some embodiments, fabricating the gate regions includes depositing or growing at least one dielectric layer, such as a gate dielectric. In some embodiments, the gate regions are formed using doped or undoped polysilicon. In some embodiments, the first and second gate regions include metals such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0618] In some embodiments, forming a first insulating material on the first gate structure of the first transistor assembly in operation 1402b includes performing one or more deposition processes to form one or more dielectric material layers and / or insulating material layers. In some embodiments, the one or more deposition processes for forming one or more dielectric material layers and / or insulating material layers include CVD, PECVD, ALD, or other processes suitable for depositing one or more material layers. In some embodiments, forming a first insulating material on the first gate structure of the first transistor assembly includes performing one or more deposition processes to form one or more insulating material layers. In some embodiments, the first insulating material is a dielectric material. In some embodiments, the dielectric material includes silicon dioxide, silicon oxynitride, or the like.

[0619] In some embodiments, operations 1402a and 1402b are replaced by forming one or more first gate regions of the first transistor assembly and one or more second gate regions of the second transistor assembly, removing a portion of the first gate regions of the first transistor assembly and the second gate regions of the second transistor assembly, and forming an insulating material between the first gate structure of the first transistor assembly and the second gate structure of the second transistor assembly. In some embodiments, the gate removal process is a polysilicon dicing process including one or more etching processes. In some embodiments, the gate removal process includes one or more etching processes suitable for removing a portion of the gate structure. In some embodiments, a photomask is used to specify the portion of the gate structure to be diced or removed. In some embodiments, the photomask is a hard photomask. In some embodiments, the photomask is a soft photomask. In some embodiments, etching corresponds to plasma etching, reactive ion etching, chemical etching, dry etching, wet etching, other suitable processes, any combination thereof, or the like.

[0620] In some embodiments, operation 1402 further includes a portion of fabricating a second transistor set in the second cell region. In some embodiments, the portion of fabricating the second transistor set in the second cell region includes fabricating a second active region set in the second cell region and fabricating a second gate set in the second cell region.

[0621] In some embodiments, the second transistor set of method 1400 includes one or more transistors at least in the set of active regions 302. In some embodiments, the second transistor set of method 1400 includes one or more transistors described herein.

[0622] In some embodiments, the second active region set of method 1400 includes a set of active regions 302. In some embodiments, the second gate set of method 1400 includes a set of gates 304.

[0623] In operation 1404 of method 1400, a set of feed perforations is formed in the second cell region.

[0624] In some embodiments, the second unit region of method 1400 includes at least one unit selected from units 204a, 204b, 204c, 206a, 206b, 206c, 301, 802, 902, 1002, 1104, 1106, 1204, 1206, or 1304.

[0625] In some embodiments, the feed perforation set of method 1400 includes at least one feed perforation selected from feed perforation sets 391, 491, 591, 691, 1191, 1192, 1291, 1292, or 1391.

[0626] In some embodiments, the second unit region extends in the X direction and has a second height in the Y direction. In some embodiments, the second unit height of method 1400 includes at least one of heights H2, H3, or H5.

[0627] In some embodiments, the second height is different from the first height.

[0628] In some embodiments, the second cell region is adjacent to the first cell region along the first boundary. In some embodiments, the first boundary of method 1400 includes at least one of cell boundaries 201a or 201b.

[0629] In some embodiments, the first boundary extends in the X direction.

[0630] In some embodiments, operation 1404 includes at least one of operations 1406, 1408, 1410, 1412, 1414, or 1416.

[0631] In operation 1406 of method 1400, a first conductive material is deposited on a first layer on the front side 303a of the substrate to form a first contact assembly.

[0632] In some embodiments, the first contact assembly extends at least in the X or Y direction.

[0633] In some embodiments, the first conductor set of method 1400 includes one or more portions of at least one set of contact sets 306, 406, 506, 806, 1116, 1118, 1216, 1218, or 1316.

[0634] In some embodiments, the first layer of method 1400 is a metal diffusion layer.

[0635] In operation 1408 of method 1400, the first gate assembly is fabricated on the second layer on the front side of the substrate.

[0636] In some embodiments, the first gate set of method 1400 includes at least one of gate sets 304 or 604.

[0637] In some embodiments, the first gate assembly extends in the Y direction.

[0638] In some embodiments, the second layer of method 1400 is a polycrystalline silicon layer.

[0639] In operation 1410 of method 1400, a second conductive material is deposited on the third layer of the front side 303a of the substrate to form a first via assembly.

[0640] In some embodiments, the first via set of method 1400 includes at least one or more portions of conductor set 330.

[0641] In some embodiments, the third layer of method 1400 is a vertically diffused resistance layer.

[0642] In some embodiments, the first via set extends at least in the X or Y direction, overlaps at least with the first contact set or gate set, and is electrically coupled at least to the first contact set or gate set.

[0643] In operation 1412 of method 1400, thinning is performed on the back side 303b of the wafer or substrate. In some embodiments, operation 1408 includes a thinning process performed on the back side 303b of the semiconductor wafer or substrate. In some embodiments, the thinning process includes grinding and polishing operations (such as chemical mechanical polishing (CMP)) or other suitable processes. In some embodiments, after the thinning process, a wet etching operation is performed to remove defects formed on the back side 303b of the semiconductor wafer or substrate.

[0644] In operation 1414 of method 1400, a first portion of the back side of the substrate is removed, thereby forming a first opening in the substrate.

[0645] In some embodiments, operation 1414 includes one or more etching operations. In some embodiments, the one or more etching operations of operation 1414 include a wet etching process or a dry etching process. In some embodiments, the etching process is performed using reactive ion etching, wet etching, or other suitable techniques.

[0646] In operation 1416 of method 1400, a third conductive material is deposited in a first opening in the substrate to form a first conductor assembly.

[0647] In some embodiments, the first conductor assembly extends in the X direction, is located on the fourth layer, and is electrically coupled to the first contact assembly. In some embodiments, the fourth layer is different from the first, second, and third layers.

[0648] In some embodiments, the fourth layer of method 1400 is a feed-through (FTV) layer.

[0649] In some embodiments, the first conductor set of method 1400 includes one or more conductors from conductor set 322.

[0650] In operation 1418 of method 1400, a fourth conductive material is deposited on the back side of the substrate on the first metal layer to form a second conductor assembly.

[0651] In some embodiments, the back side of the substrate faces the front side of the substrate. In some embodiments, the second conductor assembly extends in the X direction and is electrically coupled to the first conductor assembly.

[0652] In some embodiments, the first metal layer of method 1400 is a BMO layer.

[0653] In some embodiments, the second conductor set of method 1400 includes one or more conductors from conductor set 320.

[0654] In operation 1420 of method 1400, a fifth conductive material is deposited on the front side of the substrate on the second metal layer to form a third conductor assembly.

[0655] In some embodiments, the third conductor assembly extends in the X direction and is electrically coupled to the first via assembly.

[0656] In some embodiments, the second metal layer of method 1400 is an M0 layer.

[0657] In some embodiments, the third conductor set of method 1400 includes one or more conductors from conductor sets 840, 1140, 1240, or 1340.

[0658] In operation 1422 of method 1400, a second via set is formed on top of the third conductor set.

[0659] In some embodiments, the second via assembly is electrically coupled to the third conductor assembly.

[0660] In some embodiments, the second via set is located in the V0 layer.

[0661] In some embodiments, the second via set of method 1400 includes at least one or more portions of via set 842.

[0662] In some embodiments, operation 1420 includes forming a first set of self-aligned contacts (SACs) in an insulating layer above the wafer front side 303a.

[0663] In operation 1424 of method 1400, a sixth conductive material is deposited on the front side of the substrate on the third metal layer to form a fourth conductor assembly.

[0664] In some embodiments, the fourth conductor set extends in the Y direction, overlaps with the third conductor set, and is electrically coupled to the third conductor set through the first via set.

[0665] In some embodiments, the third metal layer of method 1400 is layer M1.

[0666] In some embodiments, the fourth conductor set of method 1400 includes one or more conductors from conductor sets 850, 1150, 1152, 1250, or 1350.

[0667] In some embodiments, one or more of operations 1402, 1404, 1406, 1410, 1414, 1416, 1418, 1420, 1422, or 1424 of method 1400 include using a combination of photolithography and material removal processes to form an opening in an insulating layer (not shown) above a substrate. In some embodiments, the photolithography process includes patterning a photoresist, such as a positive or negative photoresist. In some embodiments, the photolithography process includes forming a rigid mask, an anti-reflective structure, or another suitable photolithography structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, a reactive ion etching (RIE) process, laser drilling, or other suitable etching process. The opening is then filled with a conductive material, such as copper, aluminum, titanium, nickel, tungsten, or other suitable conductive material. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other suitable forming processes are used to fill the openings.

[0668] In some embodiments, at least one or more operations of method 1400 are performed by system 1800 of Figure 18. In some embodiments, at least one method (e.g., method 1400 described above) is performed, either entirely or partially, by at least one manufacturing system (including system 1800). One or more operations of method 1400 are performed by integrated circuit manufacturing plant 1840 of Figure 18 to manufacture integrated circuit device 1860. In some embodiments, one or more operations of method 1400 are performed by manufacturing tool 1852 to manufacture wafer 1842.

[0669] In some embodiments, the conductive material includes copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, the openings and trenches are filled using chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other suitable formation processes. In some embodiments, after depositing the conductive material in one or more of operations 1402, 1406, 1410, 1416, 1418, 1420, 1422, or 1424, the conductive material is planarized to provide a flat surface for subsequent steps.

[0670] In some embodiments, one or more operations of methods 1400, 1500, or 1600 are not performed.

[0671] One or more operations of methods 1500-1600 are performed by a processing means configured to execute instructions for manufacturing an integrated circuit, such as at least integrated circuits 100, 200A-200H, 300, 400, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, or 1300. In some embodiments, one or more operations of methods 1500-1600 are performed using the same processing means as those used in one or more different operations of methods 1500-1600. In some embodiments, the processing means for performing one or more operations of methods 1500-1600 is different from the processing means for performing one or more different operations of methods 1500-1600. In some embodiments, the order of other operations of methods 1400, 1500, or 1600 is within the scope of this disclosure. Methods 1400, 1500, or 1600 include exemplary operations, but the operations are not necessarily performed in the order shown. In accordance with the spirit and scope of the disclosed embodiments, operations in methods 1400, 1500 or 1600 may be appropriately added, replaced, altered in order and / or eliminated.

[0672] Figure 15 is a flowchart of a method 1500 for forming or manufacturing an integrated circuit according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1500 illustrated in Figure 15, and some other operations may only be briefly described herein. In some embodiments, method 1500 may be used to form an integrated circuit, such as at least integrated circuits 100, 200A-200H, 300, 400, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, or 1300.

[0673] In operation 1502 of method 1500, a layout design for the integrated circuit is generated. Operation 1502 is performed by a processing device (e.g., processor 1702 (FIG. 17)) configured to execute instructions for generating the layout design. In some embodiments, the layout design of method 1500 includes one or more patterns resembling one or more features of at least integrated circuits 100, 200A-200H, 300, 400, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, or 1300. In some embodiments, the layout design of this application is in a Graphical Database System (GDSII) file format. In some embodiments, operation 1502 corresponds to method 1600 of FIG. 16.

[0674] In operation 1504 of method 1500, an integrated circuit is manufactured based on a layout design. In some embodiments, operation 1504 of method 1500 includes manufacturing at least one photomask based on a layout design and manufacturing an integrated circuit based on the at least one photomask. In some embodiments, operation 1504 corresponds to method 1400 of Figures 14A-14B.

[0675] Figure 16 is a flowchart of a method 1600 for generating an integrated circuit layout design according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1600 illustrated in Figure 16, and some other processes may only be briefly described herein. In some embodiments, method 1600 is an embodiment of operation 1502 of method 1500. In some embodiments, method 1600 can be used to generate one or more layout patterns or features similar to at least integrated circuits 100, 200A-200H, 300, 400, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, or 1300.

[0676] In some embodiments, method 1600 can be used to generate one or more layout patterns having structural relationships, including alignment, length and width, and configuration and layers similar to one or more features of at least integrated circuits 100, 200A-200H, 300, 400, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200 or 1300, and for the sake of brevity, similar detailed descriptions will not be described in FIG16.

[0677] In operation 1602 of method 1600, a first set of active region patterns is generated or placed in a layout design. In some embodiments, the first set of active region patterns in method 1600 includes one or more regions similar to at least one of active region groups 302 or 802. In some embodiments, the first set of active region patterns in method 1600 includes one or more patterns or similar patterns in an OD layer.

[0678] In operation 1604 of method 1600, a first set of gate patterns is generated or placed in a layout design. In some embodiments, the first set of gate patterns in method 1600 includes one or more regions similar to at least one of gate sets 304 or 804. In some embodiments, the first set of gate patterns in method 1600 includes one or more patterns or similar patterns in a POLY layer.

[0679] In operation 1606 of method 1600, a first set of contact patterns is generated or placed in a layout design. In some embodiments, the first set of contact patterns in method 1600 includes one or more patterns similar to contact sets 306, 406, 506, 806, 1116, 1118, 1216, 1218, or 1316. In some embodiments, the first set of contact patterns in method 1600 includes one or more patterns or similar patterns in an MD layer.

[0680] In operation 1608 of method 1600, a first set of conductive feature patterns is generated or placed in a layout design. In some embodiments, the first set of conductive feature patterns in method 1600 includes one or more patterns similar to conductor set 320. In some embodiments, the first set of conductive feature patterns in method 1600 includes one or more patterns or similar patterns in a BMO layer.

[0681] In operation 1610 of method 1600, a second set of conductive feature patterns is generated or placed in a layout design. In some embodiments, the second set of conductive feature patterns in method 1600 includes one or more patterns similar to conductor set 322. In some embodiments, the second set of conductive feature patterns in method 1600 includes one or more patterns or similar patterns in an FTC layer.

[0682] In operation 1612 of method 1600, a third set of conductive feature patterns is generated or placed in a layout design. In some embodiments, the third set of conductive feature patterns in method 1600 includes one or more patterns similar to conductor set 330. In some embodiments, the third set of conductive feature patterns in method 1600 includes one or more patterns or similar patterns in a VDR layer.

[0683] In some embodiments, at least one or more of operations 1606, 1610, or 1612 correspond to generating or placing a set of feed via patterns on a layout design. In some embodiments, the set of feed via patterns of method 1600 includes one or more patterns or similar conductors of MD layer, FTC layer, and VDR layer.

[0684] In operation 1614 of method 1600, a fourth set of conductive feature patterns is generated or placed in a layout design. In some embodiments, the fourth set of conductive feature patterns in method 1600 includes one or more conductive feature patterns similar to at least conductor sets 840, 1140, 1240, or 1340. In some embodiments, the fourth set of conductive feature patterns in method 1600 includes one or more patterns or similar conductors in the MO layer.

[0685] In operation 1616 of method 1600, a first via pattern set is generated or placed in a layout design. In some embodiments, the first via pattern set of method 1600 includes one or more via patterns similar to at least via set 842. In some embodiments, the first via pattern set of method 1600 includes one or more patterns or similar vias in the VO layer.

[0686] In operation 1618 of method 1600, a fifth set of conductive feature patterns is generated or placed in a layout design. In some embodiments, the fifth set of conductive feature patterns in method 1600 includes one or more conductive feature patterns similar to at least conductor sets 850, 1150, 1152, 1250, or 1350. In some embodiments, the fifth set of conductive feature patterns in method 1600 includes one or more patterns or similar conductors in layer M1.

[0687] Figure 17 is a schematic diagram of a system 1700 for designing IC layout and manufacturing IC circuits according to some embodiments.

[0688] In some embodiments, system 1700 generates or places one or more IC layout designs described herein. System 1700 includes a hardware processor 1702 and a non-transitory computer-readable storage medium 1704 (e.g., memory 1704) encoded with (i.e., stored) computer program code 1706, namely a set of executable instructions 1706. Computer-readable storage medium 1704 is configured to interface with a manufacturing machine for producing integrated circuits. Processor 1702 is electrically coupled to computer-readable storage medium 1704 via bus 1708. Processor 1702 is also electrically coupled to I / O interface 1710 via bus 1708. Network interface 1712 is also electrically connected to processor 1702 via bus 1708. Network interface 1712 is connected to network 1714, enabling processor 1702 and computer-readable storage medium 1704 to be connected to external components via network 1714. The processor 1702 is configured to execute computer program code 1706 (e.g., non-temporary instructions) encoded in computer-readable storage medium 1704, so that the system 1700 can be used to perform some or all of the operations described in methods 1500-1600.

[0689] In some embodiments, the processor 1702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0690] In some embodiments, the computer-readable storage medium 1704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1704 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disc. In some embodiments using optical discs, the computer-readable storage medium 1704 includes compact disk-read-only memory (CD-ROM), a compact disk-read / write device (CD-R / W), and / or a digital video disc (DVD).

[0691] In some embodiments, storage medium 1704 stores computer program code 1706 (also referred to as "instructions 1706") configured to cause system 1700 to execute methods 1500-1600. In some embodiments, storage medium 1704 also stores information required to execute methods 1500-1600 and information generated during the execution of methods 1500-1600, such as layout design 1716, user interface 1718, and manufacturing unit 1720, and / or a set of executable instructions for performing the operations of methods 1500-1600. In some embodiments, layout design 1716 includes one or more features similar to at least integrated circuits 100, 200A-200H, 300, 400, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, or 1300.

[0692] In some embodiments, storage medium 1704 stores instructions (e.g., computer code 1706) for interfacing with a manufacturing machine. The instructions (e.g., computer code 1706) enable processor 1702 to generate manufacturing instructions readable by the manufacturing machine to efficiently implement method 1500-1600 during the manufacturing process.

[0693] System 1700 includes an I / O interface 1710. The I / O interface 1710 is coupled to external circuitry. In some embodiments, the I / O interface 1710 includes a keyboard, keypad, mouse, trackball, touchpad, and / or cursor arrow keys for transmitting information and commands to processor 1702.

[0694] System 1700 also includes a network interface 1712 coupled to processor 1702. Network interface 1712 allows system 1700 to communicate with network 1714, to which one or more other computer systems are connected. Network interface 1712 includes wireless network interfaces such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethereum, USB, or IEEE-2094. In some embodiments, methods 1500-1600 are implemented in two or more systems 1700, and information such as layout design and user interface is exchanged between different systems 1700 via network 1714.

[0695] System 1700 is configured to receive layout design-related information via I / O interface 1710 or network interface 1712. The information is transmitted via bus 1708 to processor 1702 to determine a layout design for producing at least integrated circuits 100, 200A-200H, 300, 400, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, or 1300. The layout design is then stored as layout design 1716 in computer-readable storage medium 1704. System 1700 is also configured to receive user interface-related information via I / O interface 1710 or network interface 1712. This information is stored as user interface 1718 in computer-readable storage medium 1704. System 1700 is configured to receive information related to manufacturing unit 1720 via I / O interface 1710 or network interface 1712. The information is stored as manufacturing unit 1720 in computer-readable storage medium 1704. In some embodiments, manufacturing unit 1720 includes manufacturing information utilized by system 1700. In some embodiments, manufacturing unit 1720 corresponds to photomask fabrication 1834 of FIG. 18.

[0696] In some embodiments, methods 1500-1600 are implemented as a standalone software application executed by a processor. In some embodiments, methods 1500-1600 are implemented as a software application as part of an additional software application. In some embodiments, methods 1500-1600 are implemented as a plug-in to a software application. In some embodiments, methods 1500-1600 are implemented as a software application as part of an EDA tool. In some embodiments, methods 1500-1600 are implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer-readable medium. In some embodiments, the layout is generated using tools such as VIRTUOSO®, available from Cadence Design Systems, Inc., or another suitable layout generation tool. In some embodiments, the layout is generated based on a netlist created based on a schematic design. In some embodiments, methods 1500-1600 are implemented by a manufacturing apparatus to fabricate an integrated circuit using a set of photomasks fabricated based on one or more layout designs generated by system 1700. In some embodiments, system 1700 includes a manufacturing apparatus to fabricate an integrated circuit using a set of photomasks fabricated based on one or more layout designs disclosed herein. In some embodiments, system 1700 of FIG. 17 generates a smaller integrated circuit layout design than other methods. In some embodiments, system 1700 of FIG. 17 generates a layout design for an integrated circuit structure that occupies less area and provides better wiring resources compared to other methods.

[0697] Figure 18 is a block diagram of an integrated circuit (IC) manufacturing system 1800 and an associated IC manufacturing process, according to at least one embodiment of the present disclosure. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor photomasks or (B) at least one element in a layer of a semiconductor integrated circuit is manufactured using the manufacturing system 1800.

[0698] In Figure 18, the IC manufacturing system 1800 (hereinafter referred to as "System 1800") includes entities such as a design room 1820, a photomask manufacturing room 1830, and an IC manufacturer / fabrication plant ("wafer fab") 1840, which interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 1860. The entities in System 1800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, one or more of the design room 1820, photomask manufacturing room 1830, and IC wafer fab 1840 are owned by a single, larger company. In some embodiments, one or more of the design room 1820, photomask manufacturing room 1830, and IC wafer fab 1840 coexist in a common facility and use common resources.

[0699] Design studio (or design team) 1820 produces an IC design layout 1822. IC design layout 1822 includes various geometric patterns designed for an IC device 1860. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device 1860 to be manufactured. Various layers are combined to form various IC features. For example, a portion of IC design layout 1822 includes various IC features to be formed in and disposed on a semiconductor substrate (such as a silicon wafer) in various material layers, such as active regions, gate electrodes, source electrodes and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads. Design studio 1820 performs an appropriate design process to form IC design layout 1822. This design process includes one or more of logic design, physical design, or placement and routing. IC design layout 1822 is presented in one or more files containing information about the geometric patterns. For example, IC design layout 1822 may be expressed in a GDSII file format or a DFII file format.

[0700] The photomask fabrication room 1830 includes data preparation 1832 and photomask fabrication 1834. The photomask fabrication room 1830 uses an IC design layout 1822 to fabricate one or more photomasks 1845 for use in fabricating layers of an IC device 1860 according to the IC design layout 1822. The photomask fabrication room 1830 performs photomask data preparation 1832, in which the IC design layout 1822 is translated into a representative data file (RDF). The photomask data preparation 1832 provides the RDF to the photomask fabrication 1834. The photomask fabrication 1834 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate, such as a photomask (screen) 1845 or a semiconductor wafer 1842. The IC design layout 1822 is manipulated by the photomask data preparation 1832 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC fabrication plant 1840. In Figure 18, the photomask data preparation 1832 and the photomask fabrication 1834 are shown as separate components. In some embodiments, photomask data preparation 1832 and photomask manufacturing 1834 can be collectively referred to as photomask data preparation.

[0701] In some embodiments, mask data preparation 1832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 1822. In some embodiments, mask data preparation 1832 includes further resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution aids, phase-shifting masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0702] In some embodiments, mask data preparation 1832 includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout already processed in the OPC. This set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask manufacturing 1834, which may cancel some modifications performed by the OPC to conform to the mask creation rules.

[0703] In some embodiments, mask data preparation 1832 includes lithography process checking (LPC), a simulation of the process performed by IC manufacturing plant 1840 to manufacture IC device 1860. LPC simulates this process based on IC design layout 1822 to create a simulated manufactured device, such as IC device 1860. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, and similar or combinations thereof. In some embodiments, after LPC has created a simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further improve IC design layout 1822.

[0704] It should be understood that, for clarity, the description of the above photomask data preparation 1832 has been simplified. In some embodiments, data preparation 1832 includes additional features, such as logic operations (LOPs), to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1822 during data preparation 1832 can be performed in various different sequences.

[0705] After photomask data preparation 1832 and during photomask fabrication 1834, a photomask 1845 or a set of photomasks 1845 is fabricated based on a modified IC design layout 1822. In some embodiments, photomask fabrication 1834 includes performing one or more photolithographic exposures based on the IC design layout 1822. In some embodiments, a mechanism of electron beam (e-beam) or multiple e-beams is used to form a pattern on the photomask (photomask or mask) 1845 based on the modified IC design layout 1822. The photomask 1845 can be formed using various techniques. In some embodiments, the photomask 1845 is formed using a binary technique. In some embodiments, the photomask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary version of the photomask 1845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary photomask. In another example, photomask 1845 is formed using a phase-shifting technique. In a phase-shifted photomask (PSM) version of photomask 1845, various features in the pattern formed on the photomask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifted photomask can be attenuated PSM or alternating PSM. The photomask produced by photomask fabrication 1834 is used in various processes. For example, such photomasks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0706] IC manufacturing plant 1840 is an IC manufacturing company, including one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC manufacturing plant 1840 is a semiconductor manufacturing plant. For example, there may be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple IC products, a second manufacturing facility for back-end-of-line (BEOL) manufacturing of interconnects and packaging of IC products, and a third manufacturing facility for providing other services to the manufacturing company.

[0707] IC manufacturing plant 1840 includes wafer fabrication tool 1852 (hereinafter referred to as "manufacturing tool 1852") configured to perform various manufacturing operations on semiconductor wafer 1842, such that IC device 1860 is manufactured according to a photomask (e.g., photomask 1845). In various embodiments, manufacturing tool 1852 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0708] IC manufacturing plant 1840 uses a photomask 1845 manufactured by photomask fabrication chamber 1830 to manufacture IC device 1860. Therefore, IC manufacturing plant 1840 uses IC design layout 1822 at least indirectly to manufacture IC device 1860. In some embodiments, semiconductor wafer 1842 is manufactured by IC manufacturing plant 1840 using photomask 1845 to form IC device 1860. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1822. Semiconductor wafer 1842 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1842 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0709] System 1800 is shown as having a design room 1820, a photomask manufacturing room 1830, or an IC manufacturing plant 1840 as separate elements or entities. However, it should be understood that one or more of the design room 1820, the photomask manufacturing room 1830, or the IC manufacturing plant 1840 are part of the same element or entity.

[0710] One aspect of this description relates to integrated circuits. In some embodiments, the integrated circuit includes a first cell region extending along a first direction and having a first height in a second direction different from the first direction. In some embodiments, the first cell region includes a first transistor assembly of a clock circuit. In some embodiments, the integrated circuit further includes a second cell region extending along the first direction and having a second height in the second direction, the second height being different from the first height, the second cell region being adjacent to the first cell region along a first boundary extending along the first direction. In some embodiments, the second cell region includes a feed via extending from a front side of a substrate to a back side, the feed via being configured to electrically couple elements on the front and back sides together. In some embodiments, the feed via includes a first conductor located on the back side of the substrate and extending along the first direction. In some embodiments, the feed via further includes a second conductor extending along the first direction, located on a first level and above the first conductor. In some embodiments, the feed via further includes a first contact extending at least along the first or second direction, located on a second level different from the first level and above the first conductor. In some embodiments, the feed through-hole further includes a first through-hole extending along a first direction, located on a third level different from the first and second levels and above the first conductor.

[0711] Another aspect of this description relates to integrated circuits. In some embodiments, the integrated circuit includes a first cell region extending along a first direction and having a first height in a second direction different from the first direction, the first cell region including a clock circuit. In some embodiments, the clock circuit includes a buffer circuit assembly including a first transistor assembly, or an inverter assembly including a first transistor assembly. In some embodiments, the integrated circuit further includes a second cell region extending along the first direction and having a second height in the second direction, the second height being different from the first height, the second cell region being adjacent to the first cell region along a first boundary extending along the first direction. In some embodiments, the second cell region includes a first gate assembly extending along the first direction, and a second gate assembly extending along the first direction and separated from the first gate assembly in the second direction. In some embodiments, the second cell region further includes a feed via located between the first gate assembly and the second gate assembly, the feed via extending from the front side of the substrate to the back side, the feed via being configured to electrically couple elements on the front and back sides together. In some embodiments, the feed via includes a first conductor located on the back side of the substrate and extending along the first direction. In some embodiments, the feed through-hole further includes a second conductor extending along a first direction, located on a first level and above the first conductor. In some embodiments, the feed through-hole further includes a first contact extending at least along a first direction or a second direction, located on a second level different from the first level and above the first conductor. In some embodiments, the feed through-hole further includes a first through-hole extending along a first direction, located on a third level different from the first and second levels and above the first conductor.

[0712] Another aspect of this description relates to a method of manufacturing an integrated circuit. In some embodiments, the method includes manufacturing a first transistor assembly on a substrate front side of a first cell region, the first cell region extending along a first direction and having a first height in a second direction different from the first direction, the first transistor assembly including a buffer circuit assembly of a clock circuit, or an inverter assembly of a clock circuit. In some embodiments, the method further includes manufacturing a feed via in a second cell region, the second cell region extending along the first direction and having a second height in the second direction, the second height being different from the first height, the second cell region being adjacent to the first cell region along a first boundary extending along the first direction. In some embodiments, manufacturing the feed via in the second cell region includes depositing a first conductive material on a first layer on a substrate front side to form a first contact assembly, the first contact assembly extending at least along the first direction or the second direction. In some embodiments, manufacturing the feed via in the second cell region further includes manufacturing a first gate assembly on a second layer on a substrate front side, the first gate assembly extending along the second direction. In some embodiments, fabricating feed vias in the second unit region further includes depositing a second conductive material on the front side of the substrate on a third layer to form a first via assembly. The first via assembly extends at least along a first direction or a second direction, overlaps with at least a first contact assembly or the gate assembly, and is electrically coupled to at least the first contact assembly or the first gate assembly. In some embodiments, fabricating feed vias in the second unit region further includes depositing a third conductive material in a first opening in the substrate to form a first conductor assembly. The first conductor assembly extends along a first direction, is located on a fourth layer, and is electrically coupled to the first contact assembly. The fourth layer is different from the first, second, and third layers. In some embodiments, the method further includes depositing a fourth conductive material on the back side of the substrate on a first metal layer to form a second conductor assembly. The back side of the substrate is opposite to the front side of the substrate, the second conductor assembly extends along a first direction, and is electrically coupled to the first conductor assembly.

[0713] The features of the above embodiments are beneficial for those skilled in the art to understand various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis to design or modify other processes and structures to achieve the same purpose and / or the same advantages as the above embodiments. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

[0714] 100, 200A, 200B, 200C, 200D, 200E, 200F, 200G, 200H, 300, 400, 500, 600, 700A, 700B, 800, 900, 1000, 1100, 1200, 1300: Integrated circuits 102: Time Source 201a, 201b, 301a, 301b: Boundaries 202a, 204a, 204b, 206a, 206c, 301, 802, 803, 902, 903, 1002, 1003, 1104a, 1104b, 1104c, 1104d, 1104e, 1204a, 1206a, 1302, 1304a: Unit 301a, 301b, 301c, 301d: Element boundaries 302, 802: Active Zone Set 302a, 302b, 802a, 802b: Active Zone 303: Insulation Area 303a, 390a: Front side 303b, 390b: Dorsal side 304, 604, 804: Gate assembly 304a, 304b1, 304b2, 304c1, 304c2, 304d1, 304d2, 304e, 604b, 604c, 604d, 804a, 804b, 804c, 804d, 804e, PO: Gate OD oxide diffusion MD: Metal Overdiffusion 305, 805: Well Collection 305a, 805a: Well 306, 406, 506, 806, 1116, 1118, 1216, 1218, 1316: Contact component set 306a, 306b, 406a, 406b, 506a, 806a, 806b, 806c, 806d, 1216a, 1216g, 1218a, 1218c, 1218e, 1218g', 1316a, 1316z, 1316za: Contact elements 320, 322, 330, 840, 850, 1150, 1152, 1240, 1250, 1340, 1350: Conductor set 320a, 322a, 330a, 840a, 840b, 840c, 850a, 850b, 1150a, 1150b, 1152a, 1152b, 1116a, 1116b, 1116c, 1116d, 1116e, 1118a, 1118b, 1118c, 1118d, 1118e, 1240a, 1240b, 1250a, 1250b, 1340a, 1340b, 1350a, 1350b, 1350c, 1350d: Conductors A-A', B-B', C-C', D-D', E-E', F-F': faces 390:Substrate 391, 491, 591, 691, 1191a, 1191b, 1191c, 1191d, 1191e, 1192a, 1192b, 1192c, 1192d, 1192e, 1291, 1292, 1391, FTC: Feed Through Hole / Feed Through Hole Set 702, 704, 706, I1, I2, I3: Inverters 842: Through-hole assembly 842a, 842b, 842c, 842d, 842e, 842f: Through holes 300A, 600A, 800A, 800B, 900A, 900B, 1000A, 1000B, 1100A, 1100B, 1100C, 1200A, 1200B, 1200C, 1300A, 1300B, 1300C: Partial list 1104, 1106, 1202, 1204, 1206, 1304: Unit sets / units 1400, 1500, 1600: Method 1402, 1404, 1406, 1408, 1410, 1412, 1414, 1416, 1414, 1418, 1420, 1422, 1424, 1502, 1504, 1602, 1604, 1606, 1608, 1610, 1612, 1614, 1616, 1618: Operation 1700, 1800: System 1702: Processor 1704: Non-transitory computer-readable storage media / memory 1706: Computer program code / instruction 1708: Busbar 1710:I / O interface 1712: Network Interface 1714: Internet 1716: Layout Design 1718: User Interface 1720: Manufacturing Unit 1820: Design Studio 1822: IC Design Layout 1830: Photomask Manufacturing Room 1832: Data Preparation 1834: Photomask Manufacturing 1840: IC manufacturing plant 1842: Semiconductor wafer 1845: Photomask 1852: Manufacturing Tools 1860: IC device B1, B2, B3, B4, B5: Buffers BM0: Back metal 0 M0: Metal 0 M1: Metal 1 V0: Through hole 0 CLK, CLK1, CLK2, CLK3: Clock signals CPODE: Continuous Polycrystalline Silicon H1, H2, H3, H4, H5: Height LC1, LC2, LC3, LC4: Leaf units S1, S2: Signals S1B: Inverting signal VDR: Power Rail W1, W2, W3, W4, W5: Width X: First direction Y: Second direction Z: Direction

Claims

1. An integrated circuit, comprising: A first unit region extending in a first direction and having a first height in a second direction different from the first direction, the first unit region comprising: a first transistor assembly of a clock circuit; a second unit region extending in the first direction and having a second height in the second direction, the second height being different from the first height, the second unit region being adjacent to the first unit region along a first boundary extending in the first direction, the second unit region comprising: a feed via extending from the front side to the back side of a substrate, the feed via being configured to electrically couple elements on the front side and the back side together, the feed via comprising: a first conductor on the back side of the substrate and extending in the first direction; a second conductor extending in the first direction, located on a first level and above the first conductor; a first contact extending in at least the first direction or the second direction, located on a second level different from the first level and above the first conductor; and a first via extending in the first direction, located on a third level different from the first level and the second level and above the first conductor.

2. The integrated circuit as claimed in claim 1, wherein the second unit region further comprises: A first active region extends in the first direction and is located on the fourth level, the first active region including a first doping type; And a second active region extending in the first direction, located on the fourth level, and separated from the first active region in the first direction, the second active region including a second doping type different from the first doping type, wherein the feed via is located between the first active region and the second active region.

3. The integrated circuit as claimed in claim 2, wherein the first unit region further includes: A third active region extends in the first direction and is located on the fourth level, the third active region including the second doping type; And a fourth active region, extending in the first direction, located on the fourth level, and separated from the third active region in the first direction, the fourth active region including the first doping type.

4. The integrated circuit as claimed in claim 3, wherein the second unit region further comprises: A first gate extends in the first direction and is located on a fifth level different from the first level, the third level and the fourth level, and the first gate overlaps with the first active region at least; The second gate extends in the first direction, is located on the fifth level, and overlaps at least with the first active region; And a third gate, extending in the first direction, located on the fifth level, and overlapping at least with the first active region, wherein the first gate, the second gate and the third gate are separated from each other in the first direction.

5. An integrated circuit, comprising: A first unit region extending in a first direction and having a first height in a second direction different from the first direction, the first unit region including a clock circuit, the clock circuit including: a buffer circuit assembly including a first transistor assembly; or an inverter assembly including the first transistor assembly; and a second unit region extending in the first direction and having a second height in the second direction, the second height being different from the first height, the second unit region being adjacent to the first unit region along a first boundary extending in the first direction, the second unit region including: a first gate assembly extending in the first direction; and a second gate assembly extending in the first direction and separated from the first gate assembly in the second direction; and a feed via located between the first gate assembly and the second gate assembly, the feed via extending from the front side of the substrate to the back side, the feed via being configured to electrically couple elements on the front side and the back side together, the feed via including: a first conductor on the back side of the substrate and extending in the first direction; and a second conductor extending in the first direction, located on a first level and above the first conductor; A first contact extending at least in the first or second direction, located on a second level different from the first level and above the first conductor; and a first through-hole extending in the first direction, located on a third level different from the first and second levels and above the first conductor.

6. The integrated circuit as claimed in claim 5, wherein the second unit region further comprises: A first active region extends in the first direction and is located on the fourth level, the first active region including a first dopant type; And a second active region extending in the first direction, located on the fourth level, and separated from the first active region in the first direction, the second active region including a second dopant type different from the first dopant type, wherein the feed via is located between the first active region and the second active region.

7. The integrated circuit as claimed in claim 6, wherein the first unit region further comprises: A third active region extends in the first direction and is located on the fourth level, the third active region including the second dopant type; And a fourth active region, extending in the first direction, located on the fourth level, and separated from the third active region in the first direction, the fourth active region including the first dopant type.

8. The integrated circuit as claimed in claim 7, wherein the first contact is located between the first gate of the first gate set and the second gate of the second gate set.

9. The integrated circuit as claimed in claim 7, wherein the feed via further comprises: The second contact extends in the second direction, is located on the second level, and is above the first conductor, wherein the first contact and the second contact are located between the first active region and the second active region.

10. A method of manufacturing an integrated circuit, the method comprising: A first transistor assembly is fabricated in a first unit region on the front side of a substrate. The first unit region extends in a first direction and has a first height in a second direction different from the first direction. The first transistor assembly includes a buffer circuit assembly of a clock circuit or an inverter assembly of the clock circuit. A feed via is fabricated in a second unit region. The second unit region extends in the first direction and has a second height in the second direction, which is different from the first height. The second unit region is adjacent to the first unit region along a first boundary that extends in the first direction. Fabricating the feed via in the second unit region includes: depositing a first conductive material on a first layer on the front side of the substrate to form a first contact assembly that extends in at least the first direction or the second direction; and fabricating a first gate assembly on a second layer on the front side of the substrate that extends in the second direction. A second conductive material is deposited on a third layer on the front side of the substrate to form a first via assembly, the first via assembly extending at least in the first direction or the second direction, overlapping at least with the first contact assembly or the first gate assembly, and being electrically coupled to at least the first contact assembly or the first gate assembly; and a third conductive material is deposited in a first opening of the substrate to form a first conductor assembly extending in the first direction, located on a fourth layer, and electrically coupled to the first contact assembly, the fourth layer being different from the first layer, the second layer, and the third layer; and a fourth conductive material is deposited on a first metal layer on the back side of the substrate to form a second conductor assembly, the back side of the substrate being opposite to the front side of the substrate, the second conductor assembly extending in the first direction and being electrically coupled to the first conductor assembly.

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