Semiconductor devices, methods for manufacturing semiconductor devices

Abstract

In a reverse-conducting IGBT (RC-IGBT) integrating an IGBT and a diode on the same wafer, a semiconductor device is provided that can more effectively suppress hole injection in the diode portion and improve recovery characteristics. A semiconductor device having an IGBT and a diode on the same wafer is characterized in that the IGBT has: a first semiconductor layer of a first conductivity type; a plurality of first trenches formed within the first semiconductor layer; a body layer of a second conductivity type sandwiched between the plurality of first trenches and formed on the first semiconductor layer; and a source layer of the first conductivity type sandwiched between the plurality of first trenches and formed on the body layer; the diode has: the first semiconductor layer; and a plurality of second trenches formed within the first semiconductor layer, and has: a first portion sandwiched between the plurality of second trenches having the body layer formed on the first semiconductor layer; and a second portion sandwiched between the plurality of second trenches having the first semiconductor layer and a Schottky barrier junction formed by contacts within the first semiconductor layer.

Description

Technical Field

[0001] The present invention relates to the structure of a semiconductor device and a method for manufacturing the same, and is particularly applicable to an effective technology for a reverse-conducting IGBT (RC-IGBT) having an IGBT and a diode built into the same chip. Prior Art

[0002] IGBTs (Insulated Gate Bipolar Transistors), capable of high-speed switching of large amounts of power, are widely used in a range of industrial and consumer applications, including automotive applications. Examples include motor control inverters for electric and train vehicles, and inverter circuits for IH cooking appliances, washing machines, and air conditioners.

[0003] Many IGBT applications involve a pattern whereby a circulating current flows from the emitter to the collector. Conventionally, this circulating current action has been achieved by using a separate chip from the IGBT and connecting a flywheel diode in anti-parallel to the IGBT.

[0004] In recent years, reverse-conducting IGBTs (RC-IGBTs), which combine this IGBT and flywheel diode into a single chip, have become increasingly popular. In a reverse-conducting IGBT, the flywheel diode is embedded within the IGBT chip, connected in reverse parallel to the IGBT, and performs a circulating current operation.

[0005] As background technology in this technical field, there is a technology such as Patent Document 1. Patent Document 1 discloses "a technology for suppressing gate interference in an RC-IGBT using a diode structure having a Schottky connection."

[0006] In Patent Document 1, an n-type column layer (24a, 24b) is provided in a diode portion and a Schottky barrier diode is built in to suppress hole injection from a pn diode.

[0007] Furthermore, Patent Document 2 discloses a “semiconductor device with a short recovery time”.

[0008] In Patent Document 2, a connection region 16 is provided in the diode portion, and a structure having a built-in Schottky barrier diode is formed using a lower end 16d and an n-layer 21. [Prior art literature] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-165541 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-55079 Summary of the Invention

[0010] [Problems to be solved by the invention] The reverse conducting IGBT (RC-IGBT) has the following advantages: the chip size can be reduced by commonizing the terminal regions of the IGBT and diode, and the thermal resistance can be reduced because the losses generated in the IGBT area or the diode area can be dissipated across the entire chip.

[0011] On the other hand, since IGBTs and diodes are manufactured on the same chip, it is difficult to optimize each chip simultaneously. In particular, controlling the carrier lifetime of the diode is difficult, and low injection and reduction of recovery loss in the diode are challenges.

[0012] In Patent Document 1, an n-pillar layer is formed to incorporate a Schottky barrier diode within the diode portion of the RC-IGBT. However, in addition to the conventional RC-IGBT diode formation process, additional lithography and ion implantation processes are required to form this n-pillar layer. Furthermore, since the n-pillar layer is disposed within the p-type body layer, miniaturization is difficult, which limits the improvement of characteristics.

[0013] Furthermore, in Patent Document 2, a connection region is provided in the diode portion, and a contact layer is provided between the connection region and the n-layer. However, since the diode portion does not have a p-type main layer, the electric field concentrates at the corners of the connection region when maintaining the withstand voltage, raising concerns about a decrease in the withstand voltage and an increase in leakage current.

[0014] Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can more effectively suppress hole injection into the diode portion and improve recovery characteristics in a reverse conducting IGBT (RC-IGBT) having an IGBT and a diode built in the same chip.

[0015] [Technical means to solve the problem] In order to solve the above-mentioned problems, the present invention is a semiconductor device having an IGBT and a diode in the same chip, characterized in that the IGBT has: a first semiconductor layer of a first conductivity type; a plurality of first trenches formed in the first semiconductor layer; a main layer of a second conductivity type, sandwiched between the plurality of first trenches and formed on the first semiconductor layer; and a source layer of a first conductivity type, sandwiched between the plurality of first trenches and formed on the main layer; the diode has: the first semiconductor layer; and a plurality of second trenches formed in the first semiconductor layer, and has: a first portion, the first portion is sandwiched between the plurality of second trenches, and has the main layer formed on the first semiconductor layer; and a second portion, the second portion is sandwiched between the plurality of second trenches, and has the first semiconductor layer and a Schottky barrier junction formed using contacts in the first semiconductor layer.

[0016] In addition, the present invention is characterized in that it has: (a) step: forming a plurality of first grooves in a first area of ​​the main surface of the semiconductor substrate, and forming a plurality of second grooves in a second area of ​​the main surface of the semiconductor substrate; (b) step: forming a film in the order of an insulating film and an electrode film in each of the first grooves and the second grooves, and forming a gate electrode in the first groove and an electrode in the second groove by lithography and dry etching; (c) step: selectively forming a mask between a portion of the second grooves on the second area; (d) step: forming a mask on the semiconductor substrate other than the first groove and the second groove (e) forming an interlayer insulating film on the main surface of the semiconductor substrate, and forming a contact hole by lithography and dry etching, wherein the through hole penetrates the interlayer insulating film to expose the p-type main layer and the semiconductor substrate between the first trench and the second trench; and (f) forming a metal film on the main surface of the semiconductor substrate in a manner of burying the metal film in the contact hole, and forming a contact by lithography and dry etching, wherein a Schottky barrier junction formed by the semiconductor substrate and the contact is formed between the second trenches.

[0017] [Effects of the Invention] According to the present invention, a semiconductor device and a method for manufacturing the same can achieve more effective suppression of hole injection into the diode portion and improved recovery characteristics in a reverse conducting IGBT (RC-IGBT) having an IGBT and a diode built into the same chip.

[0018] Other issues, structures and effects than those described above will become clear from the description of the following embodiments. Simple diagram description

[0019] FIG1 is a diagram schematically showing the cross-sectional structure of a reverse conducting IGBT related to Example 1 of the present invention. FIG2 is a perspective view of the reverse conducting IGBT of FIG1 . FIG3A is a diagram showing the manufacturing process of the reverse conducting IGBT of FIG1 . FIG3B is a diagram showing the manufacturing process following FIG3A . FIG3C is a diagram showing the manufacturing process following FIG3B . FIG3D is a diagram showing the manufacturing process following FIG3C . FIG3E is a diagram showing the manufacturing process following FIG3D . FIG3F is a diagram showing the manufacturing process following FIG3E . FIG4 is a diagram schematically showing the cross-sectional structure of a reverse conducting IGBT related to Example 2 of the present invention. Implementation Method

[0020] Hereinafter, the embodiment of the present invention will be described using the drawings. In addition, in each drawing, the same structure is marked with the same reference numerals, and detailed description of the repeated parts is omitted. [Example 1]

[0021] 1 to 3F, a semiconductor device and a method for manufacturing the same according to a first embodiment of the present invention will be described.

[0022] FIG1 schematically illustrates the cross-sectional structure of a reverse-conducting IGBT (RC-IGBT) according to this embodiment. FIG2 is a perspective view of the reverse-conducting IGBT 1 shown in FIG1 . FIG3A through FIG3F illustrate the manufacturing process of the reverse-conducting IGBT 1 shown in FIG1 . FIG2 omits the interlayer insulating film 12, the front surface electrode 15, and the back surface electrode 20 shown in FIG1 to facilitate understanding of the structure.

[0023] As shown in FIG. 1 and FIG. 2 , the reverse conducting IGBT (RC-IGBT) 1 of this embodiment is composed of an IGBT portion 3 and a diode portion 4 built into the same chip.

[0024] A reverse conducting IGBT (RC-IGBT) 1 includes multiple trenches 5 formed in the main surface of an n-type semiconductor substrate (silicon substrate) 2. Trenches 5 are formed at multiple locations in the region where the IGBT portion 3 is formed and in the region where the diode portion 4 is formed. Trenches 5 are also formed in the boundary region between the IGBT portion 3 and the diode portion 4.

[0025] Furthermore, the interval between the trenches 5 formed in the diode portion 4 has a portion having a width W1 and a portion having a width W2 narrower than W1 (W1>W2) for reasons described later.

[0026] An insulating film (silicon oxide film) 6 is formed inside each trench 5 so as to cover the bottom and side surfaces of the trench 5 .

[0027] In the region where the IGBT portion 3 is formed, a p-type body layer 9 is formed on the main surface of the semiconductor substrate 2 so as to sandwich both sides of the trench 5 .

[0028] Inside the trench 5 of the IGBT portion 3 , a gate electrode (polysilicon electrode) 7 is formed using an insulating film (silicon oxide film) 6 .

[0029] Furthermore, an emitter electrode (polysilicon electrode) 8 is formed by an insulating film (silicon oxide film) 6 inside the trench 5 of the diode portion 4 .

[0030] In the region where the IGBT unit 3 is formed, a p-type body layer 9 is formed on the main surface of the semiconductor substrate 2 between the trenches 5 so as to be sandwiched by the trenches 5. Furthermore, an n + layer 11 is formed above the p-type body layer 9.

[0031] On the other hand, the region where the diode portion 4 is formed has: a portion where the p-type body layer 9 is formed on the main surface of the semiconductor substrate 2 between the trenches 5 in a form sandwiched by the trenches 5; and a portion where the p-type body layer 9 is not formed between the trenches 5 and serves as the n-layer 16 of the semiconductor substrate 2.

[0032] An interlayer insulating film 12 is formed on the main surface of the semiconductor substrate 2 so as to cover the n+ layer 11 of the IGBT portion 3, the insulating film (silicon oxide film) 6, and the gate electrode (polysilicon electrode) 7 within the trench 5. It also covers the p-type body layer 9 of the diode portion 4, the insulating film (silicon oxide film) 6, and the emitter electrode (polysilicon electrode) 8 within the trench 5.

[0033] Contact holes 13 are formed in the interlayer insulating film 12 , penetrating the interlayer insulating film 12 and reaching the p-type body layers 9 of the IGBT portion 3 and the diode portion 4 , and the n − layer 16 of the diode portion 4 .

[0034] A surface electrode 15 is formed on the interlayer insulating film 12, covering the interlayer insulating film 12. The surface electrode 15 is also embedded in the contact hole 13, forming the contact 14 between the IGBT portion 3 and the diode portion 4. A p+ layer 10 is formed on each p-type body layer 9 at the bottom of the contact hole 13 to reduce the contact resistance between the contact 14 and the p-type body layer 9.

[0035] An n-buffer layer 17 is formed on the back side of the semiconductor substrate 2. A p-layer 18 is further formed outside the n-buffer layer 17 of the IGBT portion 3, and an n+ layer 19 is further formed outside the n-buffer layer 17 of the diode portion 4. A back electrode 20 is formed further outside the p-layer 18 and the n+ layer 19.

[0036] The reverse-conducting IGBT (RC-IGBT) 1 of this embodiment is constructed as described above. In a portion of the diode portion 4, a Schottky barrier diode (SBD) is provided, rather than a p-type body layer 9 (p-type anode layer), forming a Schottky contact directly with the n-layer 16 of the n-type semiconductor substrate (silicon substrate) 2. Unlike Patent Document 2, the absence of a p-layer in the SBD region reduces the p-layer area of ​​the anode, thereby achieving low diode injection and reduced recovery losses.

[0037] Furthermore, since the contact 14 is provided directly in the n-layer 16, there is a concern that the withstand voltage may be reduced or the leakage current may be increased due to electric field concentration at the corners of the contact 14. However, by making the trench spacing (W2) connected to the emitter electrode 8 smaller than the spacing (W1) of a typical IGBT or pn diode (W1>W2), the electric field at the corners of the SBD's contact 14 can be mitigated, and the withstand voltage can be maintained.

[0038] 3A to 3F , a method for manufacturing the reverse conducting IGBT (RC-IGBT) 1 of FIG. 1 and FIG. 2 will be described.

[0039] First, as shown in FIG3A , a plurality of trenches 5 are formed on the main surface of an n-type semiconductor substrate (silicon substrate) 2. At this time, trenches 5 are formed in the region where the IGBT portion 3 will be formed, the region where the diode portion 4 will be formed, and the boundary region between the IGBT portion 3 and the diode portion 4.

[0040] Next, as shown in FIG3B , an insulating film (silicon oxide film) 6 and a polysilicon film (polysilicon electrodes 7, 8) are formed in this order on the main surface of the semiconductor substrate 2 in such a manner as to fill the interiors of the trenches 5 of the IGBT portion 3, the trenches 5 of the diode portion 4, and the trenches 5 in the boundary region between the IGBT portion 3 and the diode portion 4. By photolithography and dry etching, a gate electrode 7 is formed in the trenches 5 of the IGBT portion 3, and an emitter electrode 8 is formed in the trenches 5 of the diode portion 4.

[0041] 3C , a mask is selectively formed between each trench 5 and each insulating film 6 and a portion of the trench 5 on the region where the diode portion 4 is formed, and a p-type body layer 9 is formed on the main surface of the semiconductor substrate 2 by ion implantation of p-type impurities.

[0042] Furthermore, an n + layer 11 is formed on the main surface of the semiconductor substrate 2 by ion implantation of n-type impurities.

[0043] Next, as shown in FIG3D , an interlayer insulating film 12 is formed on the main surface of the semiconductor substrate 2 , and by lithography and dry etching, contact holes 13 are formed through the interlayer insulating film 12 to expose the p-type body layer 9 and the semiconductor substrate 2 between the trenches 5 of the IGBT portion 3 and the diode portion 4 .

[0044] Next, as shown in FIG. 3E , after the contact hole 13 is exposed by covering the semiconductor substrate 2 , the p + layer 10 is formed at the bottom of the contact hole 13 by ion implantation of p-type impurities using the contact hole 13 .

[0045] Next, as shown in FIG. 3F , a metal film is formed on the main surface of the semiconductor substrate 2 so as to fill the inside of the contact hole 13 , and contacts 14 and surface electrodes 15 are formed by lithography and dry etching.

[0046] After that, the n-buffer layer 17, the p-layer 18, the n+ layer 19, and the back electrode 20 are formed on the back side, completing the structure of the reverse conducting IGBT (RC-IGBT) 1 shown in FIG. 1 .

[0047] As described above, the reverse conducting IGBT (RC-IGBT) 1 of this embodiment is a semiconductor device having an IGBT portion 3 and a diode portion 4 in the same wafer. The IGBT portion 3 includes: a first semiconductor layer (n-layer 16) of a first conductivity type; a plurality of trenches 5 formed in the first semiconductor layer (n-layer 16); a body layer (p-type body layer 9) of a second conductivity type formed on the first semiconductor layer (n-layer 16) and sandwiched between the plurality of trenches 5; and a source layer (n+ layer 11) of a first conductivity type formed on the body layer (p-type body layer 9) and sandwiched between the plurality of trenches 5. The diode portion 4 includes: a first semiconductor layer (n-layer 16); a plurality of trenches 5 formed in the first semiconductor layer (n-layer 16); a first portion consisting of the body layer (p-type body layer 9) formed on the first semiconductor layer (n-layer 16) and sandwiched between the plurality of trenches 5; and a source layer (n+ layer 11) of a first conductivity type formed on the body layer (p-type body layer 9) and sandwiched between the plurality of trenches 5. - layer 16) and the contact 14 in the first semiconductor layer to form a Schottky barrier junction.

[0048] Furthermore, the intervals (W2) between the grooves 5 in the second portion are configured to be narrower than the intervals (W1) between the grooves 5 in the first portion.

[0049] In addition, the first part and the second part are arranged alternately.

[0050] This makes it possible to more effectively suppress hole injection into the diode portion and improve recovery characteristics in a reverse-conducting IGBT (RC-IGBT) that incorporates an IGBT and a diode within the same chip. [Example 2]

[0051] 4, a semiconductor device according to a second embodiment of the present invention will be described.

[0052] FIG4 is a diagram schematically showing a cross-sectional structure of a reverse conducting IGBT (RC-IGBT) according to this embodiment, and corresponds to a modification of the first embodiment ( FIG1 ).

[0053] In the reverse conducting IGBT (RC-IGBT) 1 of Example 1 ( FIG. 1 ), in the diode portion 4 , the portions with p-type body layers 9 between the trenches 5 and the portions with Schottky barrier junctions (SBDs) between the trenches 5 are arranged alternately. In contrast, this embodiment, as shown in FIG. 4 , differs from Example 1 ( FIG. 1 ) in that the portions with p-type body layers 9 between the trenches 5 are arranged more frequently than the portions with Schottky barrier junctions (SBDs) between the trenches 5 , resulting in a ratio of 1:2 or greater between the portions with Schottky barrier junctions (SBDs) between the trenches 5 and the portions with p-type body layers 9 between the trenches 5 . The remaining structure is the same as that of Example 1 ( FIG. 1 ).

[0054] The ratio of the portion having the p-type body layer 9 between the trenches 5 to the portion having the Schottky barrier junction (SBD) between the trenches 5 may be changed according to desired characteristics of the reverse conducting IGBT (RC-IGBT) 1 .

[0055] Furthermore, the present invention is not limited to the above-described embodiments and encompasses various variations. For example, the above-described embodiments are described in detail to facilitate understanding of the present invention and are not necessarily limited to having all the described structures. Furthermore, portions of the structure of one embodiment may be replaced with those of another embodiment, or structures of another embodiment may be added to those of another embodiment. Furthermore, portions of the structure of each embodiment may be added, deleted, or replaced with other structures.

[0056] 1: Reverse conducting IGBT (RC-IGBT) 2:Semiconductor substrate (silicon substrate) 3: IGBT department 4: Diode body 5: Groove 6: Insulating film (silicon oxide film) 7: Gate electrode (polysilicon electrode) 8: Emitter electrode (polysilicon electrode) 9: p-type main layer 10:p+layer 11:n+layer 12: Interlayer insulation film 13: Contact hole 14:Contact 15: Surface electrode 16:n-layer 17:n buffer layer 18: p layer 19: n+ layers 20: Back electrode SBD: Schottky barrier diode W1, W2: width

Claims

1. A semiconductor device having an IGBT and a diode within the same wafer, characterized in that the IGBT comprises: a first semiconductor layer of a first conductivity type; a plurality of first trenches formed within the first semiconductor layer; a body layer of a second conductivity type sandwiched between the plurality of first trenches and formed on the first semiconductor layer; and a source layer of a first conductivity type sandwiched between the plurality of first trenches and formed on the body layer; the diode comprises: the first semiconductor layer; and a plurality of second trenches formed in the first semiconductor layer, and having: a first portion sandwiched between the plurality of second trenches, having the body layer formed on the first semiconductor layer; The second portion, sandwiched between a plurality of second trenches, has the first semiconductor layer and a Schottky barrier junction formed by corner contacts within the first semiconductor layer, wherein the plurality of second trenches are connected only to the body layer and the first semiconductor layer through an insulating film, and the spacing between the plurality of second trenches in the second portion is narrower than the spacing between the second trenches in the first portion.

2. The semiconductor device as claimed in claim 1, wherein, The first part and the second part are configured alternately.

3. The semiconductor device as claimed in claim 1, wherein, The number of configurations in the first part is greater than that in the second part, such that the ratio of the configurations in the first part to the second part is 1:2 or more.

4. A method for manufacturing a semiconductor device, characterized by comprising: (a) the steps of forming a plurality of first trenches in a first region of a semiconductor substrate having an n-layer, and forming a plurality of second trenches in a second region of the semiconductor substrate; (b) the steps of forming an insulating film and an electrode film in each of the first trenches and the second trenches in sequence, forming a gate electrode in the first trench and an electrode in the second trench by photolithography and dry etching; (c) the steps of selectively forming a mask between a portion of the second trenches in the second region; and (d) the steps of forming a p-type host layer on the main surface of the semiconductor substrate other than the first trenches and the second trenches by ion implantation of p-type impurities. (e) Step: Forming an interlayer insulating film on the main surface of the semiconductor substrate, and forming contact holes by photolithography and dry etching, wherein the contact holes penetrate the interlayer insulating film, exposing the p-type host layer and the semiconductor substrate between the first trench and the second trench; and (f) Step: Forming a metal film on the main surface of the semiconductor substrate by embedding it within the contact holes, and forming contacts by photolithography and dry etching, wherein... A first portion of the p-type host layer formed on the n-layer is formed between a plurality of second trenches in the second region; and a second portion of the Schottky barrier interface formed by the semiconductor substrate and the junction having corners is formed between the plurality of second trenches. The plurality of second trenches are in contact with the p-type host layer and the n-layer only through the insulating film. The spacing between the plurality of second trenches in the second portion is narrower than the spacing between the second trenches in the first portion.

5. A method for manufacturing a semiconductor device as claimed in claim 4, wherein, An IGBT is formed in the first region, and a diode is formed in the second region.

6. A method for manufacturing a semiconductor device as claimed in claim 4, wherein, In step (c), the spacing between the second grooves in the portion forming the mask is narrower than the spacing between the second grooves in the portion not forming the mask.

7. A method for manufacturing a semiconductor device as claimed in claim 4, wherein, In step (c), the portions without the mask are alternately configured with the portions that have the mask.

8. A method for manufacturing a semiconductor device as claimed in claim 4, wherein: In step (c), the width of the portion of the second region that is not covered by the mask is wider than the portion of the second region that is covered by the mask.

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