Unitized finger to bump interposer package

Abstract

This document describes electronic packaging and manufacturing methods. In one embodiment, an electronic package includes: a die stack of a plurality of vertically stacked dies; a first interposer layer laterally adjacent to the die stack; a first plurality of bonding wires electrically connecting a first group of the plurality of vertically stacked dies to the interposer layer; and a molding compound layer encapsulating the die stack, the interposer layer, and the plurality of the first plurality of bonding wires.

Description

Technical Field

[0001] Embodiments described herein relate to electronic packaging, and more particularly to wire-bonded stacked dies. Prior Art

[0002] The current market demand for portable and mobile electronic devices, such as cell phones, personal digital assistants (PDAs), digital cameras, portable players, games, and other mobile devices, requires integrating more performance and features into increasingly smaller spaces. Furthermore, the demand for higher-performance displays, such as video processing, requires larger and higher-bandwidth memories to facilitate higher data transfer rates with the lowest possible power consumption.

[0003] As a result, various packaging technologies have been developed. For example, there are various 3D solutions in which dies are stacked vertically to integrate more functionality into the same footprint. For example, memory devices are commonly stacked in stacks of 8, 16, 32, and 64 dies, with adjacent dies laterally offset from each other to provide wirebond pads for electrically connecting each stacked die to the packaging substrate via a plurality of bond wires. Summary of the Invention

[0004] Electronic packages and manufacturing methods are described herein. In one embodiment, an electronic package includes: a die stack of a plurality of vertically stacked die; a first interposer laterally adjacent to the die stack; a first plurality of bond wires electrically connecting a first set of the plurality of vertically stacked die to the interposer; and a mold compound layer encapsulating the die stack, the interposer, and the first plurality of bond wires. According to embodiments, the interposer may include a via pitch that is finer than the via pitch provided in a package substrate supporting the die stack and to which the interposer is mounted. In this way, fine wiring associated with a high bond pad and via count can be offloaded to the interposer while reducing the overall electronic package size and without substantially altering the package substrate assembly line. Simple diagram description

[0005] [FIG. 1A] is a cross-sectional side view illustration of an electronic package including a plurality of bond wires electrically connecting a die stack to bond pads of a package substrate. [FIG. 1B] is a schematic top view of the electronic package of FIG. 1A, showing a plurality of landing pads, electrical fan-out wiring, and through-hole connections within the package substrate. [FIG. 1C] is a schematic cross-sectional side view of an organic encapsulation substrate. [FIG. 2A] is a cross-sectional side view illustration of an electronic package according to one embodiment, the electronic package including a plurality of bond wires electrically connecting a die stack to bond pads of an interposer mounted on a package substrate. [ FIG. 2B ] is a schematic top view layout of the electronic package of FIG. 2A , showing a plurality of landing pads and via pitches within an interposer according to one embodiment. [ FIG. 3A ] is a schematic cross-sectional side view illustration of a silicon-based interposer according to one embodiment. [ FIG. 3B ] is a schematic cross-sectional side view illustration of an organic interposer according to one embodiment. [ FIG. 3C ] is a schematic cross-sectional side view illustration of a non-organic interposer according to one embodiment. [ FIG. 3D ] is a schematic cross-sectional side view illustration of an interposer with vertical conductive lines according to one embodiment. FIG. 4 is a schematic top view of an interposer including bonding pads and wiring extending from the bonding pads and over vias according to one embodiment. [ FIG. 5 ] is a schematic bottom view illustration of a backside contact on the bottom side of an interposer according to one embodiment. [ FIG. 6 ] is a schematic cross-sectional side view of an interposer including multiple metal wiring layers according to one embodiment. 7A]-7F are schematic cross-sectional side view illustrations of a sequence for fabricating an electronic package according to one embodiment, wherein the electronic package includes a plurality of bond wires electrically connecting a die stack to bond pads of an interposer mounted on a package substrate. [ FIG. 8 ] is a schematic cross-sectional side view illustration of an electronic package according to one embodiment, the electronic package including a plurality of bond wires electrically connecting a die stack to bond pads of a stacking interposer mounted on a package substrate. [ FIG. 9 ] is a schematic cross-sectional side view illustration of an electronic package according to one embodiment, the electronic package including a plurality of bond wires electrically connecting a die stack to bond pads of a plurality of interposers mounted on a package substrate. [ FIG. 10 ] is a schematic cross-sectional side view illustration of an electronic package including an optical interconnect according to an embodiment. [ FIG. 11 ] is a schematic cross-sectional side view illustration of a substrate-less electronic package according to one embodiment, the substrate-less electronic package including a plurality of bond wires electrically connecting a die stack to bond pads of a plurality of interposers. [FIGS. 12A]-[FIGS. 12E] are schematic cross-sectional side view illustrations of a sequence for fabricating a substrate-less electronic package including a plurality of bond wires electrically connecting a die stack to bond pads of a plurality of interposers according to one embodiment. Implementation Method

[0006] Cross-reference to related applications

[0007] This application claims priority to U.S. Provisional Patent Application No. 63 / 549,355, filed on February 2, 2024, which is incorporated herein by reference.

[0008] Embodiments describe wire-bonded stacked die and assembly methods. Specifically, embodiments describe wire-bonded stacked memory die, in which an interposer can be mounted laterally adjacent to the stacked die, with bond wires (also known as "fingers") directly connecting the stacked die to the interposer. In this manner, the bond wire landing pads and corresponding via pitch can be defined by the interposer assembly and fabricated separately from the package substrate. Furthermore, the bond wire (finger) length can be shortened, alleviating challenges associated with wire sag and sway, as well as signal and power integrity for high-speed signals.

[0009] Common packaging substrates include organic substrates, silicon substrates, and ceramic substrates. Organic substrates are particularly widely adopted due to their ease of manufacturing and the cost associated with being able to be assembled in large flat panels. Organic dielectric materials also have a dielectric constant suitable for embedding high-speed signal transmission lines. A typical organic substrate can be formed from a composite of woven fiberglass cloth, a polymer (e.g., resin), and a metal wiring layer. The packaging substrate can be formed from a variety of suitable printed circuit board materials, including epoxy resins (e.g., FR4), prepreg, polyimide, etc. The wiring layer can be formed from copper foil and connected to through-holes formed by laser etching and electroplating. Alternatively, both the wiring layer and the through-holes can be electroplated.

[0010] Referring now to FIG1A , a cross-sectional side view illustration of an electronic package 100 is provided that includes a package substrate 110 having a front side 116 and a back side 114; a die stack of a plurality of dies 120 vertically stacked on the package substrate; and a plurality of bond wires 130 (or fingers) electrically connecting the die stack to bond pads 112 of the package substrate 110. The plurality of vertically stacked dies 120 and bond wires 130 may then be encapsulated in a mold compound layer 140 over the front side 116 of the package substrate 110, followed by placement of solder bumps 118 on the back side 114 of the package substrate 110.

[0011] FIG1B is a schematic top-down layout diagram of package substrate 110, illustrating a plurality of bond pads 112, metal wiring layer 102 wiring, and via 104 connections within package substrate 110. As shown in both FIG1A and FIG1B , via 104 may require a package edge width W1 sufficient to accommodate the via connections. Therefore, the overall size of package 100 and edge width W1 may be limited by the technology used to pattern the fan-out wiring and via 104 within package substrate 110.

[0012] FIG1C illustrates a schematic cross-sectional side view of an organic packaging substrate 110. As shown, packaging substrate 110 may include a plurality of dielectric layers 105 and metal wiring layers 102. Dielectric layers 105 may be formed from organic materials such as epoxy, prepreg, or polyimide, and may alternatively be a composite of an organic material and woven fiberglass cloth. Metal wiring layers 102 may alternatively be, for example, metal foil (such as copper) and may be connected to vias 104. Packaging substrate 110 may optionally include a core 106, such as silicon, glass, or ceramic for structural stability, and core vias 108 extending therethrough. A front side 116 of the packaging substrate may include bonding pads 112, and a back side 114 of the packaging substrate may include contact pads 109 for receiving solder bumps 118. It should be understood that this is an exemplary configuration of organic packaging substrate 110 and that embodiments are not limited thereto.

[0013] In one aspect, it has been observed that as additional channels and banks are added to a memory package, the package size also increases due to the additional die and the corresponding area required to accommodate the additional bond wires and via pitch. More specifically, it has been observed that scaling down the bond pads 112 and via pitch 104 of a standard organic package substrate on existing assembly lines can be expensive because such scaling must be applied to the entire package substrate, even though it may only be necessary in the wirebond connection area. Furthermore, the inclusion of additional stacked dies and longer bond wires introduces additional challenges, such as wire sag and wire wobble, as well as degradation of signal integrity and power integrity for high-speed signals.

[0014] According to an embodiment, a stacked die package is described in which an interposer is mounted laterally adjacent to the die stack, with bond wires (fingers) directly connecting the stacked die to the interposer. The interposer can have a higher via pitch / density than the package substrate. This eliminates the need to redesign the organic package substrate 110 and assembly lines used by the industry, and the landing pads and via pitch can be offloaded to the interposer, allowing for a reduction in the overall package 100 size while maintaining existing organic package substrate 110 materials and design rules. Consequently, the size of the electronic package 100 can be reduced to the limits of wire bonding capabilities. Furthermore, the interposer allows for the use of shorter wires, which are easier to achieve with fine pitches and exhibit less droop and wobble. The shorter wires further improve signal and power integrity.

[0015] Various embodiments are described with reference to the accompanying drawings. However, some embodiments may be practiced without one or more of these specific details or in combination with other known methods and configurations. In the following description, numerous specific details (e.g., specific configurations, dimensions, and procedures) are set forth to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques are not described in detail to avoid unnecessarily detracting from the present embodiments. References throughout this patent specification to "one embodiment" mean that a particular feature, structure, configuration, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, appearances of the phrase "in one embodiment" throughout this patent specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0016] Referring now to FIG. 2A-2B , FIG. 2A is a cross-sectional side view illustration of an electronic package 100 according to one embodiment, including a plurality of bond wires 130 electrically connecting a die stack 125 to bond pads 156 of an interposer 150 mounted on a package substrate 110. FIG. 2B is a schematic top view layout of the electronic package of FIG. 2A , illustrating the plurality of bond pads 156 and the pitch of vias 157 within the interposer according to one embodiment. In one embodiment, the electronic package 100 includes a die stack 125 comprising vertically stacked dies 120; a first interposer 150 (e.g., the interposer on the right side of the figure) laterally adjacent to the die stack 125; a first plurality of bond wires 130 (e.g., the bond wires on the right side of the figure) connecting a first plurality of the vertically stacked dies 120 to the first interposer 150; and a mold compound layer 140 encapsulating the die stack 125, the interposer 150, and the first plurality of bond wires 130. Similarly, a second interposer 150 (e.g., the interposer on the left side of the figure) may be laterally adjacent to the die stack 135, and a second plurality of bond wires 130 (e.g., the bond wires on the left side of the figure) may connect a second plurality of the vertically stacked dies 120 to the second interposer 150.

[0017] In the particular embodiment depicted, the die stack 125 is supported by a package substrate 110, and corresponding interposers 150 are mounted to the package substrate 110 on laterally opposite sides (e.g., left and right) of the die stack 125, for example, using solder bumps 158. The vertically stacked die 120 can also be arranged in a stepped configuration, exposing bonding flanges for connecting bond wires 130 at ball bonds 131. Depending on the embodiment, the package substrate 110 can be an organic substrate, such as that described with respect to FIG. 1C, and the interposer(s) 150 can include a finer pitch of vias 157 than the pitch of vias 104 in the package substrate 110. For example, as shown in FIG. 2B, the vias 157 of the interposer 150 can be aligned with the bond pads 156, but this is not required.

[0018] In the particular embodiment depicted in FIG2A , electronic package 100 may be an 8-channel memory package, wherein each bond wire 130 corresponds to a different channel connected to interposer 150 . Furthermore, the wire bonds may include single or multiple rings. In the particular embodiment depicted, each wire bond connects multiple dies 120 (two shown) corresponding to a separate bank (e.g., two banks) to each bond pad 156 . Embodiments may additionally support expansion to more than four channels or more than two banks.

[0019] According to embodiments, the finer pitch of vias 157 achievable in the interposer compared to the package substrate 110 facilitates a narrower edge width W2 compared to edge width W1, and the overall size of the electronic package 100 is reduced compared to if the die stack 125 were directly wire-bonded to the organic package substrate 110.

[0020] Prefabricated interposer 150 according to embodiments can be fabricated using a variety of technologies, including organic, silicon, glass, and wire. Figure 3A illustrates a schematic cross-sectional side view of a silicon-based interposer 150 according to one embodiment. As shown, interposer 150 may include a silicon base substrate 151 and a plurality of through-silicon vias 153 extending through the silicon base substrate. Such an interposer 150 may additionally include a device layer 152 in which a plurality of active and / or passive devices may be formed. In this manner, functionality from the package substrate or die can be offloaded to interposer 150. For example, the active device(s) may be part of a buffer, repeater, or amplifier. Back-end-of-the-line (BEOL) build-up structures, including one or more metal wiring layers 159, a dielectric layer 155, and vias 157, may then be formed above the device layer, terminating at bond pads 156. As shown, solder bumps 158 may be placed onto backside contacts 154 for flip-chip connection to the package substrate.

[0021] FIG3B illustrates a schematic cross-sectional side view of an organic interposer 150 according to one embodiment. As shown, the organic interposer 150 may include a plurality of dielectric layers 155, metal wiring layers 159, and vias 157. The organic interposer may be fabricated similarly to the package substrate described in FIG1C , with a finer pitch for the vias 157.

[0022] 3C is a schematic cross-sectional side view diagram of a non-organic interposer 150 according to one embodiment. As shown, the non-organic interposer 150 may include a ceramic base substrate 161 (eg, glass, alumina, etc.).

[0023] Figure 3D is a schematic cross-sectional side view of an interposer 150 having vertical conductive lines according to one embodiment. For example, vertical conductive lines 160 may be bonded to bond pads 156 and pulled vertically, then encapsulated with a mold compound material 162, planarized, and solder bumps 158 applied.

[0024] It should be understood that the embodiments depicted in Figures 3A-3D are illustrative and may include any number of metal wiring layers and vias 157. Referring now to Figures 4-5, Figure 4 is a schematic top view illustration of an interposer 150 including bond pads 156 and wires 163 extending from the bond pads 156 and past the vias 157. It should be understood that these are the uppermost vias 157 in the interposer. As shown, for a given area of ​​the interposer 150, the bond pads 156 may be finger-shaped to accommodate bond wire 130 connections, and only so much space is available for vias 157. According to embodiments, it has been observed that if vias 157 remain the same size within the organic encapsulation substrate, there may be physical limitations on the available space for vias 157. Interposers 150 according to embodiments may be manufactured using different materials and / or equipment, allowing for finer via pitches and higher via densities. Referring now to Figure 5, an illustrative bottom view illustration of backside contacts 154 on the bottom side of the interposer is provided. As shown, the backside contacts 154 can be larger and spaced further apart than the landing pads 156 and / or the uppermost vias 157. Thus, the interposer 150 can be mounted to an organic package substrate via a flip chip and solder bumps 158.

[0025] Interposer 150 according to embodiments may include routing that can accommodate fine-pitch vias 157 escape and fan out wiring and backside contacts 154 for compatibility with available organic packaging substrates. The interposer may be limited to simple fan-out or, alternatively, may incorporate portions of a common packaging substrate, such as ground or power planes. As shown in Figures 4 and 5, the interposer may have the same number of backside contacts 154 on the backside as bond pads 156 on the frontside. In some embodiments, a greater number of backside contacts 154 may be present, such as with added logic or active devices. In some embodiments, the number of backside contacts 154 may be less than the number of bond pads 156. This can be achieved, for example, through power or ground consolidation, which reduces the number of bumps while allowing for larger vias within the interposer 150 stackup. Figure 6 is a schematic cross-sectional side view of interposer 150 including multiple metal wiring layers according to embodiments. Specifically, as shown, bond wires 130 are attached to bond pads 156. Wiring 163 extends from and over the topmost via 157. As shown, the density of vias 157 can be highest in the topmost via layer. The lower metal wiring layer can optionally include a ground plane 164, a power plane 166, etc. In the particular embodiment shown, multiple vias 157 can connect to the same ground plane 164 and backside contact 154. Lower-level vias 157 can also be wider due to space savings and fan-out. It should be understood that the illustration in Figure 6 is overly simplified. Furthermore, the interposer does not need to include a ground plane, power plane, etc., as these features can also be retained in the package substrate.

[0026] Referring now to Figures 7A-7F , schematic cross-sectional side view illustrations of a sequence for manufacturing an electronic package 100, including a plurality of bond wires 130 electrically connecting a die stack 125 to bond pads 156 of an interposer mounted on a package substrate 110, are provided according to one embodiment. As shown in Figure 7A , the process sequence may begin by surface mounting a plurality of interposers 150 onto the package substrate 110, for example by flip-chip bonding using solder bumps 158 to bond pads 112 (see Figure 1C ) of the package substrate 110. It should be understood that at this assembly stage, the package substrate 110 may be part of a panel substrate, and the individual packages have not yet been singulated. As shown in Figure 7B , a first set of die 120 are then stacked vertically on top of each other on the package substrate 110, followed by wire bonding of bond wires 130 to the die flanges and to the bond pads 156 of the interposer 150, as shown in Figure 7C . The sequence can then be repeated for the next die group, as shown in FIG7D, until a complete die stack 125 is provided and wirebonded, as shown in FIG7E. The die can then be encapsulated with a mold compound layer 140, followed by application of solder bumps 118 and singulation of the plurality of electronic packages 100, as shown in FIG7F.

[0027] Electronic packages according to embodiments may include various interposer 150 configurations. Figure 8 is a schematic cross-sectional side view of an electronic package 100 according to one embodiment, including a plurality of bond wires 130 electrically connecting a die stack 125 to bond pads 156 of a stacked interposer 150 mounted on a package substrate 110. In the illustrated embodiment, the electronic package includes a first interposer 150A and a second interposer 150B mounted on the first interposer 150A. A first and second plurality of bond wires 130 are electrically connected to corresponding sets of die 120 and the corresponding first and second interposers. As shown, the second interposer 150B can be mounted to the bond pads 156 of the first interposer using solder bumps 158. The second interposer 150B can optionally be taller than the first interposer 150A. In the illustrated configuration, the length of the bond wires 130 to the second interposer 150B is significantly reduced.

[0028] FIG9 is a schematic cross-sectional side view of an electronic package 100 according to one embodiment, including a plurality of bond wires 130 electrically connecting a die stack 125 to bond pads of a plurality of interposers mounted on a package substrate. The configuration of FIG9 is substantially similar to the configuration of FIG8 , except that a first interposer 150A and a second interposer 150B are mounted side-by-side on a package substrate 110. Similar to the description of FIG8 , the second (higher) interposer 150B can be wire-bonded to the top stacked die 120.

[0029] Interposers according to embodiments may have additional functionality. Referring now to FIG. 10 , a schematic cross-sectional side view of an electronic package 100 including an optical interconnect 170 according to one embodiment is illustrated. As shown, the optical interconnect 170 (such as an optical fiber) may be mounted alongside the interposer 150. In this case, the interposer may additionally include an optical transmitter or an optical detector aligned with the optical fiber for optical communication to / from the electronic package 100. Furthermore, the interposer may include an electrical-to-optical converter coupled to the optical transmitter and / or an optical-to-electrical converter coupled to the optical detector.

[0030] Thus far, embodiments have been described in which the die stack and interposer are supported by a package substrate. FIG11 is a schematic cross-sectional side view illustration of a substrate-less electronic package 100 according to one embodiment, including a plurality of bond wires 130 electrically connecting the die stack 125 to a plurality of bond pads on an interposer 150. As shown, a plurality of solder bumps 158 can be applied directly to the backside contacts 154 of the interposer 150 (see FIGS. 3A-3D ). Thus, electrical connections can be made directly to the interposer 150 on the bottom side of the electronic package 100. This package configuration can be manufactured using similar procedures.

[0031] Figures 12A through 12E are schematic cross-sectional side view illustrations of a sequence for fabricating a substrate-less electronic package 100 according to one embodiment, including a plurality of bond wires 130 electrically connecting a die stack 125 to bond pads of a plurality of interposers 150. It should be understood that while the processing sequence is shown with respect to the electronic package of Figure 11, this processing sequence can be used to fabricate substrate-less packages similar to any of the packages depicted and described herein. Referring now to Figure 12A, a plurality of interposers 150 can be mounted onto a carrier substrate 180, such as glass, metal, silicon, etc., which can be coated with adhesive tape. This can then be followed by mounting and wire bonding of the die stack 125, as shown in Figure 12B, followed by encapsulation with a mold compound layer 140, as shown in Figure 12C. At this point, the carrier substrate 180 and adhesive tape may be removed to expose the backside contacts 154 of the interposer (see FIGS. 3A-3D ), as shown in FIG. 12D , followed by application of solder bumps 158 and singulation of the plurality of substrate-less electronic packages 100 , as shown in FIG. 12E .

[0032] In the process of using various aspects of the embodiments, those skilled in the art will appreciate that combinations or variations of the above embodiments are possible to form a unitized finger-to-bump interposer package. Although the embodiments have been described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Instead, the specific features or acts disclosed should be understood as examples that can be used to illustrate the claims.

[0033] 100: Electronic packaging; packaging 102: Metal wiring layer 104:Through hole 105: dielectric layer 106: Core 108: Core through hole 109: Contact pad 110: packaging substrate 112: Bonding pad 114: Dorsal 116:Front 118:Solder bump 120: Grain 125: Die stacking 130:Joint wire 131: Ball joint 135: Die stacking 140: Molding compound layer 150:Intermediary layer 150A: First interposer 150B: Second interposer 151: Silicon base substrate 152: Device layer 153:Through Silicon Via 154: Dorsal contact 155: dielectric layer 156:Joint pad; Landing pad 157:Through hole 158:Solder bump 159: Metal wiring layer 160: Vertical wire 161: Ceramic base material 162: Molding compound material 163: Wiring 164: Ground plane 166: Power plane 170:Optical Interconnects 180: carrier substrate W1: Edge width W2: Edge width

Claims

1. An electronic package comprising: a die stack of a plurality of vertically stacked dies; a first interposer layer laterally adjacent to the die stack; a first plurality of bonding wires electrically connecting a first group of the plurality of vertically stacked dies to the first interposer layer; and a molding compound layer encapsulating the die stack, the first interposer layer, and the first plurality of bonding wires, wherein the die stack is supported by a package substrate, and the first interposer layer is mounted on the package substrate using a plurality of solder bumps.

2. The electronic package of claim 1, wherein the package substrate is an organic substrate.

3. The electronic package of claim 2, wherein the first interposer includes a via pitch that is finer than that of the organic substrate.

4. The electronic package of claim 3, wherein the first interposer comprises a silicon substrate.

5. The electronic package of claim 4 further includes a plurality of through-silicon vias extending through the silicon substrate.

6. The electronic package of claim 4, wherein the first interposer layer includes an active device.

7. The electronic package as claimed in claim 6, wherein the active device is part of a buffer, repeater, or amplifier.

8. The electronic package of claim 3, wherein the first interposer layer comprises a plurality of vertical conductors.

9. The electronic package of claim 3, wherein the first interposer comprises a ceramic substrate.

10. The electronic package of claim 1, further comprising: a second interposer layer mounted on the first interposer layer; and a second plurality of bonding wires, wherein a second set of the plurality of vertically stacked dies is electrically connected to the second interposer layer; wherein the molding compound layer encapsulates the second interposer layer and the second plurality of bonding wires.

11. The electronic package of claim 10, wherein the second interposer is higher than the first interposer.

12. The electronic package of claim 1, further comprising: a second interposer layer laterally adjacent to the first interposer layer; and a second plurality of bonding wires, which electrically connect a second set of the plurality of vertically stacked dies to the second interposer layer; wherein the molding compound layer encapsulates the second interposer layer and the second plurality of bonding wires.

13. The electronic package of claim 12, wherein the second interposer is higher than the first interposer.

14. The electronic package of claim 1 further includes an optical interconnect adjacent to the first interposer layer.

15. The electronic package of claim 14, wherein the optical interconnect includes an optical fiber.

16. The electronic package of claim 15, wherein the first interposer layer includes an optical transmitter or an optical detector.

17. The electronic package of claim 1, further comprising a plurality of solder bumps on a bottom side of the electronic package, wherein the plurality of solder bumps are in direct contact with the first interposer.

18. The electronic package of claim 1, wherein the chips are memory chips.

19. The electronic package of claim 18, wherein the electronic package contains at least four channels.

20. The electronic package of claim 1, wherein a pair of the first plurality of bonding wires is bonded to a first pair of bonding pads of the first interposer, and the first pair of bonding pads is electrically connected to a common back contact of the first interposer.

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