Semiconductor devices with improved leakage characteristics and methods for manufacturing the same

Abstract

This disclosure relates to a chip configured as an ISP, comprising a first region and a second region. The chip includes a first gate structure in the first region, the first gate structure being disposed around a first edge of a first active region and a second edge of a second active region, the first and second active regions extending along a first lateral direction and spaced apart from each other along the first lateral direction. The chip includes a second gate structure in the second region, the second gate structure being disposed around a third edge of a third active region and a fourth edge of a fourth active region, the third and fourth active regions extending along the first lateral direction and spaced apart from each other along the first lateral direction. The first gate structure has a first width along the first lateral direction, and the second gate structure has a second width along the first lateral direction, the first width being significantly smaller than the second width.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device with improved leakage current characteristics and a method for manufacturing the same. Prior Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density comes from the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] This disclosure relates to a semiconductor device comprising: a first active region, a second active region, a third active region, and a fourth active region, wherein the first active region to the fourth active region all extend along a first lateral direction, and wherein the first active region and the second active region are separated from each other by a first distance along the first lateral direction, and the third active region and the fourth active region are separated from each other by a second distance along the first lateral direction, the second distance being longer than the first distance; a first isolation structure inserted between the first active region and the second active region along the first lateral direction; a second isolation structure inserted between the third active region and the fourth active region along the first lateral direction; a first gate structure extending along a second lateral direction perpendicular to the first lateral direction and disposed on the first isolation structure; and a second gate structure extending along the second lateral direction and disposed on the second isolation structure; wherein a first overlap length along the first direction, measured from the edge of the first sidewall of the second gate structure toward the third active region, is configured to be less than a threshold, and a second overlap length along the first direction, measured from the edge of the second sidewall of the second gate structure toward the fourth active region, is also configured to be less than a threshold.

[0004] This disclosure also relates to a semiconductor device comprising: a first wafer operably configured as a CMOS image sensor (CIS) including a plurality of photodiodes; and a second wafer operably configured as an image signal processor (ISP) bonded to the first wafer; wherein the second wafer includes a first region and a second region disposed adjacent to each other along a first lateral direction; wherein the second wafer includes in the first region: a first gate structure extending along a second lateral direction perpendicular to the first lateral direction, wherein the first gate structure is disposed around a first edge of a first active region and a second edge of a second active region, the first active region and the second active region extending along the first lateral direction and being spaced apart from each other along the first lateral direction; wherein the second wafer includes in the first region: a second gate structure extending along the second lateral direction, wherein the second gate structure is disposed around a third edge of a third active region and a fourth edge of a fourth active region, the third active region and the fourth active region extending along the first lateral direction and being spaced apart from each other along the first lateral direction; and wherein the first gate structure has a first width along the first lateral direction, the second gate structure has a second width along the first lateral direction, the first width being significantly smaller than the second width.

[0005] This disclosure also relates to a method of manufacturing a semiconductor device, comprising: forming a first active region, a second active region, a third active region, and a fourth active region, wherein the first active region to the fourth active region all extend along a first lateral direction, and wherein the first active region and the second active region are separated from each other by a first distance along the first lateral direction, and the third active region and the fourth active region are separated from each other by a second distance along the first lateral direction, the second distance being longer than the first distance; forming a first isolation structure and a second isolation structure, the first isolation structure being inserted between the first active region and the second active region along the first lateral direction, and the second isolation structure being inserted between the third active region and the fourth active region along the first lateral direction; and forming a first gate structure and a second gate structure, the first gate structure extending along a second lateral direction perpendicular to the first lateral direction and disposed on the first isolation structure, and the second gate structure extending along the second lateral direction and disposed on the second isolation structure; wherein a first overlap length along the first direction, measured from the first sidewall of the second gate structure toward the edge of the third active region, is configured to be between -20 nanometers (nm) and 20 nm. Within a range of nm, and the second overlap length along the first direction, measured from the second sidewall of the second gate structure toward the edge of the fourth active region, is also configured to be within a range. Simple Explanation of the Diagram

[0006] The various aspects of this disclosure can be best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 shows an example schematic diagram of an image sensor device according to some embodiments.

[0008] Figure 2 shows another example schematic diagram of an image sensor device according to some embodiments.

[0009] Figure 3 shows an example top view or layout diagram of a portion of an image sensor device according to some embodiments.

[0010] Figures 4 and 5 show cross-sectional views of portions of the image sensor device of Figure 3 according to some embodiments.

[0011] Figure 6 shows another example top view of a portion of an image sensor device according to some embodiments.

[0012] Figure 7 shows a cross-sectional view of a portion of the image sensor device of Figure 6 according to some embodiments.

[0013] Figure 8 shows yet another example top view of a portion of an image sensor device according to some embodiments.

[0014] Figure 9 shows a cross-sectional view of a portion of the image sensor device of Figure 8 according to some embodiments.

[0015] Figure 10 shows a perspective view of a semiconductor device formed according to some embodiments based on the layout shown in Figure 3.

[0016] Figure 11 shows an example flowchart of a method for manufacturing a semiconductor device based on the layout shown in Figure 3, according to some embodiments.

[0017] Figures 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, and 31 show cross-sectional views of example semiconductor devices fabricated according to some embodiments through the method of Figure 11 at various manufacturing stages. Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference digits and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, prescribe relationships between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, this document uses spatially related terms such as "below," "under," "lower part," "above," "upper part," "top," and "bottom" to describe the relationship of one element or feature relative to another element(s) or feature(s) shown in the figure. These spatially related terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted accordingly.

[0020] Complementary metal-oxide-semiconductor (CMOS) image sensors are gaining popularity compared to traditional charge-coupled devices (CCDs). CMOS image sensors typically contain an array of image elements (sometimes called pixels) that utilize photosensitive CMOS circuitry to convert photons into electrons. Photosensitive CMOS circuitry typically includes photodiodes formed in a silicon substrate. When a photodiode is exposed to light, a charge is induced within it. Each pixel can generate electrons proportional to the amount of light falling on it when light from an object scene incident on it. These electrons are converted into a signal (e.g., voltage) within the pixel and further converted into a digital signal, which is typically processed by a dedicated integrated circuit (ASIC) or image signal processor (ISP).

[0021] A CMOS image sensor (CIS) (or simply CMOS sensor) may have a front side where multiple dielectric layers and interconnect layers are positioned to connect photodiodes in the substrate to peripheral circuitry. If light originates from the front side of the CMOS sensor, it is a front-side illumination (FSI) image sensor; otherwise, it is a rear-side illumination (BSI) sensor, with light incident on the rear side. For a BSI sensor, light can directly illuminate the photodiodes without being obstructed by the dielectric and interconnect layers located on the front side. This helps increase the number of photons converted into electrons and makes the CMOS image sensor more sensitive to light sources.

[0022] Based on the scaling trend of integrated density, the image sensor market is moving towards lower costs, higher image quality, and smaller camera module sizes. Typically, ISPs and CISs are initially manufactured as two separate substrates, dies, or other wafers, and then bonded together. ISPs generally contain two types of circuitry formed in regions of their respective substrates. For example, an ISP can contain various core circuits and various input / output (I / O) circuits, where typically the core circuitry is exponential bit circuitry, and the I / O circuitry refers to analog circuitry. The transistors of the core circuitry can operate at lower voltages (e.g., through a thinner gate dielectric layer), while the transistors of the analog circuitry can operate at higher voltages (e.g., through a thicker gate dielectric layer).

[0023] However, with scaling, the amount of leakage current generated by the analog circuitry (e.g., gate-induced drain leakage (GIDL) current) increases. This increased leakage current adversely affects the performance of the image sensor device; for example, the strength of observed random telegraph signals increases. These random telegraph signals are commonly referred to as noise in the image sensor device. Although existing image sensor devices and the methods used to manufacture them are generally sufficient for their intended purpose, they are not entirely satisfactory in some respects as devices continue to shrink.

[0024] This disclosure provides various embodiments of a semiconductor device that can be implemented as part of an image sensor device (e.g., an image sensor circuitry). The semiconductor device disclosed herein may include at least first and second circuits, corresponding to a core circuit and an input / output (I / O) circuit, respectively. In some embodiments, the core circuit and the I / O circuit may be formed in a first region and a second region of a single substrate, respectively. The core circuit and the I / O circuit may be electrically coupled to each other through a plurality of metallization layers or interconnect layers formed on the substrate. In some other embodiments, the core circuit and the I / O circuit may be formed on a first substrate and a second substrate, respectively. The core circuit and the I / O circuit may be electrically coupled to each other through a plurality of first metallization layers formed on the first substrate and a plurality of second metallization layers formed on the second substrate. Furthermore, to improve leakage characteristics while maintaining scaling, the transistors of the I / O circuit may be formed based on a combined (or coupled) edge gate structure (sometimes referred to as a combined polysilicon on oxide diffusion edge (CPODE) structure), wherein the CPODE structure has a minimum overlap length with adjacent active regions. For example, by controlling the overlap length to less than about 20 nanometers (nm) or even negative (e.g., reduced to about -20 nm), leakage (e.g., GIDL) current can be suppressed by up to about 40 times.

[0025] Figures 1 and 2 illustrate schematic diagrams of image sensor devices 100 and 200 according to various embodiments, respectively. Each of image sensor devices 100 and 200 may include a plurality of wafers (dies or substrates) bonded together, at least one of which may include a plurality of pixels operatively forming part of a CIS, and at least another wafer may include analog circuitry operatively forming part of an ISP. It should be understood that the schematic diagrams of Figures 1-2 are provided for illustrative purposes only, and therefore, each of image sensor devices 100 and 200 may include any of a variety of other elements while remaining within the scope of this disclosure.

[0026] In FIG1, the image sensor device 100 includes a first substrate 110 and a second substrate 120. In some embodiments, the first substrate 110 may include a CIS, and the second substrate 120 may include an ISP. The first substrate 110 and the second substrate 120 may be operatively coupled to each other through multiple interconnect layers or structures (e.g., contact pads, redistribution layers, bonding pads, add-ons, plug-ins, etc.). For simplicity, such interconnect layers / structures are not shown in FIG1.

[0027] CIS can comprise a grid or array of pixel or sensor elements fabricated on the first substrate 110. Pixels or sensor elements can be implemented as photodiodes connected to a transistor or plurality of transistors (which may be transmission transistors, reset transistors, source follower transistors, or select transistors), or simply referred to as photodiodes. Photodiodes can generate a signal related to the intensity or brightness of light striking the photodiode. Photodiodes can be pinned layer photodiodes containing PNP junctions. Non-pinned layer photodiodes can also be used. Any suitable photodiode can be used with the embodiments, and all such photodiodes are intended to be included within the scope of the embodiments. The first substrate 110 may also include multiple isolation regions to separate and isolate the various devices formed therein, and to further separate pixels from other logical regions of the sensor.

[0028] In some embodiments, the ISP may include core circuitry and I / O circuitry, which may be formed in regions 130 and 140 of the substrate 120, respectively. The core circuitry formed in region 130 may include at least one of the following: a signal processing section / circuit, a digital signal processor (DSP), a memory, or a selector circuit. Furthermore, the core circuitry may include registers, subtractors, etc., disposed within a digital-to-analog converter (ADC), and perform correlated double sampling (CDS) on the image signal converted to digital values. A transistor formed in region 130 is operatively used as the core circuitry for the aforementioned identification.

[0029] As a non-limiting example, the signal processing circuitry (of the core circuitry) can perform various types of signal processing on digital image data input from an ADC or read from memory. In the case that the digital image data is a color image, the signal processing section can convert the image data to YUV image data, RGB image data, etc. The DSP (of the core circuitry) can be used as a processing section that performs various types of processing through a learning model (sometimes called a "neural network computational model") created using a deep neural network (DNN), for example, by executing programs stored in memory.

[0030] On the other hand, the I / O circuit formed in region 140 may include at least one of the following: a portion of the ADC (e.g., a comparator, a counter), pixel circuitry, a row driver, a control section / circuit, a phase-locked loop (PLL) circuit, or a frequency divider circuit. The transistor formed in region 140 is operatively used as the aforementioned I / O circuitry for identification. For example, the pixel circuitry may read analog pixel signals from the CIS (formed on the first substrate 110), the row driver may drive the pixels of the CIS formed on the first substrate 110 (which are arranged in a two-dimensional grid in the row and column directions) row by row, the ADC's comparator and counter may convert the analog pixel signals read from the corresponding pixels into digital values, the PLL circuitry may synchronize data with externally input main clock signals, and the frequency divider circuitry may divide the frequency of the main clock to generate a low-frequency clock. The I / O circuitry may also include a reference voltage supply section disposed within the control section and configured to supply a reference voltage to the ADC's comparator.

[0031] In Figure 2, the image sensor device 200 includes a first substrate 210, a second substrate 220, and a third substrate 230. In some embodiments, the third substrate 230 may contain a CIS, the second substrate 220 may contain analog (or I / O) circuitry for an ISP, and the third substrate 210 may contain digital (or core) circuitry for the ISP. Substrates 210 to 230 may be operatively coupled to each other through multiple interconnect layers or structures (e.g., contact pads, redistribution layers, bonding pads, add-ons, plug-ins, etc.). For simplicity, such interconnect layers / structures are not shown in Figure 2. The I / O circuitry of the CIS, the ISP, and the core circuitry of the ISP formed in substrates 210, 220, and 230 are substantially similar to the circuitry discussed with respect to Figure 1, and therefore will not be discussed again.

[0032] Figure 3 illustrates a top view or layout diagram 300 for forming an example semiconductor device according to various embodiments. This example semiconductor device includes a plurality of first structures (e.g., a first active region, a first gate structure) for forming core circuitry in a first region of a substrate and a plurality of second structures (e.g., a second active region, a second gate structure) for forming I / O circuitry in a second region of the substrate. In the following discussion, such a semiconductor device is sometimes referred to as "semiconductor device 300".

[0033] In some aspects, the semiconductor device 300 may be a non-limiting implementation based on a layout configured for forming core circuitry and I / O circuitry on the substrate 120 (FIG. 1). However, it should be understood that the layout diagram of FIG. 3 is merely an example, and thus, while remaining within the scope of this disclosure, the substrate 120 including the core circuitry and I / O circuitry may be configured in any of a variety of other embodiments.

[0034] As shown in the figure, layout 300 includes a first region (hereinafter referred to as the "core region") configured for forming core circuitry on a substrate and a second region (hereinafter referred to as the "I / O region") configured for forming I / O circuitry on the substrate. Although the core region and the I / O region appear to be adjacent to each other along the X direction in Figure 3, it should be understood that the core region and the I / O region are not necessarily limited to being arranged opposite each other along a specific direction. In the core region, layout 300 includes a plurality of active regions 310 and 320 and a plurality of gate structures 330, 332 and 334; and in the I / O region, layout 300 includes a plurality of active regions 350 and 360 and a plurality of gate structures 370, 372 and 374. It should be understood that, within the scope of this disclosure, layout 300 may include any number of identical or other patterns in each core region and I / O region to form the corresponding active region or gate structure.

[0035] Active regions 310, 320, 350, and 360 may extend along a first lateral direction (e.g., the X direction), and gate structures 330, 332, 334, 370, 372, and 374 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction). In the core region, active regions 310 and 320 may be separated from each other by a spacing (S1) along the X direction, and active regions 350 and 360 may be separated from each other by a spacing (S2) along the X direction. In some embodiments, the spacing S1 is significantly shorter than the spacing S2.

[0036] In the core region, gate structures 330 and 334 can pass through active regions 310 and 320 respectively, while gate structure 332 can pass through both active regions 310 and 320. Specifically, gate structure 332 can cover the longitudinal end of active region 310 (e.g., by covering a portion of the top surface of active region 310 adjacent to one of the ends of active region 310, and by extending along the sidewall of active region 310 facing active region 320); and gate structure 332 can cover the longitudinal end of active region 320 (e.g., by covering a portion of the top surface of active region 320 adjacent to one of the ends of active region 320, and by extending along the sidewall of active region 320 facing active region 310). In other words, each of gate structures 330 and 334 can pass through a portion of the corresponding active region, and a pair of other portions are disposed on its own lateral side, while gate structure 332 can pass through each of adjacent (but spaced apart) active regions, and another portion is disposed on its own lateral side.

[0037] Similarly, in the I / O region, gate structures 370 and 374 may pass through active regions 350 and 360, respectively, while gate structure 372 may pass through both active regions 350 and 360. Specifically, gate structure 372 may cover the longitudinal end of active region 350 (e.g., by covering a portion of the top surface of active region 350 adjacent to one of the ends of active region 350, and by extending along the sidewall of active region 350 facing active region 360); and gate structure 372 may cover the longitudinal end of active region 360 (e.g., by covering a portion of the top surface of active region 360 adjacent to one of the ends of active region 360, and by extending along the sidewall of active region 360 facing active region 350). In other words, each of the gate structures 370 and 374 can pass through a portion of the corresponding active region, and a pair of other portions are disposed on its own side, while the gate structure 372 can pass through each of the adjacent (but spaced apart) active regions, and another portion is disposed on one of its own lateral sides.

[0038] Gate structures 330, 334, 370, and 374 may each correspond to an active (e.g., metallic or polysilicon) gate structure, while gate structures 332 and 372 may each correspond to a virtual (e.g., metallic or polysilicon) gate structure. For example, gate structures 330, 334, 370, and 374, together with the active regions they pass through, are operably configured to form functional transistors, while gate structures 332 and 372, even with the active regions they pass through, are operably not configured to form functional transistors. Gate structures 332 and 372 formed along the edge of at least one active region are sometimes referred to as CPODE structures. In some embodiments, active regions 310-320 and 350-360, and gate structures 330-334 and 370-374, may be formed along the main surface of the substrate and are sometimes referred to as part of a front-end process (FEOL).

[0039] As described above, the transistor formed by the active region and gate structure of layout 300 can each be configured as a fin field-effect transistor (FinFET) structure. However, layout 300 can be used to form other transistor structures, such as a gate-all-around (GAA) transistor structure. Furthermore, similar to layout 300, different layouts can be used to form transistors for core circuits and I / O circuits on substrate 120 in other transistor structures, which will be discussed in the examples of Figures 6-9 below.

[0040] In an embodiment of the FinFET structure, active regions 310, 320, 350, and 360 can each be formed as fin-like structures protruding from the front side of the substrate. Typically, active regions 310, 320, 350, and 360 can have the same material as the substrate. Active region 310 can have multiple fin-like structures extending in the X direction and arranged parallel to each other. Active regions 320, 350, and 360 can be similarly formed. Furthermore, the corresponding portions of the fin-like structures covered by each of the gate structures 330-334 and 370-374 remain unchanged, while other portions are replaced by multiple epitaxial structures.

[0041] The remaining portion of the fin structure can be configured as a channel for a corresponding transistor, and the epitaxial structure coupled to both ends of the channel (e.g., along the X direction) can be configured as a source / drain structure (or terminal) of the transistor, and the gate structure covering (e.g., bridging) the remaining portion of the fin structure can be configured as a gate terminal of the transistor. For example, active region 310 and gate structure 330 can form a plurality of first transistors (e.g., connected in parallel) in the core region; active region 320 and gate structure 334 can form a plurality of second transistors (e.g., connected in parallel) in the core region; active region 350 and gate structure 370 can form a plurality of first transistors (e.g., connected in parallel) in the I / O region; and active region 360 and gate structure 374 can form a plurality of second transistors (e.g., connected in parallel) in the I / O region.

[0042] In some embodiments, transistors formed in the core region can operate at lower supply voltages, while transistors formed in the I / O region can operate at higher supply voltages. At least for this purpose, gate structures 330 and 334 can have a width (W1) in the X direction, and gate structures 370 and 374 can have a width (W2) in the X direction, wherein width W1 is shorter than width W2. Therefore, gate structure 332 can have a width (W3) in the X direction, and gate structure 372 can have a width (W4) in the X direction, wherein width W3 is shorter than width W4. As a non-limiting example, width W1 can be about 16 nanometers (nm), while width W3 can be about 20 nm; width W2 can be about 320 nm, while width W4 can be between about 100 nm and 320 nm. Alternatively or additionally, the ratio of width W1 to width W3 can be characterized as about 80%, and the ratio of width W2 to width W4 can be characterized as between about 100% and about 320%.

[0043] Figures 4 and 5 show cross-sectional views of the semiconductor device 300 (Figure 3) according to various embodiments. For example, Figure 4 shows a cross-sectional view of the semiconductor device 300 cut along line AA (Figure 3); and Figure 5 shows a cross-sectional view of the semiconductor device 300 cut along line BB (Figure 3). Although only cross-sectional views in the I / O region are shown in Figures 4-5, it should be understood that the cross-sectional views in the core region (when formed based on layout 300) are substantially similar, and therefore will not be described further.

[0044] As shown in Figure 4, the fin-like structures of active region 350 (hereinafter referred to as "fin 350") and active region 360 (hereinafter referred to as "fin 360") are separated from each other, with an isolation structure 410 inserted between them. This isolation structure 410 can be formed to surround the corresponding lower portion of each fin-like structure of active regions 350-360, which can be better seen in Figure 5. Using this isolation structure 410 (e.g., formed of one or more dielectric materials), the transistors formed by fins 350 and 360 can be electrically isolated from each other. For example, the transistor formed by fin 350, gate structure 370, and epitaxial structure 420 and another transistor formed by fin 360, gate structure 374, and epitaxial structure 430 can be isolated through the isolation structure 410.

[0045] In the various embodiments disclosed herein, the gate structure 372 may be formed to further overlay the isolation structure 410. For example, in addition to covering a portion of the top surface of each fin 350-360 and extending along the sidewalls of each fin 350-360, the gate structure 372 may also have a bottom surface in contact with the isolation structure 410. Furthermore, in some embodiments (e.g., the illustrative example of FIG. 4), the epitaxial structure 420 formed in the fin 350 may extend laterally beneath the gate structure 372, and the epitaxial structure 430 formed in the fin 360 may extend laterally beneath the gate structure 372.

[0046] In other words, when viewed from above, there may be an overlap between the gate structure 372 and each of the "end" epitaxial structures 420 and 430. As indicated by symbolic arrow 421, the overlap can be measured from the sidewall of the gate structure 372 toward the edge of the active region 350 or 360, where such an edge of the active region 350 can be defined as the farthest point of the epitaxial structure 420 (between gate structures 370 and 372) from the gate structure 370, and such an edge of the active region 360 can be defined as the farthest point of the epitaxial structure 420 (between gate structures 374 and 372) from the gate structure 374. According to one aspect of this disclosure, such overlap can be optimized to be less than 20 nm in order to advantageously reduce GIDL current (e.g., from epitaxial structure 420 to epitaxial structure 430 and vice versa). Alternatively or additionally, the ratio of the overlap to the width of the gate structure 372 (W4) can be optimized to be less than about 14%.

[0047] Figure 6 shows a top view or layout diagram 600 for forming an example semiconductor device according to various embodiments, which includes multiple structures (e.g., active regions, gate structures) for forming circuitry. In the following discussion, such a semiconductor device may sometimes be referred to as "semiconductor device 600". Figure 7 shows a cross-sectional view of semiconductor device 600 cut along line AA. Layout 600 is configured to form the transistor in a planar structure, compared to layout 300 (Figure 3) for forming a transistor in a FinFET structure.

[0048] In some aspects, the semiconductor device 600 may be a non-limiting embodiment based on a layout configured for forming core circuitry or I / O circuitry on the substrate 120 (FIG. 1). However, it should be understood that the layout diagram of FIG. 6 is merely an example, and thus the substrate 120, which includes core circuitry and I / O circuitry, may be configured in any of a variety of other embodiments while remaining within the scope of this disclosure.

[0049] As shown in Figure 6, layout 600 includes active regions 610 and 620 and a plurality of gate structures 630, 632, and 634. It should be understood that, within the scope of this disclosure, layout 600 may include any number of identical or other patterns to form the respective active regions or gate structures. Active regions 610 and 620 may extend along a first lateral direction (e.g., the X direction), and gate structures 630, 632, and 634 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction).

[0050] Gate structures 630 and 634 can pass through active regions 610 and 620, respectively, while gate structure 632 can pass through both active regions 610 and 620. Specifically, gate structure 632 can cover the longitudinal end of active region 610 (e.g., through a portion of the top surface of active region 610 adjacent to one of its ends); and gate structure 632 can cover the longitudinal end of active region 620 (e.g., through a portion of the top surface of active region 620 adjacent to one of its ends). In other words, each of gate structures 630 and 634 can pass through a portion of its corresponding active region, and a pair of other portions are disposed on its own side, while gate structure 632 can pass through each of adjacent (but spaced apart) active regions, and another portion is disposed on one of its own lateral sides.

[0051] Gate structures 630 and 634 may each correspond to an active (e.g., metallic or polysilicon) gate structure, while gate structure 632 may correspond to a virtual (e.g., metallic or polysilicon) gate structure. For example, gate structures 630 and 634, together with the active regions they pass through, are operably configured to form functional transistors, while gate structure 632, even with the active regions it passes through, is operably not configured to form a functional transistor. Gate structure 632 is sometimes referred to as a CPODE structure. In some embodiments, active regions 610-620 and gate structures 630-634 may be formed along the main surface of the substrate and are sometimes referred to as part of a front-end process (FEOL).

[0052] As described above, the transistor formed by the active regions and gate structures of layout 600 can each be configured as a planar field-effect transistor structure. Active regions 610 and 620 can be separated from each other by a spacing (S) along the X direction. Gate structures 630 and 634 can have a width (W1) in the X direction, and gate structure 632 can have a width (W2) in the X direction. In one aspect (when the transistor formed by layout 600 is configured as part of a core circuit), the ratio of width W1 to width W2 can be characterized as approximately 80%. In another aspect (when the transistor formed by layout 600 is configured as part of an I / O circuit), the ratio of width W1 to width W2 can be characterized as between approximately 100% and approximately 320%.

[0053] As shown in Figure 7, active regions 610 (e.g., a first well in the substrate) and 620 (e.g., a second well in the substrate) are separated from each other, with an isolation structure 710 inserted between them. Such an isolation structure 710 can be formed around each active region 610-620. Using this isolation structure 710 (e.g., formed of one or more dielectric materials), transistors formed by active regions 610 and 620 can be electrically isolated from each other. For example, the isolation structure 710 can isolate a transistor formed by active region 610, gate structure 630, and epitaxial structure 720 from another transistor formed by active region 620, gate structure 634, and epitaxial structure 730.

[0054] In the various embodiments disclosed herein, the gate structure 632 may be formed over the isolation structure 710. For example, the gate structure 632 may have a bottom surface in contact with the isolation structure 710. Furthermore, in some embodiments (e.g., the illustrative example of FIG. 7), the epitaxial structure 720 formed in the active region 610 may extend laterally below the gate structure 632, and the epitaxial structure 730 formed in the active region 620 may extend laterally below the gate structure 632. In other words, when viewed from above, there may be an overlap between the gate structure 632 and each "end" epitaxial structure 720 and 730. The overlap can be measured from the sidewalls of the gate structure 632 toward the edges of the active regions 610 or 620. Such an edge of the active region 610 can be defined as the farthest point of the epitaxial structure 720 (between gate structures 630 and 632) from the gate structure 630, and such an edge of the active region 620 can be defined as the farthest point of the epitaxial structure 730 (between gate structures 634 and 632) from the gate structure 634. According to one aspect of this disclosure, such overlap can be optimized to be less than 20 nm in order to advantageously reduce GIDL current (e.g., from epitaxial structure 720 to epitaxial structure 730 and vice versa). Alternatively or additionally, the ratio of overlap to the width of gate structure 632 (W2) can be optimized to be less than about 14%.

[0055] Figure 8 shows a top view or layout diagram 800 for forming an example semiconductor device according to various embodiments, which includes multiple structures (e.g., active regions, gate structures) for forming circuitry. In the discussion below, such a semiconductor device may sometimes be referred to as "semiconductor device 800". Figure 9 shows a cross-sectional view of semiconductor device 800 cut along line AA. Layout 800 is configured to form the transistor in a mesa structure, compared to layout 300 (Figure 3) for forming a transistor in a FinFET structure.

[0056] In some aspects, the semiconductor device 800 may be a non-limiting implementation based on a layout configured for forming core circuitry or I / O circuitry on the substrate 120 (FIG. 1). However, it should be understood that the layout diagram of FIG. 8 is merely an example, and thus the substrate 120, which includes core circuitry and I / O circuitry, may be configured in any of a variety of other embodiments while remaining within the scope of this disclosure.

[0057] As shown in Figure 8, layout 800 includes active regions 810 and 820 and a plurality of gate structures 830, 832 and 834. It should be understood that, within the scope of this disclosure, layout 800 may include any number of identical or other patterns to form the respective active regions or gate structures. Active regions 810 and 820 may extend along a first lateral direction (e.g., the X direction), and gate structures 830, 832 and 834 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction).

[0058] Gate structures 830 and 834 can pass through active regions 810 and 820, respectively, while gate structure 832 can pass through both active regions 810 and 820. Specifically, gate structure 832 can cover the longitudinal end of active region 810 (e.g., by covering a portion of the top surface of active region 810 adjacent to one of the ends of active region 810 and extending along the sidewall of active region 810 facing active region 820); and gate structure 832 can cover the longitudinal end of active region 820 (e.g., by covering a portion of the top surface of active region 820 adjacent to one of the ends of active region 820 and extending along the sidewall of active region 820 facing active region 810). In other words, each of gate structures 830 and 834 can pass through a portion of the corresponding active region, and a pair of other portions are disposed on its own side, while gate structure 832 can pass through each of adjacent (but spaced apart) active regions, and another portion is disposed on one of its own lateral sides.

[0059] Gate structures 830 and 834 may each correspond to an active (e.g., metallic or polysilicon) gate structure, while gate structure 832 may correspond to a virtual (e.g., metallic or polysilicon) gate structure. For example, gate structures 830 and 834, together with the active regions they pass through, are operably configured to form functional transistors, while gate structure 832, even with the active regions it passes through, is operably not configured to form a functional transistor. Gate structure 832 is sometimes referred to as a CPODE structure. In some embodiments, active regions 810-820 and gate structures 830-834 may be formed along the main surface of the substrate and are sometimes referred to as part of a front-end process (FEOL).

[0060] As described above, the transistor formed by the active regions and gate structures of layout 800 can each be configured as a mesa structure. Active regions 810 and 820 can be spaced apart from each other by a distance (S) along the X direction. Gate structures 830 and 834 can have a width (W1) in the X direction, and gate structure 832 can have a width (W2) in the X direction. In one aspect (when the transistor formed by layout 800 is configured as part of a core circuit), the ratio of width W1 to width W2 can be characterized as approximately 80%. In another aspect (when the transistor formed by layout 800 is configured as part of an I / O circuit), the ratio of width W1 to width W2 can be characterized as being between approximately 100% and approximately 320%.

[0061] As shown in Figure 9, active regions 810 (e.g., a first mesa protruding from the substrate) and active regions 820 (e.g., a second mesa protruding from the substrate) are separated from each other, with an isolation structure 910 inserted between them. Compared to fin structures (e.g., 350 and 360 in Figures 3-5), the mesas can have a wider width extending in the Y direction. That is, compared to a FinFET with the same channel length or gate length (extending in the X direction), the transistor formed by the mesas can have a larger channel area controlled by its gate structure due to the wider channel width (extending in the Y direction). The isolation structure 910 can be formed around the lower part of each active region 810-820. Using this isolation structure 910 (e.g., formed of one or more dielectric materials), the transistors formed by the active regions 810 and 820 can be electrically isolated from each other. For example, the transistor formed by the active region 810, the gate structure 830 and the epitaxial structure 920 and another transistor formed by the active region 820, the gate structure 834 and the epitaxial structure 930 can be isolated through the isolation structure 910.

[0062] In the various embodiments disclosed herein, the gate structure 832 may be formed to further overlay the isolation structure 910. For example, in addition to covering a portion of the top surface of each mesa 810-820 and extending along the sidewalls of each mesa 810-820, the gate structure 832 may also have a bottom surface in contact with the isolation structure 910. Furthermore, in some embodiments (e.g., the illustrative example of FIG. 9), the epitaxial structure 920 formed in the active region 810 may extend laterally beneath the gate structure 832, and the epitaxial structure 930 formed in the active region 820 may extend laterally beneath the gate structure 832. In other words, when viewed from above, there may be an overlap between the gate structure 832 and each "end" epitaxial structure 920 and 930. The overlap can be measured from the edge of the sidewall of the gate structure 832 toward the active region 810 or 820. Such an edge of the active region 810 can be defined as the farthest point of the epitaxial structure 920 (between gate structures 830 and 832) from the gate structure 830, and such an edge of the active region 820 can be defined as the farthest point of the epitaxial structure 930 (between gate structures 834 and 832) from the gate structure 834. According to one aspect of this disclosure, such overlap can be optimized to be less than 20 nm in order to advantageously reduce GIDL current (e.g., from epitaxial structure 920 to epitaxial structure 930 and vice versa). Alternatively or additionally, the ratio of overlap to the width of gate structure 832 (W2) can be optimized to be less than about 14%.

[0063] In some embodiments, the transistors for the core circuitry and I / O circuitry of the ISP (e.g., formed on substrate 120, or formed on substrates 210 and 220 respectively) may be formed in the same transistor structure. In some other embodiments, the transistors for the core circuitry and I / O circuitry of the ISP (e.g., formed on substrate 120, or formed on substrates 210 and 220 respectively) may be formed in different transistor structures. For example, the transistor for the core circuitry may be formed in a FinFET structure (e.g., Figures 3-5), and the transistor for the I / O circuitry may be formed in a mesa structure (e.g., Figures 8-9). In another example, the transistor for the core circuitry may be formed in a FinFET structure (e.g., Figures 3-5), and the transistor for the I / O circuitry may be formed in a planar transistor structure (e.g., Figures 6-7). In yet another example, both the transistor for the core circuitry and the transistor for the I / O circuitry may be formed in a FinFET structure (e.g., Figures 3-5).

[0064] Figure 10 shows a perspective view of an example FinFET structure 1000 at an intermediate stage of manufacturing. In some embodiments, the FinFET structure 1000 may be formed based on the layout 300 shown in Figure 3. For example, the perspective view of Figure 10 may point to the stage of forming fins in the core region and I / O region of the substrate, respectively, which may occur before the formation of the isolation structure or the gate structure. It should be noted that the perspective view of Figure 10 is provided for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0065] For example, the FinFET structure 1000 includes a substrate 1002 having a first region 1002A and a second region 1002B, which may correspond to a core region and an I / O region, respectively. In the core region 1002A, the FinFET structure 1000 includes a plurality of fins 1010 and a plurality of fins 1020, each of which protrudes above the substrate 1002 in the Z direction and extends in the X direction; and in the I / O region 1002B, the FinFET structure 1000 includes a plurality of fins 1050 and a plurality of fins 1060, each of which protrudes above the substrate 1002 in the Z direction and extends in the X direction. Fins 1010 and 1020 in core region 1002A can be separated by a spacing (S1) in the X direction, and fins 1050 and 1060 in I / O region 1002B can be separated by a spacing (S2) in the X direction, wherein the spacing S1 is smaller than the spacing S2.

[0066] In various embodiments, at least a first gate structure (e.g., a CPODE structure) extending along the Y direction can be formed to pass through fins 1010 and 1020. For example, such a first CPODE structure can extend along the space between fins 1010 and 1020. At least a second gate structure (e.g., another CPODE structure) extending along the Y direction can be formed to pass through fins 1050 and 1060. For example, such a second CPODE structure can extend along the space between fins 1050 and 1060.

[0067] A perspective view of Figure 10 is provided for reference to illustrate multiple cross-sectional views in subsequent figures corresponding to other manufacturing stages. For example, a cross-sectional view cut along line AA (or a plane extending in the Y and Z directions) extends along the longitudinal axis of the gate structure of the FinFET structure 1000, and a cross-sectional view cut along line BB (or a plane extending in the X and Z directions) extends along the longitudinal axis of fins 1010 to 1060, and along, for example, the direction of current between the source / drain structures of the corresponding transistor. For clarity, subsequent figures (e.g., Figures 12-31) refer to these cross-sectional views.

[0068] Figure 11 illustrates a flowchart of a method 1100 for forming a transistor structure having one or more CPODE structures according to one or more embodiments of the present disclosure. For example, at least some operations of method 1100 can be used to form a FinFET structure 1000. It should be noted that method 1100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional operations may be provided before, during, and after method 1100 of Figure 11, and only some other operations are briefly described herein. In some embodiments, the operations of method 1100 may be associated, respectively, with cross-sectional views of the example FinFET structure 1000 at various manufacturing stages shown in Figures 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, and 31, which will be discussed in further detail below.

[0069] Corresponding to operation 1102 in Figure 11, Figure 12 is a cross-sectional view of the FinFET structure 1000 including a semiconductor substrate 1002 provided at one of the various stages of manufacturing. The cross-sectional view in Figure 11 is cut along section AA shown in Figure 10.

[0070] As shown in Figure 12, substrate 1002 may include regions 1002A and 1002B, which are configured to form core circuitry and I / O circuitry, respectively. Substrate 1002 may be a semiconductor substrate, such as a bulk semiconductor or semiconductor-on-insulator (SOI) substrate, which may be doped (e.g., using p-type or n-type dopants) or undoped. Substrate 1002 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 1002 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0071] Corresponding to operation 1104 in Figure 11, Figure 13 is a cross-sectional view of a FinFET structure 1000 formed at one of the various stages of manufacturing, which includes multiple active regions 1004 in region 1002A and multiple active regions 1006 in region 1002B. The cross-sectional view of Figure 13 is cut along section AA shown in Figure 10.

[0072] In some embodiments, active region 1004 may correspond to the combination of active regions 310 and 320 shown in the layout of FIG3, and active region 1006 may correspond to the combination of active regions 350 and 360 shown in the layout of FIG3. As discussed below (e.g., operations 1106 and 1108), such active regions 1004 and 1006 may each be divided into multiple parts (e.g., fins). Before being divided into multiple parts, layout 300 may include a layout pattern connecting each active region 310 to a corresponding (e.g., laterally aligned) active region 320. Similarly, layout 300 may include a layout pattern connecting each active region 350 to a corresponding (e.g., laterally aligned) active region 360.

[0073] Referring to Figure 13, active regions 1004 and 1006 can extend along the X direction, wherein adjacent regions in active region 1004 are separated from each other along the Y direction, and adjacent regions in active region 1006 are separated from each other along the Y direction. In some embodiments, active regions 1004 and 1006 can be formed by patterning substrate 1002 using techniques such as photolithography and etching. For example, a mask layer comprising a pad oxide layer and an overlying pad nitride layer is formed on substrate 1002. The pad oxide layer can be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer can serve as an adhesion layer between substrate 1002 and the overlying pad nitride layer. The pad nitride layer can be formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc., or combinations thereof. For example, the pad nitride layer can be formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0074] The mask layer can be patterned using photolithography. Typically, photolithography utilizes a photoresist material (not shown), which is deposited, irradiated (exposed), and developed to remove a portion of the photoresist. The remaining photoresist protects the underlying material (e.g., the mask layer in this example) from subsequent processing steps (e.g., etching). For example, the photoresist material is used to pattern a pad oxide layer and a pad nitride layer to form a patterned mask.

[0075] A patterned mask is then used to pattern the exposed portions of the substrate 1002 to form trenches (or openings), each trench being interposed between adjacent active regions. In some embodiments, the trenches can be formed by etching the substrate 1002 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. In some embodiments, the trenches can be stripes that are parallel to each other and closely spaced from each other (viewed from top). In some embodiments, each trench can be continuous and can surround a corresponding active region.

[0076] Active regions 1004 and 1006 can be patterned using any suitable method. For example, active regions 1004 and 1006 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with, for example, smaller pitches than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can subsequently be used to pattern the active regions.

[0077] Corresponding to operation 1106 in Figure 11, Figure 14 is a cross-sectional view of a FinFET structure 1000 formed at one of the various stages of manufacturing, which includes fins 1010 and fins 1020. The cross-sectional view of Figure 14 is cut along section BB shown in Figure 10.

[0078] As shown in Figure 14 (and in the perspective view of Figure 10), the active region 1004 in the core region 1002A can be cut or otherwise patterned to form fins 1010 and 1020. Fins 1010 and 1020 are spaced apart from each other along the X direction by a spacing (S1). In some embodiments, each of fins 1010 and 1020 can be formed by multiple gate structures passing through it to form a corresponding transistor.

[0079] In some embodiments, fins 1010 and 1020 can be formed by etching the active region 1004 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. For example, each active region 1004 can be diced to form at least one pair of fins 1010 and 1020 aligned with each other and spaced apart along the X direction. The etching can be anisotropic. Fins 1010 and 1020 can be patterned by any suitable method. For example, fins 1010 and 1020 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing patterns to be created with a pitch, for example, smaller than that achievable using a single direct photolithography process in other ways.

[0080] Corresponding to operation 1108 in Figure 11, Figure 15 is a cross-sectional view of a FinFET structure 1000 formed at one of the various stages of manufacturing, which includes fins 1050 and fins 1060. The cross-sectional view of Figure 15 is cut along section BB shown in Figure 10.

[0081] As shown in Figure 15 (and in the perspective view of Figure 10), the active region 1006 in the I / O region 1002B can be cut or otherwise patterned to form fins 1050 and 1060. Fins 1050 and 1060 are spaced apart from each other along the X direction by a spacing (S2). In some embodiments, each of fins 1050 and 1060 can be formed by multiple gate structures passing through it to form a corresponding transistor.

[0082] In some embodiments, fins 1050 and 1060 can be formed by etching the active region 1006 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. For example, each active region 1006 can be cut to form at least one pair of fins 1050 and 1060 aligned with each other and spaced apart along the X direction. Fins 1050 and 1060 can be patterned by any suitable method. For example, fins 1050 and 1060 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing patterns to be created with a pitch, for example, smaller than that achievable using a single direct photolithography process in other ways.

[0083] Corresponding to operation 1110 in Figure 11, Figures 16 and 17 are cross-sectional views of a FinFET structure 1000 formed at one of the various stages of manufacturing, which includes multiple isolation structures 1070. The cross-sectional view in Figure 16 corresponds to the core region 1002A, and the cross-sectional view in Figure 17 corresponds to the I / O region 1002B. The cross-sectional views in Figures 16-17 are cut along section BB shown in Figure 10, respectively.

[0084] As shown in Figures 16-17, isolation structures 1070 may surround the lower portion of each fin 1010 to 1060. Isolation structures 1070 may be oxides (e.g., silicon oxide, nitrides, etc.) or combinations thereof, and may be formed via high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material (e.g., oxide)), or combinations thereof. Other isolation dielectrics and / or other formation processes may be used. In this example, isolation structures 1070 all comprise silicon oxide formed by an FCVD process. The silicon oxide may fill trenches between adjacent fins. Once the silicon oxide is deposited, an annealing process may be performed. After the deposition process, (e.g., dry) etching may be performed to recess the deposited silicon oxide, thereby forming the isolation structure 1070 surrounding the lower portion of each fin 1010 to 1060. For example, dry etching involves using an etchant gas to anisotropically etch deposited silicon oxide. The etchant gas contains at least one of the following: chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), or nitrogen trifluoride (NF3).

[0085] Corresponding to operation 1112 in Figure 11, Figures 18 and 19 are cross-sectional views of a FinFET structure 1000 formed at one of the various stages of manufacturing. This FinFET structure 1000 includes multiple virtual gate structures 1072, 1074, and 1076, and multiple virtual gate structures 1078, 1080, and 1082. The cross-sectional view in Figure 18 corresponds to the core region 1002A, and the cross-sectional view in Figure 19 corresponds to the I / O region 1002B. The cross-sectional views in Figures 18 and 19 are each cut along section BB shown in Figure 10.

[0086] As shown in Figure 18, virtual gate structures 1072 and 1074, extending along the Y direction, pass through the non-edge portions of fins 1010 and 1020, respectively, while virtual gate structure 1076, also extending along the Y direction, passes through the corresponding edge portions of fins 1010 and 1020. Similarly, as shown in Figure 19, virtual gate structures 1078 and 1080, extending along the Y direction, pass through the non-edge portions of fins 1050 and 1060, respectively, while virtual gate structure 1082, also extending along the Y direction, passes through the corresponding edge portions of fins 1050 and 1060.

[0087] Thus, the virtual gate structure 1076 can have a sidewall whose lower portion contacts the corresponding sidewalls of the fins 1010 and 1020 facing each other along the X direction; and the virtual gate structure 1082 can have a sidewall whose lower portion contacts the corresponding sidewalls of the fins 1050 and 1060 facing each other along the X direction. Furthermore, the virtual gate structure 1076 can have a bottom surface that contacts the top surface of the isolation structure 1070 inserted between the fins 1010 and 1020, and the virtual gate structure 1082 can have a bottom surface that contacts the top surface of the isolation structure 1070 inserted between the fins 1050 and 1060.

[0088] In some other embodiments, although not shown, the virtual gate structure 1076 may also include portions extending laterally to each other in the X direction, and the virtual gate structure 1082 may also include portions extending laterally to each other in the X direction. Thus, in addition to extending along the sidewalls of fins 1010 and 1020 respectively, the virtual gate structure 1076 may also have portions covering portions of the top surfaces of fins 1010 and 1020 respectively; and in addition to extending along the sidewalls of fins 1050 and 1060 respectively, the virtual gate structure 1082 may also have portions covering portions of the top surfaces of fins 1050 and 1060 respectively.

[0089] According to various embodiments disclosed herein, virtual gate structures 1072 and 1074, as well as virtual gate structures 1078 and 1080, can each be replaced with active gate structures or reused as active gate structures, while virtual gate structures 1076 and 1082 can remain as virtual gate structures. As disclosed herein, a virtual gate structure can refer to a gate structure not operatively configured to control or modularize the amount of current flowing through a corresponding transistor channel, and an active gate structure can refer to a gate structure operatively configured to control or modularize the amount of current flowing through a corresponding transistor channel.

[0090] In this manufacturing stage (operation 1112), in some embodiments, the virtual gate structures 1072 to 1082 may each include a virtual gate dielectric and a virtual gate. To form the virtual gate structures 1072 to 1082, a dielectric layer is formed on fins 1010-1020 and 1050-1060. The dielectric layer can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, multilayers thereof, and can be deposited or thermally grown. Next, a gate layer is formed on the dielectric layer, and a masking layer is formed on the gate layer. The gate layer can be deposited on the dielectric layer and then planarized, for example, through CMP. The masking layer can be deposited on the gate layer. The gate layer can be formed of, for example, polycrystalline silicon, but other materials can also be used. The masking layer can be formed of, for example, silicon nitride. After forming layers (e.g., dielectric layer, gate layer, and masking layer), suitable photolithography and etching techniques can be used to pattern the masking layer to form a mask. Then, the pattern of the mask can be transferred to the gate layer and dielectric layer by suitable etching techniques to form the corresponding virtual gate dielectric and the corresponding virtual gate of the virtual gate structures 1072 to 1082, as shown in the figure.

[0091] Corresponding to operation 1114 in Figure 11, Figures 20, 21, and 22 are each cross-sectional views of a FinFET structure 1000 formed at one of the various stages of manufacturing. This FinFET structure 1000 includes multiple layers of gate spacers (e.g., 1081, 1083, 1085). The cross-sectional view in Figure 20 corresponds to the core region 1002A, and the cross-sectional views in Figures 21 and 22 correspond to the I / O region 1002B. The cross-sectional views in Figures 20-22 are each cut along section BB shown in Figure 10.

[0092] Referring first to FIG. 20, the gate spacer 1081 formed by dielectric layers 1084 and 1086 can be formed to extend along the sidewalls of at least each of the virtual gate structures 1072 to 1076 in the core region 1002A. In some embodiments, dielectric layer 1084 can have an L-shaped profile around a corner formed by the sidewalls of each of the virtual gate structures 1072 to 1076 and the top surface of fins 1010 or 1020. For example, dielectric layer 1084 can have a first L-shaped profile around a corner formed by one of the sidewalls of the virtual gate structure 1076 and the top surface of fin 1010, and a second L-shaped profile around a corner formed by one of the sidewalls of the virtual gate structure 1076 and the top surface of fin 1020. Dielectric layer 1086 can be disposed on dielectric layer 1084, and each of dielectric layers 1084 can be formed as a conformal layer with a thickness equal to or less than 3 nm. Therefore, dielectric layer 1086 may follow the contour of dielectric layer 1084. In some embodiments, dielectric layer 1084 may be formed of silicon carbonitride (SiOCN), and dielectric layer 1086 may be formed of silicon nitride (SiN).

[0093] Referring now to FIG. 21, the gate spacer 1083 formed by dielectric layers 1084-1086 and an additional dielectric layer 1090 can be formed to extend along the sidewalls of each of the virtual gate structures 1078 to 1082 in at least the I / O region 1002B. In some embodiments, dielectric layer 1084 may have an L-shaped profile around a corner formed by the sidewalls of each of the virtual gate structures 1078 to 1082 and the top surface of fins 1050 or 1060. For example, dielectric layer 1084 may have a first L-shaped profile around a corner formed by one sidewall of the virtual gate structure 1082 and the top surface of fin 1050, and a second L-shaped profile around a corner formed by the other sidewall of the virtual gate structure 1082 and the top surface of fin 1060. An additional dielectric layer 1090 may be formed on dielectric layer 1084 to extend along each sidewall of the virtual gate structures 1078 to 1082. Furthermore, the thickness of the dielectric layer 1090 can be controlled (e.g., between about 4 nm and about 6 nm) to allow lateral portions of the underlying dielectric layer 1084 to extend beyond the dielectric layer 1090. A dielectric layer 1086 can be disposed above the dielectric layer 1090 to extend along the sidewalls of each of the virtual gate structures 1078 to 1082. In some embodiments, the dielectric layer 1090 can be formed of plasma-enhanced oxide (PEOX).

[0094] Referring then to FIG22, the gate spacer 1085 formed by dielectric layers 1084-1090 can be formed to extend along the sidewalls of each of the virtual gate structures 1078 to 1082 in at least the I / O region 1002B. In some embodiments, dielectric layer 1084 may have an L-shaped profile around a corner formed by the sidewalls of each of the virtual gate structures 1078 to 1082 and the top surface of fins 1050 or 1060. For example, dielectric layer 1084 may have a first L-shaped profile around a corner formed by one sidewall of the virtual gate structure 1082 and the top surface of fin 1050, and a second L-shaped profile around a corner formed by the other sidewall of the virtual gate structure 1082 and the top surface of fin 1060. Dielectric layer 1086 may be disposed on dielectric layer 1084 to extend along each sidewall of the virtual gate structures 1078 to 1082. An additional dielectric layer 1090 may be formed on top of the dielectric layer 1086 to extend along each sidewall of the virtual gate structures 1078 to 1082. Furthermore, the thickness of the dielectric layer 1090 (e.g., between about 4 nm and about 6 nm) may be controlled to allow it to fall onto the side of the underlying dielectric layer 1086.

[0095] In some embodiments, the gate spacer 1081 in the core region 1002A (FIG. 20) and the gate spacer 1083 in the I / O region 1002B (FIG. 21) can be formed simultaneously by performing at least some of the following processes: a first deposition process (e.g., thermal oxidation, chemical vapor deposition (CVD), etc.) for forming a first uniform thickness layer having the same material as the dielectric layer 1084 and covering the virtual gate structures 1072-1082 and fins 1010-1020 and 1050-1060; and a second deposition process (e.g., thermal oxidation, chemical vapor deposition (CVD), etc.) for forming a second uniform thickness layer having the same material as the dielectric layer 1090 and covering the virtual gate structures 1072-1082 and fins 1010- 1020 and 1050-1060; a first etching process for removing portions of dielectric layer 1090 covering the top surfaces of virtual gate structures 1072-1082 and fins 1010-1020 and 1050-1060; covering virtual gate structures 1078-1082 (with their respective dielectric layers 1090) in I / O region 1002B, wherein a second etching process is used to remove dielectric layer 1090 in core region 1002A; and a third deposition process (e.g., thermal oxidation, chemical vapor deposition (CVD) etc.) for forming a third uniform thickness layer having the same material as dielectric layer 1086 and covering virtual gate structures 1072-1082 and fins 1010-1020 and 1050-1060.

[0096] In some embodiments, the gate spacer 1081 in the core region 1002A (FIG. 20) and the gate spacer 1085 in the I / O region 1002B (FIG. 22) can be formed simultaneously by performing at least some of the following processes: a first deposition process (e.g., thermal oxidation, chemical vapor deposition (CVD), etc.) for forming a first uniform thickness layer having the same material as the dielectric layer 1084 and covering the virtual gate structures 1072-1082 and fins 1010-1020 and 1050-1060; and a second deposition process (e.g., thermal oxidation, chemical vapor deposition (CVD), etc.) for forming a second uniform thickness layer having the same material as the dielectric layer 1086 and covering the virtual gate structures 1072-1082 and fins 1010- 1020 and 1050-1060; a third deposition process (e.g., thermal oxidation, chemical vapor deposition (CVD) etc.) for forming a third uniform thickness layer having the same material as the dielectric layer 1090 and covering the virtual gate structures 1072-1082 and fins 1010-1020 and 1050-1060; a first etching process for removing portions of the dielectric layer 1090 covering the top surfaces of the virtual gate structures 1072-1082 and the top surfaces of the fins 1010-1020 and 1050-1060; and covering the virtual gate structures 1078-1082 (with their respective dielectric layers 1090) in the I / O region 1002B, wherein a second etching process is used to remove the dielectric layer 1090 in the core region 1002A.

[0097] Corresponding to operation 1116 in Figure 11, Figures 23 and 24 are cross-sectional views of a FinFET structure 1000 formed at one of the various stages of manufacturing. This FinFET structure 1000 includes multiple source / drain structures (e.g., 1091A, 1091B, 1091C, 1091D, 1091E, 1091F, 1091G, 1091H). The cross-sectional view in Figure 23 corresponds to the core region 1002A, and the cross-sectional view in Figure 24 corresponds to the I / O region 1002B. The cross-sectional views in Figures 23-24 are cut along section BB shown in Figure 10, respectively.

[0098] As shown in Figure 23, source / drain structures 1091A to 1091D are formed in the recess of an adjacent fin 1010 or 1020 corresponding to the virtual gate structures 1072-1076. For example, source / drain structures 1091B and 1091C are formed in the recesses of fins 1020 and 1010, respectively. Source / drain structures 1091B and 1091C are disposed on opposite sides of the virtual gate structure 1076, with gate spacers 1081 inserted therebetween. Similarly, in Figure 24, source / drain structures 1091E to 1091H are formed in the recess of an adjacent fin 1050 or 1060 corresponding to the virtual gate structures 1078-1082. For example, source / drain structures 1091F and 1091G are formed in the recesses of fins 1060 and 1050, respectively. Source / drain structures 1091F and 1091G are disposed on opposite sides of the virtual gate structure 1082, wherein gate spacers 1083 or 1085 are inserted therebetween. In some embodiments, the recesses are formed by an anisotropic etching process, for example, using the virtual gate structure as an etching mask, but any other suitable etching process may also be used.

[0099] Source / drain structures 1091A to 1091H are formed by epitaxially growing semiconductor materials (hereinafter referred to as "epitaphedral source / drain structures 1091A to 1091H") in a recess using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or combinations thereof. Epitaxial source / drain structures 1091A to 1091H may have a surface protruding from the top surface of the fin and may have small facets. Epitaxial source / drain structures 1091A to 1091H may be implanted with dopants and subsequently annealed. Source / drain structures 1091A to 1091H may have an impurity (e.g., dopant) concentration in the range of about 1 × 10¹⁹ cm⁻³ to about 1 × 10²¹ cm⁻³. P-type impurities (e.g., boron or indium) can be implanted into the source / drain structure of a P-type transistor. N-type impurities (e.g., phosphorus or arsenide) can be implanted into the source / drain structure of an N-type transistor. In some embodiments, the epitaxial source / drain structure can be in-situ doped during its growth. Alternatively or additionally, epitaxial source / drain structures 1091A to 1091H of different conductivity types can have corresponding shapes. For example, an n-type epitaxial source / drain structure can have a heart-shaped shape with a V-shaped bottom surface and a relatively curved top surface, and a p-type epitaxial source / drain structure can have a cupcake-shaped shape with a flat bottom surface and a relatively flat top surface, which will be further illustrated, for example, in Figures 29-31.

[0100] Referring again to Figure 4, which defines the overlap between the gate structure and the epitaxial (source / drain) structure, with the gate spacer formed along the sidewall of the dummy gate structure, the overlap can be reduced to approximately -20 nm. Alternatively or additionally, the ratio of the overlap to the width of the dummy gate structure (e.g., 1082) can be optimized to be as low as approximately -14%. For example, in Figure 24, by controlling the thickness of the gate spacers 1083 / 1085, the aforementioned defined overlap (as indicated by symbolic arrow 1093, measured from the sidewall of the dummy gate structure 1082 to the farthest point of the epitaxial source / drain structure 1091F) can have a negative value.

[0101] Corresponding to operation 1118 in Figure 11, Figures 25 and 26 are cross-sectional views of a FinFET structure 1000 formed at one of the various stages of manufacturing, which includes an interlayer dielectric (ILD) 1094. The cross-sectional view of Figure 25 corresponds to the core region 1002A, and the cross-sectional view of Figure 26 corresponds to the I / O region 1002B. The cross-sectional views of Figures 25-26 are each cut along section BB shown in Figure 10.

[0102] In some embodiments, a contact etch stop layer (CESL) may be formed on the structure prior to the formation of ILD 1094. The CESL can be used as an etch stop layer in subsequent etch processes and may contain suitable materials such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may be formed by suitable formation methods such as CVD, PVD, or combinations thereof. Next, ILD 1094 is formed on the CESL and on the virtual gate structures 1072-1082. In some embodiments, ILD 1094 is formed from a dielectric material such as silicon oxide, phospholipid glass (PSG), borosilicate glass (BSG), boron-doped phospholipid glass (BPSG), or undoped silicate glass (USG), and may be deposited by any suitable method (e.g., CVD, PECVD, or FCVD). After the formation of ILD 1094, an optional dielectric layer may be formed on ILD 1094. The dielectric layer can serve as a protective layer to prevent or reduce the loss of ILD 1094 during subsequent etching processes. The dielectric layer can be formed from suitable materials such as silicon nitride or silicon carbonitride using appropriate methods such as CVD, PECVD, or FCVD. After forming the dielectric layer, a planarization process (e.g., CMP) can be performed to achieve a horizontal upper surface of the dielectric layer. CMP can also remove the masking of the patterned virtual gate structures 1072-1082 and the portion of the CESL disposed above the virtual gate structures 1072-1082. After the planarization process, the upper surface of the dielectric layer is flush with the upper surface of the virtual gate structures 1072-1082.

[0103] Corresponding to operation 1120 in Figure 11, Figures 27 and 28 are cross-sectional views of a FinFET structure 1000 formed at one of the various stages of manufacturing. This FinFET structure 1000 includes multiple active / virtual gate structures (e.g., 2702, 2704, 2706, 2802, 2804, 2806). The cross-sectional view in Figure 27 corresponds to the core region 1002A, and the cross-sectional view in Figure 28 corresponds to the I / O region 1002B. The cross-sectional views in Figures 27-28 are each cut along section BB shown in Figure 10.

[0104] As shown in Figure 27, gate structures 2702, 2704, and 2706 can be formed by replacing virtual gate structures 1072, 1074, and 1076 respectively. In one embodiment, gate structures 2702 to 2706 can replace virtual gate structures 1072 to 1076 respectively, wherein gate structures 2702-2704 are each used as active gate structures, and gate structure 2706 is still used as a virtual gate structure. In another embodiment, gate structures 2702 and 2704 can replace virtual gate structures 1072 and 1074 respectively, wherein the original virtual gate structure 1076 remains unchanged. Thus, gate structures 2702-2704 are each used as active gate structures, and gate structure 2706 (which is the original virtual gate structure 1076) is still used as a virtual gate structure.

[0105] Similarly, in Figure 28, gate structures 2802, 2804, and 2806 can be formed by replacing virtual gate structures 1078, 1080, and 1082, respectively. In one embodiment, gate structures 2802 to 2806 can replace virtual gate structures 1078 to 1082, respectively, wherein gate structures 2802-2804 each serve as active gate structures, and gate structure 2806 remains as a virtual gate structure. In another embodiment, gate structures 2802 and 2804 can replace virtual gate structures 1078 and 1080, respectively, wherein the original virtual gate structure 1082 remains unchanged. Thus, gate structures 2802-2804 each serve as active gate structures, and gate structure 2806 (which is the original virtual gate structure 1082) remains as a virtual gate structure.

[0106] If the original virtual gate structure is replaced, gate structures 2702 to 2806 may each comprise a gate dielectric layer, a metal gate layer, and one or more other layers (e.g., capping layer, adhesive layer), which are not shown for clarity. The gate dielectric layer comprises silicon oxide, silicon nitride, or multiples thereof. In example embodiments, the gate dielectric layer comprises a high-k dielectric material, and in these embodiments the gate dielectric material may have a k value greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. The gate dielectric layer may be formed by methods including molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. The thickness of the gate dielectric layer may be between about 8 angstroms (Å) and about 20 angstroms.

[0107] A metallic gate layer is formed on a corresponding gate dielectric layer. In some embodiments, the metallic gate layer may be a P-type work function layer, an N-type work function layer, multiple layers thereof, or a combination thereof. Therefore, the metallic gate layer is sometimes referred to as a work function layer. For example, the metallic gate layer may be an N-type work function layer. In the discussion herein, the work function layer may also be referred to as a work function metal. Example P-type work function metals that may be included in the gate structure for a P-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Example N-type work function metals that may be included in the gate structure for an N-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof.

[0108] The work function value is related to the material composition of the work function layer; therefore, the work function layer material is selected to adjust its work function value, thereby achieving the target threshold voltage Vt in the device to be formed. The work function layer can be deposited through CVD, physical vapor deposition (PVD), ALD, and / or other suitable processes. For example, the thickness of a P-type work function layer can be between about 8 Å and about 15 Å, and the thickness of an N-type work function layer can be between about 15 Å and about 30 Å.

[0109] Corresponding to operation 1122 in Figure 11, Figures 29, 30, and 31 are each cross-sectional views of a FinFET structure 1000 formed at one of the various stages of manufacturing, which includes multiple interconnect structures. Although the cross-sectional views of Figures 29 to 31 each correspond to I / O region 1002B, it should be understood that the FinFET structure 1000 in core region 1002A may include similar interconnect structures. The cross-sectional views of Figures 29-31 are each taken along section BB shown in Figure 10.

[0110] As shown in Figure 29, the FinFET structure 1000 includes interconnect structures 2902, 2904, 2906, 2908, 2910, 2912, 2914, and 2916. Interconnect structure 2902 can electrically couple the source / drain structure 1091F to interconnect structure 2910; interconnect structure 2906 can electrically couple the source / drain structure 1091G to interconnect structure 2914; interconnect structure 2904 can electrically couple the dummy gate structure 2806 to interconnect structure 2912; and interconnect structure 2908 can electrically couple the active gate structure 2802 to interconnect structure 2916. In some embodiments, when an adjacent functional transistor is configured as N-type, interconnect structure 2912 electrically coupled to dummy gate structure 2806 can be connected to a positive voltage (e.g., 1V, 2V, 3V). Therefore, GIDL leakage can be further suppressed.

[0111] Although shown as a single portion, each of interconnect structures 2902 to 2908 may have multiple interconnect structures interconnected to each other. For example, interconnect structure 2902 may have a first via structure (sometimes referred to as VD) penetrating the ILD to contact the source / drain structure 1091F and a second via structure (sometimes referred to as V0) connecting the first via structure to interconnect structure 2910 (sometimes referred to as M1). In another example, interconnect structure 2904 may have a first contact structure (sometimes referred to as MP) and a second via structure (e.g., V0) to connect the first via structure to interconnect structure 2912 (e.g., M1). Interconnect structures (VD, MP) are sometimes referred to as portions of intermediate process online (MEOL) processing, and interconnect structures (V0, M1) are sometimes referred to as portions of back-end process online (BEOL) processing. The aforementioned interconnect structures may each contain tungsten (W), copper (Cu), cobalt (Co), or combinations thereof, and may be formed using a dual damascene process.

[0112] As shown in Figure 30, the FinFET structure 1000 includes interconnect structures 3002, 3004, 3006, 3008, 3010, 3012, and 3014. Interconnect structure 3002 can electrically couple the source / drain structure 1091F to interconnect structure 3008; interconnect structure 3004 can electrically couple the source / drain structure 1091G to interconnect structure 3012; the virtual gate structure 2806 can be floating, for example, electrically isolated from the interconnect structure 3010 disposed thereon; and interconnect structure 3006 can electrically couple the active gate structure 2802 to interconnect structure 3014.

[0113] Although shown as a single portion, each of interconnect structures 3002 to 3006 may have multiple interconnect structures interconnected to each other. For example, interconnect structure 3002 may have a first via structure (sometimes referred to as VD) penetrating the ILD to contact the source / drain structure 1091F and a second via structure (sometimes referred to as V0) connecting the first via structure to interconnect structure 3008 (sometimes referred to as M1). In another example, interconnect structure 3006 may have a first contact structure (sometimes referred to as MP) and a second via structure (e.g., V0) to connect the first via structure to interconnect structure 3014 (e.g., M1). Interconnect structures (VD, MP) are sometimes referred to as portions of intermediate process online (MEOL) processing, and interconnect structures (V0, M1) are sometimes referred to as portions of back-end process online (BEOL) processing. The aforementioned interconnect structures may each contain tungsten (W), copper (Cu), cobalt (Co), or combinations thereof, and may be formed using a dual damascene process.

[0114] As shown in Figure 31, the FinFET structure 1000 includes interconnect structures 3102, 3106, 3108, 3110, 3112, 3114, 3116, and 3118. Interconnect structure 3102 can electrically couple the source / drain structure 1091F to interconnect structure 3114; interconnect structure 3108 can electrically couple the virtual gate structure 2806 to the source / drain structure 1091G through interconnect structure 3106, wherein interconnect structure 3108 is also coupled to interconnect structure 3116 through interconnect structure 3110; and interconnect structure 3112 can electrically couple the active gate structure 2802 to interconnect structure 3118.

[0115] Although shown as a single portion, each of interconnect structures 3102 and 3112 may have multiple interconnect structures connected to each other. For example, interconnect structure 3102 may have a first via structure (sometimes referred to as VD) that penetrates the ILD to contact the source / drain structure 1091F and a second via structure (sometimes referred to as V0) that connects the first via structure to interconnect structure 3114 (sometimes referred to as M1). In another example, interconnect structure 3112 may have a first contact structure (sometimes referred to as MP) and a second via structure (e.g., V0) to connect the first via structure to interconnect structure 3118 (e.g., M1). In some embodiments, interconnect structure 3108 may contact the dummy gate structure 2806 and further extend laterally to contact interconnect structure 3106. In some embodiments, interconnect structure 3108 electrically coupled to dummy gate structure 2806 may be connected to a positive voltage (e.g., 1V, 2V, 3V) when the adjacent functional transistor is configured as N-type. Therefore, GIDL leakage can be further suppressed. Interconnect structure 3108 may sometimes be referred to as MP. The interconnect structure (VD, MP) is sometimes referred to as the intermediate process (MEOL) processing portion, and the interconnect structure (V0, M1) is sometimes referred to as the back-end process (BEOL) processing portion. These interconnect structures may each contain tungsten (W), copper (Cu), cobalt (Co), or combinations thereof, and can be formed using a dual damascene process.

[0116] In one aspect of this disclosure, a semiconductor device is disclosed. The semiconductor device includes: a first active region, a second active region, a third active region, and a fourth active region, wherein the first active region to the fourth active region all extend along a first lateral direction, and wherein the first active region and the second active region are separated from each other by a first distance along the first lateral direction, and the third active region and the fourth active region are separated from each other by a second distance along the first lateral direction, the second distance being longer than the first distance; a first isolation structure inserted between the first active region and the second active region along the first lateral direction; a second isolation structure inserted between the third active region and the fourth active region along the first lateral direction; a first gate structure extending along a second lateral direction perpendicular to the first lateral direction and disposed on the first isolation structure; and a second gate structure extending along the second lateral direction and disposed on the second isolation structure. The first overlap length along the first direction, measured from the edge of the first sidewall of the second gate structure toward the edge of the third active region, is configured to be less than a threshold, and the second overlap length along the first direction, measured from the edge of the second sidewall of the second gate structure toward the edge of the fourth active region, is also configured to be less than a threshold.

[0117] In another aspect of this disclosure, a semiconductor device is disclosed. The semiconductor device includes: a first wafer operably configured as a CMOS image sensor (CIS) comprising a plurality of photodiodes; and a second wafer operably configured as an image signal processor (ISP) bonded to the first wafer. The second wafer includes a first region and a second region disposed adjacent to each other along a first lateral direction. The second wafer includes, in the first region: a first gate structure extending along a second lateral direction perpendicular to the first lateral direction, wherein the first gate structure is disposed around a first edge of a first active region and a second edge of a second active region, the first active region and the second active region extending along the first lateral direction and being spaced apart from each other along the first lateral direction. The second wafer includes, in the first region: a second gate structure extending along the second lateral direction, wherein the second gate structure is disposed around a third edge of a third active region and a fourth edge of a fourth active region, the third active region and the fourth active region extending along the first lateral direction and being spaced apart from each other along the first lateral direction. The first gate structure has a first width along the first lateral direction, and the second gate structure has a second width along the first lateral direction, wherein the first width is significantly smaller than the second width.

[0118] In another aspect of this disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes: forming a first active region, a second active region, a third active region, and a fourth active region, wherein the first active region to the fourth active region all extend along a first lateral direction, and wherein the first active region and the second active region are separated from each other by a first distance along the first lateral direction, and the third active region and the fourth active region are separated from each other by a second distance along the first lateral direction, the second distance being longer than the first distance; forming a first isolation structure and a second isolation structure, the first isolation structure being inserted between the first active region and the second active region along the first lateral direction, and the second isolation structure being inserted between the third active region and the fourth active region along the first lateral direction; and forming a first gate structure and a second gate structure, the first gate structure extending along a second lateral direction perpendicular to the first lateral direction and disposed on the first isolation structure, and the second gate structure extending along the second lateral direction and disposed on the second isolation structure. The first overlap length along the first direction, measured from the first sidewall of the second gate structure toward the edge of the third active region, is configured to be in the range of approximately -20 nanometers (nm) and approximately 20 nm, and the second overlap length along the first direction, measured from the second sidewall of the second gate structure toward the edge of the fourth active region, is also configured to be within the range.

[0119] As used herein, the terms “about” and “approximately” generally refer to the value of a given quantity that can vary depending on the specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term “about” can refer to the value of a given quantity that varies, for example, within a range of 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0120] The features of several embodiments have been outlined above to enable those skilled in the art to better understand the detailed description that follows. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various alterations, substitutions, and changes can be made to this document without departing from the spirit and scope of this disclosure.

[0121] 100, 200: Image sensor device 110: First substrate 120: First substrate 130, 140: Area 210: First substrate / substrate 220: Second substrate / substrate 230: Second substrate / substrate 300: Semiconductor Devices / Layout 310, 320: Active Area 350, 360: Active area / fin 330, 334, 370, 374: Gate structure 332, 372: Gate structure / CPODE structure 410: Isolation Structure 420, 430: Epitaxial structure 421: Arrow 600: Layout Diagram / Top View / Semiconductor Device 610, 620: Active Area 630, 634: Gate structure 632: Gate structure / CPODE structure 710: Isolation Structure 720, 730: Epitaxial structure 800: Layout Diagram / Top View / Semiconductor Device 810, 820: Active Area 830, 834: Gate structure 832: Gate structure / CPODE structure 910: Isolation Structure 920, 930: Epitaxial structure 1000: FinFET Structure 1002:Substrate 1002A: First Zone / Core Zone 1002B: Second Region / I / O Region 1004, 1006: Active Region 1010, 1020, 1050, 1060: Fins 1070: Isolation Structure 1072, 1074, 1076, 1078, 1080, 1082: Virtual gate structure 1081, 1083, 1085: Gate spacers 1084, 1086, 1090: Dielectric layer 1091A~1091H: Source / Drain Structure / Epilithographic Source / Drain Structure 1093: Arrow 1094: Interlayer Dielectric (ILD) 1100: Method 1102~1122: Operation 2702, 2704, 2706, 2802, 2804, 2806: Active / Virtual Gate Structure 2902, 2904, 2906, 2908, 2910, 2912, 2914, 2916: Interconnection Structure 3002, 3004, 3006, 3008, 3010, 3012, 3014: Interconnection Structure 3102, 3106, 3108, 3110, 3112, 3114, 3116, 3118: Interconnection Structure CIS: CMOS Image Sensor ISP: Image Signal Processor S1, S2: Spacing Vt: Target threshold voltage W1, W2, W3, W4: Width AA, BB: Line / Cross Section

Claims

1. A semiconductor device comprising: a first active region, a second active region, a third active region, and a fourth active region, wherein the first active region to the fourth active region extend along a first lateral direction, and wherein the first active region and the second active region are separated from each other by a first distance along the first lateral direction, and the third active region and the fourth active region are separated from each other by a second distance along the first lateral direction, the second distance being longer than the first distance; a first isolation structure inserted between the first active region and the second active region along the first lateral direction; a second isolation structure inserted between the third active region and the fourth active region along the first lateral direction; a first gate structure extending along a second lateral direction perpendicular to the first lateral direction and disposed on the first isolation structure; and a second gate structure extending along the second lateral direction and disposed on the second isolation structure. A first overlap length along the first lateral direction, measured from a first sidewall of the second gate structure toward an edge of the third active region, is configured to be less than a threshold, and a second overlap length along the first lateral direction, measured from a second sidewall of the second gate structure toward an edge of the fourth active region, is also configured to be less than the threshold; wherein the threshold is in the range between -20 nanometers (nm) and 20 nm.

2. The semiconductor device as claimed in claim 1, wherein the threshold is 20 nanometers (nm).

3. The semiconductor device as claimed in claim 1, wherein the threshold is 0 nm.

4. The semiconductor device of claim 3 further comprises: a first spacer and a second spacer extending along the first sidewall and the second sidewall of the second gate structure, respectively; wherein the first spacer and the second spacer are each formed of plasma-enhanced oxide (PEOX).

5. The semiconductor device of claim 4, further comprising: a first dielectric layer in contact with each of a first sidewall and a second sidewall of the first gate structure; a second dielectric layer in contact with each of the first sidewall and the second sidewall of the second gate structure; a third dielectric layer in contact with the first dielectric layer; and a fourth dielectric layer coupled to the second dielectric layer through the first spacer or the second spacer; wherein the first dielectric layer and the second dielectric layer are each formed of silicon carbonitride oxide (SiOCN), and the third dielectric layer and the fourth dielectric layer are each formed of silicon nitride (SiN).

6. The semiconductor device of claim 4, further comprising: a first dielectric layer in contact with each of the first sidewall and the second sidewall of the first gate structure; a second dielectric layer in contact with each of the first sidewall and the second sidewall of the second gate structure; a third dielectric layer in contact with the first dielectric layer; and a fourth dielectric layer in contact with the second dielectric layer, wherein the first spacer or the second spacer is in contact with the fourth dielectric layer; wherein the first dielectric layer and the second dielectric layer are each formed of silicon carbonitride oxide (SiOCN), and the third dielectric layer and the fourth dielectric layer are each formed of silicon nitride (SiN).

7. The semiconductor device of claim 1, wherein the first gate structure has a first width along the first lateral direction, and the second gate structure has a second width along the first lateral direction, wherein the second width is significantly greater than the first width.

8. The semiconductor device of claim 7, wherein the ratio of the second width to the second distance is between 1.3 and 0.

7.

9. A semiconductor device comprising: a first wafer operably configured as a CMOS image sensor (CIS) including a plurality of photodiodes; and a second wafer operably configured as an image signal processor (ISP) and coupled to the first wafer; wherein the second wafer includes a first region and a second region disposed adjacent to each other along a first lateral direction; wherein the second wafer includes in the first region: a first gate structure extending along a second lateral direction perpendicular to the first lateral direction, wherein the first gate structure is disposed around a first edge of a first active region and a second edge of a second active region, the first active region and the second active region extending along the first lateral direction and spaced apart from each other along the first lateral direction; wherein the second wafer includes in the first region: A second gate structure extends along the second lateral direction, wherein the second gate structure is disposed around a third edge of a third active region and a fourth edge of a fourth active region, the third active region and the fourth active region extending along the first lateral direction and separated from each other along the first lateral direction; and wherein the first gate structure has a first width along the first lateral direction, the second gate structure has a second width along the first lateral direction, the first width being smaller than the second width; wherein a first overlap length along the first lateral direction, measured from a first sidewall of the second gate structure toward the third edge of the third active region, is less than a threshold, and a second overlap length along the first lateral direction, measured from a second sidewall of the second gate structure toward the fourth edge of the fourth active region, is also less than the threshold; wherein the threshold is in the range between -20 nanometers (nm) and 20 nm.

10. A method of manufacturing a semiconductor device, comprising: forming a first active region, a second active region, a third active region, and a fourth active region, wherein the first active region to the fourth active region all extend along a first lateral direction, and wherein the first active region and the second active region are separated from each other by a first distance along the first lateral direction, and the third active region and the fourth active region are separated from each other by a second distance along the first lateral direction, the second distance being longer than the first distance; forming a first isolation structure and a second isolation structure, the first isolation structure being inserted between the first active region and the second active region along the first lateral direction, and the second isolation structure being inserted between the third active region and the fourth active region along the first lateral direction; and forming a first gate structure and a second gate structure, the first gate structure extending along a second lateral direction perpendicular to the first lateral direction and disposed on the first isolation structure, and the second gate structure extending along the second lateral direction and disposed on the second isolation structure; The first overlap length along the first lateral direction, measured from the edge of the first sidewall of the second gate structure toward the edge of the third active region, is configured to be in the range of -20 nm and 20 nm, and the second overlap length along the first lateral direction, measured from the edge of the second sidewall of the second gate structure toward the edge of the fourth active region, is also configured to be within this range.

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