Display device

Abstract

According to an embodiment, the display device of the present invention includes: a substrate; a first inorganic insulating layer; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer and overlapping the periphery of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers disposed on the first inorganic insulating layer in a peripheral region and arranged in a first direction along an end of the substrate; and a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layers. The second inorganic insulating layer has a plurality of first openings overlapping the second metal layers, and the organic insulating layer has: a plurality of second openings overlapping the first openings for contact between the first metal layers and the second metal layers; and a plurality of first slots formed between adjacent second openings for contact between the second inorganic insulating layers and the first inorganic insulating layers.

Description

Technical Field

[0001] The present invention relates to a display device. Prior Technology

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. These display elements include: pixel circuits containing thin-film transistors, a lower electrode connected to the pixel circuits, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer also includes functional layers such as hole transport layers or electron transport layers. In such display devices, techniques to suppress reliability degradation are needed. Summary of the Invention

[0003] Generally speaking, according to the embodiment, the display device includes: a substrate; a first inorganic insulating layer disposed above the substrate, spanning a display area for displaying an image and a peripheral area surrounding the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the display area and on the organic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer and overlapping the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral area and arranged in a first direction along the end of the substrate; and a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layers.

[0004] The aforementioned second inorganic insulating layer has a plurality of first openings overlapping the aforementioned second metal layer, and the aforementioned organic insulating layer has: a plurality of second openings overlapping the aforementioned first openings for contact between the aforementioned first metal layer and the aforementioned second metal layer; and a plurality of first slots formed between adjacent aforementioned second openings for contact between the aforementioned second inorganic insulating layer and the aforementioned first inorganic insulating layer.

[0005] Furthermore, according to another embodiment, the display device includes: a substrate; a first inorganic insulating layer disposed above the substrate, spanning a display area for displaying an image and a peripheral area surrounding the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer in the display area; a second inorganic insulating layer disposed on the organic insulating layer and overlapping the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral area and arranged in a first direction along an end of the substrate; and a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layers. The second inorganic insulating layer has a third opening that spans and overlaps the plurality of first metal layers.

[0006] Furthermore, according to another embodiment, the display device includes: a substrate; a first inorganic insulating layer disposed above the substrate, spanning a display area for displaying an image and a peripheral area surrounding the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer in the display area; a second inorganic insulating layer disposed on the organic insulating layer and overlapping the periphery of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; and a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral area, arranged in a first direction along an end of the substrate. The organic insulating layer in the peripheral area has a slot formed between the lower electrode and the first metal layer along the first direction.

[0007] Based on this configuration, a display device capable of suppressing the reduction of reliability is provided. Simple Explanation of the Diagram

[0008] Figure 1 is a diagram showing an example of the configuration of the display device in the first embodiment. Figure 2 shows an example of the layout of subpixels. Figure 3 is a schematic cross-sectional view of the display device along line III-III in Figure 2. Figure 4 is a plan view showing one example of the configuration of a region including a plurality of pads of the display device shown in Figure 1. Figure 5 is a plan view showing one example of the configuration of a region including the plurality of pads of the display device shown in Figure 1. Figure 6 shows a plan view of the metal layer shown in Figure 5. Figure 7 is a cross-sectional view of the display device along line VII-VII in Figure 5. Figure 8 is a cross-sectional view of the display device along line VIII-VIII in Figure 5. Figure 9 is a plan view showing one of the configuration examples of the regions of the display device including the comparative example and the plurality of pads. Figure 10 is a cross-sectional view of the display device along line XX in Figure 9. Figure 11 is a cross-sectional view of the display device along line XI-XI in Figure 9. Figure 12 is a plan view showing one example of the configuration of a region comprising a plurality of pads of the display device of the second embodiment. Figure 13 is a cross-sectional view of the display device along line XIII-XIII in Figure 12. Figure 14 is a cross-sectional view of the display device along line XIV-XIV in Figure 12. Figure 15 is a plan view showing one example of the configuration of a region comprising a plurality of pads of the display device of the third embodiment. Figure 16 is a plan view showing one example of the configuration of a plurality of pads in the display device of the third embodiment. Figure 17 is a cross-sectional view of the display device along line XVII-XVII in Figure 16. Figure 18 is a cross-sectional view of the display device along line XVIII-XVIII in Figure 16. Figure 19 is a plan view showing one example of the configuration of the area of ​​the pad of the display device in the fourth embodiment. Figure 20 is a cross-sectional view of the display device along line XX-XX in Figure 19. Figure 21 is a cross-sectional view of the display device along line XXI-XXI in Figure 19. Implementation

[0009] Several embodiments will be described with reference to the illustrations. The disclosed examples are merely one instance, and appropriate modifications that can be readily conceived by those skilled in the art to maintain the spirit of the invention are of course included within the scope of this invention.

[0010] Furthermore, while the drawings may schematically show the width, thickness, and shape of various parts compared to the actual form in order to make the explanation clearer, they are ultimately only one example and are not intended to limit the interpretation of the invention. Also, in this specification and the drawings, elements that perform the same or similar functions to the elements described in the existing drawings are given the same reference numerals, and repeated detailed descriptions are appropriately omitted.

[0011] Furthermore, in the diagram, to facilitate understanding as needed, mutually orthogonal X-axis, Y-axis, and Z-axis are shown. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. The view of various elements parallel to the third direction Z is called a top view.

[0012] In the following explanation, "overlap" refers not only to the situation where other elements overlap with the element that becomes the object from the third direction Z, but also to the situation where they overlap from the opposite direction Z. Furthermore, "overlap" refers not only to the situation where the elements that become the object are directly connected to each other, but also to the situation where the elements that become the object are separated from each other, or to the situation where there are other elements between the elements that become the object.

[0013] The display devices in each embodiment are organic electroluminescent display devices with organic light-emitting diodes (OLEDs) as display elements, and can be installed in various electronic devices such as TVs, personal computers, in-vehicle machines, tablet terminals, smartphones, and mobile phone terminals.

[0014] [First Implementation Form] Figure 1 is a diagram showing an example of the configuration of the display device DSP according to this embodiment. The display device DSP includes a display panel PNL. The display panel PNL has an insulating substrate 10. The substrate 10 can be glass or a flexible resin film.

[0015] In this embodiment, the substrate 10 has a rectangular shape that is elongated in the second direction Y when viewed from above. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle, and may also be other shapes such as a square, a circle, or an ellipse.

[0016] The display panel PNL has a display area DA for displaying images and a peripheral area SA surrounding the display area DA on the substrate 10. The display area DA has a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y.

[0017] Pixel PX comprises a plurality of subpixels SP. In one example, pixel PX comprises subpixels SP1 of color 1, SP2 of color 2, and SP3 of color 3. The colors 1, 2, and 3 are all different from each other. Furthermore, pixel PX may comprise subpixels SP1, SP2, SP3 and / or subpixels SP of other colors such as white that replace any of subpixels SP1, SP2, SP3.

[0018] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are, for example, switching elements made of thin-film transistors.

[0019] The gate electrode of pixel switch 2 is connected to scan line GL. One of the source electrode and drain electrode of pixel switch 2 is connected to signal line SL, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source electrode and drain electrode is connected to power line PL and capacitor 4, and the other is connected to the anode of display element 20.

[0020] Furthermore, the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may include more thin-film transistors and capacitors. Display element 20 is an organic light-emitting diode (OLED), sometimes referred to as an organic EL element.

[0021] The display device DSP has a plurality of pads PD in the peripheral area SA. The plurality of pads PD constitute, for example, pads for a touch panel. The plurality of pads PD are arranged in one direction along the panel end PNLE. Here, the end includes the end and the area nearby. The panel end PNLE includes the end of the substrate 10. In this embodiment, the direction along the end of the substrate 10 corresponds to the first direction X.

[0022] Each pad PD extends along the second direction Y, but is not limited thereto. For example, a portion of a plurality of pad PDs may extend in an oblique direction. The pad PDs may be composed of, for example, a plurality of metal layers as described later. Such a plurality of pad PDs may be electrically connected to, for example, a flexible printed circuit board (FPC) indicated by a single-point chain line.

[0023] Figure 2 shows an example of the layout of subpixels SP1, SP2, and SP3. In the example shown in Figure 2, subpixels SP2 and SP3 are arranged in the second direction Y. Subpixels SP1 and SP2 are arranged in the first direction X, and subpixels SP1 and SP3 are arranged in the first direction X.

[0024] With sub-pixels SP1, SP2, and SP3 arranged in this manner, within the display area DA, there are rows of sub-pixels SP2 and SP3 alternately arranged in the second direction Y, and rows of multiple sub-pixels SP1 arranged in the second direction Y. These rows are alternately arranged in the first direction X.

[0025] Furthermore, the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example shown in Figure 2. As another example, the sub-pixels SP1, SP2, and SP3 of each pixel PX can also be arranged sequentially along the first direction X.

[0026] An insulating layer 5 and a partition wall 6 are disposed in the display area DA. The insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. Sometimes, the insulating layer 5 with openings AP1, AP2, and AP3 is referred to as a rib.

[0027] The partition wall 6 overlaps with the insulating layer 5 when viewed from above. The partition wall 6 is formed in a grid shape surrounding the openings AP1, AP2, and AP3. Similarly to the insulating layer 5, the partition wall 6 may have openings in the sub-pixels SP1, SP2, and SP3.

[0028] Sub-pixels SP1, SP2, and SP3, as display elements 20, respectively include display elements 201, 202, and 203. The display element 201 of sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with the opening AP1. The peripheral portions of each of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap with the insulating layer 5 when viewed from above. Here, the peripheral portion includes the edge and the area nearby.

[0029] The display element 202 of sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with the opening AP2. The periphery of each of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlaps with the insulating layer 5 when viewed from above.

[0030] The display element 203 of sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with the opening AP3. The periphery of each of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlaps with the insulating layer 5 when viewed from above.

[0031] In the example shown in Figure 2, the shapes of the lower electrodes LE1, LE2, and LE3 are represented by dashed lines, and the shapes of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are represented by dotted chain lines. Furthermore, the shapes of the lower electrodes, organic layers, and upper electrodes shown in the figure may not accurately reflect their shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to the anode of the display element, for example. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of the display element or the common electrode.

[0033] The lower electrode LE1 is connected to pixel circuit 1 of sub-pixel SP1 via contact hole CH1 (shown in Figure 1). The lower electrode LE2 is connected to pixel circuit 1 of sub-pixel SP2 via contact hole CH2. The lower electrode LE3 is connected to pixel circuit 1 of sub-pixel SP3 via contact hole CH3.

[0034] In the example shown in Figure 2, the areas of openings AP1, AP2, and AP3 are all different. The area of ​​opening AP1 is larger than that of opening AP2, and the area of ​​opening AP2 is larger than that of opening AP3. In other words, the area of ​​electrode LE1 exposed from opening AP1 is larger than that of electrode LE2 exposed from opening AP2, and the area of ​​electrode LE2 exposed from opening AP2 is larger than that of electrode LE3 exposed from opening AP3.

[0035] Figure 3 is a schematic cross-sectional view of the display device DSP along line III-III in Figure 2. The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Figure 1, as well as various wiring such as scan lines GL, signal lines SL, and power lines PL.

[0036] The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 is disposed on the circuit layer 11. The insulating layer 12 has the function of planarizing the unevenness caused by the circuit layer 11. The insulating layer 12 is an organic insulating layer.

[0037] Lower electrodes LE1, LE2, and LE3 are disposed on insulating layer 12 and spaced apart from each other. Insulating layer 5 is disposed on insulating layer 12 and lower electrodes LE1, LE2, and LE3. Insulating layer 5 is an inorganic insulating layer. In this embodiment, insulating layer 5 is equivalent to a second inorganic insulating layer.

[0038] The opening AP1 of the insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered by the insulating layer 5.

[0039] The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of sub-pixels SP1, SP2, and SP3 respectively via contact holes provided in the insulating layer 12. Furthermore, the contact holes of the insulating layer 12 are omitted in Figure 3 and are equivalent to the contact holes CH1, CH2, and CH3 in Figure 2.

[0040] The partition wall 6 includes a conductive lower portion 61 disposed on the insulating layer 5 and an upper portion 62 disposed on the lower portion 61. The lower portion 61 of the partition wall 6 shown on the right side of the figure is located between opening AP1 and opening AP2. The lower portion 61 of the partition wall 6 shown on the left side of the figure is located between opening AP2 and opening AP3.

[0041] The lower part 61 can be a single layer or multiple layers. The upper part 62 has a wider width than the lower part 61. The two ends of the upper part 62 protrude beyond the sides of the lower part 61. Such a shape of the partition wall 6 is called an outward projection.

[0042] In the example shown in Figure 3, the lower part 61 has a bottom layer 63 disposed on the insulating layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the shaft layer 64. Also, in the example shown in Figure 3, the two ends of the bottom layer 63 protrude from the side of the shaft layer 64.

[0043] The organic layer OR1 is connected to the lower electrode LE1 via the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and its periphery is located above the insulating layer 5. The upper electrode UE1 is covered by the organic layer OR1 and connected to the lower part 61.

[0044] The organic layer OR2 is connected to the lower electrode LE2 via the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and its periphery is located above the insulating layer 5. The upper electrode UE2 is covered by the organic layer OR2 and is connected to the lower part 61.

[0045] The organic layer OR3 is connected to the lower electrode LE3 via the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and its periphery is located above the insulating layer 5. The upper electrode UE3 is covered by the organic layer OR3 and is connected to the lower part 61.

[0046] In the example shown in Figure 3, sub-pixel SP1 has a capping layer CP1 and a sealing layer SE1, sub-pixel SP2 has a capping layer CP2 and a sealing layer SE2, and sub-pixel SP3 has a capping layer CP3 and a sealing layer SE3. The capping layers CP1, CP2, and CP3 respectively serve as optical adjustment layers to improve the light extraction efficiency emitted by the organic layers OR1, OR2, and OR3.

[0047] Covering layer CP1 is disposed on the upper electrode UE1. Covering layer CP2 is disposed on the upper electrode UE2. Covering layer CP3 is disposed on the upper electrode UE3.

[0048] Sealing layer SE1 is disposed on top of cover layer CP1, and is in contact with partition wall 6, continuously covering all elements of sub-pixel SP1. Sealing layer SE2 is disposed on top of cover layer CP2, and is in contact with partition wall 6, continuously covering all elements of sub-pixel SP2. Sealing layer SE3 is disposed on top of cover layer CP3, and is in contact with partition wall 6, continuously covering all elements of sub-pixel SP3.

[0049] In the example shown in Figure 3, a portion of each of the organic layer OR1, the upper electrode UE1, and the cover layer CP1 is located on the partition wall 6 surrounding the sub-pixel SP1. These portions are separated from the portions of the organic layer OR1, the upper electrode UE1, and the cover layer CP1 located at the opening AP1 (the portion constituting the display element 201).

[0050] Similarly, a portion of each of the organic layer OR2, the upper electrode UE2, and the cover layer CP2 is located on the partition wall 6 surrounding the sub-pixel SP2, and these portions are separated from the portions of the organic layer OR2, the upper electrode UE2, and the cover layer CP2 located at the opening AP2 (the portion constituting the display element 202).

[0051] Similarly, a portion of each of the organic layer OR3, the upper electrode UE3, and the cover layer CP3 is located on the partition wall 6 surrounding the sub-pixel SP3, and these portions are separated from the portions of the organic layer OR3, the upper electrode UE3, and the cover layer CP3 located at the opening AP3 (the portions constituting the display element 203).

[0052] The ends of sealing layers SE1, SE2, and SE3 are located on the partition wall 6. In the example shown in Figure 3, the ends of sealing layers SE1 and SE2 located on the partition wall 6 between sub-pixels SP1 and SP2 are spaced apart from each other, and the ends of sealing layers SE2 and SE3 located on the partition wall 6 between sub-pixels SP2 and SP3 are spaced apart from each other.

[0053] Sealing layers SE1, SE2, and SE3 are covered by resin layer 13. Resin layer 13 is covered by sealing layer 14. Sealing layer 14 is covered by resin layer 15.

[0054] Insulating layer 5, sealing layers SE1, SE2, SE3 and sealing layer 14 are formed, for example, inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or aluminum oxide (Al2O3).

[0055] The bottom layer 63 and the axial layer 64 of the partition wall 6 are formed of metallic materials. For example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material of the bottom layer 63.

[0056] The metal material for the axial layer 64 can be, for example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). Furthermore, the axial layer 64 can also be formed of an insulating material.

[0057] For example, the upper part 62 of the partition wall 6 has a laminated structure consisting of a lower layer formed of a metallic material and an upper layer formed of a conductive oxide. For example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used as the metallic material forming the lower layer.

[0058] As the conductive oxide forming the upper layer, indium tin oxide (ITO) or indium zinc oxide (IZO) may be used. Furthermore, the upper portion 62 may have a single-layer structure of metallic material. Moreover, the upper portion 62 may include a layer formed of insulating material.

[0059] The lower electrodes LE1, LE2, and LE3 are, for example, multilayers comprising a transparent electrode formed of an oxide conductive material such as ITO and a metal electrode formed of a metal material such as silver.

[0060] Organic layer OR1 contains light-emitting layer EM1. Organic layer OR2 contains light-emitting layer EM2. Organic layer OR3 contains light-emitting layer EM3. Light-emitting layers EM1, EM2, and EM3 are formed from different materials.

[0061] In one example, the luminescent layer EM1 is formed of a material that emits light in the blue wavelength region, the luminescent layer EM2 is formed of a material that emits light in the green wavelength region, and the luminescent layer EM3 is formed of a material that emits light in the red wavelength region. Furthermore, each of the organic layers OR1, OR2, and OR3 comprises multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0062] The upper electrodes UE1, UE2, and UE3 are formed, for example, from metallic materials such as magnesium and silver alloys (MgAg). The capping layers CP1, CP2, and CP3 are multilayers of multiple thin films. All of the multiple thin films are transparent and have different refractive indices.

[0063] The circuit layer 11, insulating layer 12 and insulating layer 5 shown in Figure 3 are configured to span the display area DA and the surrounding area SA.

[0064] Figures 4 and 5 are plan views showing one example of the configuration of a plurality of pads PD of the display device DSP shown in Figure 1. Figure 6 is a plan view showing the metal layers M1, M2, M3, and M4 shown in Figure 5.

[0065] Figures 4 and 5 show the area near the panel end PNLE in the peripheral region SA. In Figures 4 and 5, the display area DA is formed at the top. In Figure 4, a dotted chain line represents the flexible printed circuit board (FPC) shown in Figure 1. In Figure 5, the insulating layer 5 is omitted from the configuration shown in Figure 4.

[0066] As shown in Figures 4 and 5, a plurality of pads PD are arranged along the first direction X, and each extends along the second direction Y. As described above, insulating layer 5 and insulating layer 12 are formed in the region containing the pads PD (peripheral region SA).

[0067] As shown in Figure 4, insulating layer 5 is formed to the panel end PNLE. In contrast, as shown in Figure 5, insulating layer 12 is not formed to the panel end PNLE. In other words, the peripheral region SA has a region A11 within the panel end PNLE where insulating layer 12 is not formed.

[0068] As shown in FIG. 4, insulating layer 5 has an opening 51 that overlaps with each of the pads PD. As shown in FIG. 5, insulating layer 12 has an opening 121 that overlaps with each of the pads PD. In this embodiment, opening 51 corresponds to the first opening, and opening 121 corresponds to the second opening.

[0069] The opening 51 of the insulating layer 5 overlaps with the opening 121 of the insulating layer 12. In the examples shown in Figures 4 and 5, opening 51 and opening 121 overlap for a single pad PD.

[0070] The opening 51 of insulating layer 5 and the opening 121 of insulating layer 12 extend in a direction different from the direction in which the pads PD are arranged. For example, the openings 51 and 121 extend in a second direction Y. Specifically, the openings 51 and 121 have a rectangular shape that is elongated in the second direction Y.

[0071] In the example shown in Figure 4, the area of ​​opening 51 in insulating layer 5 is larger than the area of ​​opening 121 in insulating layer 12 when viewed from above. The edge of opening 51 is located further outward than the edge of opening 121. Insulating layer 12 is exposed through opening 51.

[0072] As shown in FIG. 5, the insulating layer 12 further has a slot 123. In this embodiment, the slot 123 corresponds to the first slot. The slot 123 is located between adjacent pads PD. In other words, the slot 123 is formed between the openings 121 of adjacent insulating layers 12. Also, the slot 123 is formed between the openings 51 of adjacent insulating layers 5.

[0073] The slot 123 extends along the second direction Y. A plurality of slots 123 are arranged along the first direction X. In the example shown in FIG5, the slot 123 opens toward the end panel PNLE. The length of the slot 123 in the second direction Y is greater than the length of the opening 121 of the insulating layer 12 in the second direction Y. The slot 123 is connected to the region A11 of the end panel PNLE.

[0074] As shown in FIG5, the insulating layer 12 further has slots 125, 127, and 129 in the peripheral region SA. In this embodiment, slot 125 corresponds to the second slot, and slots 127 and 129 correspond to the third slot.

[0075] The slot 125 is located between the display area DA, which includes the lower electrodes LE1, LE2, and LE3, and the pad PD. The slot 125 is formed along the first direction X. The width of the slot 125 in the first direction X is greater than the distance between the pads PD disposed at both ends in the first direction X.

[0076] The two ends of slots 127 and 129 are connected to slot 125 in the first direction X. Slots 127 and 129 are formed in the second direction Y from slot 125 toward the end of the panel PNLE.

[0077] Slots 127 and 129 are connected to region A11 of PNLE at the end of the panel. The insulating layer 5 overlaps with slots 123, 125, 127, 129 and region A11 when viewed from above.

[0078] A plurality of pads PD are surrounded by slots 125 and 127, 129 in a top view. In another view, the plurality of pads PD are separated by slots 125 and 127, 129 from an insulating layer 12 formed around them. Here, the insulating layer 12 formed around them includes an insulating layer 12 formed on the display area DA side.

[0079] As shown in Figure 6, the display device DSP further comprises a plurality of metal layers M1, M2, M3, and M4. In this embodiment, metal layer M1 corresponds to the fourth metal layer, metal layer M2 corresponds to the third metal layer, metal layer M3 corresponds to the first metal layer, and metal layer M4 corresponds to the second metal layer.

[0080] Metal layers M1, M2, M3, and M4 each extend along the second direction Y. Adjacent metal layers M1, M2, M3, and M4 are arranged with gaps in the first direction X. The pad PD is composed of metal layers M3 and M4.

[0081] Figure 7 is a cross-sectional view of the display device DSP along line VII-VII in Figure 5. Figure 8 is a cross-sectional view of the display device DSP along line VIII-VIII in Figure 5. The circuit layer 11 has insulating layers 111, 112, and 113. The aforementioned metal layers M1 and M2, together with the insulating layers 111, 112, and 113, constitute the circuit layer 11.

[0082] Insulating layer 111 is an inorganic insulating layer disposed on substrate 10. Metal layer M1 is disposed on insulating layer 111. Metal layer M1 is formed, for example, on the same layer as scan line GL.

[0083] Insulating layer 112 is an inorganic insulating layer, disposed on insulating layer 111 and metal layer M1. Insulating layer 112 has contact holes CH4 and CH5.

[0084] Metal layer M2 is disposed on insulating layer 112. In another view, metal layer M1 is disposed between substrate 10 and metal layer M2. Metal layer M2 is formed, for example, on the same layer as signal line SL.

[0085] When focusing on slot 125, metal layer M2 does not overlap with slot 125 as shown in Figure 8. Metal layer M2 is electrically connected to metal layer M1 via contact holes CH4 and CH5.

[0086] Specifically, the metal layer M2 has a first portion P1 connected to the metal layer M1 via a contact hole CH4, and a second portion P2 connected to the metal layer M1 via a contact hole CH5. The second portion P2 extends toward the display area DA.

[0087] Part 1 P1 is arranged with a gap between Part 2 P2 in the second direction Y. In other words, a gap G1 is formed between Part 1 P1 and Part 2 P2 in the metal layer M2.

[0088] The gap G1 overlaps with the slot 125. In the example shown in Figure 8, the length of the second direction Y of the slot 125 is smaller than the length of the second direction Y of the gap G1. A portion of the metal layer M1 overlaps with the slot 125 across the gap G1.

[0089] Insulating layer 113 is an inorganic insulating layer disposed on insulating layer 112 and metal layer M2. In this embodiment, insulating layer 113 corresponds to the first inorganic insulating layer. Metal layer M2 is disposed between substrate 10 and insulating layer 113. Insulating layer 113 has contact hole CH6.

[0090] Metal layer M3 is located directly above metal layer M1 and is disposed on insulating layer 113. Metal layer M3 is electrically connected to metal layer M2. Specifically, metal layer M3 is connected to the first part P1 of metal layer M2 via contact hole CH6.

[0091] An insulating layer 12 is disposed on top of an insulating layer 113 and a metal layer M3. The metal layer M3 is exposed through an opening 121 in the insulating layer 12. As shown in Figures 7 and 8, the insulating layer 12 covers the periphery of the metal layer M3 across its entire circumference.

[0092] As shown in Figure 7, insulating layer 113 is exposed from insulating layer 12 in slot 123. Insulating layer 5 is disposed on insulating layer 12. Insulating layer 5 is in contact with insulating layer 113 in slot 123. In other words, insulating layer 113 is covered by insulating layer 5 in slot 123.

[0093] As shown in Figure 8, insulating layer 113 is exposed from insulating layer 12 in slot 125. Insulating layer 5 is in contact with insulating layer 113 in slot 125. In other words, insulating layer 113 is covered by insulating layer 5 in slot 125. Not shown in Figures 7 and 8, insulating layer 5 is also in contact with insulating layer 113 in slots 127 and 129.

[0094] Metal layer M4 is located directly above metal layer M3 and is disposed on insulating layer 5. Metal layer M4 is in contact with metal layer M3 exposed from opening 121 of insulating layer 12 through opening 51 of insulating layer 5. In other words, metal layer M4 is electrically connected to metal layer M3 through openings 51 and 121. Metal layer M4 overlaps with the periphery 121E of opening 121.

[0095] Insulating layers 111, 112, and 113 are formed of any one of silicon oxide, silicon nitride, and silicon oxynitride. Insulating layer 5, for example, is formed of silicon oxynitride.

[0096] Metal layers M2, M3, and M4 are formed, for example, from multiple layers. In one example, there are two titanium layers formed of a titanium-based material and an aluminum layer formed of an aluminum-based material located between the two titanium layers. Furthermore, at least one of the metal layers M2, M3, and M4 can also be formed by distributing an aluminum layer between layers formed of a molybdenum-based material.

[0097] Figure 9 is a plan view showing one of the configuration examples of the regions of the plurality of pads PD of the display device DSP10 including the comparative example. Figure 10 is a cross-sectional view of the display device DSP10 along line XX in Figure 9. Figure 11 is a cross-sectional view of the display device DSP10 along line XI-XI in Figure 9. In Figure 9, only the opening 51 in the insulating layer 5 is shown.

[0098] In the comparative example display device DSP10, the difference from the display device DSP of this embodiment lies in the fact that the insulating layer 12 does not have slots 123, 125, 127, and 129.

[0099] In the display device DSP10, as shown in FIG10, there is an insulating layer 12 between adjacent openings 121. Therefore, the insulating layer 5 is in contact with the insulating layer 12 between adjacent openings 121.

[0100] In other words, the insulating layer 5 is not in contact with the insulating layer 113 between adjacent openings 121. Furthermore, as shown in FIG11, in this embodiment, even in the area where the slot 125 is formed, the insulating layer 5 is in contact with the insulating layer 12.

[0101] The adhesion between insulating layer 5 (an inorganic insulating layer) and insulating layer 12 (an organic insulating layer) is weaker than the adhesion between insulating layer 5 (an inorganic insulating layer) and insulating layer 113. Therefore, in the display device DSP10, insulating layer 5 is easily peeled off from insulating layer 12. This peeling reduces the reliability of the display device.

[0102] In contrast, in the display device DSP of this embodiment, insulating layer 5 and insulating layer 113 are connected to each other and are firmly and tightly bonded. As a result, compared with the case where insulating layer 5 is connected to insulating layer 12, the improved adhesion between insulating layer 5 and the underlying ground layer can suppress the peeling of insulating layer 5. As a result, in this embodiment, the reduction in reliability can be suppressed.

[0103] In the comparative example display device DSP10, the pad PD, as shown in Figures 9 and 11, is connected to the insulating layer 12 formed around it. Therefore, moisture can easily penetrate the pad PD from its surroundings through the insulating layer 12.

[0104] Moisture, for example, refers to moisture in the atmosphere (outside air). In Figure 9, arrow W indicates the path of moisture intrusion. Intruding moisture can sometimes corrode the metal layers M3 and M4 that make up the pad PD. Such corrosion can cause the peeling of the insulating layer 5 or the metal layers M3 and M4.

[0105] In this embodiment, the pad PD is separated from the surrounding insulating layer 12 by slots 125, 127, and 129. This prevents moisture from easily penetrating the pad PD from the outside through the slots 125, 127, and 129, as indicated by arrow W in FIG. 5. Consequently, corrosion that could lead to delamination is less likely to occur in the metal layers M3 and M4. Thus, according to this embodiment, a decrease in reliability can be suppressed.

[0106] In this embodiment, as shown in Figures 7 and 8, the insulating layer 12 covers the periphery of the metal layer M3 across its entire circumference. In other words, the periphery of the metal layer M3 is not exposed. This suppresses undesirable erosion of the aluminum layer by the etching solution used in the process of forming the lower electrode on the insulating layer 12.

[0107] In this embodiment, the metal layer M2 does not overlap with the slot 125 as shown in FIG8. Thereby, during the process of forming the slot 125 in the manufacturing process, undesirable erosion (broken lines of the metal layer M2) caused by the etching solution in the area overlapping with the slot 125 can be suppressed.

[0108] As explained above, according to the configuration of this embodiment, a display device DSP capable of suppressing reliability degradation can be provided. Furthermore, various superior effects can be obtained from this embodiment.

[0109] Next, another embodiment will be described. For the parts of the following embodiments not specifically mentioned in the composition, the same as those in the first embodiment may be applied.

[0110] [Second Implementation] Figure 12 is a plan view showing one configuration example of the region containing the plurality of pads PD of the display device DSP of this embodiment. Figure 13 is a cross-sectional view of the display device DSP along line XIII-XIII in Figure 12. Figure 14 is a cross-sectional view of the display device DSP along line XIV-XIV in Figure 12. In Figure 12, the vicinity of two pads PD is magnified and shown.

[0111] In this embodiment, the point at which the insulating layer 5 covers the periphery 121E of the opening 121 of the insulating layer 12 differs from that in the first embodiment.

[0112] In the example shown in Figure 12, the area of ​​the opening 121 of the insulating layer 12 is larger than the area of ​​the opening 51 of the insulating layer 5 when viewed from above. The edge of the opening 121 is located further outward than the edge of the opening 51. The insulating layer 12 does not protrude from the opening 51.

[0113] As shown in Figures 13 and 14, the insulating layer 5 covers the periphery 121E of the opening 121 of the insulating layer 12. In other words, the insulating layer 12 is not exposed from the insulating layer 5. In another viewpoint, the metal layer M4 is not in contact with the insulating layer 12.

[0114] In this embodiment, the same effect as in the first embodiment is achieved. In this embodiment, the insulating layer 5 covers the periphery 121E of the opening 121 of the insulating layer 12. Therefore, during the manufacturing process of forming the opening 51 of the insulating layer 5, undesirable erosion (disappearance) of the insulating layer 12 can be suppressed. According to this embodiment, the reduction in reliability can be further suppressed.

[0115] [Third Implementation Form] Figure 15 is a plan view showing one example of the configuration of a plurality of pad PDs including the display device DSP of this embodiment. Figure 16 is a plan view showing one example of the configuration of a plurality of pad PDs including the display device DSP of this embodiment. Figure 17 is a cross-sectional view of the display device DSP along line XVII-XVII in Figure 16. Figure 18 is a cross-sectional view of the display device DSP along line XVIII-XVIII in Figure 16. In Figure 16, the vicinity of two pad PDs is magnified and shown.

[0116] In this embodiment, the insulating layer 5 has an opening with a shape different from the opening 51 in the above embodiments, which is different from the above embodiments.

[0117] As shown in FIG. 15, the insulating layer 5 has an opening 53. In this embodiment, the opening 53 corresponds to the third opening. The opening 53 overlaps across a plurality of pads PD. In other words, as shown in FIG. 16, the opening 53 overlaps across a plurality of metal layers M3. The opening 53 is formed along the first direction X. The slot 123 of the insulating layer 12 overlaps with the opening 53 of the insulating layer 5. As shown in FIGS. 15 and 18, the insulating layer 12 is exposed from the opening 53.

[0118] The opening 53 has edges 531 and 533. In this embodiment, edge 531 corresponds to the first edge, and edge 533 corresponds to the second edge. Edges 531 and 533 each extend in the first direction X. Edge 531 faces edge 533 in the second direction Y. Edges 531 and 533 are located outside the edge of the opening 121 of the insulating layer 12.

[0119] As shown in Figure 16, edges 531 and 533 each have a plurality of protrusions 531P and 533P. In this embodiment, protrusion 531P corresponds to the first protrusion, and protrusion 533P corresponds to the second protrusion.

[0120] Protrusion 531P protrudes in the second direction Y, and protrusion 533P protrudes in the direction opposite to the second direction Y. In another view, protrusions 531P and 533P protrude in directions that are close to each other.

[0121] Protrusion 531P is disposed at a distance from protrusion 533P in the second direction Y. Protrusions 531P and 533P have a shape that tapers towards the front end. The front ends of protrusions 531P and 533P overlap with slot 123.

[0122] As shown in Figure 17, insulating layer 5 is not formed between adjacent pads PD (metal layers M3, M4). In other words, the peripheral region SA has a region A13 between adjacent pads PD where insulating layer 5 is not formed.

[0123] In this embodiment, the same effect as in the first embodiment is achieved. During the etching process in the manufacturing process, residues sometimes occur between adjacent pads (PDs) due to the components constituting the pads (e.g., metal layer M4). These residues may, for example, occur along the step difference of the insulating layer 5. Such residues may cause short circuits between adjacent pads (PDs), resulting in malfunctions.

[0124] In this embodiment, the edges 531 and 533 of the opening 53 of the insulating layer 5 have protrusions 531P and 533P, respectively. This allows the components constituting the metal layer M4 to be removed before the protrusions 531P and 533P during the etching process, thus suppressing the formation of residues. This also reduces the likelihood of short circuits between adjacent pads PD. According to this embodiment, the reduction in reliability can be further suppressed.

[0125] [Fourth Implementation Form] Figure 19 is a plan view showing one configuration example of the region containing the plurality of pads PD of the display device DSP of this embodiment. Figure 20 is a cross-sectional view of the display device DSP along line XX-XX in Figure 19. Figure 21 is a cross-sectional view of the display device DSP along line XXI-XXI in Figure 19. In Figure 19, the vicinity of two pads PD is magnified and shown.

[0126] In this embodiment, the point at which the insulating layer 12 is removed in the area overlapping with the opening 53 during the manufacturing process differs from that in the third embodiment.

[0127] As shown in Figures 19 to 21, insulating layer 12 is not disposed in the area overlapping with opening 53. As shown in Figure 20, insulating layers 5 and 12 are not formed between adjacent pads PD (metal layers M3 and M4). In other words, the peripheral region SA has a region A15 between adjacent pads PD where insulating layers 5 and 12 are not formed.

[0128] In this embodiment, the same effect as in the first embodiment is achieved. In this embodiment, the periphery of the metal layer M3 is not covered by the insulating layer 12. In the manufacturing process, if there is no step such as etching the aluminum layer constituting the metal layer M3 by an etching solution after the step of forming the opening 53, then even the configuration of this embodiment is not problematic.

[0129] The above description of the display device, based on an embodiment of the present invention, includes all display devices that can be implemented by appropriate design modifications by those skilled in the art, provided they contain the essence of the present invention. Within the scope of the present invention, various variations will be conceived by those skilled in the art, and such variations should also be understood to be within the scope of the present invention. For example, for the above-described embodiments, appropriate additions, deletions, or design changes to constituent elements, or additions, omissions, or changes to steps or conditions by those skilled in the art, are also included within the scope of the present invention, provided they possess the essence of the present invention.

[0130] Furthermore, any other effects resulting from the embodiments described above, which are clear from the description in this specification or which can be reasonably conceived by those skilled in the art, should of course be understood as being brought about by the present invention.

[0131] Cross-reference of related applications This invention application claims priority based on Japanese Patent Application No. 2024-022858, filed on February 19, 2024, and incorporates all the contents described in that Japanese Patent Application.

[0132] 1: Pixel circuit 2: Pixel switch 3: Driving transistor 4: Capacitor 5: Insulation layer 6: Partition wall 10:Substrate 11: Circuit Layer 12: Insulation layer 13: Resin layer 14: Sealing layer 15: Resin layer 20: Display element 51, 53: Opening 61: Lower part 62: Upper part 63: Bottom layer 64: Axis Layer 111, 112, 113: Insulation layer 121: Opening 121E: Peripheral Part 123, 125, 127, 129: Slots 201, 202, 203: Display elements 531, 533: Fate 531P, 533P: Protrusions A11, A13, A15: Areas AP1, AP2, AP3: Openings CH1, CH2, CH3, CH4, CH5, CH6: Contact holes CP1, CP2, CP3: Overlay layers DA: Display area DSP, DSP10: Display device EM1, EM2, EM3: Emissive layers FPC: Flexible Printed Circuit Board G1: Gap GL: Scan line III-III, VII-VII, VIII-VIII, XX, XI-XI, XII-XII, XVII-XVII, XVIII-XVIII, XX-XX, XXI-XXI, XXIV-XIV: lines LE1, LE2, LE3: Lower electrodes M1, M2, M3, M4: Metal layers OR1, OR2, OR3: Organic layer P1: Part 1 P2: Part 2 PD: Pad PL: Power cord PNL: Display Panel PNLE: Panel end PX: pixel SA: Surrounding Area SE1, SE2, SE3: Sealing layer SL: Signal line SP, SP1, SP2, SP3: Subpixels UE1, UE2, UE3: Upper electrode W: Arrow X: Axis / First Direction Y: Axis / Second Direction Z: Axis / Third Direction

Claims

1. A display device comprising: a substrate; a first inorganic insulating layer disposed above the substrate, spanning a display area for displaying an image and a peripheral area surrounding the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the display area and on the organic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer and overlapping the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral area and arranged in a first direction along an end of the substrate; and a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layers; wherein the second inorganic insulating layer has a plurality of first openings overlapping the second metal layers. The aforementioned organic insulating layer system has: a plurality of second openings overlapping the aforementioned first opening for contact between the aforementioned first metal layer and the aforementioned second metal layer; and a plurality of first slots formed between adjacent aforementioned second openings for contact between the aforementioned second inorganic insulating layer and the aforementioned first inorganic insulating layer.

2. The display device of claim 1, wherein each of the aforementioned plurality of first slots opens toward the end of the aforementioned substrate.

3. The display device of claim 2, wherein the aforementioned second metal layer overlaps with the periphery of the aforementioned second opening of the aforementioned organic insulating layer.

4. The display device according to any one of claims 1 to 3, wherein the aforementioned second inorganic insulating layer covers the periphery of the aforementioned second opening of the aforementioned organic insulating layer.

5. A display device comprising: a substrate; a first inorganic insulating layer disposed above the substrate, spanning a display area for displaying an image and a peripheral area surrounding the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the display area and on the organic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer and overlapping the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral area and arranged in a first direction along an end of the substrate; and a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layers; wherein the second inorganic insulating layer has a third opening that spans and overlaps the plurality of first metal layers.

6. The display device of claim 5, wherein the aforementioned third opening has a first edge and a second edge facing each other in a second direction intersecting the aforementioned first direction, the aforementioned first edge having a plurality of first protrusions located between adjacent previously described second metal layers and protruding toward the aforementioned second edge, and the aforementioned second edge having a plurality of second protrusions located between adjacent previously described second metal layers and protruding toward the aforementioned first edge.

7. The display device of claim 6, wherein the aforementioned organic insulating layer has a plurality of first slots overlapping the aforementioned first protrusion and the aforementioned second protrusion, formed between adjacent aforementioned first metal layers.

8. The display device of claim 6, wherein the aforementioned peripheral region has an area between adjacent first metal layers where the aforementioned second inorganic insulating layer is not formed.

9. The display device of claim 6, wherein the aforementioned organic insulating layer is not disposed in the area overlapping with the aforementioned third opening.

10. The display device of claim 1 or 5, wherein the aforementioned organic insulating layer further has a second slot in the aforementioned peripheral region, located between the aforementioned lower electrode and the aforementioned first metal layer, formed along the aforementioned first direction.

11. The display device of claim 10, further comprising a third metal layer disposed between the first inorganic insulating layer and the substrate, electrically connected to the first metal layer, and not overlapping the second slot.

12. The display device of claim 11, further comprising a fourth metal layer disposed between the aforementioned third metal layer and the aforementioned substrate, electrically connected to the aforementioned third metal layer, and overlapping the aforementioned second slot.

13. The display device of claim 10, wherein the aforementioned organic insulating layer further has a third slot, the third slot being connected to the aforementioned second slot and formed at the end facing the aforementioned substrate.

14. A display device comprising: a substrate; a first inorganic insulating layer disposed above the substrate, spanning a display area for displaying an image and a peripheral region surrounding the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the display area and on the organic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer and overlapping the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; and a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral region and arranged in a first direction along an end of the substrate; wherein the organic insulating layer has a slot in the peripheral region formed between the lower electrode and the first metal layer along the first direction.

15. The display device of claim 14, wherein the aforementioned peripheral region further includes a plurality of second metal layers, which are disposed on the aforementioned second inorganic insulating layer and electrically connected to the aforementioned first metal layer.

16. The display device of claim 15 further includes a third metal layer disposed between the first inorganic insulating layer and the substrate, electrically connected to the first metal layer, and not overlapping the slot.

17. The display device of claim 16 further includes a fourth metal layer disposed between the aforementioned third metal layer and the aforementioned substrate, electrically connected to the aforementioned third metal layer, and overlapping the aforementioned slot.

18. The display device of claim 17, wherein the aforementioned third metal layer includes a first portion connected to the aforementioned first metal layer and the aforementioned fourth metal layer, and a second portion connected to the aforementioned fourth metal layer.

19. The display device of claim 18, wherein the aforementioned fourth metal layer overlaps the aforementioned slot through the gap formed between the aforementioned first portion and the aforementioned second portion.

20. The display device of claim 14, wherein the aforementioned second inorganic insulating layer is in contact with the aforementioned first inorganic insulating layer in the aforementioned slot.

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