Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

An embodiment of the present invention provides a semiconductor device and a method for manufacturing the semiconductor device that can reduce the contact resistance between a channel layer and a lower electrode. The semiconductor device of this embodiment includes: a first electrode; a first insulating layer disposed on the first electrode; a gate electrode disposed on the first insulating layer; a second insulating layer disposed on the gate electrode; a second electrode disposed on the second insulating layer; a channel layer having one end connected to the first electrode and the other end connected to the second electrode; and a gate insulating layer disposed between the channel layer and the gate electrode; and in the channel layer, at a first height position between the two ends of the first insulating layer in the thickness direction, the length of a first direction intersecting the thickness direction increases discontinuously from the gate electrode side toward the first electrode side.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Prior Technology

[0002] A semiconductor device is known to be constructed as a vertical transistor with a composite oxide semiconductor as the channel layer. This semiconductor device has: a channel layer connected at both ends to upper and lower electrodes, and connected laterally to a gate electrode disposed between the electrodes.

[0003] The channel layer is provided, for example, by passing through the interlayer insulating layer separating the upper and lower electrodes and the gate electrode. In this case, the diameter of the lower end of the channel layer connected to the lower electrode is deviated, thereby increasing the contact resistance between the channel layer and the lower electrode. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the contact resistance between the channel layer and the lower electrode.

[0005] The semiconductor device of the embodiment includes: a first electrode; a first insulating layer disposed on the first electrode; a gate electrode disposed on the first insulating layer; a second insulating layer disposed on the gate electrode; a second electrode disposed on the second insulating layer; a channel layer having one end connected to the first electrode and the other end connected to the second electrode; and a gate insulating layer disposed between the channel layer and the gate electrode; and in the channel layer, at a first height position between the two ends of the first insulating layer in the thickness direction, the length of a first direction intersecting the thickness direction increases discontinuously from the gate electrode side toward the first electrode side. Simple Explanation of the Diagram

[0006] Figures 1(a) to (c) are schematic diagrams showing an example of the configuration of the semiconductor device in Embodiment 1. Figures 2(Aa) to (Bf) are cross-sectional views illustrating a portion of the steps in the manufacturing method of the semiconductor device according to Embodiment 1. Figures 3(Aa) to (Bd) are cross-sectional views illustrating a portion of the steps in the manufacturing method of the semiconductor device according to Embodiment 1. Figures 4(Aa) to (Bd) are cross-sectional views illustrating a portion of the steps in the manufacturing method of the semiconductor device according to Embodiment 1. Figures 5(a) and (b) are schematic diagrams showing an example of the configuration of the semiconductor device in Embodiment 2. Figures 6(Aa) to (Bd) are cross-sectional views illustrating a portion of the steps in the manufacturing method of the semiconductor device according to Embodiment 2. Figures 7(Aa) to (Bd) are cross-sectional views illustrating a portion of the steps in the manufacturing method of the semiconductor device according to Embodiment 2. Figures 8(Aa) to (Bd) are cross-sectional views illustrating a portion of the steps in the manufacturing method of the semiconductor device of Example 1, a variation of Embodiment 2. Figures 9(a) and (b) are schematic diagrams showing one example of the configuration of the semiconductor device in Embodiment 2, Variation 2. Figures 10(Aa) to (Bd) are cross-sectional views illustrating a portion of the steps in the manufacturing method of the semiconductor device of Embodiment 2, Variation 2. Figure 11 is a schematic diagram illustrating the definition of the cone angle when the channel layer of Embodiment 2 and Variations 1 and 2 is regarded as a cone shape. Implementation

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited by the embodiments described below. Furthermore, the constituent elements in the embodiments described below include elements readily conceived by those skilled in the art or substantially the same elements.

[0008] [Implementation Form 1] The following description, with reference to the diagram, details implementation form 1.

[0009] (Example of a semiconductor device) Figure 1 is a schematic diagram showing an example of the configuration of the semiconductor device 1 in Embodiment 1. Figure 1(a) is an XY cross-sectional view of the semiconductor device 1 at the height position of the gate electrode 30, which will be described later. Figure 1(b) is a cross-sectional view of the semiconductor device 1 along the X direction. Figure 1(c) is a cross-sectional view of the semiconductor device 1 along the Y direction.

[0010] Furthermore, in this specification, the X and Y directions are both along the surface of the gate electrode 30 described later, and the X and Y directions are orthogonal to each other. The Z direction is the stacking direction of each layer of the semiconductor device 1, and it is orthogonal to the X and Y directions.

[0011] Furthermore, the extension direction of the gate electrode 30 is sometimes referred to as the first direction, which is along the X direction. Also, the extension direction of the bit line 70 described later, which intersects the first direction, is sometimes referred to as the second direction, which is along the Y direction. However, since the semiconductor device 1 may contain manufacturing errors, the first and second directions are not necessarily orthogonal.

[0012] As shown in FIG1, the semiconductor device 1 includes a lower electrode 11 as a first electrode, a gate electrode 30, an upper electrode 51 as a second electrode, and a pillar 60. The lower electrode 11, the gate electrode 30, the upper electrode 51, and the pillar 60 are disposed above a substrate (not shown) such as a silicon substrate.

[0013] More specifically, insulating layers 10 and 20, a gate electrode 30, and insulating layers 40 and 50 are sequentially disposed on the substrate. The thickness of the gate electrode 30 and the insulating layers 20 and 40 is, for example, about tens of nm.

[0014] The insulating layer 10 is, for example, a SiN layer. Contacts 13 extending from the insulating layer 10 are disposed at predetermined intervals in the X and Y directions. The contacts 13 are, for example, a SiGe layer, and are connected to the substrate via source lines (not shown) or directly.

[0015] At the upper end of contact 13, for example, an indium tin oxide (ITO) layer, i.e., a lower electrode 11, is provided. Herein, the lower electrode 11 drops to the substrate potential. In addition, the upper surfaces of the insulating layer 10 and the lower electrode 11 are located on substantially the same plane, and the upper surface of the lower electrode 11 is not covered by the insulating layer 10.

[0016] The sides of the contact 13 and the lower electrode 11 are covered by a pad layer 12. The pad layer 12 is a multilayer structure formed by sequentially stacking, for example, TiN layer, ZrO layer and ZrAlO layer (all not shown) from one side of the contact 13 and the lower electrode 11 outward.

[0017] An insulating layer 20 is provided on the insulating layer 10, covering the insulating layer 10, the contact 13, and the upper surface of the lower electrode 11. The insulating layer 20, which is the first insulating layer, is, for example, a SiO layer. The insulating layer 20 may also be a Low-k layer such as a SiOC layer.

[0018] A plurality of gate electrodes 30 are disposed on the insulating layer 20, extending along the X direction and arranged at predetermined intervals in the Y direction. The plurality of gate electrodes 30 are tungsten layers or the like, and are disposed at a position overlapping the lower electrode 11, which is arranged in a grid pattern in the X and Y directions, in the Z direction. The insulating layer 20 is also disposed between adjacent gate electrodes 30 in the Y direction.

[0019] However, an insulating layer 40 may also be filled between adjacent gate electrodes 30 in the Y direction. This difference may arise, for example, due to differences in the timing of patterning the gate electrodes 30 in the manufacturing method of the semiconductor device 1 described later.

[0020] An insulating layer 40 is provided on a plurality of gate electrodes 30, covering the gate electrodes 30. The insulating layer 40, which is a second insulating layer, may be made of the same type of material as the insulating layer 20, such as a SiO layer or a SiOC layer or other low-k layer.

[0021] An insulating layer 50, such as a SiO layer, is provided on the insulating layer 40. On the lower surface side of the insulating layer 50, a plurality of upper electrodes 51 are disposed at positions overlapping with a plurality of lower electrodes 11 in the Z direction. These upper electrodes 51, like the lower electrodes 11, are, for example, ITO layers, and are connected to a bit line 70 located above the insulating layer 50 via a connector 52 penetrating the insulating layer 50. The plurality of bit lines 70 extend along the Y direction and are arranged at predetermined intervals in the X direction.

[0022] At the position held by the lower electrode 11 and the upper electrode 51, a plurality of posts 60 are respectively provided, including a penetrating insulating layer 40, a gate electrode 30 corresponding to the position, and an insulating layer 20. Each of the plurality of posts 60 has a channel layer 61 and a gate insulating layer 62.

[0023] The channel layer 61 includes a lower channel layer 61b and an upper channel layer 61a, and penetrates the insulating layer 40, the gate electrode 30, and the insulating layer 20, connecting the lower electrode 11 and the upper electrode 51. The channel layer 61 is a composite oxide semiconductor layer such as an indium (In), gallium (Ga), or zinc (Zn) oxide layer, i.e., an IGZO layer.

[0024] The lower channel layer 61b, as the second part, is disposed in the insulating layer 20, and its lower end is connected to the lower electrode 11. The upper end of the lower channel layer 61b is disposed at a height position between the two surfaces in the Z direction of the insulating layer 20. The height position of the upper end of the lower channel layer 61b is also referred to as the first height position.

[0025] The upper end of the upper channel layer 61a, which is part 1, is connected to the upper electrode 51 and extends through the insulating layer 40 and the gate electrode 30, and further extends in the insulating layer 20. The lower end is connected to the upper end of the lower channel layer 61b. At this time, the lower end of the upper channel layer 61a can also extend into the lower channel layer 61b.

[0026] Both the lower channel layer 61b and the upper channel layer 61a have, for example, a circular shape when viewed from the Z direction, and the diameter of the lower channel layer 61b is larger than the diameter of the upper channel layer 61a. However, the lower channel layer 61b and the upper channel layer 61a may also have shapes other than circular, such as elliptical or oval. Even in this case, when viewed from the Z direction, the cross-sectional area of ​​the lower channel layer 61b is larger than the cross-sectional area of ​​the upper channel layer 61a.

[0027] That is, the length of the lower channel layer 61b in the X direction and the length of the upper channel layer 61a in the X direction are both greater than the length of the upper channel layer 61a in the X direction and the length of the upper channel layer 61a in the Y direction.

[0028] At this time, the upper channel layer 61a may have the following shape: the diameter of the lower end, that is, the length in the X and Y directions, is smaller than the diameter of the upper end, that is, the length in the X and Y directions. That is, the upper channel layer 61a may also have a conical shape in which the diameter decreases from the upper end to the lower end.

[0029] However, it is also possible that the upper channel layer 61a has a roughly vertical sidewall, so that the diameter of the lower end is roughly equal to the diameter of the upper end.

[0030] Furthermore, the lower channel layer 61b may have the following shape: the diameter of the lower end, i.e., the length in the X and Y directions, is smaller than the diameter of the upper end, i.e., the length in the X and Y directions. That is, the lower channel layer 61b may also have a tapered shape in which the diameter decreases from the upper surface side of the insulating layer 20 to the lower surface side. Even in this case, the diameter of the lower channel layer 61b is generally larger than the diameter of the upper channel layer 61a.

[0031] Alternatively, the lower channel layer 61b may have approximately vertical sidewalls, thereby making the diameter of the lower end approximately equal to the diameter of the upper end.

[0032] Furthermore, as mentioned above, both the lower channel layer 61b and the upper channel layer 61a are composite oxide semiconductor layers such as IGZO layers. The composition ratios of various metals in the composite oxide semiconductor layers contained in the lower channel layer 61b and the upper channel layer 61a may be equal or different.

[0033] As an example, when the composite oxide semiconductor layer is, for example, an IGZO layer, and the composition ratio of various metals is equal, the lower channel layer 61b and the upper channel layer 61a may have a composition ratio of In:Ga:Zn=1:1:1.

[0034] When the composition ratios of various metals are different, it is preferable that, among the metals contained in the composite oxide semiconductor layer, the content of metals with lower oxygen binding strength than other metals in the lower channel layer 61b is higher than that in the upper channel layer 61a. Furthermore, it is preferable that, in the upper channel layer 61a, the content of metals with higher oxygen binding strength than other metals is higher than that in the lower channel layer 61b.

[0035] As an example, when the composite oxide semiconductor layer is, for example, an IGZO layer, among the In, Ga, and Zn contained in the IGZO layer, In has a lower bonding strength with oxygen than the other metals. Therefore, when the composition ratio of the various metals is different, the lower channel layer 61b may also have a composition ratio of In:Ga:Zn=2:1:1.

[0036] On the other hand, in the IGZO layer, Ga has a higher bonding strength with oxygen than other metals. Therefore, when the composition ratio of various metals is different, the upper channel layer 61a can replace the lower channel layer 61b with the above composition ratio, or in addition, it can have a composition ratio of In:Ga:Zn=1:2:1.

[0037] Alternatively, the composite oxide semiconductor layer contained in the lower channel layer 61b is sometimes referred to as the second semiconductor layer, and the composite oxide semiconductor layer contained in the upper channel layer 61a is referred to as the first semiconductor layer.

[0038] As described above, the semiconductor device 1 is configured, for example, as a vertical transistor. That is, by applying a predetermined voltage from the gate electrode 30 to the channel layer 61 through the pillar 60 of the gate electrode 30, the vertical transistor can be turned on.

[0039] Therefore, each pillar 60, along with the lower electrode 11, gate electrode 30, and upper electrode 51 connected to the pillar 60, can be considered as a vertical transistor, and the semiconductor device 1 can be regarded as containing a plurality of vertical transistors. Furthermore, in the vertical transistor, the gate electrode 30, which applies voltage to the channel layer 61, functions as a word line.

[0040] As described above, in the IGZO layer, the bonding strength between In and oxygen is lower than that of other metals. Therefore, oxygen easily deviates from the In-O bond, creating voids that function as donors in the traces of oxygen deviation. In the lower channel layer 61b directly connected to the lower electrode 11, as described above, the bonding strength between In and oxygen is lower than that of other metals. Increasing the content of metals that easily generate donors increases the number of donors in the composite semiconductor layer, thereby increasing the turn-on current of the semiconductor device 1, which is constructed as a vertical transistor, and enabling the semiconductor device 1 to operate at high speed.

[0041] Furthermore, as mentioned above, in the IGZO layer, the bonding strength between Ga and oxygen is higher than that of other metals. Therefore, oxygen is difficult to deviate from the Ga-O bond, making it difficult to create voids that can act as donors. In the upper channel layer 61a, which is directly affected by the electric field effect from the gate electrode 30, as mentioned above, the bonding strength between Ga and oxygen is higher than that of other metals, increasing the content of metals that are difficult to generate donors. This reduces the number of donors in the composite semiconductor layer, increases the threshold voltage of the semiconductor device 1, which is composed of a vertical transistor, and reduces the leakage current.

[0042] Therefore, by increasing the content of metals such as In in the lower channel layer 61b and further increasing the content of metals such as Ga in the upper channel layer 61a, both high turn-on current and high threshold voltage can be achieved in the vertical transistor.

[0043] The gate insulating layer 62, like the upper channel layer 61a, extends within the insulating layer 40, the gate electrode 30, and the insulating layer 20, covering the sidewall portion of the upper channel layer 61a. As described above, when the lower end of the upper channel layer 61a extends into the lower channel layer 61b, the lower end of the gate insulating layer 62 may also extend into the lower channel layer 61b.

[0044] The gate insulating layer 62 may have a multilayer structure, for example, formed by sequentially stacking gate insulating layers 62x and 62n from the channel layer 61 side. The gate insulating layer 62x may be, for example, a SiO layer, and the gate insulating layer 62n may be, for example, a SiN layer. Furthermore, the gate insulating layer 62n, which covers the gate insulating layer 62x from the outside, may also cover the lower end of the gate insulating layer 62x.

[0045] (Manufacturing method of semiconductor devices) Next, using Figures 2 to 4, an example of the manufacturing method of semiconductor device 1 in Embodiment 1 will be described.

[0046] Figures 2 to 4 are cross-sectional views illustrating a portion of the steps in the manufacturing method of the semiconductor device 1 according to Embodiment 1. More specifically, the diagram labeled (A) in Figures 2 to 4 is a cross-sectional view of the semiconductor device 1 during manufacturing along the X direction, and the diagram labeled (B) in Figures 2 to 4 is a cross-sectional view of the semiconductor device 1 during manufacturing along the Y direction.

[0047] As shown in Figures 2(Aa)(Ba), an insulating layer 10, such as a SiN layer, is formed on top of the substrate. A plurality of contacts 13 are formed penetrating the insulating layer 10, and a plurality of lower electrodes 11 are formed at the upper ends of the contacts 13. A padding layer 12 is formed covering the sidewalls of the contacts 13 and the lower electrodes 11.

[0048] Furthermore, when forming the lower electrode 11 at the upper end of the contact 13, the ITO layer serving as the lower electrode 11 is formed in such a way that it covers the entire upper surface of the insulating layer 10, including the upper end of the contact 13. Then, by means of CMP (Chemical Mechanical Polishing), the ITO layer is processed into the shape of the lower electrode 11 so that the upper surface of the ITO layer is located on a plane substantially the same as the upper surface of the insulating layer 10. At this time, the upper surface of the lower electrode 11 may have a recessed portion referred to as a depression.

[0049] Furthermore, an insulating layer 20, such as a SiO layer or a Low-k layer, is formed covering the insulating layer 10 and the upper surface of the lower electrode 11. At this time, the insulating layer 20 is formed to be thinner than the insulating layer 20 of the final semiconductor device 1, for example, equivalent to the thickness of the lower channel layer 61b mentioned above.

[0050] As shown in Figures 2(Ab)(Bb), a plurality of recessed patterns 61p are formed at the location where the channel layer 61 will be formed after the insulating layer 20. At this time, the recessed pattern 61p may be a conical shape with a diameter that decreases from the upper surface side to the lower surface side of the insulating layer 20.

[0051] As shown in Figures 2(Ac)(Bc), a semiconductor layer 61d, such as an IGZO layer, is formed that includes a plurality of recessed patterns 61p covering the entire upper surface of the insulating layer 20. The semiconductor layer 61d also fills the plurality of recessed patterns 61p, thereby making the upper surface of the semiconductor layer 61d slightly recessed at the arrangement positions of the plurality of recessed patterns 61p.

[0052] As shown in Figure 2(Ad)(Bd), the semiconductor layer 61d is processed into the shape of the lower channel layer 61b by means of CMP or the like, so that the upper surface of the semiconductor layer 61d is located on the same plane as the upper surface of the insulating layer 20.

[0053] As shown in Figure 2(Ae)(Be), an insulating layer 20 is added to cover the lower channel layer 61b. At this time, the insulating layer 20 is formed to be thicker than the insulating layer 20 of the final semiconductor device 1, for example, equivalent to the thickness of the gate electrode 30 described above.

[0054] As shown in Figures 2(Af) and (Bf), a plurality of trench patterns 30p are formed in the insulating layer 20, spaced at predetermined intervals in the Y direction and extending along the X direction. These trench patterns 30p are formed at positions that overlap with the plurality of lower electrodes 11 in the Z direction.

[0055] As shown in Figures 3(Aa)(Ba), a plurality of trenches 30t are filled with tungsten layers, etc. thereby forming a plurality of gate electrodes 30 with insulating layers 20 in the wiring bay.

[0056] As shown in Figures 3(Ab)(Bb), an insulating layer 40, such as a SiO layer or a Low-k layer, is formed on the upper surface of the insulating layer 20 and a plurality of gate electrodes 30.

[0057] Furthermore, the method for forming the gate electrode 30 shown in Figures 2(Ae)(Be) to 3(Aa)(Ba) is also called the mosaic method. However, multiple gate electrodes 30 can also be formed by methods other than the mosaic method.

[0058] As an example, the insulating layer 20 is formed with the same thickness as the insulating layer 20 of the final semiconductor device 1 from the beginning, and a tungsten layer is formed covering the insulating layer 20. Furthermore, a resist layer having a pattern of a plurality of gate electrodes 30 is formed on the tungsten layer, and the tungsten layer is etched to form a plurality of gate electrodes 30.

[0059] After the resist layer is stripped, an insulating layer 40 is formed covering the plurality of gate electrodes 30, similar to that shown in Figures 3(Ab)(Bb). In this case, the insulating layer 40 is filled between the plurality of gate electrodes 30 arranged in the Y direction.

[0060] As shown in Figures 3(Ac)(Bc), a through-insulating layer 40 and a gate electrode 30 are formed at a position overlapping with the plurality of lower electrodes 11 in the Z direction, and then extend in the insulating layer 20 to reach the plurality of through holes TH in the lower channel layer 61b. At this time, the lower end of the through holes TH can also extend slightly in the lower channel layer 61b.

[0061] As shown in Figures 3(Ad)(Bd), gate insulating layers 62bx (such as SiO layer) and gate insulating layers 62bn (such as SiN layer) are sequentially formed, covering the sidewalls and bottom surfaces of each of the plurality of through holes TH. At this time, gate insulating layers 62bx and 62bn also cover the upper surface of insulating layer 40.

[0062] As shown in Figures 4(Aa)(Ba), the gate insulation layers 62bx and 62bn are removed from the bottom surface of each of the plurality of through holes TH. At this time, the gate insulation layer 62bx may also remain at the lower end of the gate insulation layer 62bn remaining on the sidewall of the through hole TH. Furthermore, at this time, the gate insulation layers 62bx and 62bn on the upper surface of the insulation layer 40 are also removed.

[0063] This forms a gate insulation layer 62 covering the sidewalls of each through hole TH. Also, the upper end of the lower channel layer 61b is exposed from the bottom surface of the through hole TH.

[0064] As shown in Figures 4(Ab)(Bb), for example, an atomic layer deposition (ALD) method is used to form a semiconductor layer 61f, such as an IGZO layer, in a plurality of through-holes TH. At this time, the semiconductor layer 61f also covers the upper surface of the insulating layer 40.

[0065] As shown in Figures 4(Ac)(Bc), the semiconductor layer 61f on the upper surface of the insulating layer 40 is removed by CMP or the like. This separates the semiconductor layers 61f, forming a plurality of upper channel layers 61a connected to a plurality of lower channel layers 61b. Furthermore, this forms a channel layer 61 comprising the lower channel layers 61b and the upper channel layers 61a, and a plurality of pillars 60 having the channel layer 61 and the gate insulating layer 62.

[0066] As shown in Figures 4(Ad)(Bd), an insulating layer 50, such as a SiO layer, is formed covering the insulating layer 40 and the upper surface of the plurality of pillars 60. Furthermore, a plurality of upper electrodes 51 are formed in the insulating layer 50, and a plurality of plugs 52 are formed penetrating the insulating layer 50 and connected to the upper electrodes 51.

[0067] Based on the above, semiconductor device 1 of embodiment 1 is manufactured.

[0068] (Summary) Miniaturization is sought in semiconductor devices constructed using vertical transistors. Consequently, the diameter of the pillars containing the channel layer is also reduced. These pillars are formed, for example, through an interlayer insulating layer separating the upper and lower electrodes and a gate electrode disposed between the upper and lower electrodes. However, due to the reduced pillar diameter, the diameter of the lower end of the through-hole is prone to deviation, and the contact resistance between the channel layer of the pillar and the lower electrode may increase.

[0069] Furthermore, there are cases where the gate insulating layer covering the sidewalls of the channel layer has a multilayer structure, such as a SiO layer and a SiN layer. When forming the gate insulating layer, a SiN layer and a SiO layer are sequentially formed on the sidewalls and bottom surface of the aforementioned through-hole. However, when a SiN layer is formed on the ITO layer or the lower electrode layer, the ITO layer may sublimate due to the reduction effect of the raw material gas of the SiN layer, and the lower electrode may disappear.

[0070] According to the semiconductor device 1 of Embodiment 1, in the channel layer 61, at a predetermined height position between the two ends of the insulating layer 20 in the thickness direction, the length in the X direction discontinuously increases from the gate electrode 30 side toward the lower electrode 11 side. This reduces the contact resistance between the channel layer 61 and the lower electrode 11.

[0071] According to the semiconductor device 1 of Embodiment 1, in the composite oxide semiconductor layer included in the lower channel layer 61b, the content of metals with lower binding strength to oxygen than other metals is higher than that in the composite oxide semiconductor layer included in the upper channel layer 61a. This increases the on-state current of the semiconductor device 1, enabling the semiconductor device 1 to operate at high speed.

[0072] According to the semiconductor device 1 of Embodiment 1, in the composite oxide semiconductor layer included in the upper channel layer 61a, the content of the metal with a higher binding strength to oxygen than the other metals is higher than that in the composite oxide semiconductor layer included in the lower channel layer 61b. This increases the threshold voltage of the semiconductor device 1 and reduces leakage current.

[0073] According to the manufacturing method of the semiconductor device 1 in Embodiment 1, the formation of the channel layer 61 includes: forming a lower channel layer 61b having a predetermined length in the X direction in the insulating layer 20 on the lower electrode 11; and forming an upper channel layer 61a, which extends from the insulating layer 40 to the insulating layer 10, is connected to the lower channel layer 61b in the insulating layer 10, and has a length in the X direction that is smaller than the length of the lower channel layer 61b.

[0074] This reduces the contact resistance between the channel layer 61 and the lower electrode 11. Furthermore, since the lower channel layer 61b and the upper channel layer 61a are formed in two stages, the embedding properties of the composite oxide semiconductor layer in the channel layer 61 are improved, which further reduces the contact resistance between the channel layer 61 and the lower electrode 11.

[0075] Furthermore, the through hole TH, which forms the upper channel layer 61a, does not reach the lower electrode 11, but reaches the upper surface of the lower channel layer 61b. Therefore, the lower channel layer 61b can function as a barrier layer, which can suppress the damage to the lower electrode 11 when the through hole TH is formed.

[0076] According to the manufacturing method of the semiconductor device 1 in Embodiment 1, the formation of the gate insulating layer 62 includes forming a gate insulating layer 62bn on the sidewall and bottom surface of the through hole TH extending from the insulating layer 40 to the insulating layer 20 and connected to the lower channel layer 61b in the insulating layer 20.

[0077] Thus, when forming the gate insulating layer 62, the SiN layer, i.e., the gate insulating layer 62bn, is not formed directly on the lower electrode 11, but on the lower channel layer 61b. In this way, the sublimation of the ITO layer, etc., constituting the lower electrode 11 due to the reduction effect of the raw material gas of the gate insulating layer 62bn is suppressed, and the lower electrode 11 disappears.

[0078] [Implementation Mode 2] Hereinafter, with reference to the figures, Embodiment 2 will be described in detail. In Embodiment 2, the shape and formation method of the channel layer 161 are different from those in Embodiment 1.

[0079] Additionally, in the following diagrams, sometimes the same symbols are used to mark components that are the same as those in Embodiment 1 above, and their descriptions are omitted.

[0080] (Example of a semiconductor device) Figure 5 is a schematic diagram showing an example of the configuration of the semiconductor device 2 in Embodiment 2. Figure 5(a) is a cross-sectional view of the semiconductor device 2 along the X direction. Figure 5(b) is a cross-sectional view of the semiconductor device 2 along the Y direction.

[0081] As shown in FIG5, the lower electrode 110 of the semiconductor device 2 replaces the lower electrode 11 of the above embodiment 1 and is configured to include a base electrode 112 and a protruding electrode 111.

[0082] The base electrode 112 is, for example, a TiN layer, and is disposed at the upper end of the contact 13 such that the height of its upper surface is approximately the same as that of the upper surface of the insulating layer 10. The protruding electrode 111 is, for example, an ITO layer, and is disposed protruding upward from the upper surface of the base electrode 112.

[0083] Furthermore, the pillar 160 of the semiconductor device 2 replaces the channel layer 61 of embodiment 1 above, and has a channel layer 161.

[0084] The channel layer 161 is a composite oxide semiconductor layer such as an IGZO layer, and includes an upper channel layer 161a and a lower channel layer 161b, penetrating the upper electrode 51, the insulating layer 40, the gate electrode 30, and the insulating layer 20, thereby connecting the lower electrode 110 and the upper electrode 51. Furthermore, the channel layer 161 may also have a gap 161s extending in the Z direction across the upper channel layer 161a and the lower channel layer 161b.

[0085] When viewed from the Z direction, both the upper channel layer 161a and the lower channel layer 161b can have, for example, a circular shape when viewed from the Z direction, or other shapes such as circular or oval.

[0086] The upper channel layer 161a penetrates the upper electrode 51, the insulating layer 40, and the gate electrode 30, and reaches the upper surface of the insulating layer 20. The upper channel layer 161a has generally vertical sidewalls, thereby the diameter of the lower end of the upper channel layer 161a, i.e., the length in the X and Y directions, is approximately equal to the diameter of the upper end, i.e., the length in the X and Y directions.

[0087] However, the upper channel layer 161a may also have a conical shape with a diameter that decreases from the upper surface side of the insulating layer 20 toward the lower surface side.

[0088] The upper end of the lower channel layer 161b is connected to the lower end of the upper channel layer 161a and penetrates the insulating layer 20. The lower end is connected to the protruding electrode 111 that protrudes from the upper surface of the base electrode 112. In other words, the protruding electrode 111 penetrates the gate insulating layer 62 at the lower end of the lower channel layer 161b and protrudes into the lower channel layer 161b, thereby connecting the lower channel layer 161b to the lower electrode 110.

[0089] The lower channel layer 161b has the following shape: the diameter of the lower end, i.e., the length in the X and Y directions, is larger than the diameter of the upper end, i.e., the length in the X and Y directions. In this case, the diameter of the lower channel layer 161b changes continuously from the upper end to the lower end.

[0090] That is, the lower channel layer 161b has a conical shape in which the diameter increases from the upper surface side of the insulating layer 20 toward the lower surface side. However, the lower channel layer 161b may also have a curved shape in which the sidewall portion protrudes slightly outward.

[0091] Therefore, the lower channel layer 161b has a diameter at its upper end that is approximately equal to the diameter at its lower end of the upper channel layer 161a. Furthermore, the lower channel layer 161b has a diameter at its lower end that is larger than the maximum diameter of the upper channel layer 161a. That is, the lower channel layer 161b has a length at its lower end that is greater than the maximum length of the upper channel layer 161a in both the X and Y directions.

[0092] As described above, the channel layer 161 of embodiment 2 generally has a conical shape with a diameter that increases from the upper end to the lower end.

[0093] The gate insulating layer 62 of the semiconductor device 2 covers the sidewalls of the channel layer 161 and the bottom surface of the channel layer 161, excluding the through portion of the protruding electrode 111, at a height equal to that of the insulating layer 40, the gate electrode 30, and the insulating layer 20. The gate insulating layer 62 does not cover the portion of the channel layer 161 that penetrates the upper electrode 51. Therefore, the channel layer 161 can be laterally connected to the upper electrode 51.

[0094] (Manufacturing method of semiconductor devices) Next, using Figures 6 and 7, an example of the manufacturing method of semiconductor device 2 in Embodiment 2 will be described.

[0095] Figures 6 and 7 are cross-sectional views illustrating a portion of the steps in the manufacturing method of the semiconductor device 2 according to Embodiment 2. More specifically, the diagram labeled (A) in Figures 6 and 7 is a cross-sectional view of the semiconductor device 2 during manufacturing along the X direction, and the diagram labeled (B) in Figures 6 and 7 is a cross-sectional view of the semiconductor device 2 during manufacturing along the Y direction.

[0096] As shown in Figures 6(Aa)(Ba), an insulating layer 10, such as a SiN layer, is formed on the substrate. A plurality of contacts 13, a plurality of base electrodes 112, and a pad layer 12 are formed on the insulating layer 10. Furthermore, an insulating layer 20, such as a SiO layer or a Low-k layer, a gate electrode 30, and an insulating layer 40, such as a SiO layer or a Low-k layer, are sequentially formed on the insulating layer 10.

[0097] That is, apart from the process of forming the lower channel layer 61b in the insulating layer 20, the above processes are performed in the same way as those before FIG3(Aa)(Ba) of Embodiment 1.

[0098] As shown in Figures 6(Ab)(Bb), a plurality of through holes THs are formed at positions that overlap with the plurality of base electrodes 112 in the Z direction, penetrating the insulating layer 40 and the gate electrode 30 and reaching the upper surface of the insulating layer 20.

[0099] Multiple through-holes (THs) can be formed, for example, using reactive ion etching (RIE) under highly anisotropic conditions. This creates through-holes (THs) with substantially vertical sidewalls.

[0100] As shown in Figure 6(Ac)(Bc), a sidewall protective layer CB is formed on the sidewall of the plurality of through holes THs.

[0101] The sidewall protective layer CB can be obtained, for example, by forming a CVD (Chemical Vapor Deposition) carbon layer on the upper surface of the insulating layer 40 with a plurality of through-holes THs under conditions of reduced coverage. Alternatively, in the process shown in Figures 6(Ab)(Bb) above, by using a CF-based etching gas and conditions that facilitate deposition, a CF-based deposition can be formed on the sidewalls of the through-holes THs as a sidewall protective layer CB, in parallel with the formation of the through-holes THs.

[0102] As shown in Figure 6(Ad)(Bd), with the sidewall of the through hole THs protected by the sidewall protective layer CB, the bottom surface of the through hole THs is further etched to form a through hole THt that penetrates the insulating layer 40, the gate electrode 30, and the insulating layer 20.

[0103] At this point, by using conditions that weaken anisotropy and facilitate side etching, additional etching of the through-hole THs can be performed, thereby expanding the diameter of the bottom surface of the through-hole THt. This results in a through-hole THt with a generally vertical shape at the height of the insulating layer 40 and the gate electrode 30, and a larger diameter at the height of the lower surface of the insulating layer 20 than the upper vertical portion.

[0104] Subsequently, the sidewall protective layer CB is removed by ashing treatment, such as using oxygen plasma.

[0105] As shown in Figures 7(Aa)(Ba), gate insulating layers 62bx (such as SiO layer) and gate insulating layers 62bn (such as SiN layer) are sequentially formed, covering the sidewalls and bottom surfaces of each of the plurality of through holes THt. At this time, gate insulating layers 62bx and 62bn also cover the upper surface of insulating layer 40.

[0106] Furthermore, the TiN layer, i.e., the base electrode 112, is exposed on the bottom surface of the through hole THt. In this way, the gate insulating layer 62bn, such as the SiN layer, is not directly grounded to the protruding electrode 111, such as the ITO layer, which is formed later. Therefore, by implementing the method of embodiment 2, the disappearance of the protruding electrode 111 can also be suppressed.

[0107] As shown in Figures 7(Ab)(Bb), the gate insulation layers 62bx and 62bn are removed from the bottom surface of each of the plurality of through holes THt. At this time, the gate insulation layers 62bx and 62bn on the upper surface of the insulation layer 40 are also removed.

[0108] Furthermore, processing is then performed through the opening at the upper end of the through-hole THt, whose diameter is smaller than the diameter of the bottom surface of the through-hole THt. Therefore, the gate insulation layers 62bx and 62bn on the bottom surface of the through-hole THt do not need to be completely removed. That is, the gate insulation layers 62bx and 62bn can be removed only from a portion of the bottom surface of the through-hole THt that overlaps with the opening of the through-hole THt in the Z direction.

[0109] This forms a gate insulating layer 62 covering part of the sidewalls and bottom surface of each through hole THt. Furthermore, the upper surface of the base electrode 112 is exposed from the bottom surface of the through holes THt where the gate insulating layers 62bx and 62bn are partially removed.

[0110] As shown in Figures 7(Ac)(Bc), an ITO layer 51b is formed using physical vapor deposition (PVD) or similar methods. This ITO layer 51b covers the upper surface of the insulating layer 40 through the openings of a plurality of through-holes THt. The ITO layer 51b is also formed on the bottom surface of the through-holes THt exposed by the base electrode 112 through the openings of the through-holes THt. Thus, a protruding electrode 111 is formed on the bottom surface of the through-holes THt, protruding into the through-holes THt and connected at its lower end to the base electrode 112.

[0111] As shown in Figures 7(Ad)(Bd), a semiconductor layer 161f, such as an IGZO layer, is formed in a plurality of through-holes THt using methods such as ALD. At this time, the semiconductor layer 161f also covers the upper surface of the insulating layer 40.

[0112] Furthermore, at this time, processing is performed through the opening at the upper end of the through-hole THt, which has a smaller diameter than the bottom diameter of the through-hole THt. Therefore, the through-hole THt may not be completely filled by the IGZO layer or the like. In this case, a void 161s extending in the Z direction may be generated in the semiconductor layer 161f filled in the through-hole THt.

[0113] Subsequently, the semiconductor layer 161f is removed from the upper surface of the insulating layer 40 by means of CMP or the like. This forms an independent channel layer 161 extending through the ITO layer 51b, the insulating layer 40, the gate electrode 30, and the insulating layer 20. Furthermore, a pillar 160 having the channel layer 161 and the gate insulating layer 62 is formed.

[0114] Furthermore, the ITO layer 51b is processed into a pattern of upper electrodes 51 to form a plurality of upper electrodes 51 connected to each channel layer 161. Furthermore, an insulating layer 50 is formed and embedded between the plurality of upper electrodes 51.

[0115] Based on the above, semiconductor device 2 of embodiment 2 is manufactured.

[0116] (Summary) According to the semiconductor device 2 of Embodiment 2, in the channel layer 161, the length in the X direction continuously varies between the two ends in the thickness direction of the insulating layer 20, and the length in the X direction is greater at the height position of the lower surface of the insulating layer 20 than at the height position of the upper surface of the insulating layer 20. This reduces the contact resistance between the channel layer 161 and the lower electrode 110.

[0117] According to the semiconductor device 2 of embodiment 2, the lower electrode 110 has a protruding electrode 111 protruding into the channel layer 161. This can further increase the contact area between the channel layer 161 and the lower electrode 110, and further reduce the contact resistance.

[0118] In addition to the above, the semiconductor device 2 of embodiment 2 also performs the same effect as the semiconductor device 1 of embodiment 1.

[0119] (Variation Example 1) Next, using FIG8, the semiconductor device 2a of variation 1 of embodiment 2 will be described. The difference between the semiconductor device 2a of variation 1 and the semiconductor device 2 of embodiment 2 is that the lower end of the protruding electrode 111a is buried in the base electrode 112.

[0120] Figure 8 is a cross-sectional view of a portion of the manufacturing process of the semiconductor device 2a according to a variation of Embodiment 2, Example 1. More specifically, Figures 8(Aa) to 8(Ad) are cross-sectional views of the semiconductor device 2a during manufacturing along the X direction, and Figures 8(Ba) to 8(Bd) are cross-sectional views of the semiconductor device 2a during manufacturing along the Y direction.

[0121] Additionally, in the following diagrams, sometimes the same symbols are used to mark components that are the same as those in Embodiment 2 above, and their descriptions are omitted.

[0122] In the manufacturing steps of the semiconductor device 2a in Variation Example 1, the same process as shown in Figures 6(Aa)(Ba) to 7(Aa)(Ba) of Embodiment 2 is performed. This forms a through-insulating layer 40, a gate electrode 30, and an insulating layer 20, and provides a plurality of through-holes THt of gate insulating layers 62bx and 62bn on the sidewalls and bottom surface.

[0123] As shown in Figures 8(Aa)(Ba), the gate insulation layers 62bx and 62bn are removed from the bottom surface of each of the plurality of through holes THt. At this time, the gate insulation layers 62bx and 62bn on the upper surface of the insulation layer 40 are also removed.

[0124] Furthermore, at this time, the over-etching amount of the gate insulating layers 62bx and 62bn is increased, and a portion of the base electrode 112 exposed on the bottom surface of the through hole THt after the gate insulating layers 62bx and 62bn are removed is also removed. In this way, a recess 112r is formed at the upper end of the base electrode 112.

[0125] As shown in Figures 8(Ab)(Bb), an ITO layer 51b is formed covering the upper surface of the insulating layer 40 by means of PVD or the like. The ITO layer 51b is also formed on the bottom surface of the through hole THt exposed by the base electrode 112.

[0126] Furthermore, an ITO layer 51b is also filled into the recess 112r of the base electrode 112 to form a protruding electrode 111a with its lower end extending into the base electrode 112 and its upper end protruding into the through hole THt. Also, a lower electrode 110a is formed having the protruding electrode 111a and the base electrode 112.

[0127] The subsequent processing is carried out in the same way as in embodiment 2 described above.

[0128] That is, as shown in Figures 8(Ac)(Bc), a semiconductor layer 161f, such as an IGZO layer, is filled into the through-hole THt. As shown in Figures 8(Ad)(Bd), the semiconductor layer 161f is cut apart to form a pillar 160 having a channel layer 161 and a gate insulating layer 62. Furthermore, the ITO layer 51b is patterned to form the upper electrode 51.

[0129] Based on the above, a semiconductor device 2a of variation 1 is manufactured.

[0130] According to the semiconductor device 2a of Variation 1, the lower end of the protruding electrode 111a extends into the base electrode 112. This increases the contact area between the protruding electrode 111a and the base electrode 112, thereby reducing the contact resistance.

[0131] In addition to the above, the semiconductor device 2a according to Variation Example 1 also performs the same effect as the semiconductor device 2 in Embodiment 2.

[0132] (Variation Example 2) Next, using Figures 9 and 10, the semiconductor device 3 of Variation 2 of Embodiment 2 will be described. The shape of the channel layer 261 of the semiconductor device 3 of Variation 2 is different from that of Embodiment 2 described above.

[0133] Additionally, in the following diagrams, sometimes the same symbols are used to mark components that are the same as those in Embodiment 1 above, and their descriptions are omitted.

[0134] Figure 9 is a schematic diagram showing an example of the configuration of the semiconductor device 3 in Embodiment 2, Variation 2. Figure 9(a) is a cross-sectional view of the semiconductor device 3 along the X direction. Figure 9(b) is a cross-sectional view of the semiconductor device 3 along the Y direction.

[0135] As shown in Figure 9, the semiconductor device 3 replaces the insulating layers 20 and 40 of Embodiment 2, and has insulating layers 220 and 240. Insulating layers 220 and 240 can be the same as in Embodiment 2, such as SiO layers or Low-1k layers. However, insulating layer 220 has a lower density than insulating layer 240.

[0136] Furthermore, the pillar 260 of the semiconductor device 3 replaces the channel layer 161 of embodiment 2 above, and has a channel layer 261e.

[0137] The channel layer 261e is a composite oxide semiconductor layer such as an IGZO layer, and includes an upper channel layer 261a, a middle channel layer 161c, and a lower channel layer 261b. It penetrates the upper electrode 51, the insulating layer 240, the gate electrode 30, and the insulating layer 220, thereby connecting the lower electrode 110 and the upper electrode 51. Furthermore, the channel layer 261e may also have a gap 261s extending in the Z direction from the upper channel layer 261a through the middle channel layer 261c to the lower channel layer 261b.

[0138] When viewed from the Z direction, the upper channel layer 261a, the middle channel layer 261c, and the lower channel layer 261b can all have, for example, a circular shape when viewed from the Z direction, or other shapes such as circular or oval.

[0139] The upper channel layer 261a penetrates the upper electrode 51 and the insulating layer 240, and reaches the upper surface of the gate electrode 30.

[0140] The upper channel layer 261a, which penetrates and connects to the upper electrode 51, has a generally vertical sidewall. Therefore, the diameter of the upper channel layer 161a at the height of the upper surface of the upper electrode 51, i.e., its length in the X and Y directions, is approximately equal to the diameter of the upper channel layer 161a at the height of the lower surface of the upper electrode 51, i.e., its length in the X and Y directions.

[0141] However, the upper channel layer 261a may also have a conical shape with a diameter that decreases from the upper surface side of the upper electrode 51 toward the lower surface side.

[0142] In the portion penetrating the insulating layer 240, the diameter of the upper channel layer 261a at the height position of the lower surface of the insulating layer 240, i.e., its length in the X and Y directions, is larger than the diameter of the upper channel layer 261a at the height position of the upper surface of the insulating layer 240, i.e., its length in the X and Y directions. In this case, the diameter of the upper channel layer 261a changes continuously from the height position of the upper surface to the height position of the lower surface of the insulating layer 240.

[0143] That is, in the portion penetrating the insulating layer 240, the upper channel layer 261a has a conical shape in which the diameter increases from the upper surface side to the lower surface side of the insulating layer 240. However, the upper channel layer 261a may also have a curved shape in which the sidewall portion protrudes slightly outward.

[0144] The upper end of the middle channel layer 261c is connected to the lower end of the upper channel layer 261a and penetrates the gate electrode 30, reaching the upper surface of the insulating layer 220. The middle channel layer 261c has a generally vertical sidewall, thereby the diameter of the lower end of the middle channel layer 261c, i.e., its length in the X and Y directions, is approximately equal to the diameter of the upper end, i.e., its length in the X and Y directions.

[0145] However, the middle channel layer 261c may also have a conical shape with a diameter that decreases from the upper surface side of the gate electrode 30 toward the lower surface side.

[0146] The upper end of the lower channel layer 261b is connected to the lower end of the middle channel layer 261c, penetrating the insulating layer 220, and the lower end is connected to the protruding electrode 111 that protrudes from the upper surface of the base electrode 112.

[0147] Furthermore, the lower channel layer 261b, like the lower channel layer 161b in embodiment 2, has the following shape: the diameter of the lower end, i.e., the length in the X and Y directions, is larger than the diameter of the upper end, i.e., the length in the X and Y directions. In this case, the diameter of the lower channel layer 261b changes continuously from the upper end to the lower end.

[0148] That is, the lower channel layer 261b has a conical shape in which the diameter increases from the upper surface side of the insulating layer 220 toward the lower surface side. However, the lower channel layer 261b may also have a curved shape in which the sidewall portion protrudes slightly outward.

[0149] Thus, the upper channel layer 261a and the middle channel layer 261c correspond to the upper channel layer 161a in the channel layer 161 of Embodiment 2 described above, and the lower channel layer 262b corresponds to the lower channel layer 161b in the channel layer 161 of Embodiment 2 described above. In these embodiments, the shape of the upper channel layer 261a in Variation 2 is different from that in the channel layer 161 of Embodiment 2 described above.

[0150] With the configuration described above, the maximum diameter of the upper channel layer 261a, the maximum diameter of the middle channel layer 261c, and the maximum diameter of the lower channel layer 261b increase in the order of the middle channel layer 261c, the upper channel layer 261a, and the lower channel layer 261b (maximum diameter of the middle channel layer 261c < maximum diameter of the upper channel layer 261a < maximum diameter of the lower channel layer 261b).

[0151] By having this shape, the channel layer 261 of Variation Example 2 becomes a shape that is closer to a cone shape in which the diameter increases from the upper end to the lower end.

[0152] Figure 10 is a cross-sectional view of a portion of the steps in the manufacturing method of the semiconductor device 3, which is an example of a variation of Embodiment 2.

[0153] More specifically, Figures 10(Aa) to 10(Ad) are cross-sectional views of the semiconductor device 3 during manufacturing along the X direction, and Figures 10(Ba) to 10(Bd) are cross-sectional views of the semiconductor device 3 during manufacturing along the Y direction.

[0154] As shown in Figures 10(Aa)(Ba), an insulating layer 10 having a contact 13, a base electrode 112, and a pad layer 12 is formed on a substrate. An insulating layer 220 and a gate electrode 30 are sequentially formed on the insulating layer 10.

[0155] As shown in Figure 10(Ab)(Bb), an insulating layer 240 is formed on the gate electrode 30.

[0156] Here, insulating layers 220 and 240 are SiO layers or Low-k layers, formed, for example, by chemical vapor deposition (CVD) or ALD using a Si-based raw material gas and an oxidizing gas such as O2 to oxidize Si. In this case, the film formation conditions are adjusted so that the density of insulating layer 220 is lower than that of insulating layer 240.

[0157] As an example, the densities of insulating layers 220 and 240 can be adjusted by varying the flow rate of the Si feed gas relative to the oxidizing gas. More specifically, when forming insulating layer 220, increasing the flow rate of the Si feed gas relative to the oxidizing gas can reduce the density of insulating layer 220. On the other hand, when forming insulating layer 240, decreasing the flow rate of the Si feed gas relative to the oxidizing gas can increase the density of insulating layer 240.

[0158] As shown in Figures 10(Ac)(Bc), a plurality of through-holes THv are formed, penetrating the insulating layer 240, the gate electrode 30, and the insulating layer 220, respectively reaching a plurality of base electrodes 112. The plurality of through-holes THv can be formed, for example, using a resonant interconnect (RIE) under highly anisotropic conditions. This forms through-holes THv with substantially vertical sidewalls.

[0159] As shown in Figure 10(Ad)(Bd), the sidewall portions of multiple through-holes THv are wet-etched using a solution of SiO layer or Low-k layer, i.e., insulating layers 220 and 240. This forms through-holes THw with retracted sidewalls penetrating portions of insulating layers 220 and 240.

[0160] Here, in the aforementioned RIE process, except for etching specifically in the Z direction, almost no difference in the sidewall shape of the through-hole THv caused by the density difference between the insulating layers 220 and 240 is obtained. However, in wet etching, the etching process is isotropic, and based on the density difference between the insulating layers 220 and 240, for example, an etching rate difference of about 2 times can be generated.

[0161] Therefore, in the via THw, the retreat speed of the sidewalls after wet etching is lower in the portion penetrating the high-density insulating layer 240, and higher in the portion penetrating the low-density insulating layer 220. Furthermore, in the via THw, the sidewalls of the portion penetrating the tungsten layer, i.e., the gate electrode 30, hardly retreat.

[0162] Based on the above, in the through-hole THw, the diameter of the portion penetrating the gate electrode 30, i.e., the length in the X and Y directions, is the smallest. Furthermore, the diameter of the portion penetrating the insulating layer 240, i.e., the length in the X and Y directions, is larger than the portion penetrating the gate electrode 30. Also, the diameter of the portion penetrating the insulating layer 220, i.e., the length in the X and Y directions, is larger than the portion penetrating the insulating layer 240.

[0163] The subsequent processing is performed in the same manner as that shown in Figures 7(Aa)(Ba) of Embodiment 2 above. However, when removing the gate insulating layers 62bx and 62bn from the bottom surface of the through hole THw, the processing of Variation 1 above can also be applied to form a protruding electrode 111a extending from the lower end into the base electrode 112.

[0164] Based on the above, a semiconductor device 2a of variation 1 is manufactured.

[0165] According to the semiconductor device 3 of Variation 2, the shape of the channel layer 261 can be made closer to a cone shape. In this way, the embedding of semiconductor layers such as the IGZO layer can be further improved, and the contact resistance between the channel layer 261 and the lower electrode 110 can be further reduced.

[0166] In addition to the above, the semiconductor device 3 according to Variation Example 2 also performs the same effect as the semiconductor device 2 in Embodiment 2.

[0167] Furthermore, in the aforementioned variation 2, the semiconductor device 3 has a low-density insulating layer 220 and a high-density insulating layer 240. However, the density within each of the insulating layers 220 and 240 can also vary. That is, the insulating layers 220 and 240 can be configured such that the density gradually increases from the lower surface of the insulating layer 220 toward the upper surface, and the density further increases from the lower surface of the insulating layer 240 toward the upper surface.

[0168] In this case, when forming insulating layers 220 and 240, by gradually reducing the flow rate of the Si raw material gas, insulating layers 220 and 2240 with continuously varying density within the layers can be formed.

[0169] By using wet etching to process these insulating layers 220 and 240, the shape of the channel layer can be made to more closely resemble a conical shape with the diameter increasing from the top end to the bottom end.

[0170] Furthermore, in Embodiment 2 and Variations 1 and 2 described above, the channel layers 161 and 261 can be generally considered as a cone shape with a diameter that increases from the upper end to the lower end. In Figure 11, which schematically shows the channel layers 161 and 261 of Embodiment 2 and Variations 1 and 2, an example of the definition of the cone angle of such a channel layer is explained.

[0171] Figure 11 is a schematic diagram illustrating the definition of the cone angle when the channel layers 161 and 261 of Embodiment 2 and Variations 1 and 2 are regarded as cone-shaped.

[0172] As shown in Figure 11, when the channel layer is considered to be conical, the cone angle θ of the channel layer can be defined, for example, as the angle between the inner surface of the sidewall of the channel layer and the lower surface of the upper electrode. In this case, in Embodiment 2 and Variations 1 and 2, the cone angle θ of the channel layer is greater than 90°.

[0173] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, with omissions, substitutions, and modifications made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention described in the claims and their equivalents. [Reference to relevant application cases]

[0174] This application enjoys priority from Japanese Patent Application No. 2024-159433 (filed on September 13, 2024). This application incorporates the entire contents of the basic application by reference to that basic application.

[0175] 1, 2, 2a, 3: Semiconductor devices 10, 20, 40, 50, 220, 240: Insulation layer 11, 110, 110a: Lower electrode 12: Lining layer 13:Contact 30: Gate electrode 30p: Groove pattern 51: Upper electrode 51b: ITO layer 52: Plug 60, 160, 260:column 61, 161, 261, 261e: Channel layer 61a, 161a, 261a: Upper channel layer 61b, 161b, 261b: Lower channel layer 61d, 61f, 161f: Semiconductor layers 61p: Recessed pattern 62, 62n, 62x, 62bn, 62bx: Gate insulation layer 70: Bit line 111, 111a: Protruding electrodes 112: Base electrode 112r: concave part 161s, 261s: gap 261c: Middle Channel Layer CB: Sidewall Protective Layer TH, THs, THt, THv, THw: Through holes

Claims

1. A semiconductor device comprising: a first electrode; a first insulating layer disposed on the first electrode; a gate electrode disposed on the first insulating layer; a second insulating layer disposed on the gate electrode; a second electrode disposed on the second insulating layer; a channel layer having one end connected to the first electrode and the other end connected to the second electrode; and a gate insulating layer disposed between the channel layer and the gate electrode; wherein, in the channel layer, at a first height position between the two ends in the thickness direction of the first insulating layer, the length in a first direction intersecting the thickness direction increases discontinuously from the gate electrode side toward the first electrode side; the channel layer comprising: a first portion extending from the other end to the first height position and having a first length in the first direction; and a second portion extending from the first height position to the first end and having a second length in the first direction greater than the first length; The first part is a first semiconductor layer mainly composed of a composite oxide semiconductor containing a plurality of metals; the second part is a second semiconductor layer mainly composed of a composite oxide semiconductor containing a plurality of metals of the same kind as the first semiconductor layer; in the second semiconductor layer, the content of metals among the plurality of metals with lower binding strength with oxygen than other metals is higher than that in the first semiconductor layer.

2. The semiconductor device of claim 1, wherein in the first semiconductor layer, the content of the metal with a higher binding strength with oxygen than the other metals is higher than that in the second semiconductor layer.

3. The semiconductor device of claim 1, wherein the gate insulating layer extends from the height position of the upper surface of the second insulating layer, through the gate electrode, to the first height position.

4. A semiconductor device comprising: a first electrode; a first insulating layer disposed on the first electrode; a gate electrode disposed on the first insulating layer; a second insulating layer disposed on the gate electrode; a second electrode disposed on the second insulating layer; a channel layer having one end connected to the first electrode and the other end connected to the second electrode; and a gate insulating layer disposed between the channel layer and the gate electrode; wherein in the channel layer, the length of a first direction intersecting the thickness direction between the two ends of the first insulating layer is continuously varied; the length of the first direction is greater at a height position of the lower surface of the first insulating layer than at a height position of the upper surface of the first insulating layer; the first electrode having: a protrusion protruding into the channel layer.

5. The semiconductor device of claim 4, wherein the first electrode has: a base portion that supports the protrusion.

6. The semiconductor device of claim 5, wherein the lower end of the aforementioned protrusion extends into the aforementioned base portion.

7. A method for manufacturing a semiconductor device, comprising: forming a first electrode; forming a first insulating layer on the first electrode; forming a gate electrode on the first insulating layer; forming a second insulating layer on the gate electrode; forming a channel layer that penetrates the second insulating layer, the gate electrode, and the first insulating layer and is connected to the first electrode, comprising a first and a second portion; and forming the channel layer comprising: forming a second portion having a first length in the first insulating layer on the first electrode in a first direction intersecting the thickness direction of the first insulating layer; and forming the first portion, the first portion extending from the second insulating layer to the first insulating layer, being connected to the second portion in the first insulating layer, and having a second length in the first direction that is smaller than the first length; the formation of the first portion comprising: A through-hole is formed, which extends from the second insulating layer to the first insulating layer and reaches the second portion in the first insulating layer; a gate insulating layer is formed on the sidewall of the through-hole; and a first semiconductor layer, which is mainly composed of a composite oxide semiconductor containing a plurality of metals, is filled in the through-hole in which the gate insulating layer is formed.

8. The method of manufacturing a semiconductor device as claimed in claim 7, wherein the formation of the gate insulating layer comprises: forming a first gate insulating layer on the sidewall and bottom surface of the through hole; forming a second gate insulating layer on the sidewall and bottom surface of the through hole, separated by the first gate insulating layer; and removing the first and second gate insulating layers formed on the bottom surface of the through hole.

9. The method for manufacturing a semiconductor device as claimed in claim 8, wherein the first gate insulating layer is a SiN layer; and the second gate insulating layer is a SiO layer.

10. A method for manufacturing a semiconductor device as claimed in claim 7, wherein forming the second part comprises: processing the first insulating layer into a pattern of the second part to expose the first electrode; and filling the pattern with a second semiconductor layer comprising a composite oxide semiconductor containing a plurality of metals of the same kind as the first semiconductor layer.

11. A method for manufacturing a semiconductor device as claimed in claim 10, wherein the formation of the second part further comprises: additionally forming the first insulating layer in a manner that covers the second semiconductor layer.

12. A method for manufacturing a semiconductor device as claimed in claim 10, wherein the formation of the second part comprises: filling the pattern with the second semiconductor layer, wherein in the second semiconductor layer, the content of the metal with a lower binding strength with oxygen than the other metals is higher than that of the first semiconductor layer.

13. A method for manufacturing a semiconductor device as claimed in claim 10, wherein the formation of the first part comprises: filling the first semiconductor layer into the through hole, wherein in the first semiconductor layer, the content of the metal with a higher bonding strength with oxygen than the other metals is higher than that of the second semiconductor layer.

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