Semiconductor memory devices, memory systems, and control methods for semiconductor memory devices
By implementing a semiconductor memory device with a feature register group having multiple pages and a controller that assigns storage based on specific instruction sequences, the challenge of insufficient space for parameter data in interface chips is addressed, enhancing data storage capacity and efficiency.
Patent Information
- Application Number
- TW114105176
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2024-03-18
- Filing Date
- 2025-02-12
- Publication Date
- 2026-08-01
- Estimated Expiration
- 2045-02-11
AI Technical Summary
Existing semiconductor memory devices face challenges in efficiently allocating and expanding the feature register space for interface chips due to increasing demands for high-speed communication functions, leading to insufficient space for parameter data storage.
The implementation of a semiconductor memory device with an interface chip that includes a feature register group with multiple pages, allowing shared address space for parameter data storage, and a controller that interprets specific instruction sequences to assign pages for data storage, thereby expanding the available address space for parameter data.
This solution effectively increases the capacity of the feature register group in the interface chip to store parameter data, addressing the space limitations and enabling efficient storage of increased amounts of data without reducing the space allocated to memory chips.