Semiconductor memory devices, memory systems, and control methods for semiconductor memory devices

Abstract

A semiconductor memory device, memory system, and method are provided that can appropriately store parameter data in a group of feature registers provided in an interface chip. The semiconductor memory device includes a terminal group, a first device, and a second device. The first device includes a first group of registers mapped to a first address space and a memory cell array. The second device is disposed between the terminal group and the first device. The second device includes a second group of registers mapped to a plurality of pages in a second address space that is exclusively shared with the aforementioned first address space. When the second device receives a sequence of instructions for setting a parameter data, if the address included in the sequence of instructions for setting the parameter data is a first value, it identifies the page from the plurality of pages that is the target page for storing the parameter data based on the sequence of instructions for setting the parameter data.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device, memory system and method. [Previous Technology]

[0002] A semiconductor memory device exists in which a semiconductor integrated circuit called an interface chip is arranged between a plurality of memory chips and an external terminal group that is connected to an external controller (hereinafter referred to as a memory controller). In this semiconductor memory device, data transmission between the memory controller and the plurality of memory chips is performed via the interface chip. By distributing the load of the transmission lines through the interface chip, the memory system can operate at high speed even when a plurality of memory chips are provided.

[0003] The interface chip is the same as the memory chip, and has a group of feature registers that serve as temporary registers for function settings. The storage of parameter data for each of the feature register groups of the memory chip and the feature register groups of the interface chip is executed using common specific commands. [Summary of the Invention]

[0004] One embodiment aims to provide a semiconductor memory device, memory system and method capable of appropriately storing parameter data in a group of feature registers provided by an interface chip.

[0005] According to one embodiment, the semiconductor memory device includes a terminal group, a first device, and a second device. At the terminal group, a command sequence containing a setting instruction (address) is input. The first device includes a first register group mapped to a first address space and a memory cell array. When the address is included in the first space, the first device stores parameter data for the first register group. When the address is not included in the first space, the first device does not store parameter data for the first register group. The second device is disposed between the terminal group and the first device. The second device includes a second register group mapped to a plurality of pages in a second address space that exclusively shares the first address space. The second device is configured to, when the address is the first value, specify the page containing the storage target of parameter data in a plurality of pages based on the instruction sequence.

Implementation Method

[0007] Hereinafter, with reference to the attached drawings, a detailed description will be provided of the semiconductor memory device, memory system, and method according to embodiments. However, the present invention is not limited to these embodiments.

[0008] (First Embodiment) Figure 1 is a schematic diagram showing one example of the configuration of the memory system SYS in the first embodiment.

[0009] The memory system SYS is capable of connecting to the host HS. The communication path connecting the host HS and the memory system SYS, and the specifications used for communication via this path, are not limited to a specific specification. The host HS may be, for example, a personal computer, a portable information terminal, or a server. When the host HS accesses the memory system SYS, it sends access commands to the memory system SYS. Access commands include write commands and read commands, etc.

[0010] The memory system SYS includes a semiconductor memory device 1, a memory controller MC, and RAM (Random Access Memory) 2.

[0011] The memory controller MC is a control device for controlling the semiconductor memory device 1. The memory controller MC is one part of the control of the semiconductor memory device 1, and performs data transfer between the host HS and the semiconductor memory device 1 in accordance with the access instructions from the host HS.

[0012] RAM2 provides functions such as a buffer area, a cache area, and a program loading area for the memory controller MC. For example, the memory controller MC can buffer the data transferred between the host HS and the semiconductor memory device 1 into RAM2. Furthermore, the memory controller MC loads firmware programs into RAM2 for use, or buffers or caches various management data into RAM2. In the example shown in Figure 1, RAM2 is configured outside the memory controller MC. RAM2 can also be embedded within the memory controller MC.

[0013] The semiconductor memory device 1 includes a terminal group T, an interface chip IFC, and a plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3. The interface chip IFC is disposed between the terminal group T and the plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3.

[0014] Each of the plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 is, for example, a non-volatile memory chip such as NAND flash memory. Here, it is assumed that each of the plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 is a NAND flash memory chip.

[0015] The semiconductor memory device 1 can be mounted as an MCP (Multi Chip Package) in which memory chips CP0-0 to CP0-3 and memory chips CP1-0 to CP1-3 are laminated respectively. When the semiconductor memory device 1 is mounted as an MCP, the interface chip IFC and the surrounding area of ​​the plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 can also be sealed with molding resin at the semiconductor memory device 1.

[0016] Furthermore, the semiconductor memory device 1 has a plurality of channels that connect a plurality of memory chips CP0-0 to CP0-3, CP1-0 to CP1-3 to an interface chip IFC. Based on the meaning of the channels that connect NAND flash memory, each of these plurality of channels is labeled as a memory channel MCH.

[0017] In the example of Figure 1, the semiconductor memory device 1 is a plurality of memory channels MCH, and has memory channels MCH0 and MCH1. Through memory channel MCH0, four memory chips CP0-0 to CP0-3 are connected to the interface chip IFC, and through memory channel MCH1, four memory chips CP1-0 to CP1-3 are connected to the interface chip IFC.

[0018] Each memory channel (MCH) is configured based on a specific specification. When each memory chip CP0-0 to CP0-3 and CP1-0 to CP1-3 is a NAND flash memory, the specific specification is, for example, Toggle DDR specification.

[0019] Furthermore, the number of memory chips CP included in the semiconductor memory device 1 is not limited to 8. Also, the number of memory channels MCH that connect the interface chip IFC to the plurality of memory chips CP is not limited to 2.

[0020] In addition, memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 are examples of the first device. Interface chip IFC is an example of the second device.

[0021] Thereafter, there will be cases where memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 are each marked as memory chip CP.

[0022] The semiconductor memory device 1 is connected to the memory controller MC via a channel. Based on the fact that it is a host-side channel when viewed from the interface chip IFC, this channel is labeled as the host channel HCH.

[0023] The host channel HCH is configured based on specific specifications. When each memory chip CP is a NAND flash memory, the specific specifications are, for example, Toggle DDR specifications.

[0024] The host channel HCH includes signal lines for transmitting the chip enable signal CEn, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal RE / REn, the data strobe signal DQS / DQSn, the data signal DQ[7:0] with a specific bit width (here, as an example, it is an 8-bit width), the ready-busy signal R / Bn1, and the ready-busy signal R / Bn2. Additionally, the "n" at the end of the component symbol representing the signal indicates that it is a signal operated with negative logic. Whether each signal is acted upon using negative logic or positive logic can be designed arbitrarily.

[0025] Cen is a chip enable signal used to enable the memory chip CP of the accessed object. DQS / DQSn is a signal indicating that data sent via data signal DQ[7:0] should be imported into the target device. DQS / DQSn is a differential signal composed of DQS and DQSn. CLE is a signal indicating that data signal DQ[7:0] is an instruction. ALE is a signal indicating that data signal DQ[7:0] is an address. The write enable signal WEn is a signal indicating to the target device that an instruction or address to be sent via data signal DQ[7:0] will be imported. The read enable signal RE / REn is a signal indicating to the target device that data signal DQ[7:0] will be output. The read enable signal RE / REn is a differential signal composed of the read enable signal RE and the read enable signal REn. The ready / busy signals R / Bn1 and R / Bn2 are signals indicating whether the device is in a ready state (waiting for instruction reception) or a busy state (unable to execute even if an instruction is received). Furthermore, the configuration of the transmission ready / busy signal R / Bn included in the host channel HCH is not limited to the above examples. For example, the host channel HCH may also have a signal line for transmitting a single preparation or busy signal R / Bn generated by a wired or connected connection based on the preparation or busy signal R / Bn associated with memory channel MCH0 and the preparation or busy signal R / Bn associated with memory channel MCH1.

[0026] Each of memory channels MCH0 and MCH1 is capable of sending and receiving signals of the same type as the host channel HCH. That is, each of memory channels MCH0 and MCH1 includes signal lines for transmitting chip enable signal CEn, signal lines for transmitting instruction latch enable signal CLE, signal lines for transmitting address latch enable signal ALE, signal lines for transmitting write enable signal WEn, signal lines for transmitting read enable signal RE / REn, signal lines for transmitting data strobe signal DQS / DQSn, signal line group for transmitting data signal DQ[7:0], and signal lines for transmitting ready-busy signal R / Bn.

[0027] Figure 2 is a schematic diagram used to explain the more detailed connection relationship between the interface chip IFC and each memory chip CP in the first embodiment.

[0028] As shown in Figure 2, the four memory chips CP0-0 to CP0-3 are connected in common with memory channel MCH0. Similarly, the four memory chips CP1-0 to CP1-3 are connected in common with memory channel MCH1.

[0029] In addition, memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 may not be connected in common with all the signal lines constituting the corresponding memory channel MCH. Memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 may also be configured such that several signal lines constituting the corresponding memory channel MCH, excluding the signal lines transmitting data signals DQ[7:0], are used to connect the interface chip IFC to the individual memory chips CP one-to-one.

[0030] The interface chip IFC is capable of independently performing data transfers via memory channel MCH0 and memory channel MCH1. Furthermore, the host channel HCH, which connects the memory controller MC and the interface chip IFC, is controlled to prevent data from lingering at the interface chip IFC even when data transfers via memory channel MCH0 and memory channel MCH1 are performed in parallel. Therefore, the host channel HCH is configured to transmit data at a rate that is the sum of the transfer rates of memory channel MCH0 and memory channel MCH1. In other words, the host channel HCH can transmit data at twice the transfer rate of memory channel MCH.

[0031] Each memory chip CP is assigned a unique identification number (LUN) within the semiconductor memory device 1. The memory controller MC pre-memorizes the relationship between the LUN assigned to each memory chip CP and the memory channel MCH that is the connection target of the memory chip CP. In the example shown in Figure 2, the memory controller MC pre-memorizes the following: "LUN0 is assigned at memory chip CP0-0, LUN1 is assigned at memory chip CP0-1, LUN2 is assigned at memory chip CP0-2, LUN3 is assigned at memory chip CP0-3, LUN4 is assigned at memory chip CP1-0, LUN5 is assigned at memory chip CP1-1, LUN6 is assigned at memory chip CP1-2, and LUN7 is assigned at memory chip CP1-3."

[0032] Figure 3 is a diagram illustrating one example of the configuration of the interface chip IFC and each memory chip CP in the first embodiment. Memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 have a common configuration. In this figure, the configuration of memory chips CP0-0 and CP1-0 is shown as representative of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3, and the configuration of other memory chips CP is omitted.

[0033] The interface chip IFC has a host interface 101, two memory interfaces 102, and a controller 103.

[0034] The host interface 101 is a PHY circuit for sending and receiving electrical signals to and from the host HA via the host channel HCH.

[0035] Memory interface 102-0, one of the two memory interfaces 102, is a PHY circuit for transmitting and receiving electrical signals via memory channel MCH0 for the four memory chips CP0-1 to CP0-3. Memory interface 102-1, one of the two memory interfaces 102, is a PHY circuit for transmitting and receiving electrical signals via memory channel MCH1 for the four memory chips CP1-0 to CP1-3.

[0036] Controller 103 is configured between host interface 101 and two memory interfaces 102. Controller 103 controls the transmission and reception of signals between host interface 101 and two memory interfaces 102.

[0037] The controller 103 is equipped with an instruction decoder 111 and a feature temporary register group 112.

[0038] The instruction decoder 111 parses signals such as instructions received from the host HA via the host channel HCH. The instruction decoder 111 can transmit signals to the memory chip CP according to the parsing results. When the instruction is an action instruction for the interface chip IFC, the instruction decoder 111 can act according to the instruction.

[0039] Feature register group 112 is a group of registers used for setting the functions of the interface chip IFC. In feature register group 112, parameter data is stored for one or more functions of the interface chip IFC.

[0040] Each memory chip CP has a memory interface 201, access circuit 202, feature temporary register group 203 and memory cell array 204.

[0041] The memory interface 201 is a PHY circuit for sending and receiving electrical signals via the memory channel MCH to the interface chip IFC.

[0042] The memory cell array 204 has a plurality of memory cell transistors. Each memory cell transistor is associated with a row and a column. The memory cell array 204 stores data indicated by write instructions from the memory controller MC via the interface chip IFC.

[0043] Feature register group 203 is a register used for setting the function of memory chip CP. In feature register group 203, parameter data is stored for one or more functions of memory chip CP.

[0044] The access circuit 202, for example, includes a signal processing circuit, a row decoder, a column decoder, a sense amplifier, a latching circuit, and a voltage generation circuit. The access circuit 202 performs access to the memory cell array 204 or storage of parameter data of the feature temporary register group 203 in response to instructions received from the memory controller MC via the interface chip IFC.

[0045] In addition, feature register group 203 is one example of the first register group. Feature register group 112 is one example of the second register group.

[0046] The memory controller MC uses a common setting instruction to store parameter data of the feature register group 112 of the interface chip IFC and the feature register group 203 of each memory chip CP. This setting instruction is called the SetFeature instruction.

[0047] The size of the address space (marked as the feature register space) that can be designated as the storage target for parameter data via the SetFeature instruction is defined based on specifications. For example, for semiconductor memory devices with NAND flash memory, a feature register space consisting of 256 addresses is defined based on JEDEC (Joint Electron Device Engineering Councils). Each memory manufacturer is able to assign the required functions to this feature register space.

[0048] The semiconductor memory device 1 is equipped with feature register groups 112 and 203. Therefore, it is necessary for the feature register groups 112 and 203 to share a limited feature register space.

[0049] As one example of a technique for sharing feature register space, a technique compared with an embodiment will be described. The technique compared with the embodiment is referred to as a "comparative example". According to the comparative example, a portion of the feature register space is mapped to the feature register group of each memory chip, and another portion is mapped to the feature register group of the interface chip. That is, the feature register space is simply divided into a portion of space used by each memory chip and a portion of space used by the interface chip.

[0050] In recent years, the demand for high-speed interface chips has been increasing. As a result, there is a need for interface chips to prepare a large number of temporary registers that can perform various communication-related functions such as training functions or equalizer functions. That is, the amount of parameter data set for interface chips (and memory chips) is increasing.

[0051] In contrast, according to the comparative example, the feature register space is simply divided into a portion of space for each memory chip and a portion of space for the interface chip. Therefore, it is difficult to allocate a large space for the portion of space for the interface chip, and the portion of space for the interface chip may become insufficient relative to the amount of parameter data increased.

[0052] In the first embodiment, the feature register group 112 has a plurality of pages, and a common space is mapped across the plurality of pages. Furthermore, the interface chip IFC is configured such that when the address contained in the instruction sequence of the SetFeature instruction is a specific value, the instruction sequence of the SetFeature instruction is interpreted as an instruction for page assignment. In this way, the space used by the interface chip IFC is expanded without reducing the space used by each memory chip CP.

[0053] In the example shown in Figure 3, the feature register group 203 of each memory chip CP has 240 memory regions with distinct addresses ranging from 00h to EFh. That is, the feature register group 203 is a feature register space mapped to the range of 00h to EFh. Each of the 240 memory regions has a memory capacity of 32 bits.

[0054] The feature register group 112 of the interface chip IFC comprises a plurality of 16 memory regions, each with a distinct address in the range of F0h to FFh. Each of the 16 memory regions is considered a distinct page. That is, each of the plurality of pages in the feature register group 112 is mapped to a feature register space in the range of F0h to FFh. At each page, a unique value is assigned as an identification number. The value assigned to each page is marked as a page number. Each of the 16 memory regions contained in each page has a memory capacity of 32 bits.

[0055] Each address assigned to the feature register group 203 of the memory chip CP (in the example shown in FIG1, addresses 00h to EFh) is marked as a memory feature address. Each address assigned to the feature register group 112 of the interface chip IFC (in the example shown in FIG1, addresses F0h to FFh) is marked as an interface feature address. Furthermore, there may be cases where addresses contained within the feature register space are marked as feature addresses.

[0056] The instruction decoder 111 is configured to interpret the address F0h in the interface feature address as an instruction for page specification (marked as a page specification identifier).

[0057] The SetFeature instruction is transmitted within a specific instruction sequence. The instruction sequence used to transmit the SetFeature instruction includes address fields and data fields, and the page instruction identifier is transmitted using the address fields.

[0058] Figure 4 is a diagram showing the structure of the instruction sequence used to transmit the SetFeature instruction in the first embodiment.

[0059] Furthermore, the SetFeature instruction includes a first SetFeature instruction and a second SetFeature instruction. The first SetFeature instruction is a SetFeature instruction used to set parameter data for a plurality of memory chip CPs in a common manner. The second SetFeature instruction is a SetFeature instruction used to specify one memory chip CP using a LUN and to set parameter data for the specified memory chip CP. Figure 4 shows the instruction sequence used to perform the transmission of the first SetFeature instruction. Hereinafter, the instruction sequence used to perform the transmission of the first SetFeature instruction will be labeled as the first sequence.

[0060] The first sequence is configured to transmit the first SetFeature instruction C1, the first address, and the setting data in this order. The first SetFeature instruction C1, the first address, and the setting data are transmitted via the signal line group of the data signal DQ[7:0]. The first SetFeature instruction C1 is transmitted in one instruction transmission cycle. The first address is transmitted in one address transmission cycle. The setting data is transmitted in four data transmission cycles. The instruction transmission cycle is a cycle in which the data signal DQ[7:0] is transmitted as an instruction using the latch enable signal CLE. The address transmission cycle is a cycle in which the data signal DQ[7:0] is transmitted as an address using the address enable signal ALE. The data transmission cycle is a cycle in which the data signal DQ[7:0] is transmitted as data.

[0061] The data signal DQ[7:0] is transmitted in 8-bit width. Since the first address is transmitted in one address transmission cycle, the first address is an address that can transmit the range of 00h to FFh, that is, an address that can transmit the range of the feature register space.

[0062] The setting data is transmitted in a 4-bit data transmission cycle. Therefore, in the first sequence of one, 32 bits (=8 bits × 4) of setting data can be transmitted.

[0063] In the first embodiment, the first sequence is configured to be able to transmit any one of "an address conforming to a memory feature address", "an address conforming to an interface feature address", and "an address conforming to a page identifier" as the first address.

[0064] Furthermore, the first sequence is configured to transmit not only parameter data but also data that specifies a page (hereinafter referred to as page specification) as setting data. When the memory controller MC transmits page specification as setting data, it transmits the page number as setting data, thereby specifying any one of the plurality of pages in the feature register group 112.

[0065] Figure 5 is a diagram illustrating the method for setting parameter data for the first embodiment using the first sequence.

[0066] In the example shown in Figure 5, the memory controller MC transmits the first sequence SQ1, the first sequence SQ2, the first sequence SQ3, and the first sequence SQ4 to the semiconductor memory device 1 in this order.

[0067] The first sequence SQ1 contains the address F0h, which is the first address and serves as the page assigner identifier, and also contains the value 01h, which is the page assignment value for page #1, as the setting data. If the interface chip IFC receives the first sequence SQ1, the instruction decoder 111 recognizes that the first sequence SQ1 contains the page assigner identifier, and therefore identifies it as an instruction sequence for page assignment. The instruction decoder 111 recognizes that page #1 has been assigned because the first sequence SQ1 contains the value 01h, which is the setting data.

[0068] The first sequence SQ2 is an address F1h that conforms to the interface feature address and is also parameter data that is configured. If the interface chip IFC receives the first sequence SQ2 after the first sequence SQ1, the instruction decoder 111 stores the parameter data contained in the first sequence SQ2 at the address F1h, which is the address of the page #1 that has been assigned, within the feature temporary register group 112.

[0069] The first sequence SQ3 contains the address F0h, which is the first address and serves as the page assigner identifier, and contains the value 02h, which is the page assignment value for page #2, as the setting data. If the interface chip IFC receives the first sequence SQ3, the instruction decoder 111 recognizes that the first sequence SQ3 contains the page assigner identifier, and therefore identifies it as an instruction sequence for page assignment. The instruction decoder 111 recognizes that page #2 has been assigned because the first sequence SQ3 contains the value 02h, which is the setting data.

[0070] The first sequence SQ4 contains address FFh, which is the first address and conforms to the interface feature address, and contains parameter data as setting data. If the interface chip IFC receives the first sequence SQ4 after the first sequence SQ3, the instruction decoder 111 stores the parameter data contained in the first sequence SQ4 at the address FFh, which is the address of the page #2 that has been assigned, within the feature temporary register group 112.

[0071] Thus, the feature register group 112 of the interface chip IFC has a plurality of pages with a total of 16 addresses, from F0h to FFh. The first sequence is configured to allow switching the storage target of parameter data from the plurality of pages. Therefore, the address space that can be used in setting parameter data for the interface chip IFC is expanded in accordance with the number of pages provided by the feature register group 112. Therefore, the capacity of the feature register group 112 of the interface chip IFC that can store parameter data can be increased. That is, the amount of parameter data that can be stored in the feature register group 112 is increased compared to the comparative example.

[0072] Figure 6 is a flowchart illustrating one example of the operation of the interface chip IFC in the first embodiment.

[0073] If the interface chip IFC receives the first sequence from the memory controller MC via the terminal group T (S101), then the controller 103 transmits the received first sequence to the memory chip CP group (S102).

[0074] The instruction decoder 111 determines whether the first address contained in the received first sequence conforms to the page specification identifier (S103). If following the example shown in Figures 3 and 5, the address F0h conforms to the page specification identifier.

[0075] When the first address matches the page identifier (S103, Yes), the instruction decoder 111 identifies the specified page based on the setting data contained in the first sequence. Then, the instruction decoder 111 remembers the specified page (S104).

[0076] When the first address does not conform to the page specified identifier (S103, No), the instruction decoder 111 determines whether the first address conforms to the interface feature address (S105).

[0077] Following the examples shown in Figures 3 and 5, addresses F0h to FFh conform to interface feature addresses. Furthermore, address F0h is used as a page identifier. Therefore, at S105, when the first address is one of addresses F1h to FFh, the instruction decoder 111 determines that the first address conforms to the interface feature address.

[0078] When the first address matches the interface feature address (S105, Yes), the instruction decoder 111 stores the parameter data, which is included as setting data in the first sequence, at the location represented by the first address of the specified page in the feature register group 112 (S106).

[0079] When the first address does not conform to the interface feature address (S105, No), or after S104, or after S106, the interface chip IFC system ends its operation.

[0080] The interface chip IFC performs operations S102 to S106 during each first sequence of signal reception. This enables the operation shown in Figure 5.

[0081] Figure 7 is a flowchart illustrating one example of the operation of the memory chip CP in the first embodiment. Furthermore, all the memory chip CPs included in the semiconductor memory device 1 perform common operations. Here, as a representative of all memory chip CPs, the operation of one memory chip CP will be explained.

[0082] If the memory chip Cp receives the first sequence through the interface chip IFC (S201), the access circuit 202 determines whether the first address contained in the received first sequence matches the memory characteristic address (S202).

[0083] If we follow the example shown in Figures 3 and 5, then addresses 00h to EFh are memory characteristic addresses. Therefore, at S202, when the first address is one of addresses 00h to EFh, the access circuit 202 determines that the first address is a memory characteristic address.

[0084] When the first address matches the memory feature address (S202, Yes), the access circuit 202 stores the parameter data, which is included as setting data in the first sequence, at the location represented by the first address in the feature temporary register group 203 (S203).

[0085] When the first address does not conform to the memory feature address (S202, No), or after S203, the memory chip CP system ends its operation.

[0086] Furthermore, the above explanation pertains to an example where a first sequence is used as the instruction sequence for transmitting the SetFeature instruction. The semiconductor memory device 1, even when receiving an instruction sequence (labeled as the second sequence) for transmitting the second SetFeature instruction, can perform the same operation as when receiving the first sequence (for example, the operation shown in Figures 5 and 6).

[0087] Figure 8 is a diagram showing the structure of the second sequence of other instruction sequences used to transmit the SetFeature instruction in the first embodiment.

[0088] The second sequence is configured to transmit the 2nd SetFeature instruction C2, the 2nd address, the 1st address, and the setting data in this order. The 2nd SetFeature instruction C2 is transmitted in one instruction transmission cycle. The 1st address and the 2nd address are each transmitted in one address transmission cycle. The setting data is transmitted in four data transmission cycles.

[0089] The second address is the address that can be specified by the LUN.

[0090] At the interface chip IFC, the instruction decoder 111 performs a series of actions as shown in Figure 6 based on the first address and setting data, regardless of the second address.

[0091] When the second address of each memory chip CP is in accordance with the LUN assigned to the memory chip CP it possesses, the access circuit 202 performs a series of operations as shown in FIG7.

[0092] As described above, according to the first embodiment, an instruction sequence containing a SetFeature instruction for the first address is input at the terminal group T. The memory chip CP includes a feature register group 203 that is mapped to a portion of the feature register space (e.g., a space ranging from 00h to EFh) and a memory cell array 204. When the first address is included in the portion of the space mapped to the feature register group 203, the memory chip CP stores parameter data for the feature register group 203; when the first address is not included in the portion of the space mapped to the feature register group 203, it does not store parameter data for the feature register group 203. The interface chip IFC includes a feature register group 112. Feature register group 112 includes a plurality of pages that are exclusively shared with the portion of space mapped to feature register group 203 (e.g., the space in the range of F0h to FFh). When the first address contained in the received instruction sequence matches the page specification identifier, the interface chip IFC specifies the page of the parameter data storage target based on the setting data contained in the instruction sequence.

[0093] Therefore, the space available for setting parameter data in the interface chip IFC is expanded according to the number of pages provided by the feature register group 112. This increases the capacity of the feature register group 112 of the interface chip IFC, which can store parameter data. This makes it possible to increase the amount of parameter data that can be stored in the feature register group 112 compared to the comparative example. That is, it makes it possible to appropriately store parameter data in the feature register group 112 provided by the interface chip IFC.

[0094] Furthermore, according to the first embodiment, when the interface chip IFC receives an instruction sequence containing a value conforming to the page specification identifier as the first address, it specifies one of the multiple pages of the feature register group 112 based on the setting data contained in the instruction sequence. Then, when the interface chip IFC receives an instruction sequence containing an interface feature address that does not conform to the page specification identifier as the first address, it stores the parameter data included as setting data in the instruction sequence at the specified page of the multiple pages of the feature register group 112.

[0095] Therefore, it is possible to increase the amount of parameter data that can be stored in the feature register group 112 compared to the comparative example. That is, it is possible to appropriately store parameter data in the feature register group 112 provided by the interface chip IFC.

[0096] (Second Embodiment) In the second embodiment, the description addresses matters that differ from those in the first embodiment. For matters that are the same as those in the first embodiment, the description is omitted or a brief description is given.

[0097] Figure 9 is a diagram illustrating one example of the configuration of the interface chip IFC and each memory chip CP in the second embodiment.

[0098] In the second embodiment, the controller 103 of the interface chip IFC is equipped with an instruction decoder 111a instead of the instruction decoder 111. The instruction decoder 111a is configured to specify a page based on the second sequence.

[0099] Each memory chip CP replaces the access circuit 202 and has an access circuit 202a.

[0100] Figure 10 is a diagram showing the composition of the second sequence in the second embodiment.

[0101] The second sequence is configured to transmit the second SetFeature instruction C2, the second address, the first address, and the setting data in this order.

[0102] The second sequence is configured to be able to transmit both "an address conforming to memory feature addresses" and "an address conforming to interface feature addresses" as the first address. In other words, it is used as the first address to transmit the address of either "a portion of the space mapped to feature register group 203 (here, the space in the range of 00h to EFh)" or "a portion of the space mapped to feature register group 112 (for example, the space in the range of F0h to FFh)".

[0103] The second sequence is configured to be able to transmit both the LUN and the page specification as the second address. More specifically, the instruction decoder 111a interprets the second address as a page specification when the first address is included in the interface feature address, that is, in the portion of space mapped to the feature register group 112.

[0104] Following the example shown in Figures 2 and 9, the semiconductor memory device 1 has eight memory chips CP that are assigned LUN0 to LUN7. Therefore, the memory controller MC can specify one of the eight memory chips CPs' LUNs by transmitting a value in the range of 00h to 07h as the second address.

[0105] Furthermore, when the memory controller MC transmits page assignments as the second address, it can transmit the page number as the second address and assign any page.

[0106] The second sequence is configured to transmit parameter data as setting data.

[0107] Figure 11 is a diagram illustrating the method for setting parameter data for the second implementation form using the second sequence.

[0108] In the example shown in Figure 11, the memory controller MC transmits the second sequence SQ11 and the second sequence SQ21 to the semiconductor memory device 1 in this order.

[0109] The second sequence SQ11 contains an address F1h that conforms to the interface feature address and contains the value 01h as the second address. If the second sequence SQ11 is the interface chip IFC receiving signal, then the instruction decoder 111a recognizes the second sequence SQ11 as an instruction sequence of a SetFeature instruction targeting the interface chip IFC because the first address conforms to the interface feature address. Regarding the second sequence targeting the interface chip IFC, the instruction decoder 111a interprets the second address as a page specification. In the example shown in Figure 11, since the second sequence SQ11 contains the value 01h as the second address, the specification decoder 111a recognizes that page #1 has been specified. Therefore, the instruction decoder 111a stores the parameter data, which is included as setting data in the second sequence SQ11, at the address F1h of page #1 in the feature register group 112.

[0110] The second sequence SQ21 contains an address FFh that conforms to the interface feature address, and has the value 02h as the second address. The instruction decoder 111a, because the first address conforms to the interface feature address, recognizes the second sequence SQ21 as an instruction sequence targeting the interface chip IFC as a SetFeature instruction, and interprets the second address as a page specification. In the example shown in Figure 11, since the second sequence SQ21 contains the value 02h as the second address, the specification decoder 111a recognizes that page #2 has been specified. Therefore, the instruction decoder 111a stores the parameter data contained in the second sequence SQ21 as setting data at the location represented by the address FFh of page #2 within the feature register group 112.

[0111] Figure 12 is a flowchart illustrating one example of the operation of the interface chip IFC in the second embodiment.

[0112] If the interface chip IFC receives the second sequence from the memory controller MC (S301), the controller 103 transmits the received second sequence to the memory chip CP group (S302).

[0113] The instruction decoder 111a determines whether the first address contained in the received second sequence conforms to the interface feature address (S303).

[0114] In addition, if we follow the example shown in Figures 9 and 11, the addresses F0h to FFh are consistent with the interface feature addresses.

[0115] When the first address matches the interface feature address (S303, Yes), the instruction decoder 111a specifies the designated page based on the value contained as the second address in the second sequence (S304). Furthermore, the instruction decoder 111a stores the parameter data contained as setting data in the second sequence at the location represented by the first address of the designated page within the feature register group 112 (S305).

[0116] When the first address does not conform to the interface feature address (S303, No), or after S305, the interface chip IFC system ends its operation.

[0117] The interface chip IFC performs operations S302 to S305 during each second reception sequence. As a result, the operation shown in Figure 11 is realized.

[0118] Figure 13 is a flowchart illustrating one example of the operation of the memory chip CP in the second embodiment. Similar to the first embodiment, all memory chip CPs in the semiconductor memory device 1 perform common operations. Here, as a representative of all memory chip CPs, the operation of one memory chip CP will be explained.

[0119] If the memory chip CP receives the second sequence via the interface chip IFC (S401), the access circuit 202 determines whether the second address contained in the received second sequence matches the LUN assigned to the memory chip CP it possesses (S402).

[0120] When the second address is consistent with the LUN assigned to the memory chip CP it possesses (S402, Yes), the access circuit 202 determines whether the second address contained in the received second sequence is consistent with the memory feature address (S403).

[0121] If we follow the example shown in Figures 9 and 11, then addresses 00h to EFh are memory characteristic addresses. Therefore, at S403, when the first address is one of addresses 00h to EFh, the access circuit 202 determines that the first address is a memory characteristic address.

[0122] When the first address is a memory feature address (S403, Yes), the access circuit 202 stores the parameter data, which is included in the first sequence as setting data, at the location represented by the first address in the feature temporary register group 203 (S404).

[0123] When the second address does not conform to the LUN of the memory chip CP that is assigned to its own access circuit 202 (S402, No), or when the first address does not conform to the memory feature address (S403, No), or after S404, the memory chip CP ends its operation.

[0124] Thus, according to the second embodiment, the second sequence is configured to transmit a LUN or a page number as a second address. When the first address is included in a portion of the space mapped to the feature register group 112, the interface chip IFC interprets the second address as a page designation, that is, as a page number. Subsequently, the interface chip IFC stores parameter data at the location represented by the first address of the page corresponding to the page number among the plurality of pages included in the feature register group 112.

[0125] Since the second address of the second sequence can be used to specify the page, the memory controller MC becomes capable of issuing instructions for both page specification and parameter data storage through a second sequence.

[0126] (Third Embodiment) In the third embodiment, explanations are provided for matters that differ from those in the second embodiment. For matters that are the same as those in the second embodiment, explanations are omitted or provided in a brief manner.

[0127] In the third embodiment, the memory controller MC is the same as in the second embodiment, capable of using the second sequence to store parameter data in the feature register group of the interface chip IFC. However, the method of specifying the page is different from that in the second embodiment.

[0128] The second address is transmitted in one address transmission cycle with a width of 8 bits, therefore, 256 values ​​can be transmitted as the second address. However, when the number of memory chips CP provided in the semiconductor memory device 1 is less than 256, 256 values ​​are not required in the designation of the LUN. For example, following the example shown in FIG1, since the number of memory chips CP provided in the semiconductor memory device 1 is 8, only 8 values ​​are required in the designation of the LUN.

[0129] In the third embodiment, a plurality of values ​​that are not used in the LUN specification are used in the page specification, which are among the 256 values ​​that can be transmitted as the second address.

[0130] Figure 14 is a diagram showing the composition of the second sequence in the third implementation.

[0131] The second sequence is configured to transmit the second SetFeature instruction C2, the second address, the first address, and the setting data in this order.

[0132] The second sequence is configured to be able to transmit both the LUN and the page specification as the second address. Of the 256 values ​​that can be transmitted as the second address, the value of "the number of memory chips CP present at least at the semiconductor memory device 1" is used in the LUN specification, and the remaining quantity values ​​are used in the page specification. According to the example shown in FIG14, values ​​in the range of 00h to 0Fh are used in the LUN specification, and values ​​in the range of 10h to FFh are used in the page specification.

[0133] When the second address is a value within the range of address 00h to 0Fh (condition 1), the first address is interpreted as conforming to the memory characteristic address at the interface chip IFC. When the second address is a value within the range of address 10h to FFh (condition 2), the first address is interpreted as conforming to the interface characteristic address at the interface chip IFC.

[0134] Figure 15 is a diagram illustrating one example of the configuration of the interface chip IFC and each memory chip CP in the third embodiment.

[0135] In the third embodiment, the controller 103 of the interface chip IFC is equipped with an instruction decoder 111b instead of an instruction decoder 111a. Furthermore, the controller 103 is equipped with a feature register group 112b instead of a feature register group 112. Also, the controller 103 is equipped with memory 113.

[0136] The feature register group 112b comprises a complex set of 256 memory regions, each assigned a distinct address ranging from 00h to FFh. Each group of 256 memory regions is treated as a distinct page and assigned a unique page number. Each of the 256 memory regions contained in each group has a memory capacity of 32 bits.

[0137] Memory 113 is a non-volatile memory in which the translation table 120 is stored. Memory 113 may be, for example, an eFuse or a ROM (Read Only Memory). The translation table 120 is stored in memory 113 during the manufacture of semiconductor memory device 1. However, the type of memory 113 and the timing of the storage of translation table 120 are not limited to these.

[0138] Each memory chip CP replaces the feature register group 203 with a feature register group 203b. The feature register group 203b has 256 memory regions with distinct addresses ranging from 00h to FFh. Each of the 256 memory regions in the feature register group 203 has a memory capacity of 32 bits.

[0139] Each memory chip CP replaces the access circuit 202 and has an access circuit 202b.

[0140] Figure 16 is a diagram showing one example of the configuration of the transformation table 120 for the third embodiment.

[0141] In the conversion table 120, at each page number, the correspondence between "a value that can be transmitted as a second address for page assignment" and "page number" is recorded. "A value that can be transmitted as a second address for page assignment," following the example shown in Figure 14, is a value in the range of 10h to FFh. In the third embodiment, since LUNs can be transmitted as second addresses, page numbers cannot be directly used as second addresses. Through the conversion table 120, "values ​​that are exclusive to values ​​that can be used as LUNs" are associated with page numbers, thereby enabling the use of values ​​in a range that would not be used as LUNs for page assignment.

[0142] Based on the example of the conversion table 120 shown in Figure 16, it can be understood that the value 10h transmitted as the second address corresponds to page number 1, and the value 11h transmitted as the second address corresponds to page number 2.

[0143] The instruction decoder 111b can specify the specified page by referring to the translation table 120 according to the page specified as the second address.

[0144] Figure 17 is a flowchart illustrating one example of the operation of the interface chip IFC in the third embodiment.

[0145] If the interface chip IFC receives the second sequence from the memory controller MC (S501), the controller 103 transmits the received second sequence to the memory chip CP group (S502).

[0146] The instruction decoder 111b determines whether the second address contained in the received second sequence conforms to the page specification (S503).

[0147] If following the example shown in Figure 14, the range of addresses 10h to FFh is used as a page specification. The instruction decoder 111b determines whether the second address conforms to the page specification based on whether the second address is a value of address 10h to FFh.

[0148] Furthermore, the method for determining whether the second address conforms to the page specification is not limited to this. For example, the instruction decoder 111b can also determine whether the second address conforms to the page specification by referring to the translation table 120. The page specification value is associated with a certain page number through the translation table. The instruction decoder 111b can also determine whether the second address conforms to the page specification based on whether the second address is associated with a certain page number through the translation table 120.

[0149] When the second address matches the page specification condition (S503, Yes), the instruction decoder 111b specifies the specified page based on the second address and the translation table 120 (S504). The instruction decoder 111b specifies the specified page by obtaining the page number corresponding to the second address from the translation table 120.

[0150] The instruction decoder 111b stores the parameter data, which is included as setting data in the second sequence, at the location represented by the first address of the specified page in the feature temporary register group 112 (S505).

[0151] When the second address does not conform to the page specification (S503, No), or after S505, the interface chip IFC system ends its operation.

[0152] Figure 18 is a flowchart illustrating one example of the operation of the memory chip CP in the third embodiment. Similarly, in this figure, the operation of one memory chip CP is explained as a representative of all memory chip CPs.

[0153] If the memory chip CP receives the second sequence via the interface chip IFC (S601), the access circuit 202b determines whether the second address contained in the received second sequence matches the LUN assigned to the memory chip CP it possesses (S602).

[0154] When the second address is in accordance with the LUN assigned to the memory chip CP it possesses (S602, Yes), the access circuit 202b stores the parameter data included in the second sequence as setting data at the location represented by the first address in the feature temporary register group 203b (S603).

[0155] When the second address does not conform to the LUN of the memory chip CP that is assigned to its own access circuit 202b (S602, No), or after S603, the memory chip CP system ends its operation.

[0156] As described above, according to the third embodiment, the second sequence is configured to transmit, as the second sequence, a value corresponding to each of the plurality of pages possessed by the feature register group 112b (in the above example, a value corresponding to the page number in the range of 10h to FFh) that is exclusive to the value that can be used as a LUN. When the second address is a value corresponding to a page, the interface chip IFC stores the parameter data at the location represented by the first address of the page corresponding to the second address.

[0157] In the first and second embodiments, the instruction sequence of the SetFeature instruction is constructed in a way that determines whether the target of the SetFeature instruction is the interface chip IFC or the memory chip CP based on whether the first address conforms to the interface feature address or the memory feature address. Therefore, the situation where the value at the interface feature address and the memory feature address overlaps is prohibited.

[0158] In contrast, in the third embodiment, since the second sequence is configured to determine whether the target is the interface chip IFC or the memory chip CP based on the second address, it is permissible for "the values ​​at the interface feature address and the memory feature address to overlap". Therefore, each page of the feature register group 112b and the feature register group 203b can be mapped to a common address space (in the above example, the space in the range of 00h to EFh). As a result, the capacity of the feature register group 112b of the interface chip IFC, which can store parameter data, can be increased, and the feature register group 203b can be mapped to a feature register space of the full size defined according to the specification.

[0159] (Fourth Embodiment) The memory manufacturer does not assign memory chip CP functionality to all 256 addresses contained in the feature register space. Among the 256 addresses contained in the feature register space, there will be addresses that are not assigned memory chip CP functionality, that is, addresses that are not used at the memory chip CP.

[0160] In the fourth embodiment, the addresses that are not used by the memory chip CP among the 256 addresses included in the feature register space are used at the interface chip IFC.

[0161] Hereinafter, the fourth embodiment will be described. In the fourth embodiment, the description will focus on matters that differ from the first embodiment. For matters that are the same as in the first embodiment, the description will be omitted or a brief description will be given.

[0162] Figure 19 is a diagram illustrating one example of the configuration of the interface chip IFC and each memory chip CP in the fourth embodiment.

[0163] The controller 103 of the interface chip IFC is an instruction decoder 111c instead of the instruction decoder 111. Also, the controller 103 is a feature register group 112c instead of the feature register group 112.

[0164] The feature register group 112c has 32 memory regions with distinct addresses ranging from 00h to 1Fh. Each of the 32 memory regions has a memory capacity of 32 bits. In the fourth embodiment, the 32 addresses ranging from 00h to 1Fh assigned to the feature register group 112c are marked as interface feature addresses.

[0165] The controller 103 further includes a memory 113c. The memory 113c is a non-volatile memory in which a lookup table 120c is stored. The memory 113c is, for example, an eFuse or a ROM (Read Only Memory). The lookup table 120c is stored in the memory 113c during the manufacture of the semiconductor memory device 1. However, the type of memory 113c and the timing of the storage of the lookup table 120c are not limited to these.

[0166] Each memory chip CP replaces the access circuit 202 and has an access circuit 202c. Also, each memory chip CP replaces the feature register group 203 and has a feature register group 203c.

[0167] The feature register group 203c has 256 memory regions with distinct addresses ranging from 00h to FFh. Each of the 256 memory regions in the feature register group 203c has a memory capacity of 32 bits. Furthermore, 32 addresses within the range of 00h to FFh in the feature register group 203c are not assigned any function. That is, these 32 addresses in the feature register space are set to be unused at the memory chip CP.

[0168] The 32 addresses in the feature register space that are not used at the memory chip CP are corresponding to the 32 memory regions of the feature register group 112c of the interface chip IFC. The conversion table 120c is a table that records the correspondence between the "32 addresses that are not used at the memory chip CP" and the "32 memory regions of the feature register group 112c".

[0169] Figure 20 is a diagram showing one example of the configuration of the transformation table 120c for the fourth embodiment.

[0170] In the conversion table 120c, the correspondence between "addresses that are not used at the memory chip CP" and "interface feature addresses" is recorded in "256 addresses that can be transferred as the first address".

[0171] In the example shown in Figure 20, according to the conversion table 120c, it can be understood that "the value 80h transmitted as the first address corresponds to the interface feature address 00h" and "the value A2h transmitted as the first address corresponds to the interface feature address 01h", etc.

[0172] Based on this configuration, the following general considerations can be made. That is, the feature register space (an example of the first access space) includes "the space used in accessing feature register group 203c (an example of the first space)" and "the space used in accessing feature register group 112c (an example of the second space)". The "space used in accessing feature register group 203c" and the "space used in accessing feature register group 112c" are mutually exclusive. In the transformation table 120c, the correspondence between "the address group included in the space used in accessing feature register group 112c" and "feature register group 112c" is recorded.

[0173] Figure 21 is a diagram illustrating the method for setting parameter data for the fourth implementation form using the first sequence.

[0174] In the example shown in Figure 21, the memory controller MC transmits the first sequence SQ31 and the first sequence SQ32 to the semiconductor memory device 1 in this order.

[0175] The first sequence SQ31 is the first address and includes address 80h, which is an address that is not used at the memory chip CP. If the interface chip IFC receives the first sequence SQ31, the instruction decoder 111c determines whether the first address is associated with an interface feature address by referring to the translation table 120c. Following the example shown in Figure 20, address 80h is associated with the interface feature address 00h. Therefore, the instruction decoder 111c stores the parameter data included in the first sequence SQ31 at the location represented by the interface feature address 00h in the feature register group 112c.

[0176] The first sequence SQ32 is the first address and includes address A2h, which is an address that is not used at the memory chip CP. If the interface chip IFC receives the first sequence SQ31, the instruction decoder 111c determines whether the first address is associated with an interface feature address by referring to the translation table 120c. Following the example shown in Figure 20, address A2h is associated with the interface feature address 01h. Therefore, the instruction decoder 111c stores the parameter data included in the first sequence SQ32 at the location represented by the interface feature address 01h in the feature register group 112c.

[0177] Figure 22 is a flowchart illustrating one example of the operation of the interface chip IFC in the fourth embodiment.

[0178] If the interface chip IFC receives the first sequence from the memory controller MC (S701), the controller 103 transmits the received first sequence to the memory chip CP group (S702).

[0179] The instruction decoder 111c determines whether the first address contained in the received first sequence is corresponding to the interface feature address by means of the translation table 120c (S703).

[0180] When the first address is associated with an interface feature address (S703, Yes), the instruction decoder 111c converts the first address into an interface feature address (S704). At S704, the instruction decoder 111c identifies the interface feature address corresponding to the first address by referring to the conversion table 120c.

[0181] The instruction decoder 111c stores the parameter data, which is included as setting data in the first sequence, at the location represented by the interface feature address obtained by conversion within the feature register group 112c (S705). The instruction decoder 111c stores the parameter data in the memory area represented by the interface feature address obtained by conversion within the 32 memory areas of the feature register group 112c.

[0182] When the first address is associated with the interface feature address (S703, No), or after S705, the interface chip IFC system ends its operation.

[0183] Figure 23 is a flowchart illustrating one example of the operation of the memory chip CP in the fourth embodiment. Similarly, in this figure, the operation of one memory chip CP is explained as a representative of all memory chip CPs.

[0184] If the memory chip CP receives the first sequence through the interface chip IFC (S801), the access circuit 202c determines whether the first address contained in the received first sequence is a non-used address (S802).

[0185] When the first address does not conform to the case of an address that is not used (S802, No), the access circuit 202c stores the parameter data included in the first sequence as setting data at the location represented by the first address in the feature temporary register group 203 (S803).

[0186] When the first address is a non-used address (S802, Yes), or after S803, the memory chip CP system ends its operation.

[0187] Furthermore, in the description of the fourth embodiment, an example was described using a first sequence as an instruction sequence for transmitting the SetFeature instruction. The semiconductor memory device 1 can perform the same operation as when the first sequence is received, even when the second sequence is received (for example, the operation shown in FIG22).

[0188] As described above, according to the fourth embodiment, the first address included in the instruction sequence of the SetFeature instruction is included in either "the space used for accessing the feature register group 203c (labeled as the first space)" or "the space used exclusively for accessing the feature register group 112c (labeled as the second space)". The correspondence between "the address group included in the second space" and "the feature register group 112c" is recorded in the translation table 120c. When the first address is included in the first space, the memory chip CP stores the parameter data included in the instruction sequence in the feature register group 203c. When the first address is not included in the first space, the memory chip CP does not store the parameter data in the feature register group 203c. When the first address is included in the second space, the interface chip IFC stores the parameter data included in the instruction sequence in the feature temporary register group 112c. When the first address is not included in the second space, the interface chip IFC does not store the parameter data in the feature temporary register group 112c.

[0189] Since it is possible to use addresses in the feature register space that are not used at the memory chip CP at the interface chip IFC, it is possible to obtain as many addresses as possible for the interface chip IFC without reducing the number of addresses used at the memory chip CP. That is, it is possible to appropriately store parameter data in the feature register group 112c provided by the interface chip IFC.

[0190] Furthermore, according to the fourth embodiment, the feature register group 112c contains a plurality of memory regions (32 memory regions in the example shown in FIG19), and the second space contains a plurality of addresses (32 addresses in the example shown in FIG19). The translation table 120c records the correspondence between the "plural addresses contained in the second space" and the "plural memory regions contained in the feature register group 112c". When the first address is contained in the second space, the parameter data contained in the instruction sequence is stored in the memory regions contained in the plurality of memory regions of the feature register group 112c that are corresponding to the first address through the translation table 120c.

[0191] Therefore, it is possible to use addresses in the feature register space that are not used at the memory chip CP at the interface chip IFC.

[0192] (Fifth Embodiment) In the instruction sequence of the SetFeature instruction, the setting data is transmitted in four data transfer cycles. That is, the instruction sequence of the SetFeature instruction has four "8-bit data transfer fields (data transfer fields B0 to B3 described below)," and the memory controller MC can transmit parameter data in 8-bit (=1 Byte) units within one address. The feature register group of the memory chip CP, each with a memory capacity of 32 bits (=4 Bytes), can be considered as having four Byte regions, each capable of storing "1 Byte of parameter data transmitted through one data transfer field." Furthermore, each of the 256 addresses included in the feature register space can be considered as containing four segments corresponding to the four Byte regions.

[0193] Among the multiple memory regions of the feature register group of the memory chip CP, there may be a memory region with an unused Byte region.

[0194] In the fifth embodiment, the space in the feature register space corresponding to the unused byte area can be used at the interface chip IFC. That is, the group of segments that are not used at the memory chip CP within the 1024 segments (=256 addresses × 4 segments) included in the feature register space can be used at the interface chip IFC.

[0195] Hereinafter, the fifth embodiment will be explained. In the fifth embodiment, the explanation will focus on matters that differ from the fourth embodiment. For matters that are the same as in the fourth embodiment, the explanation will be omitted or a brief explanation will be given.

[0196] Figure 24 is a diagram illustrating one example of the configuration of the interface chip IFC and each memory chip CP in the fifth embodiment.

[0197] The controller 103 of the interface chip IFC has an instruction decoder 111d instead of the instruction decoder 111c. Also, the controller 103 has a feature register group 112d instead of the feature register group 112c.

[0198] The feature register group 112d has 32 memory regions with distinct addresses ranging from 00h to 1Fh. Each of the 32 memory regions has a memory capacity of 32 bits (=4 bytes). In the fifth embodiment, the 32 addresses ranging from 00h to 1Fh assigned to the feature register group 112d are marked as interface feature addresses.

[0199] The controller 103 further includes a memory 113d. The memory 113d is a non-volatile memory in which a lookup table 120d is stored. The memory 113d is, for example, an eFuse or a ROM. The lookup table 120d is stored in the memory 113d during the manufacture of the semiconductor memory device 1. Furthermore, the type of memory 113d and the timing of the storage of the lookup table 120d are not limited to these.

[0200] Each memory chip CP replaces the access circuit 202c and has an access circuit 202d. Also, each memory chip CP replaces the feature register group 203c and has a feature register group 203d.

[0201] The feature register group 203d has 256 memory regions with distinct addresses in the range of 00h to FFh. Each of the 256 memory regions in the feature register group 203d has a memory capacity of 32 bits (=4 bytes).

[0202] In the example shown in Figure 24, 32 of the 256 memory regions of the feature register group 203d each have at least one unused byte region. The total capacity of the unused byte regions of the feature register group 203d is 64 bytes.

[0203] The 32 addresses assigned to the "32 memory regions containing 1 or more unused byte regions" are correspondingly associated with the 32 memory regions of the feature register group 112d of the interface chip IFC through the translation table 120d. Furthermore, the translation table 120d further records the positions of each unused byte region.

[0204] Figure 25 is a diagram showing one example of the configuration of the transformation table 120d for the fifth embodiment.

[0205] In the conversion table 120d, the correspondence between the "address assigned to the memory area containing the unused Byte area" and the "interface feature address" is recorded in the "address of the 256 addresses that can be transmitted as the first address".

[0206] Furthermore, in the conversion table 120d, for each of the "addresses assigned to the memory area containing unused Byte areas" among the "256 addresses that can be transmitted as the first address", the positions of the unused Byte areas are recorded respectively.

[0207] As described above, the instruction sequence of the SetFeature instruction includes four data transfer fields B0 to B3, each containing 1 byte of parameter data. In Figure 25, the positions of unused byte regions within the 32-bit memory area are represented as flags for data transfer field units. A flag value of "1" represents an unused byte region, and a flag value of "0" represents a used byte region.

[0208] In the example shown in Figure 25, address 80h is associated with interface feature address 00h. For data transfer fields B2 and B3 among data transfer fields B0 to B3, the flag is set to "1". This means that among the four byte areas of the "memory area assigned to address 80h" in the feature register group 203d, the third and fourth byte areas are unused byte areas.

[0209] Furthermore, address A2h is associated with interface feature address 01h, and for data transfer field B1 among data transfer fields B0 to B3, the flag is set to "1". This means that among the four byte regions of the "memory region assigned address A2h" in feature register group 203d, the first byte region is an unused byte region.

[0210] Thus, the conversion table 120d is a unit of Byte region, in other words, a unit of segment that is "the address space corresponding to the Byte region", and is remembered to have the correspondence between "the space in the feature register space that is not used at the memory chip CP" and "feature register group 112d".

[0211] Figure 26 is a diagram showing the composition of the first sequence of the fifth implementation.

[0212] The first sequence is configured to transmit the first SetFeature instruction C1, the first address, and the setting data in this order. The first sequence includes data transmission fields B0 to B3, and the setting data is transmitted in 1-byte units through the data transmission fields B0 to B3.

[0213] As the first address, it is capable of transmitting both the feature address and the field setting identifier. The field setting identifier is a specific address among 256 feature addresses. The instruction decoder 111d interprets the field setting identifier as an instruction used to set the target of the 4-byte parameter data to be transmitted through the data transmission fields B0 to B3.

[0214] In addition to parameter data, field setting values ​​can also be transmitted in each of the data transmission fields as setting data. Field setting values ​​represent the target of the parameter data and whether the parameter data is valid or invalid.

[0215] In the example shown in Figure 26, the field setting value can be 00h, 01h, 10h and 11h.

[0216] Field setting value 00h represents invalid data used by the memory chip CP. When a field setting value of 00h is transmitted in a certain data transmission field, the parameter data transmitted subsequently through that data transmission field will be parameter data with the memory chip CP as the target, and will be invalid data.

[0217] Field setting value 01h represents valid data used by the memory chip CP. When a field setting value of 01h is transmitted in a certain data transmission field, the parameter data transmitted subsequently through that data transmission field is parameter data with the memory chip CP as the target, and is valid data.

[0218] Field setting value 10h represents invalid data used by the interface chip IFC. When a field setting value of 10h is transmitted in a certain data transmission field, the parameter data transmitted subsequently through that data transmission field will be parameter data with the interface chip IFC as the target, and will be invalid data.

[0219] Field setting value 11h represents valid data used by the interface chip IFC. When a field setting value of 11h is transmitted in a certain data transmission field, the parameter data transmitted subsequently through that data transmission field is parameter data with the interface chip IFC as the target, and is valid data.

[0220] Figures 27 and 28 are diagrams illustrating the method for setting parameter data for the fifth embodiment using the first sequence.

[0221] In the example shown in Figure 27, the memory controller MC transmits the first sequence SQ41 and the first sequence SQ42 to the semiconductor memory device 1 in this order.

[0222] The first sequence SQ41 is used as the first address and contains a field setting identifier. In this example, address 55h is used as a field setting identifier. At the interface chip IFC and each memory chip CP, if the first sequence SQ41 is received, since the first sequence SQ41 contains a field setting identifier, it is recognized that field setting values ​​will be transmitted in each of the data transmission fields B0 to B3.

[0223] In the first sequence SQ41, the field setting value 00h is transmitted through each of the data transmission fields B0 and B1. Therefore, at the interface chip IFC and each memory chip CP, it is recognized that "the parameter data transmitted thereafter through the data transmission fields B0 and B1 is parameter data with the memory chip CP as the target, and is invalid data".

[0224] Furthermore, in the first sequence SQ41, the field setting value 11h is transmitted via each of the data transmission fields B2 and B3. Therefore, at the interface chip IFC and each memory chip CP, it is recognized that "the parameter data transmitted thereafter via the data transmission fields B2 and B3 is parameter data with the interface chip IFC as the target, and is valid data".

[0225] The first sequence SQ42 is the first address and includes the feature address 80h. At the interface chip IFC and each memory chip CP, the following general operations are performed based on the field settings included in the previously transmitted first sequence SQ41. That is, at the interface chip IFC and each memory chip CP, the parameter data transmitted via the data transmission fields B0 and B1 included in the first sequence SQ42 is not stored in the feature register groups 112d and 203d. Furthermore, the parameter data transmitted via the data transmission fields B2 and B3 included in the first sequence SQ42 is stored in the feature register group 112d at the interface chip IFC. Additionally, the feature address 80h is correspondingly appended to the interface feature address 00h via the translation table 120d. Therefore, the parameter data transmitted via data transfer fields B2 and B3 included in the first sequence SQ42 is stored in the memory area assigned the interface feature address 00h within the feature register group 112d. At each memory chip CP, the storage of the parameter data transmitted via data transfer fields B2 and B3 included in the first sequence SQ42 in the feature register group 203d is not performed.

[0226] In the example shown in Figure 28, the memory controller MC transmits the first sequence SQ51 and the first sequence SQ52 to the semiconductor memory device 1 in this order.

[0227] The first sequence SQ51 is the first address and contains a field setting identifier. At the interface chip IFC and each memory chip CP, if the first sequence SQ51 is received, since the first sequence SQ51 contains a field setting identifier, it is recognized that the field setting value will be transmitted in each of the data transmission fields B0 to B3.

[0228] In each of the data transmission fields B0 and B1 of the first sequence SQ51, the field setting value 01h is transmitted. Therefore, at the interface chip IFC and each memory chip CP, it is recognized that "the parameter data transmitted thereafter through the data transmission fields B0 and B1 is parameter data with the memory chip CP as the target, and is valid data".

[0229] In each of the data transmission fields B2 and B3 of the first sequence SQ51, the field setting value 10h is transmitted. Therefore, at the interface chip IFC and each memory chip CP, it is recognized that "the parameter data transmitted subsequently through the data transmission fields B2 and B3 is parameter data with the interface chip IFC as the target, and is invalid data".

[0230] The first sequence SQ52 is the first address and includes the feature address 80h. At the interface chip IFC and each memory chip CP, the following general operations are performed based on the field settings included in the previously transmitted first sequence SQ51. That is, at the interface chip IFC, the parameter data transmitted via the data transmission fields B0 and B1 included in the first sequence SQ52 is not stored in the feature register group 112d. At each memory chip CP, the parameter data transmitted via the data transmission fields B0 and B1 is stored in the memory area within the feature register group 203d assigned to the feature address 80h. Furthermore, at the interface chip IFC and each memory chip CP, the parameter data transmitted through the data transmission fields B2 and B3 included in the first sequence SQ52 is not stored in the feature temporary register groups 112d and 203d.

[0231] Figure 29 is a flowchart illustrating one example of the operation of the interface chip IFC in the fifth embodiment.

[0232] If the interface chip IFC receives the first sequence from the memory controller MC (S901), the controller 103 transmits the received first sequence to the memory chip CP group (S902).

[0233] The instruction decoder 111d determines whether the first address contained in the received first sequence matches the field setting identifier (S903). When the first address matches the field setting identifier (S903, Yes), the instruction decoder 111d remembers the field setting values ​​of the data transmission fields B0 to B3 contained in the received first sequence (S904).

[0234] When the first address contained in the received first sequence does not match the field setting identifier (S903, No), the instruction decoder 111d determines whether there is a data transmission field with a memorized field setting value of "11h" among the data transmission fields B0 to B3 (S905).

[0235] When there is a data transmission field with a field setting value of "11h" (S905, Yes), the instruction decoder 111d converts the first address into an interface feature address (S906). The instruction decoder 111d identifies the interface feature address that corresponds to the first address by referring to the conversion table 120d.

[0236] The instruction decoder 111d stores the data of the data transmission field with the memory field set to "11h" in the feature register group 112d at the location represented by the interface feature address obtained by conversion (S907).

[0237] After S904, or when there is no data transmission field with a field setting value of "11h" (S905, No), or after S907, the interface chip IFC system ends its operation.

[0238] Figure 30 is a flowchart illustrating one example of the operation of the memory chip CP in the fifth embodiment. Similarly, in this figure, the operation of one memory chip CP is explained as a representative of all memory chip CPs.

[0239] If the memory chip CP receives the first sequence via the interface chip IFC (S1001), the access circuit 202d determines whether the first address contained in the received first sequence matches the field setting identifier (S1002). When the first address matches the field setting identifier (S1002, Yes), the access circuit 202d remembers the field setting values ​​of the data transmission fields B0 to B3 contained in the received first sequence (S1003).

[0240] When the first address contained in the received first sequence does not match the field setting identifier (S1002, No), the access circuit 202d determines whether there is a data transmission field with a field setting value of "01h" among the data transmission fields B0 to B3 (S1004).

[0241] When there is a data transmission field with a field setting value of "01h" (S1004, Yes), the access circuit 202d stores the data of the data transmission field with the field setting value of "01h" in the feature temporary register group 203d at the address represented by the first address (S1005).

[0242] After S1003, or when there is no data transmission field with a field setting value of "01h" (S1004, No), or after S1005, the memory chip CP system ends its operation.

[0243] Furthermore, in the above description, the transmission of field setting values ​​and parameter data was performed using the first sequence. In the fifth embodiment, it is also possible to use the second sequence, either as a replacement for the first sequence or together with the first sequence.

[0244] Furthermore, the semiconductor memory device 1 is configured to use field setting values ​​to set whether the target of the parameter data transmitted through each data transmission field is an interface chip IFC or a memory chip CP. The method of switching the storage target of parameter data in units of data transmission fields is not limited to this.

[0245] For example, the memory controller MC can also use the GetFeature instruction to read parameter data in units of 32-bit memory areas. After that, the memory controller MC can also use the SetFeature instruction to transfer the parameter data in the form of read-modify-write.

[0246] As described above, according to the fifth embodiment, each feature address contains a plurality of segments (in the example above, four segments). At the interface chip IFC, space that is not used at the memory chip CP can be used in units of segments. That is, at the interface chip IFC, a group of segments that are exclusive to the "group of segments that are used at the memory chip CP" are used.

[0247] This system enables the use of portions of the feature register space that are not used at the memory chip CP at the interface chip IFC. This allows for maximizing the space available for the interface chip IFC without reducing the space used at the memory chip CP within the feature register space. In other words, this system enables the appropriate storage of parameter data within the feature register group 112d of the interface chip IFC.

[0248] In addition, the fourth and fifth embodiments can also be applied together with the first or second embodiment.

[0249] Although several embodiments of the present invention have been described, these embodiments are merely illustrative examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or their variations are also included in the scope or spirit of the invention, and are also included within the scope of the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0006] [Figure 1] is a schematic diagram illustrating one example of the configuration of the memory system in the first embodiment. [Figure 2] is a schematic diagram illustrating a more detailed connection relationship between the interface chip and each memory chip in the first embodiment. [Figure 3] is a diagram illustrating one example of the configuration of the interface chip and each memory chip in the first embodiment. [Figure 4] is a diagram illustrating the configuration of the instruction sequence used to transmit the SetFeature instruction in the first embodiment. [Figure 5] is a diagram illustrating the method of setting parameter data in the first embodiment using the first sequence. [Figure 6] is a flowchart illustrating one example of the operation of the interface chip in the first embodiment. [Figure 7] is a flowchart illustrating one example of the operation of the memory chip in the first embodiment. [Figure 8] is a diagram illustrating the structure of the second sequence, which is used to transmit the SetFeature instruction in the first embodiment. [Figure 9] is a diagram illustrating one example of the structure of the interface chip and memory chips in the second embodiment. [Figure 10] is a diagram illustrating the structure of the second sequence in the second embodiment. [Figure 11] is a diagram illustrating the method for setting parameter data in the second embodiment using the second sequence. [Figure 12] is a flowchart illustrating one example of the operation of the interface chip in the second embodiment. [Figure 13] is a flowchart illustrating one example of the operation of the memory chip in the second embodiment. [Figure 14] is a diagram illustrating the structure of the second sequence in the third embodiment. [Figure 15] is a diagram illustrating one example of the structure of the interface chip and memory chips in the third embodiment. [Figure 16] is a diagram showing one example of the structure of the conversion table in the third embodiment. [Figure 17] is a flowchart showing one example of the operation of the interface chip in the third embodiment. [Figure 18] is a flowchart showing one example of the operation of the memory chip in the third embodiment. [Figure 19] is a diagram illustrating one example of the structure of the interface chip and memory chips in the fourth embodiment. [Figure 20] is a diagram showing one example of the structure of the conversion table in the fourth embodiment. [Figure 21] is a diagram illustrating the method of setting parameter data using the first sequence in the fourth embodiment. [Figure 22] is a flowchart showing one example of the operation of the interface chip in the fourth embodiment. [Figure 23] is a flowchart showing one example of the operation of the memory chip in the fourth embodiment. [Figure 24] is a diagram illustrating one example of the configuration of the interface chip and memory chips in the fifth embodiment.[Figure 25] is a diagram showing one example of the structure of the conversion table for the fifth embodiment. [Figure 26] is a diagram showing the structure of the first sequence for the fifth embodiment. [Figure 27] is a diagram explaining the method for setting parameter data for the fifth embodiment using the first sequence. [Figure 28] is another diagram explaining the method for setting parameter data for the fifth embodiment using the first sequence. [Figure 29] is a flowchart showing one example of the operation of the interface chip in the fifth embodiment. [Figure 30] is a flowchart showing one example of the operation of the memory chip in the fifth embodiment.

Claims

1. A semiconductor memory device comprising: a terminal group having an instruction sequence input with a setting instruction including an address; and a first device having a first register group mapped to a first address space and a memory cell array, wherein when the address is included in the first address space, parameter data of the first register group is stored, and when the address is not included in the first address space, parameter data of the first register group is not stored; and a second device disposed between the terminal group and the first device, having a second register group including a plurality of pages mapped to a second address space that is exclusively shared with the first address space, and configured to, when the address is a first value, specify a page as a storage target for parameter data among the plurality of pages based on the instruction sequence.

2. The semiconductor memory device as described in claim 1, wherein, The aforementioned setting instruction sequence includes data in addition to the aforementioned address. The aforementioned first value is included in the aforementioned second address space. When the aforementioned second device receives the first instruction sequence of the aforementioned setting instruction sequence containing the address of the aforementioned first value via the aforementioned terminal group, it identifies one of the aforementioned plurality of pages based on the data included in the aforementioned first instruction sequence. When, after the aforementioned first instruction sequence, it receives the second instruction sequence of the aforementioned setting instruction sequence containing the address of the second value, which is different from the aforementioned first value and included in the aforementioned second address space, via the aforementioned terminal group, it stores the data included in the aforementioned second instruction sequence as parameter data at the position represented by the aforementioned second value within the identified page.

3. The semiconductor memory device as described in claim 1, wherein, At the aforementioned first device, a LUN (Logical Unit Number) is assigned. The instruction sequence of the aforementioned setting instruction includes parameter data in addition to the aforementioned address. The aforementioned address includes a first address contained in either the aforementioned first address space or the aforementioned second address space, and a second address that can be specified by the aforementioned LUN. The aforementioned first value is one of a group of values ​​that are corresponding to the aforementioned plurality of pages that are different from each other. When the aforementioned second device is contained in the aforementioned second address space, it interprets the aforementioned second address as the aforementioned first value and stores the aforementioned parameter data at the position represented by the aforementioned first address before the page that corresponds to the aforementioned first value among the aforementioned plurality of pages.

4. The semiconductor memory device as described in claim 1, wherein, At the aforementioned first device, a LUN is assigned. The aforementioned first value is one of a group of values ​​that are mutually exclusive with the aforementioned LUN and are corresponding to the aforementioned plurality of pages that are different from each other. The aforementioned instruction sequence of the setting instruction includes parameter data in addition to the aforementioned address. The aforementioned address includes a first address contained in either the aforementioned first address space or the aforementioned second address space, and a second address that can be specified by the aforementioned LUN or the aforementioned first value. When the aforementioned second address is the aforementioned first value, the aforementioned second device stores the aforementioned parameter data at the position represented by the aforementioned first address before the page corresponding to the aforementioned first value among the aforementioned plurality of pages.

5. A semiconductor memory device comprising: a terminal group for inputting an instruction sequence including a setting instruction for an address contained in a first address space; and a first device comprising a first register group and a memory cell array; and a second device disposed between the terminal group and the first device, comprising a second register group and a memory storing first information, wherein the first address space comprises a first space used for accessing the first register group, and a second space used for accessing the second register group and being exclusive to the first space, and the first information is information recording the correspondence between the second space and the second register group. The first device, when the address is included in the first space, stores the parameter data of the first register group; when the address is not included in the first space, it does not store the parameter data of the first register group. The second device, when the address is included in the second space, stores the parameter data of the second register group; when the address is not included in the second space, it does not store the parameter data of the second register group.

6. The semiconductor memory device as described in claim 5, wherein, The aforementioned second temporary storage group includes a plurality of memory regions. The aforementioned second space includes a plurality of first addresses. The aforementioned first information records the correspondence between the aforementioned plurality of first addresses and the aforementioned plurality of memory regions. When the aforementioned address is one of the aforementioned plurality of first addresses, the aforementioned second device stores the aforementioned parameter data of the memory regions that are corresponding to the aforementioned addresses by the aforementioned first information within the aforementioned plurality of memory regions.

7. The semiconductor memory device as described in claim 6, wherein, The aforementioned first address space includes a plurality of third spaces that correspond to the plurality of second addresses. Each of the aforementioned plurality of third spaces includes a plurality of segments. The aforementioned first space and the aforementioned second space are composed of mutually exclusive groups of segments.

8. The semiconductor memory device as described in claim 1 or claim 5, wherein, The aforementioned setting command is the SetFeature command.

9. A memory system comprising: a semiconductor memory device as described in any one of claims 1 to 7; and a memory controller, which sends a sequence of instructions to the semiconductor memory device to send the aforementioned setting instructions.

10. A control method for a semiconductor memory device, comprising: a terminal group having an instruction sequence containing a setting instruction for an address input; a first device having a first register group mapped to a first address space and a memory cell array; and a second device disposed between the terminal group and the first device, having a second register group containing a plurality of pages mapped to a second address space that is exclusively shared with the first address space, the method comprising: when the address contained in the instruction sequence received by the second device is a first value, identifying a page as a storage target for parameter data among the plurality of pages based on the instruction sequence.

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