Semiconductor memory devices and control methods for semiconductor memory devices

Abstract

This invention provides a semiconductor memory device that can suppress the expansion of the threshold value distribution even under the influence of NWI. One embodiment of the semiconductor memory device includes: a plurality of memory cell arrays; a plurality of memory cells included in a first memory cell array, which is one of the plurality of memory cell arrays; a plurality of word lines, each connected to a gate of the plurality of memory cells; a bit line connected to a first end of the first memory cell array; and a control circuit that executes at least one cycle in response to an instruction sequence for writing data to the first memory cell, which is one of the plurality of memory cells, connected to the first word line of the plurality of word lines, each cycle including writing data to the first memory cell, which is one of the plurality of memory cells. The first program operation for writing data to the first memory cell and the verification operation for verifying the data written to the first memory cell; and the instruction sequence includes threshold voltage information related to the threshold voltage level to be set in the second memory cell, the second memory cell being connected to the second word line adjacent to the first word line as one of the aforementioned plurality of word lines, and after exiting the aforementioned loop, the control circuit determines whether to perform the operation of adjusting the threshold voltage of the first memory cell based on the threshold voltage level set in the second memory cell.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a control method for the semiconductor memory device. Prior Technology

[0002] In recent years, NAND flash memory has become widely used as a semiconductor memory device. In such a semiconductor memory device, when writing to word line WLn, and then writing to word line WLn+1, neighbor word-line interference (NWI) occurs, which causes the threshold voltage of each memory cell on the word line WLn that has been written to to rise.

[0003] Due to the influence of NWI, the threshold value distribution of each memory cell in the word line WLn becomes wider, the margin between threshold value distributions decreases, and the failure bit count (FBC) increases. The influence of NWI increases with the reduction of gate spacing to increase memory density or with the advancement of multi-valued architectures. Summary of the Invention

[0004] One embodiment provides a semiconductor memory device and a control method for the semiconductor memory device that can suppress the expansion of the threshold value distribution even when affected by NWI.

[0005] An embodiment of a semiconductor memory device includes: a plurality of memory cell arrays; a plurality of memory cells included in a first memory cell array, which is one of the plurality of memory cell arrays; a plurality of word lines, which are connected to the gates of the plurality of memory cells; bit lines, which are connected to a first end of the first memory cell array; and a control circuit that executes at least one cycle in response to an instruction sequence for writing data to the first memory cell, which is one of the plurality of memory cells, connected to the first word line of the plurality of word lines, wherein each cycle includes writing data to the first memory cell, which is one of the plurality of memory cells. The first program operation for writing data to the first memory cell and the verification operation for verifying the data written to the first memory cell; and the instruction sequence includes threshold voltage information related to the threshold voltage level to be set in the second memory cell, the second memory cell being connected to the second word line adjacent to the first word line as one of the aforementioned plurality of word lines, and after exiting the aforementioned loop, the control circuit determines whether to perform the operation of adjusting the threshold voltage of the first memory cell based on the threshold voltage level set in the second memory cell. Simple Explanation of the Diagram

[0006] Figure 1 is a block diagram showing one example of the structure of a memory system. Figure 2 is a block diagram showing one example of the composition of the non-volatile memory 2 in Figure 1. Figure 3 shows an example of the composition of blocks in the three-dimensional memory cell array 20. Figure 4 is a block diagram showing an example of the configuration of the sense amplifier unit group 28 and the data register 29 in Figure 2. Figure 5 is a circuit diagram showing one example of the specific configuration of the sense amplifier unit SAU in Figure 4. Figure 6 is an explanatory diagram of 2-3-2 encoding as an example of encoding. Figure 7 is an example of a basic instruction sequence for writing data. Figure 8 is an example of the potential changes of the bit lines and selection word lines during program operation. Figure 9 is an illustrative diagram showing an example of the write sequence from state A to state G. Figure 10 is a flowchart illustrating the actions of this embodiment. Figure 11 is a diagram illustrating the changes in the distribution of the action threshold values ​​in this embodiment. Implementation

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0008] In this embodiment, when writing data to the memory cell of character line WLn, the data to be written to the memory cell of character line WLn+1 is confirmed in advance. By matching the data mode, the threshold value of the data written to the memory cell of character line WLn is adjusted to suppress the influence of NWI.

[0009] (The structure of the memory system) Figure 1 is a block diagram showing an example of the configuration of a memory system. The memory system 1 of this embodiment includes non-volatile memory 2 and a memory controller 3. Furthermore, the non-volatile memory 2 may include a plurality of memory chips. The memory system 1 can be connected to a host device 4. The host device 4 is, for example, a personal computer, a portable terminal, or other electronic device.

[0010] The memory system 1 can be constructed by mounting a plurality of chips constituting the memory system 1 on a motherboard equipped with the host device 4, or the memory system 1 can be constructed as a system LSI (Large-Scale Integrated Circuit) or SoC (System-on-a-Chip) implemented by a single module. Examples of memory systems 1 include memory cards such as SD cards, SSDs (Solid-State Drives), and eMMCs (embedded Multi-Media Cards).

[0011] Non-volatile memory 2 is a NAND-type memory with multiple memory cells, storing data non-volatilely. The specific structure of non-volatile memory 2 will be described later.

[0012] The memory controller 3, for example, responds to commands from the host device 4, and performs commands such as writing (also known as programming), reading, and erasing on the non-volatile memory 2. Furthermore, the memory controller 3 manages the memory space of the non-volatile memory 2. The memory controller 3 includes: host interface (host I / F) circuitry 10, a processor 11, RAM (Random Access Memory) 12, buffer memory 13, memory interface circuitry (memory I / F) circuitry 14, and ECC (Error Checking and Correcting) circuitry 15, etc.

[0013] The host I / F circuit 10 is connected to the host device 4 via the host bus and performs interface processing with the host device 4. Furthermore, the host I / F circuit 10 transmits and receives commands, addresses, and data with the host device 4.

[0014] Processor 11 includes, for example, a CPU (Central Processing Unit). Processor 11 controls the overall operation of memory controller 3. For example, when processor 11 receives a write command from host device 4, it issues a write command corresponding to the write command from host device 4 to non-volatile memory 2 via memory I / F circuit 14. The same applies to read and erase operations. Furthermore, processor 11 performs various processes such as wear leveling to manage non-volatile memory 2.

[0015] RAM 12 is used as the operating area of ​​processor 11, storing firmware data loaded from non-volatile memory 2 and various tables created by processor 11. RAM 12 may include, for example, DRAM or SRAM.

[0016] Buffer memory 13 temporarily holds data sent from host device 4 and temporarily holds data sent from non-volatile memory 2.

[0017] The memory I / F circuit 14 is connected to the non-volatile memory 2 via a bus and performs interface processing between the two. Furthermore, the memory I / F circuit 14 performs command, address, and data transmission and reception between the two.

[0018] When writing data, the ECC circuit 15 generates an error correction code for the written data, appends the error correction code to the written data, and sends it to the memory I / F circuit 14. Furthermore, when reading data, the ECC circuit 15 uses the error correction code contained in the read data to perform error detection and / or error correction. Moreover, the ECC circuit 15 can be located within the memory I / F circuit 14.

[0019] (The composition of non-volatile memory) Figure 2 is a block diagram showing an example of the configuration of the non-volatile memory 2 in Figure 1. The non-volatile memory 2 includes: a memory cell array 20, an input / output circuit 21, a logic control circuit 22, a temporary register 23, a control circuit 24, a voltage generation circuit 25, a column decoder 26, a row decoder 27, a group of sense amplifier units 28, and a data temporary register (data cache) 29.

[0020] The memory cell array 20 comprises j blocks BLK0~BLK(j-1) and block BLKX. j is an integer greater than or equal to 1. Each of the plurality of blocks BLK comprises a plurality of memory cell transistors. The memory cell transistors constitute electrically rewritable memory cells. In the memory cell array 20, a plurality of bit lines BL, a plurality of word lines WL, and source lines CELSRC are provided to control the voltage applied to the memory cell transistors. The specific structure of the blocks BLK will be described later.

[0021] The input / output circuit 21 and the logic control circuit 22 are connected to the memory controller 3 via a bus. The input / output circuit 21 transmits and receives signals DQ (e.g., DQ0~DQ7) with the memory controller 3 via a bus.

[0022] The logic control circuit 22 receives external control signals (e.g., chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REN, and write protect signal WPn) from the memory controller 3 via a bus. Note that 'n' in the signal name indicates active low. Furthermore, the logic control circuit 22 sends a ready / busy signal R / Bn to the memory controller 3 via a bus.

[0023] The chip enable signal CEn is used in a system configuration using multiple non-volatile memory modules 2 to select a specific non-volatile memory module 2 and enable it. The chip enable signal CLE enables the instruction sent as the DQ signal to be latched in the temporary register 23. The address latch enable signal ALE enables the address sent as the DQ signal to be latched in the temporary register 23. The write enable signal WEn enables writing. The read enable signal REn enables reading. The write protect signal WPn disables writing and erasing. The ready / busy signal R / Bn, when using basic operation instructions, indicates whether the non-volatile memory module 2 is in a ready state (able to accept commands from external sources) or a busy state (unable to accept commands from external sources).

[0024] Temporary register 23 includes an instruction register, an address register, and a status register. The instruction register temporarily holds instructions. The address register temporarily holds addresses. The status register temporarily holds data required for the operation of non-volatile memory 2. Temporary register 23 may include, for example, SRAM.

[0025] The control circuit 24 receives instructions from the temporary register 23 and comprehensively controls the non-volatile memory 2 according to the sequence of instructions.

[0026] The voltage generation circuit 25 receives a power supply voltage from the external source of the non-volatile memory 2, and uses this power supply voltage to generate a plurality of voltages required for write, read, and erase operations. The voltage generation circuit 25 supplies the generated plurality of voltages to the memory cell array 20, the column decoder 26, and the sense amplifier unit group 28, etc.

[0027] The column decoder 26 receives the column address from the register 23 and decodes it. Based on the decoded column address, the column decoder 26 performs word line selection. Furthermore, the word lines connected to the memory cell transistor MT, which will be the object of writing and reading, are called select word lines. Then, the column decoder 26 transmits multiple voltages required for write, read, and erase operations to the selected block BLK.

[0028] The line decoder 27 receives the line address from the register 23 and decodes the line address. Based on the decoded line address, the line decoder 27 supplies the specified voltage to each bit line BL.

[0029] When data is read out, the sensing amplifier unit group 28 detects and amplifies the data read from the memory cell transistor MT to the bit line BL. Furthermore, when data is written, the sensing amplifier unit group 28 supplies the written data to the bit line BL.

[0030] When data is read, the data buffer 29 temporarily holds the data transmitted from the self-sensing amplifier unit group 28 and transmits it in series to the input / output circuit 21. Similarly, when data is written, the data buffer 29 temporarily holds the data transmitted in series from the input / output circuit 21 and transmits it to the sensing amplifier unit group 28. The data buffer 29 includes SRAM, etc.

[0031] (The block structure of a memory cell array) Figure 3 is a diagram showing an example of the block structure of the three-dimensional memory cell array 20. Figure 3 shows one block BLK among the plurality of blocks constituting the memory cell array 20. The other blocks of the memory cell array also have the same structure as in Figure 3.

[0032] As shown in the figure, block BLK, for example, contains four serial cells SU0 to SU3 (hereinafter referred to as serial cells SU). Each serial cell SU has a NAND string NS containing a plurality of memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. Furthermore, the number of memory cell transistors MT contained in the NAND string NS is eight in Figure 3, but it can be more. Select gate transistors ST1 and ST2 are shown as a single transistor in the circuit, but their construction can be the same as that of the memory cell transistors. Also, a plurality of select gate transistors can be used for each of ST1 and ST2. Furthermore, a dummy cell transistor can be placed between the memory cell transistor MT and the select gate transistors ST1 and ST2.

[0033] The memory cell transistor MT is configured in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one end (bit line side) is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other end (source line side) is connected to the select gate transistor ST2.

[0034] The gates of the select gate transistors ST1 of each of the serial units SU0 to SU3 are respectively connected to select gate lines SGD0 to SGD3 (hereinafter referred to as select gate lines SGD). Furthermore, the gates of the select gate transistors ST2 of each of the serial units SU0 to SU3 are respectively connected to select gate lines SGS0 to SGS3 (hereinafter referred to as select gate lines SGS). Moreover, the gates of multiple select gate transistors ST2 located within each block BLK can be connected to a common select gate line SGS.

[0035] The gates of memory cell transistors MT0 to MT7 located within the same block BLK are commonly connected to word lines WL0 to WL7. That is, word lines WL0 to WL7 are commonly connected across multiple serial units SU0 to SU3 within the same block BLK. In contrast, the select gate line SGD is independent for each of the serial units SU0 to SU3, even within the same block BLK. The gates of memory cell transistors MTi located in the same column within the block BLK are connected to the same word line WLi.

[0036] Each NAND string NS is connected to a corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistor ST1, ST2, or other memory cell transistor MTs contained in the NAND string NS. Generally, data on memory cell transistor MTs located within the same block BLK is batch-erased. On the other hand, data reading and writing are typically performed in batches on a plurality of memory cell transistor MTs that are commonly connected to a single word line WL within a single string unit SU. A group of memory cell transistor MTs that share a word line WL within a single string unit SU is called a cell CU.

[0037] Write operations to a cell (CU) are performed on a page-by-page basis. For example, in the case of a Triple Level Cell (TLC) where each cell can hold 3 bits (8 values) of data, one CU can hold 3 pages of data. The 3 bits that each memory cell transistor (MT) can hold correspond to these 3 pages.

[0038] (Composition of the sense amplifier unit and data buffer) Figure 4 is a block diagram showing an example of the configuration of the sense amplifier unit group 28 and the data register 29 in Figure 2.

[0039] The sense amplifier unit group 28 includes sense amplifier units SAU0 to SAU(m-1) corresponding to bit lines BL0 to BL(m-1) (hereinafter, these are referred to as sense amplifier units SAU). Each sense amplifier unit SAU includes a sense amplifier SA and data latch circuits SDL, ADL, BDL, and CDL. The sense amplifier SA and the data latch circuits SDL, ADL, BDL, and CDL are connected in a manner that allows them to transmit data to each other.

[0040] The data latch circuits SDL, ADL, BDL, and CDL temporarily hold the data. During a write operation, the sense amplifier SA controls the voltage of the bit line BL based on the data held by the data latch circuit SDL. The data latch circuits ADL, BDL, and CDL are used for multi-value operations where the memory cell transistor MT holds more than 2 bits of data. That is, the data latch circuit ADL is used to hold the write data of the lower page, the data latch circuit BDL is used to hold the write data of the middle page, and the data latch circuit CDL is used to hold the write data of the upper page. The number of data latch circuits in the sense amplifier unit SAU is determined by the number of bits held by one memory cell transistor MT.

[0041] During the readout operation, the sense amplifier SA detects the data read to the corresponding bit line BL and determines whether the data is 0 or 1. During the write operation, the sense amplifier SA applies a voltage to the bit line BL based on the data to be written.

[0042] The data buffer 29 has a number of data latch circuits XDL corresponding to the sense amplifier units SAU0 to SAU(m-1). The data latch circuits XDL are connected to the input / output circuit 21. The data latch circuits XDL temporarily hold write data transmitted from the input / output circuit 21 and temporarily hold read data transmitted from the sense amplifier units SAU. More specifically, data transfer between the input / output circuit 21 and the sense amplifier unit group 28 is performed via a one-page data latch circuit XDL. Write data received by the input / output circuit 21 is transmitted via the data latch circuits XDL to any of the data latch circuits ADL, BDL, and CDL. Read data read from the sense amplifier SA is transmitted via the data latch circuits XDL to the input / output circuit 21.

[0043] Furthermore, as will be described later, when the data latch circuit XDL writes data to the memory cell of the word line WLn, it maintains the threshold information corresponding to the data mode of the word line WLn+1.

[0044] (Sensing amplifier circuit) Figure 5 is a circuit diagram showing one example of the specific configuration of the sense amplifier unit SAU in Figure 4.

[0045] As shown in Figure 5, the sense amplifier unit SAU includes a sense amplifier section SA and data latch circuits SDL, ADL, BDL, and CDL. The sense amplifier section SA and the data latch circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus LBUS in a manner that allows them to receive data from each other.

[0046] The data latch circuit SDL includes, for example, inverters 60 and 61 and n-channel MOS transistors 62 and 63. The input node of inverter 60 and the output node of inverter 61 are connected to node LAT. The input node of inverter 61 and the output node of inverter 60 are connected to node / LAT. Inverters 60 and 61 hold the data at nodes / LAT and LAT. Write data is supplied to node LAT. The data held at node / LAT is the inverted version of the data held at node LAT.

[0047] One end of the drain-source path of transistor 62 is connected to node LAT, and the other end is connected to bus LBUS. Similarly, one end of the drain-source path of transistor 63 is connected to node LAT, and the other end is connected to bus LBUS. A control signal STL is input to the gate of transistor 63, and a control signal STI is input to the gate of transistor 62.

[0048] Furthermore, since the circuit configurations of the data latch circuits ADL, BDL, CDL, and XDL are the same as those of the data latch circuit SDL, their descriptions are omitted. Furthermore, the various control signals supplied to the sense amplifier unit SAU are provided by the control circuit 24.

[0049] The sensing amplifier section SA includes, for example, a p-channel MOS transistor 50, n-channel MOS transistors 51-58, and a capacitor 59.

[0050] During the readout operation, the sensing amplifier section SA senses the data read to the corresponding bit line BL and determines whether the read data is "0" or "1". In addition, during the programming operation, the sensing amplifier section SA sets the corresponding bit line BL to the voltage value corresponding to the written data "0" or "1".

[0051] In the sensing amplifier section SA, transistors 50 to 54 are related to program operation. Between the power line supplying the internal power supply voltage VDD and node COM, the source-drain path of transistor 50 (serving as the second transistor) and the drain-source path of transistor 51 are connected in series. Furthermore, between node COM and node CELSRC (supplying the ground voltage VSS), the drain-source path of transistor 54 (serving as the third transistor) is connected. Also, between node COM and bit line BL, the drain-source path of transistor 52 (serving as the first transistor) and the drain-source path of transistor 53 are connected in series.

[0052] The gates of transistors 50 and 54 are connected to node / LAT. Therefore, when node LAT is at a low level (hereinafter referred to as L level) corresponding to "0" data, node / LAT remains at a high level (hereinafter referred to as H level), transistor 50 is turned off and transistor 54 is turned on. Conversely, when node LAT is at an H level corresponding to "1" data, node / LAT remains at L level, transistor 50 is turned on and transistor 54 is turned off.

[0053] During program operation, the control signals HLL and XXL supplied to the gates of transistors 55 and 56 are at the L level, respectively, and transistors 55 and 56 are turned off. The control signal BLX supplied to transistor 51 is at the H level, and transistor 51 is turned on. Furthermore, during normal program operation, transistors 52 and 53 are turned on by the control signals BLC and BLS.

[0054] Therefore, when "0" data is held at node LAT, transistor 50 is turned off and transistor 54 is turned on, and the bit line voltage VSS (e.g., 0 V) ​​from node CELSRC is supplied to bit line BL. Similarly, when "1" data is held at node LAT, transistor 50 is turned on and transistor 54 is turned off, and corresponding to the control signals BLC and BLS applied to transistors 52 and 53, a bit line voltage of, for example, 2.5 V is supplied to bit line BL.

[0055] Figure 6 is an explanatory diagram of 2-3-2 encoding as an example of encoding. Figure 6 shows the values ​​of the UPPER, MIDDLE, and LOWER bits for data with different threshold distributions.

[0056] In the example of Figure 6, the memory cell electrophysiological data of Er level (1,1,1), A level (1,1,0), B level (1,0,0), C level (0,0,0), D level (0,1,0), E level (0,1,1), F level (0,0,1), and G level (1,0,1) are shown.

[0057] Along with the data written to the memory cell on word line WLn, threshold information corresponding to the data mode written to the memory cell on word line WLn+1 is transmitted to the data latch circuit XDL. The data mode written to the memory cell on word line WLn+1 is binarized into two threshold values: one for "high" and one for "low". For example, when the data mode written to the memory cell on word line WLn+1 is at Er level to C level, the threshold value is determined to be "low", and when it is at D level to G level, the threshold value is determined to be "high". Then, when the threshold value of the data written to the memory cell on word line WLn+1 is "low", "1" is input as the threshold value information, and when the threshold value of the data written to the memory cell on word line WLn+1 is "high", "0" is input as the threshold value information. The threshold information is calculated by the memory controller 3 based on the data pattern written to the memory cell on word line WLn+1. Alternatively, the data pattern written to the memory cell on word line WLn+1 can be temporarily stored in the memory cell of the memory cell array 20, and the threshold information is calculated by the control circuit 24 of the non-volatile memory 2 based on the stored data pattern. Furthermore, the control circuit 24 can temporarily store the calculated threshold information in the memory cell.

[0058] The input of threshold information corresponding to the data mode of character line WLn+1 is performed by the instruction sequence shown in Figure 7. Figure 7 is a diagram showing an example of the basic instruction sequence when writing data.

[0059] As shown in Figure 7, the instruction sequence sequentially inputs the data of the lower bit, the middle bit, and the upper bit. Then, after inputting the upper bit data, the input includes the threshold value information indicating whether the threshold value of the character line WLn+1 is "high" or "low".

[0060] As described above, the data of the lower, middle, and upper bits are temporarily held in the data latch circuit XDL, and then transferred to the data latch circuits ADL, BDL, and CDL, respectively.

[0061] Therefore, during data writing, after the data is transferred from the data latch circuit XDL to the data latch circuits ADL, BDL, and CDL, the data latch circuit XDL becomes idle and is not used. Thus, after the upper bit data is input, the threshold value information of the input word line WLn+1 is stored in the idle (unused) data latch circuit XDL. This eliminates the need for a new data latch circuit to store the threshold value information of word line WLn+1, and the circuit size does not increase.

[0062] In this embodiment, when writing data to the character line WLn, which is the selected character line to be written, the threshold value information of the adjacent character line WLn+1 is used to determine whether to apply a weaker program pulse and adjust the threshold value when writing data to the character line WLn.

[0063] The application of this weaker program pulse is performed similarly to the QPW (Quick Pass Write) operation by adjusting the voltage of the bit line BL. The QPW operation applies a voltage to the bit line BL corresponding to the memory cell whose threshold value is to be increased by a smaller increment, for example, a voltage higher than the "L" level (ground voltage Vss, e.g., 0 V) ​​and lower than the "H" level (write inhibit voltage Vdd, e.g., 2.5 V). Thus, in the QPW operation, three types of control are applied to the multiple memory cells contained in the memory cell group: increasing the threshold value, maintaining the threshold value, or increasing the threshold value by a smaller increment.

[0064] Figure 8 is an example of the potential changes of the bit lines and selection word lines during program operation.

[0065] During a program operation (write operation), a ground voltage Vss is applied to the bit line BL connected to the memory cell where the write operation is not yet complete. Also during a program operation, a program voltage VPGM is applied to the select word line. The program voltage VPGM increases in stages with a predetermined voltage amplitude (ΔVPGM) as the cycle progresses. Furthermore, a write pass voltage VPASS is applied to the non-select word line. The write pass voltage VPASS is a lower voltage than the program voltage VPGM.

[0066] Here, the loop that passes verification is designated as loop N. In the next loop N+1, the threshold information corresponding to the data mode of word line WLn+1 is checked. In loop N+1, the bit line BL connected to the memory cell of word line WLn adjacent to the memory cell with a high threshold value of word line WLn+1 has its voltage increased to the write inhibit voltage Vdd, thereby preventing additional writes.

[0067] On the other hand, in loop N+1, the bit line BL connected to the memory cell of the word line WLn, which has a lower threshold value than the memory cell of word line WLn+1, has its potential difference with the program voltage VPGM reduced by slightly increasing the voltage to voltage Vm, thus applying a weaker program pulse. In this way, similar to the QPW operation, by controlling the voltage applied to bit line BL, the threshold value can be increased by a smaller change. Voltage Vm is higher than the ground voltage Vss and lower than the write inhibit voltage Vdd. Therefore, by simply adding one loop to the normal program operation loop number, an additional program operation (the application of a weaker program pulse) can be achieved.

[0068] To explain in more detail, Figure 9 is an illustrative diagram showing an example of the write sequence from state A to state G. For example, assume that the memory cell connected to word line WLn passes the verification of the threshold voltage A in the 3rd cycle. Let this memory cell be memory cell M. Let the memory cell adjacent to memory cell M and connected to word line WLn+1 be memory cell X. In this comparative example, when the program voltage VPGM_4 is applied to WLn in the 4th cycle, a write inhibit voltage Vdd is applied to bit line B connected to memory cell M, regardless of the threshold voltage to be written to memory cell X. In this embodiment, if the threshold voltage to be written to memory cell X is low, a voltage Vm is applied to bit line B to perform a weak write to memory cell M. If the threshold voltage to be written to memory cell X is high, a write inhibit voltage Vdd is applied to bit line B, and the write to memory cell M is inhibited.

[0069] Assume that the memory cell connected to word line WLn passes the verification of reaching the threshold voltage G in the 18th cycle of the predetermined final cycle. Designate this memory cell as memory cell N. Designate the memory cell adjacent to memory cell N and connected to word line WLn+1 as memory cell Y. Because it is the final cycle, regardless of the threshold voltage to be written to memory cell Y, a weak write to memory cell N will not be performed in the 19th cycle.

[0070] In this embodiment, since the number of cycles will not be increased beyond the predetermined number of cycles, the write time will not be increased.

[0071] Alternatively, a weak write can be performed to memory cell N in the 19th cycle, corresponding to the threshold voltage that should be written to memory cell Y.

[0072] Figure 10 is a flowchart illustrating the actions of this embodiment. Figure 11 is a diagram illustrating the changes in the distribution of threshold values ​​resulting from the actions of this embodiment.

[0073] First, data is input to the memory cell on character line WLn (S1). The data written to the memory cell on character line WLn is transferred to data latch circuits ADL, BDL, and CDL via data latch circuit XDL, and is held by data latch circuits ADL, BDL, and CDL. Next, the threshold value information of the memory cell on character line WLn+1 is input (S2). The threshold value information of the memory cell on character line WLn+1 is held in the unused data latch circuit XDL.

[0074] Next, a program pulse (program voltage VPGM) is applied to the character line corresponding to the page to be written (S3) to perform the program operation. After the program operation, a program verification is performed to determine whether the threshold voltage has reached the expected target voltage, and the result of the program verification is determined as either verification passed or verification failed (S4).

[0075] If the verification fails (S4: unqualified), the process returns to S3, and the program action and verification loop is executed multiple times. On the other hand, if the verification passes (S4: qualified), the process proceeds to S5. Figure 11 shows the threshold value distribution D1 when the memory cell of the character line WLn is determined to have passed the verification.

[0076] Subsequently, in the processing of S4, when the verification is deemed successful, the threshold information of character line WLn+1 is confirmed (S5).

[0077] When the threshold value of memory cell WLn+1 is determined to be low based on the threshold value information of character line WLn+1, a weaker program pulse (S6) is applied to the memory cell of character line WLn, and the process ends. On the other hand, when the threshold value of memory cell WLn+1 is determined to be high based on the threshold value information of character line WLn+1, the process ends.

[0078] As shown in Figure 11, when a weaker program pulse is applied and an additional write is performed, the threshold value of the memory cell being written to rises. The threshold value distribution D2 represents the threshold value distribution of the memory cell being written to.

[0079] On the other hand, when no weaker program pulse is applied and no additional write is performed, the threshold values ​​of memory cells that have not been written to remain unchanged. The threshold value distribution D3 represents the threshold value distribution of memory cells that have not been written to. As a result, at the point when the program operation of word line WLn is completed, the threshold value distribution of word line WLn becomes an expanded state.

[0080] When the programming operation of character line WLn is completed, the programming operation of character line WLn+1 is performed. When the threshold value of the data written to the memory cell of character line WLn+1 is low, the influence of NWI is small, and the threshold value of the memory cell of character line WLn remains almost unchanged. The threshold value distribution D4 represents the threshold value distribution of the memory cell of character line WLn when the influence of NWI is small.

[0081] On the other hand, when the threshold value of the data written to the memory cell of character line WLn+1 is high, the threshold value of the memory cell of character line WLn becomes higher due to the influence of NWI. The threshold value distribution D5 represents the threshold value distribution of the memory cell of character line WLn whose threshold value becomes higher due to the influence of NWI.

[0082] Thus, when the program operation of character line WLn+1 is completed, the threshold values ​​of memory cells of character line WLn adjacent to the memory cells with higher threshold values ​​of character line WLn+1 become higher due to the influence of NWI. As a result, when the program operation of character line WLn+1 is completed, the threshold value distribution of character line WLn becomes narrower.

[0083] As described above, after successful verification, the threshold information corresponding to the data mode of character line WLn+1 is checked. Processing ends when the threshold value is "high" and a weaker program pulse is applied when the threshold value is "low". Through this process, after the write (programming) operation of character line WLn+1 is completed, the threshold value of the memory cell of character line WLn that did not receive a weaker program pulse becomes high due to the influence of NWI.

[0084] Therefore, since the threshold value of the memory cell of character line WLn becomes the same threshold value in both the low and high cases of the threshold value of the memory cell of character line WLn+1, the expansion of the threshold value distribution (widening of the distribution) can be suppressed. Furthermore, since the margin between threshold value distributions can be ensured, the increase in the failure bit count (FBC) can be suppressed.

[0085] Several embodiments of the present invention have been described, but these embodiments are shown as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit and scope of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are also included within the scope of the invention described in the claims and their equivalents.

[0086] 1: Memory System 2: Non-volatile memory 3: Memory controller 4: Main unit 10: Host I / F circuit 11: Processor 12: RAM 13: Buffer memory 14: Memory I / F circuit 15: ECC circuit 20: Memory Cell Array 21: Input / output circuit 22: Logic control circuit 23: Temporary Register 24: Control Circuit 25: Voltage generation circuit 26: Column Decoder 27: Line Decoder 28: Sensing Amplifier Unit Group 29: Data Temporary Memory 50:p-channel MOS transistor / transistor 51~58: n-channel MOS transistors / transistors 59: Capacitor 60, 61: Inverters 62, 63: n-channel MOS transistors ADL, BDL, CDL, SDL, XDL: Data latch circuits ALE: Address Latch Enable Signal BL, BL0~BL(m-1): Bit lines BLK: Block BLC, BLS, BLX, HLL, STI, STL, XXL: Control signals CELSRC: Source Line CEn: Chip Enable Signal CLE: Instruction Latch Enable Signal COM, / LAT: Node CU: Cell unit DQ0~DQ7: Busbar transmit / receive signals LBUS: Bus MT0~MT7: Memory Cell Electron NS: NAND string R / Bn: Ready / Busy Signal REn: Read the enable signal SA: Sensing Amplifier / Sensing Amplifier Section SAU, SAU0~SAU(m-1): Sensing amplifier unit SGD0~SGD3: Select gate line SGS0~SGS3: Select gate wire ST1, ST2: Selector gate transistor SU0~SU3: Serial Units VDD: Write Disable Voltage WEn: Write enable signal WL0~WL7: Character Lines WPn: Write-protect signal

Claims

1. A semiconductor memory device comprising: a plurality of memory cell arrays; a plurality of memory cells included in a first memory cell array, which is one of the plurality of memory cell arrays; and a plurality of word lines, each connected to a gate of the plurality of memory cells; The bit line is connected to the first end of the aforementioned first memory cell array; and the control circuit executes a loop more than once in response to an instruction sequence for writing data to the first memory cell, which is one of the aforementioned plurality of memory cells, connected to the first word line, which is one of the aforementioned plurality of word lines. Each loop includes a first program action for writing data to the aforementioned first memory cell and a verification action for verifying the data written to the aforementioned first memory cell; and the aforementioned instruction sequence includes threshold voltage information related to a threshold voltage level to be set in a second memory cell, which is connected to the second word line, which is one of the aforementioned plurality of word lines, adjacent to the aforementioned first word line; and after exiting the aforementioned loop, the aforementioned control circuit determines whether to perform an action to adjust the threshold voltage of the aforementioned first memory cell based on the threshold voltage level set in the aforementioned second memory cell.

2. The semiconductor memory device of claim 1, wherein the aforementioned control circuit exits the aforementioned loop when it determines that the aforementioned data has been normally written to the aforementioned first memory cell.

3. The semiconductor memory device of claim 1, wherein the aforementioned threshold voltage information indicates whether the threshold voltage level of the aforementioned second memory cell is set to high or low, and the aforementioned control circuit performs the operation of adjusting the aforementioned threshold voltage of the aforementioned first memory cell when the aforementioned threshold voltage information indicates that the threshold voltage level of the aforementioned second memory cell is set to low.

4. The semiconductor memory device of claim 3, wherein the aforementioned control circuit does not perform the operation of adjusting the aforementioned threshold voltage of the aforementioned first memory cell when the aforementioned threshold voltage information indicates that the threshold voltage level of the aforementioned second memory cell is high.

5. The semiconductor memory device of claim 3, wherein the aforementioned control circuit performs a second program operation on the aforementioned first memory cell to raise the threshold voltage.

6. The semiconductor memory device of claim 5, further comprising a sense amplifier circuit capable of applying a bit line voltage to the aforementioned bit line, wherein the sense amplifier circuit applies the aforementioned bit line voltage of a first value in the aforementioned first program operation and applies the aforementioned bit line voltage of a second value in the aforementioned second program operation, wherein the aforementioned second value is lower than the aforementioned first value.

7. The semiconductor memory device as claimed in claim 6, wherein the aforementioned second value is higher than the ground voltage value and lower than the write inhibit voltage value.

8. The semiconductor memory device of claim 6, wherein the aforementioned control circuit generates the aforementioned threshold voltage information based on the data pattern of the data written to the memory cell connected to the aforementioned second word line.

9. The semiconductor memory device of claim 8, wherein the aforementioned control circuit stores information representing the aforementioned data pattern in a portion of the aforementioned plurality of memory cell arrays.

10. The semiconductor memory device of claim 8, wherein the aforementioned control circuit stores the aforementioned threshold voltage information in a portion of the aforementioned plurality of memory cell arrays.

11. A control method for a semiconductor memory device, comprising: a plurality of memory cell arrays; a plurality of memory cells included in a first memory cell array, which is one of the plurality of memory cell arrays; a plurality of word lines, each connected to a gate of the plurality of memory cells; and a bit line connected to a first end of the first memory cell array; and executing a loop at least once in response to an instruction sequence for writing data to the first memory cell, which is one of the plurality of memory cells, connected to the first word line of the plurality of word lines, wherein each loop includes a first program action for writing data to the first memory cell and a verification action for verifying the data written to the memory cell. The aforementioned instruction sequence includes threshold voltage information related to the threshold voltage level set in the second memory cell, which is connected to the second word line adjacent to the first word line and is one of the aforementioned plurality of word lines. The aforementioned instruction sequence includes, after exiting the aforementioned loop, determining whether to perform the action of adjusting the threshold voltage of the aforementioned first memory cell based on the threshold voltage level to be set in the aforementioned second memory cell.

12. The control method of the semiconductor memory device as claimed in claim 11, wherein the aforementioned loop ends when the aforementioned data is normally written to the aforementioned first memory cell.

13. The control method of the semiconductor memory device as claimed in claim 11, wherein the aforementioned threshold voltage information indicates whether the threshold voltage level of the aforementioned second memory cell is set to high or low, and when the aforementioned threshold voltage information indicates that the threshold voltage level of the aforementioned second memory cell is set to low, the aforementioned threshold voltage of the aforementioned first memory cell is adjusted.

14. The control method of the semiconductor memory device as claimed in claim 13, wherein when the aforementioned threshold voltage information indicates that the threshold voltage level of the aforementioned second memory cell is high, the aforementioned threshold voltage of the aforementioned first memory cell is not adjusted.

15. The control method of the semiconductor memory device of claim 13, comprising performing a second program operation on the first memory cell in order to increase the aforementioned threshold voltage.

16. The control method of the semiconductor memory device of claim 15, wherein during the first program operation, a first value of bit line voltage is applied to the bit line, and during the second program operation, a second value of bit line voltage is applied to the bit line, wherein the second value is lower than the first value.

17. The control method for a semiconductor memory device as claimed in claim 16, wherein the aforementioned second value is higher than the ground voltage value and lower than the write inhibit voltage value.

18. The control method of the semiconductor memory device as claimed in claim 11, which generates the aforementioned threshold voltage information based on the data pattern of the data written to the memory cell connected to the aforementioned second word line.

19. A method for controlling a semiconductor memory device as claimed in claim 18, wherein information representing the aforementioned data pattern is stored in a portion of the aforementioned plurality of memory cell arrays.

20. The control method of the semiconductor memory device of claim 11, wherein the aforementioned threshold voltage information is stored in a portion of the aforementioned plurality of memory cell arrays.

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