Integrated circuit with offset trimming using field-effect transistors and method for operating the same

Abstract

According to some embodiments of the present invention, an integrated circuit includes a first voltage source, a second voltage source, a first trimmer circuit, and a second trimmer circuit. The first voltage source is configured to generate a first voltage that decreases monotonically with an absolute temperature of the integrated circuit. The second voltage source is configured to generate a second voltage that increases monotonically with the absolute temperature. The first and second voltages are compensated to generate a reference voltage. The first trimmer circuit includes trimmers connected in parallel with the first voltage source, and uses these trimmers to adjust the first voltage to reduce a temperature coefficient of the reference voltage. The second trimmer circuit is configured to multiply the reference voltage by a predetermined multiplication ratio to adjust a deviation of the reference voltage to generate an output reference voltage at an output terminal of the integrated circuit.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to an integrated circuit and its operation method for using field-effect transistors for deviation fine-tuning. [Previous Technology]

[0002] The current trend towards miniaturized integrated circuits (ICs) has led to the development of smaller, more efficient devices with increased functionality and higher operating speeds. This miniaturization process also brings more stringent design and manufacturing requirements, as well as reliability challenges. Electronic design automation (EDA) tools are used to create, optimize, and verify standard cell layout designs for integrated circuits, thereby ensuring that they comply with both design and manufacturing specifications. [Summary of the Invention]

[0003] According to an embodiment of the present invention, an integrated circuit includes: a first voltage source configured to generate a first voltage that decreases monotonically with an absolute temperature of the integrated circuit; and a second voltage source configured to generate a second voltage that increases monotonically with the absolute temperature of the integrated circuit, wherein the first voltage is used to compensate the second voltage to generate a reference voltage; a first trimming circuit including a plurality of trimming devices configured in parallel with the first voltage source and configured to use the plurality of trimming devices to adjust the first voltage to reduce a temperature of the reference voltage; and a second trimming circuit configured to multiply the reference voltage by a predetermined multiplication ratio to adjust a deviation of the reference voltage to generate an output reference voltage at an output terminal of the integrated circuit.

[0004] According to an embodiment of the present invention, an integrated circuit includes: a first temperature-sensitive device configured to function as a first voltage source varying with an absolute temperature of the integrated circuit; and a second temperature-sensitive device coupled to the first temperature-sensitive device and configured to function as a second voltage source varying with the absolute temperature of the integrated circuit, wherein the second voltage source compensates the first voltage source to generate a reference voltage; a first trimming circuit including a plurality of trimming devices configured in parallel with the first temperature-sensitive device and configured to use the plurality of trimming devices to adjust a temperature coefficient of the reference voltage; and a second trimming circuit configured to multiply the reference voltage by a predetermined multiplication ratio to adjust a deviation of the reference voltage to generate an output reference voltage at an output terminal of the integrated circuit having an inaccuracy level lower than the reference voltage.

[0005] According to an embodiment of the present invention, an operation method of an integrated circuit includes: generating a reference voltage by compensating a first voltage (V1) provided by a first voltage source with a second voltage provided by a second voltage source, wherein the first voltage is complementary to an absolute temperature of the integrated circuit, and the second voltage is proportional to the absolute temperature of the integrated circuit; fine-tuning the first voltage using a plurality of fine-tuning devices of a first fine-tuning circuit to reduce a temperature coefficient of the reference voltage; and multiplying the reference voltage by a predetermined multiplication ratio using a second fine-tuning circuit to fine-tune a deviation of the reference voltage to generate an output reference voltage.

Implementation Method

[0021] The following disclosure provides numerous different embodiments or examples of various components for implementing the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first component formed above or on a second component may include embodiments in which the first component and the second component form direct contact, and may also include embodiments in which an additional component may be formed between the first component and the second component so that the first component and the second component do not form direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate any relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatial relative terms such as "below," "under," "down," "above," "over," "above," "on," and the like may be used herein to describe the relationship of one element or component to another element(s) shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0023] Furthermore, it will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it may be directly connected to or coupled to the other element, or there may be an intermediary element.

[0024] The embodiments or examples illustrated in the drawings are disclosed below using specific language. However, it will be understood that the embodiments and examples are not intended to be limiting. Any changes or modifications to the disclosed embodiments and any further applications of the principles disclosed in this document may be considered, as would normally be apparent to those skilled in the art.

[0025] Furthermore, it should be understood that only a few processing steps and / or components of an apparatus may be briefly described. Additionally, extra processing steps and / or components may be added, and certain processing steps and / or components may be removed or modified, while still fulfilling the claims of the invention. Therefore, it should be understood that the following description is merely illustrative and is not intended to imply the need for one or more steps or components.

[0026] In addition, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate any relationship between the various embodiments and / or configurations discussed.

[0027] In some embodiments, a voltage reference circuit is provided, comprising a first trimming circuit and a second trimming circuit. The first trimming circuit is configured to reduce a temperature coefficient of a reference voltage generated by the voltage reference circuit, while the second trimming circuit is configured to adjust a deviation of the reference voltage to generate an output reference voltage having an inaccuracy level lower than the reference voltage.

[0028] FIG1 is a block diagram of a voltage reference circuit according to some embodiments of the present disclosure.

[0029] In some embodiments, the voltage reference circuit 100 shown in FIG1 includes temperature coefficient fine-tuning and deviation fine-tuning functions, thereby providing an output reference voltage VREF_trimmed with higher accuracy compared to a reference voltage VREF generated therein. The voltage reference circuit 100 includes a bias current generator 110, a first voltage source 120, a second voltage source 130, a temperature coefficient fine-tuning circuit 140, and a deviation fine-tuning circuit 150, as depicted in FIG1. ​​The bias current generator 110 can be configured to generate a first bias current Ib1 and a second bias current Ib2 respectively provided to the first voltage source 120 and the second voltage source 130.

[0030] In some embodiments, the first voltage source 120 may be configured to generate a first voltage V1 based on a first bias current Ib1, which decreases monotonically with the absolute temperature of one of the voltage reference circuits 100. The second voltage source 130 may be configured to generate a second voltage V2 based on a second bias current Ib2, which increases monotonically with the absolute temperature of the voltage reference circuit 100. Both the first voltage source 120 and the second voltage source 130 may include one or more metal-oxide-semiconductor field-effect transistors (MOSFETs) and / or stacked gate devices of MOSFETs. In some embodiments, the MOSFETs used in the first voltage source 120 and the second voltage source 130 are not limited to SVT (Standard Threshold Voltage) transistors. Alternatively or alternatively, HTV (High Threshold Voltage), LVT (Low Threshold Voltage), SLVT (Extra-Low Threshold Voltage), and ULVT (Ultra-Low Threshold Voltage) transistors may also be used.

[0031] A second voltage V2 is used to compensate for the first voltage V1 to generate a reference voltage VREF. The working principle of this compensation is detailed with reference to FIG2, which illustrates a voltage-temperature curve resulting from the compensation between the first voltage V1 and the second voltage V2 according to some embodiments of this disclosure. In some embodiments, the first voltage V1 is complementary to the absolute temperature (CTAT), while the second voltage V2 is proportional to the absolute temperature (PTAT), as shown by curves 222 and 212 in FIG220 and 210, respectively. The compensation of the first voltage V1 and the second voltage V2 results in a reference voltage VREF, which exhibits the temperature-voltage relationship depicted by curve 232 in FIG230.

[0032] Specifically, the voltage reference circuit 100 is designed to operate within an operating temperature range defined by an upper temperature TH and a lower temperature TL, thereby indicating that the reference voltage VREF and the output reference voltage VREF_trimmed are applicable to all PVT (process, voltage, and temperature) combinations within the operating temperature range. In some embodiments, the upper temperature TH and the lower temperature TL may be 120°C and -40°C, respectively, but this disclosure is not limited thereto. The upper temperature TH and the lower temperature TL may be adjusted as needed. In addition, the reference voltage VREF is subjected to variations between voltage VREF_MAX and VREF_MIN within the operating temperature range between the upper temperature TH and the lower temperature TL. Therefore, the temperature coefficient TC of the reference voltage VREF can be expressed using the following equation (1).

[0033] In equation (1), V REF_AVG (which may be referred to as a nominal voltage V nominal) represents the average temperature of the reference voltage V REF at a specified temperature (usually room temperature, such as 25°C).

[0034] Figure 3 is a schematic diagram of a voltage reference circuit according to some embodiments of the present disclosure. Figure 4A is a schematic diagram of a stacked gate device according to some embodiments of the present disclosure. Figure 4B is an equivalent circuit diagram of the stacked gate device in Figure 4A.

[0035] In some embodiments, the voltage reference circuit 100 shown in FIG1 may be implemented using a voltage reference circuit 300, which is a bandgap voltage reference circuit capable of generating an output reference voltage VREF_trimmed. It should be noted that the embodiment of the voltage reference circuit 300 shown in FIG3 is used to describe the operation of the voltage reference circuit 100 shown in FIG1, and it may alternatively be implemented by other voltage reference circuits having similar functional blocks.

[0036] In some embodiments, the voltage reference circuit 300 may include a bias current generator 310, temperature sensing devices 320 and 330, a temperature coefficient fine-tuning circuit 340, and a deviation fine-tuning circuit 350, as depicted in FIG3. The bias current generator 310 includes a current mirror formed by transistors M1 to M2, which may be field-effect transistors (FETs, hereinafter referred to as "transistors"). Each of the transistors M1 to M2 has a gate terminal and a channel between a source terminal and a drain terminal. The bias current (e.g., Ib1 and Ib2) traveling through the channel depends on the voltage difference applied to the gate terminals of each of the transistors M1 to M2.

[0037] Temperature-sensitive devices 330 and 320 can be implemented using stacked gate devices X1 and X2, respectively. Additionally, the temperature coefficient fine-tuning circuit 340 includes a plurality of stacked gate devices, such as X2_trim0 to X2_trimx. Each of the stacked gate devices X1 and X2 includes a plurality of field-effect transistors stacked together. References X1 and X2 also indicate the number of FETs connected in series in each of the respective stacked gate devices X1 and X2. Furthermore, each of the stacked gate devices X2_trim0 to X2_trimx has the same number of stacked transistors as the stacked gate device X2 in the temperature-sensitive device 320, but the number of fingers in the stacked gate devices X2_trim0 to X2_trimx may differ from the number of fingers in the stacked gate device X2. A detailed description of a stacked gate device is as follows.

[0038] In some embodiments, a stacked gate device 450 (also referred to as "stack X" in FIG. 4A) can be considered as a three-terminal transistor device having a gate terminal 451, a source / drain (S / D) terminal 452, and a source / drain terminal 453. An equivalent circuit diagram of the stacked gate device 450 includes a plurality of transistors 4501 configured in a stacked or overlapping structure, as shown in FIG. 4B. The total number of stacked transistors 4501 is represented as an integer X. For example, the gate terminals of transistors 4501 are connected together to form the gate terminal 451 of the stacked gate device 450. Additionally, the transistors 4501 may be N-type FETs, and the N-type channels of transistors 4501 (e.g., X transistors 4501) are connected in series between the (S / D) terminals 452 and 453 of the stacked gate device 450. For example, the (S / D) terminal of the first transistor 4501 is used as the (S / D) terminal 452 of the stacked gate device 450, and one (S / D) terminal of the first transistor 4501 is connected to one (S / D) terminal of the second transistor 4501, one (S / D) terminal of the second transistor 4501 is connected to one (S / D) terminal of the third transistor 4501, and so on. In other words, for each integer n between 1 and X-1, the (S / D) terminal of the nth transistor 4501 is connected to the (n+1)th transistor 4501. Therefore, the (S / D) terminal of the last transistor 4501 (i.e., the Xth transistor 4501) is used as the (S / D) terminal 453 of the stacked gate device 450.

[0039] FIG4C is a schematic diagram of a stacked gate device having a plurality of finger structures according to some embodiments of the present disclosure. FIG4D is an equivalent circuit diagram of the stacked gate device in FIG4C.

[0040] In some embodiments, the stacked gate device 450 shown in FIG4A includes one or more stacked gate devices TX1 to TXN configured in parallel, as shown in FIG4C, where N is a positive integer. Each of the stacked gate devices TX1 to TXN can be considered as a finger structure or a "finger" containing X transistors 4501 configured in a stacked or overlapping structure, as shown in FIG4D. For example, the channels of the transistors 4501 in each stacked gate device TX1 to TXN are connected in series to form the respective channels of each stacked gate device TX to TXN. In addition, the channels of each stacked gate device TX1 to TXN are coupled between the (S / D) terminals 452 and 453 of the stacked gate device 450, and the gate terminals of the stacked gate devices TX1 to TXN are connected to the gate terminals 451 of the stacked gate device 450. When the stacked gate device 450 includes a finger structure, the equivalent circuit diagram of the stacked gate device 450 can be found in Figure 4B.

[0041] It should be noted that the transistors 4501 within the stacked gate devices TX1 to TXN can be manufactured in the same process and therefore have substantially the same electrical characteristics, such as channel width, channel length, threshold voltage, and transconductance. The design of the stacked gate device X with one or more finger structures shown in Figures 4C and 4D can be applied to the stacked gate devices X1, X2, and X2_trim0 to X2_trimx in Figure 3, wherein the transistors have substantially the same electrical characteristics.

[0042] In some embodiments, the gate-to-source voltage Vgs of the stacked gate device 450 shown in FIG4A can be expressed by the following equation (2).

[0043] Where Vth represents the threshold voltage of the stacked gate device 450; I represents the bias current flowing through the stacked gate device 450; L1 and W1 represent the channel length and channel width of the stacked gate device 450, respectively; Cox represents the gate oxide capacitance per unit area of ​​the stacked gate device 450; and μ represents the electron mobility. It should be noted that as temperature increases, electrons become more energetic, and the energy barrier between the (S / D) terminal 453 of the stacked gate device 450 and the channel is lower, allowing more carriers to exist in the channel, which in turn reduces the threshold voltage. In other words, when the bias current I is constant, the threshold voltage Vth decreases with increasing temperature, resulting in a monotonically decreasing gate-to-source voltage Vgs of the stacked gate device 450 with increasing absolute temperature (e.g., complementary to absolute temperature, CTAT).

[0044] Figure 5A is a schematic diagram of a stacked gate device in a diode connection configuration according to some embodiments of the present disclosure. Figure 5B is a schematic diagram illustrating the voltage-temperature curve of the stacked gate device in Figure 5A.

[0045] In some embodiments, the stacked gate device 450 is configured with a diode connection, indicating that the gate terminal 451 of the stacked gate device 450 is connected to the (S / D) terminal 452 of the stacked gate device 450, and a bias current Ib is provided to the stacked gate device 450, as shown in FIG5A. In this case, the voltage difference (e.g., gate-to-source voltage) Vgs between the gate terminal 451 and the (S / D) terminal 453 of the stacked gate device 450 decreases as the absolute temperature of the stacked gate device X increases, as shown by curve 502 in FIG5B. In addition, the downward slope of the voltage-temperature curve depends on the number of stacked transistors in the stacked gate device X. For example, as the number of stacked transistors increases (e.g., a larger stack X), the slope of the VT (voltage-temperature) curve decreases, as shown by curve 504 in Figure 5B, indicating that the voltage difference Vgs between the gate terminal 451 and the (S / D) terminal 453 of the stacked gate device X becomes less sensitive to changes in absolute temperature. Therefore, the output voltage VO1 generated by the stacked gate device 450 decreases monotonically with respect to absolute temperature (e.g., in a complementary manner to absolute temperature, CTAT). Thus, the stacked gate device 450 configured as shown in Figure 5A can be considered a CTAT device.

[0046] In some embodiments, the stacked gate device 450 configured as shown in FIG. 4A has a downward VT curve similar to that shown by curve 502 in FIG. 5B. For example, as the number of stacked transistors increases (e.g., a larger stack X), the downward slope of the VT curve decreases, as shown by curve 504 in FIG. 5B, thereby indicating that the voltage difference Vgs between the gate terminal 451 and the (S / D) terminal 453 of the stacked gate device X becomes less sensitive to changes in absolute temperature. That is, as the number of stacked transistors in the stacked gate device 450 increases, the downward slope of the VT (Vgs vs. absolute temperature) curve of the stacked gate device 450 can become less steep. This mechanism of the VT curve can be applied to the stacked gate devices X1 and X2 shown in FIG. 3.

[0047] Now turn our attention back to Figure 3. In some embodiments, temperature-sensitive devices 330 and 320 respectively include stacked gate devices X1 and X2. The number of stacked transistors X1 in stacked gate device X1 is greater than the number of stacked transistors X2 in stacked gate device X2. Based on the embodiments described above in Figures 5A to 5B, it can be seen that both stacked gate devices X1 and X2 are CTAT devices, and the gate-to-source Vgs1 of stacked gate device X1 and the gate-to-source Vgs2 of stacked gate device X2 decrease as the absolute temperature of voltage reference circuit 300 increases. It should be noted that since the number X1 is greater than the number X2, stacked gate device X1 is less sensitive to changes in absolute temperature compared to stacked gate device X2. Therefore, the decrease in the gate-to-source voltage Vgs1 of the stacked gate device X1 is greater than the decrease in the gate-to-source voltage Vgs2 of the stacked gate device X2, thus indicating that the voltage difference Vgs1-Vgs2 increases with increasing absolute temperature. Furthermore, although the bias current Ib2 can be calculated as (Vgs1-Vgs2) / R, this means that the bias current Ib2 flowing through the stacked gate device X1 increases with increasing absolute temperature. Therefore, the bias current Ib2 is a PTAT current that increases monotonically with the absolute temperature of the voltage reference circuit 300.

[0048] In some embodiments, the reference voltage VREF is the same as the gate-to-source voltage Vgs1 of the stacked gate device X1, as depicted in FIG3. According to Equation (2), the critical threshold voltage Vth of the stacked gate device X1 decreases with increasing absolute temperature, while the bias current Ib2 increases with increasing absolute temperature, thereby indicating that the temperature-sensitive device 330 is used as both a PTAT voltage source and a CTAT voltage source. This means that the CTAT scheme of the critical threshold voltage Vth of the stacked gate device X1 can be compensated by the PTAT scheme of the bias current Ib2 flowing through the stacked gate device X1, resulting in a self-compensating temperature coefficient of the reference voltage VREF. In addition, with proper design of the number of stacked transistors in the stacked gate devices X1 and X2 and the number of finger structures in the stacked gate device X2, the reference voltage VREF generated at node N2 can achieve a temperature coefficient that is substantially equal to 0. The details of adjusting the number of finger structures in the stacked gate device X2 using the temperature coefficient fine-tuning circuit 340 are described below.

[0049] In some embodiments, the reference voltage VREF generated at node N2 can be expressed in another way, such as VREF = Vgs2 + Ib2*R, where Vgs2 represents the gate-to-source voltage Vgs2 of the stacked gate device X2, and Ib2*R represents the voltage drop across resistor R. When the gate-to-source voltage Vgs2 is CTAT and the bias current Ib2 is PTAT, the CTAT scheme can also be compensated by the PTAT scheme in another way to generate the reference voltage VREF, thereby resulting in a self-compensated temperature coefficient of the reference voltage VREF.

[0050] In some embodiments, the gate terminals of transistors M1 and M2 are electrically connected to node N1, and the source terminals of transistors M1 and M2 are electrically connected to the power supply voltage VDD. Since transistors M1 and M2 have the same gate-to-source voltage Vgs, transistors M1 and M2 can be configured to function as a first current mirror, and the bias current Ib2 flowing through the channel of transistor M2 is proportional to the bias current Ib1 flowing through the channel of transistor M1. When transistors M1 and M2 are designed to have substantially the same electrical characteristics (such as channel width, channel length, threshold voltage, and transconductance), the bias current Ib2 flowing through transistor M2 is substantially equal to the bias current Ib1 flowing through transistor M1. Therefore, transistor M1 can be used as a current source as well as transistor M2. As described above, the bias current Ib2 is a PTAT current, thus indicating that the bias current Ib1 is also a PTAT current.

[0051] In some embodiments, the temperature coefficient fine-tuning circuit 340 may be configured to use a dynamic element matching ("DEM") technique to adjust (e.g., fine-tune) the voltage-temperature drop rate of the temperature-sensitive device 320, thereby resulting in a lower temperature coefficient for the reference voltage VREF generated at node N2 compared to the reference voltage VREF without the temperature coefficient fine-tuning circuit 340. The temperature coefficient fine-tuning circuit 340 may include a plurality of fine-tuning stacked gate devices X2_trim0 to X2_trimx. The gate terminals of each fine-tuning stacked gate device X2_trim0 to X2_trimx are coupled to a respective bit of a fine-tuning code signal TC[0:x] via corresponding buffer circuits FB0 to FBx. The drain and source terminals of each fine-tuning stacked gate device X2_trim0 to X2_trimx are coupled between the voltage VBP (the voltage at node N1) and the ground node. In addition, each of the buffer circuits FB0 to FBx can be supplied with a voltage VG (the voltage at node N3) and a ground voltage VSS, as shown in Figure 3.

[0052] It should be noted that each of the fine-tuning stacked gate devices X2_trim0 to X2_trimx may include one or more finger structures configured in parallel, wherein each finger structure has the same number of stacked transistors as the stacked gate device X2. Furthermore, depending on the type of fine-tuning code signal TC[0:x] used, the fine-tuning stacked gate devices X2_trim0 to X2_trimx may have the same or different numbers of finger structures. Details are described below with reference to Figures 6A to 6D.

[0053] In some embodiments, referring to FIG3, the number of fingers coupled in parallel to the stacked gate device X2 can be adjusted using the temperature coefficient fine-tuning circuit 340. For simplicity, the temperature coefficient fine-tuning circuit 340 within the voltage reference circuit 300 includes four fine-tuning stacked gate devices X2_trim0 to X2_trim3, which are controlled by the respective bits of the fine-tuning code signal TC[0:3] via their respective buffer circuits FB0 to FB3. For example, the buffer circuits FB0 to FB3 are supplied with a voltage VG (e.g., the gate voltage of the stacked gate device X2) and a ground voltage VSS. In addition, each bit of the fine-tuning code signal TC[0:3] can be transmitted to the gate terminals B0 to B3 of the fine-tuning stacked gate devices X2_trim0 to X2_trim3 via their respective buffer circuits FB0 to FB3. Furthermore, the voltage range of each bit of the fine-tuning code signal TC[0:3] is between the voltage VG and the ground voltage VSS.

[0054] In some embodiments, each of the fine-tuning stacked gate devices X2_trim0 to X2_trim3 has the same number of finger structures, such as 1 to N, where N is a positive integer. When the calorimeter code is used for the temperature coefficient fine-tuning circuit 340, each bit of the fine-tuning code signal TC[0:3] can control an equal number of finger structures to be coupled in parallel to the stacked gate device X2. For simplicity, it is assumed that there are 4 stacked transistors in the stacked gate device X2, and that the stacked gate device X2 includes one finger structure. In addition, each of the fine-tuning stacked gate devices X2_trim0 to X2_trim3 includes one finger structure. When the trimming code signal TC[3:0]=4'b1101, voltage VG is transmitted to gate terminals B0, B2, and B3 of the trimming stacked gate devices X2_trim0, X2_trim2, and X2_trim3, thereby activating the trimming stacked gate devices X2_trim0, X2_trim2, and X2_trim3. Simultaneously, ground voltage VSS is transmitted to gate terminal B1, thereby deactivating the trimming stacked gate device X2_trim1. Therefore, three finger structures are activated and coupled in parallel to the finger structure of the stacked gate device X2, indicating that a total of four finger structures are used to adjust the downward slope of the VT (e.g., Vgs2 versus absolute temperature) curve of the stacked gate device X2, thereby performing temperature coefficient trimming on the PTAT current (e.g., Ib2=(Vgs1-Vgs2) / R) generated by the voltage reference circuit 300.

[0055] In some embodiments, each of the fine-tuning stacked gate devices X2_trim0 to X2_trim3 may have a different number of finger structures, such as powers of 2. For simplicity, it is assumed that there are 4 stacked transistors in the stacked gate device X2, and that the stacked gate device X2 includes one finger structure. In addition, the fine-tuning stacked gate devices X2_trim0 to X2_trim3 respectively include 1, 2, 4 and 8 finger structures, wherein each finger structure includes 4 stacked transistors, as shown in Figures 6A to 6D. When the binary code is used for the temperature coefficient fine-tuning circuit 340, each bit of the fine-tuning code signal TC[0:3] can control a different number of finger structures to be coupled in parallel to the stacked gate device X2. When the trimming code signal TC[3:0]=4'b1101, voltage VG is transmitted to gate terminals B0, B2, and B3 of the trimming stacked gate devices X2_trim0, X2_trim2, and X2_trim3, thereby activating the trimming stacked gate devices X2_trim0, X2_trim2, and X2_trim3. Simultaneously, ground voltage VSS is transmitted to gate terminal B1, thereby deactivating the trimming stacked gate device X2_trim1. Therefore, 13 (e.g., 1+4+8) finger structures are activated and coupled in parallel to the finger structure of the stacked gate device X2, indicating that a total of 14 finger structures are used to adjust the downward slope of the VT (e.g., Vgs2 versus absolute temperature) curve of the stacked gate device X2, thereby performing temperature coefficient trimming on the PTAT current (e.g., Ib2=(Vgs1-Vgs2) / R) generated by the voltage reference circuit 300.

[0056] Figure 7 is a schematic diagram of one of the deviation fine-tuning circuits according to the embodiment of Figure 3. Please refer to both Figure 3 and Figure 7.

[0057] In some embodiments, the deviation fine-tuning circuit 350 may include an operational transconductance amplifier (OTA) 352, transistors M3 and M4, resistors R1 and R2, fine-tuning resistors Rt[0:5], and switches SW0 to SW5, as depicted in FIG7. For illustrative purposes, six switches SW0 to SW5 and six fine-tuning resistors Rt[0:5] are shown in FIG7. It should be noted that the number of switches and fine-tuning resistors may be adjusted as needed.

[0058] In some embodiments, the OTA 352 may be implemented using a differential amplifier, an operational amplifier, or a circuit with an equivalent virtual ground function, but this disclosure is not limited thereto. The OTA 352 may be configured to receive a reference voltage VREF at a first input terminal and pass the reference voltage VREF to its second input terminal (e.g., node N4) due to the virtual ground of the OTA 352. Therefore, the current I1 flowing from transistor M3 through resistor R1 to ground can be expressed as: I1 = VREF / R1.

[0059] In some embodiments, the gate terminals of transistors M3 and M4 are both connected to the output terminals of OTA 352 (e.g., node N6). Additionally, the first (S / D) terminals of transistors M3 and M4 receive the power supply voltage VDD, resulting in transistors M3 and M4 having equal gate-source voltages. Therefore, transistors M3 and M4 form a current mirror, whereby the current I1 flowing through transistor M3 is mirrored to the current I2 flowing through transistor M4. Thus, depending on the control signal C[5:0], current I2 flows from transistor M4 through resistor R2 and trimming resistor Rt[0:5] or their respective switches SW0 to SW5 to ground. In some embodiments, each control bit of the control signal C[5:0] controls its respective switches SW5 to SW0. For simplicity, the operation of switch SW0 based on its respective control bit C[0] is described herein. For example, when control bit C[0] = 1, switch SW0 is activated (e.g., closed or shorted), thereby indicating that current I2 flows through the activated switch SW0. Conversely, when control bit C[0] = 0, switch SW0 is deactivated (e.g., opened), thereby indicating that current I2 flows through the trimmer resistor Rt[0]. The operation of switches SW1 to SW5 can be derived in a similar manner.

[0060] In some embodiments, reference Rt[5:0] may also represent the resistance of the corresponding trimmer resistor. The resistance value of the trimmer resistor Rt[5:0] can be organized using a binary coding scheme aligned with the control signal C[5:0]. For example, the resistances of the respective trimmer resistors Rt[5] to Rt[0] can be expressed as: Rt[5]=2Rt[4]=2 2Rt[3]=2 3Rt[2]=2 4R[1]=2 5Rt[0], where the trim resolution associated with the deviation of the output reference voltage VREF_trimmed is determined by the resistance value of the trimmer resistor Rt[0], which corresponds to the least significant bit (LSB) of the control signal C[5:0] (e.g., C[0]). Alternatively, the resistance value of the trimmer resistor Rt[5:0] can be organized using a calorimeter coding scheme aligned with the control signal C[5:0]. For example, the resistances of the respective fine-tuning resistors Rt[5] to Rt[0] can be expressed as: Rt[5]=Rt[4]=Rt[3]=Rt[2]=R[1]=Rt[0], where the fine-tuning resolution is determined by the resistance value of the fine-tuning resistor Rt[0], which corresponds to the least significant bit (LSB) of the control signal C[5:0] (e.g., C[0]). In addition, when using the calorimeter encoding scheme, the number of fine-tuning resistors and the width of the control signal C can be increased to 64, thereby implementing 64 fine-tuning steps as a binary encoding scheme.

[0061] It should be noted that the number of trimming resistors Rt[5:0] is for descriptive purposes and can be adjusted according to actual needs. Furthermore, the trimming resolution of the output reference voltage VREF_trimmed is based on the total step size of the trimming resistors Rt[X-1:0] controlled by the control signal C[X-1:0]. Larger steps in the trimming resistors can result in higher resolution for deviation trimming.

[0062] In some embodiments, the current I1 is mirrored to the current I2 by the current mirror formed by transistors M3 and M4, and the output reference voltage VREF_trimmed can be calculated as I2*(R2+Rt[0:5]). Therefore, by replacing the current I2 with the current I1 which is equal to VREF / R1, the output reference voltage VREF_trimmed can be expressed by the following equation (3).

[0063] In some embodiments, when the value is greater than 1, the indication deviation fine-tuning circuit 350 fine-tunes the reference voltage VREF upward, thereby causing the output reference voltage VREF_trimmed to be higher than the reference voltage VREF. When the value is equal to 1, the indication deviation fine-tuning circuit 350 maintains the reference voltage VREF at the output reference voltage VREF_trimmed, thereby causing the output reference voltage VREF_trimmed to be equal to the reference voltage VREF. When the value is less than 1, the indication deviation fine-tuning circuit 350 fine-tunes the reference voltage VREF downward, thereby causing the output reference voltage VREF_trimmed to be lower than the reference voltage VREF.

[0064] It should be noted that resistors R1 and R2, as well as the trimmer resistor Rt[5:0], can be manufactured using a back-end process (BEOL) procedure, in which the resistance values ​​undergo inherent variations during the BEOL process. Since resistors R1 and R2, as well as the trimmer resistor Rt[5:0], are manufactured using the same BEOL process, their resistance values ​​may exhibit similar variations. For example, if the resistance value of resistor R1 changes by +15% or -10% from its expected resistance value, it indicates that the resistance values ​​of resistors R2 and the trimmer resistor Rt[5:0] will also change by +15% or -10% from their expected resistance values. Furthermore, the deviation fine-tuning circuit 350 utilizes the ratio of a second resistor (e.g., R2+Rt[5:0]) along a second current path (e.g., the path from transistor M4 through resistor R2 and fine-tuning resistor Rt[5:0] to ground current I2) to a first resistor (e.g., R1) along a first current path (e.g., the path from transistor M3 through resistor R1 to ground current I1), thereby allowing the resistance variations of resistors R1 and R2 and the fine-tuning resistor Rt[5:0] to be ignored. Therefore, the variation of the output reference voltage REF_trimmed can be controlled to remain within 1%. Thus, the output reference voltage VREF_trimmed derived by fine-tuning the reference voltage VREF can maintain accuracy within ±0.5 LSB using either a binary encoding scheme or a calorimeter encoding scheme.

[0065] Figures 8A to 8C are graphs illustrating different voltage-temperature curves for different fine-tuning schemes of the reference voltage according to some embodiments of the present disclosure. Please also refer to Figure 3 and Figures 8A to 8C.

[0066] In some embodiments, without utilizing the temperature coefficient fine-tuning circuit 340 or the deviation fine-tuning circuit 350, the reference voltage VREF generated at node N2 (referred to as VREF_NoTrim) can exhibit a voltage-temperature curve with an increasing temperature coefficient, as shown by curve 812 in FIG8A. For example, the reference voltage VREF_NoTrim has a maximum voltage VMAX1 and a minimum voltage VMIN1 within the operating temperature voltage between the upper temperature TH and the lower temperature TL. Alternatively, when utilizing the temperature coefficient fine-tuning circuit 340, the reference voltage VREF generated at node N2 (referred to as VREF_TCTrim) can exhibit a voltage-temperature curve with a relatively decreasing temperature coefficient, as shown by curve 822 in FIG8B. For example, the reference voltage VREF_TCTrim has a maximum voltage VMAX2 and a minimum voltage VMIN2 within the operating temperature voltage between the upper temperature TH and the lower temperature TL. Furthermore, the difference between the maximum voltage VMAX2 and the minimum voltage VMIN2 on curve 822 is much smaller than the difference between the maximum voltage VMAX1 and the minimum voltage VMIN1 on curve 812, thus indicating that the temperature coefficient of the reference voltage VREF_TCTrim is smaller than that of the reference voltage VREF_NoTrim. It should be noted that the nominal voltage of the reference voltage VREF_TCTrim on curve 822 may differ from the nominal voltage of the reference voltage VREF_NoTrim on curve 812.

[0067] In some embodiments, the voltage deviation of the reference voltage VREF_TCTrim can be adjusted by the deviation fine-tuning circuit 350. For example, the deviation fine-tuning circuit 350 is configured to multiply the reference voltage VREF (i.e., VREF_TCTrim) having a finely tuned temperature coefficient using a specific multiplication ratio (such as one of the multiplication ratios MR1 ​​to MRN). These multiplication ratios are controlled by the control signal C[5:0], where n is a positive integer between 1 and N. The multiplication ratios MR1 ​​to MRN can correspond to those described in the embodiment of FIG7. For example, when Rt[5:0] = 6'b0, the multiplication ratio MR1 can be calculated as R2 / R1. When Rt[5:0] = 6'b000001, the multiplication ratio MR2 can be calculated as (R2 + Rt[0]) / R1. The remaining multiplication ratios can be derived in a similar manner. Specifically, the difference between the maximum and minimum voltages on curves 831 to 833 shown in Figure 8C is equivalent to the difference between the maximum and minimum voltages on curve 822 shown in Figure 8B, wherein the difference is the difference in nominal voltages on these curves at a specified temperature (or an average temperature within the operating temperature range).

[0068] Figure 9 is a schematic diagram illustrating one of the voltage-temperature curves under different extreme conditions according to some embodiments of the present disclosure.

[0069] In some embodiments, due to variations in the front-end process (FEOL) procedure of the voltage reference circuit 300, the N-type and P-type FETs within the voltage reference circuit 300 fabricated on a semiconductor wafer can be in any FEOL condition, such as TT, FF, SS, FS, and SF conditions. For example, the first letter of each FEOL condition indicates the extreme type of the N-type FET, and the second letter of each FEOL condition indicates the extreme type of the P-type FET, where T, F, and S represent a typical case, a fast extreme case, and a slow extreme case, respectively. Therefore, the term TT condition refers to the typical-typical case, while the terms FF, SS, FS, and SF refer to the fast-fast, slow-slow, fast-slow, and slow-fast extreme cases, respectively.

[0070] Referring to Figure 9, curves 902, 904, 906, 908, and 910 correspond to the extreme cases of SS, SF, TT, FS, and FF, respectively. For the extreme cases of SS, SF, TT, FS, and FF, the nominal voltages on curves 902 to 910 at a specified temperature (e.g., 0°C) are approximately 0.515 V, 0.508 V, 0.48 V, 0.452 V, and 0.445 V, respectively. Furthermore, the temperature coefficient (TC) of the reference voltage VREF corresponding to the TT, FF, SS, FS, and SF cases is plotted in Table 1 below. Condition TT FF SS FS SF TC (ppm / ℃) 26 49 twenty one 70 49 Table 1

[0071] For descriptive purposes, the N-type and P-type FETs within a subsequent integrated circuit of the voltage reference circuit 300 are designed to operate under TT conditions. When the N-type and P-type FETs within the voltage reference circuit 300 are classified into any extreme case after manufacturing, the nominal voltage (or average voltage) of the reference voltage VREF generated by the voltage reference circuit 300 may not meet the voltage requirements of the subsequent integrated circuit. For example, the temperature coefficient adjustment circuit 340 can fine-tune the temperature coefficient of the reference voltage VREF by adjusting the first voltage V1 (e.g., PTAT voltage) generated by the temperature-sensitive device 320 (e.g., corresponding to the first voltage source 120 shown in FIG. 1). However, when the deviation of the nominal voltage (or average voltage) of the reference voltage VREF falls within any extreme case, the temperature coefficient adjustment circuit 340 cannot adjust the deviation to meet the TT condition. After manufacturing the voltage reference circuit 300, the characteristics of the N-type and P-type transistors can be measured to determine its extreme or TT condition. Additionally, the difference between the nominal voltage (or average voltage) under extreme conditions and the expected voltage level under TT conditions can be measured to determine the appropriate control signal C[5:0] to adjust the nominal voltage (or average voltage) under extreme conditions to the nominal voltage (or average voltage) under TT conditions. Therefore, using the deviation fine-tuning circuit 350, the nominal voltage (or average voltage) of the reference voltage VREF after TC fine-tuning in any extreme condition can be adjusted to the voltage level under TT conditions using appropriately designed resistors R1, R2 and fine-tuning resistor Rt[5:0], thereby enabling the subsequent integrated circuit to operate normally. It should be noted that the adjustment of the nominal voltage of the reference voltage VREF at a specified temperature (e.g., 25°C) is also applicable to the adjustment of the reference voltage VREF at other temperatures within the operating temperature range.

[0072] In some embodiments, the resistance values ​​of resistors R1 and R2 and the trimming resistor Rt[5:0] can be appropriately designed to ensure that the bias voltage trimming range covers all extreme cases. In some methods, without implementing the bias trimming circuit 350, the reference voltage VREF level can exhibit an inaccuracy of 5% and a temperature coefficient of less than 100 ppm / °C. For example, for a voltage level of 0.48 V, 5% inaccuracy corresponds to a resolution of approximately 24 mV. The voltage reference circuit 300 can provide an output reference voltage VREF_trimmed with an inaccuracy of 2.5% or less. For example, for a voltage level of 0.48 V, 2.5% inaccuracy corresponds to a resolution of approximately 12 mV. Furthermore, when the trimming resistor Rt[5:0] is designed using a binary encoding scheme, there are 64 steps available for fine-tuning the deviation of the output reference voltage VREF_trimmed, resulting in a trimming resolution of approximately 3 mV for the least significant bit (LSB) of each control signal C[5:0], with a temperature coefficient less than 100 ppm / ℃. Therefore, this trimming resolution ensures that the voltage level of the output reference voltage VREF remains within ±3 mV of the expected voltage level, thus meeting the requirement of 2.5% inaccuracy of the output reference voltage VREF_trimmed.

[0073] Figure 10 is a flowchart of one method for operating a voltage reference circuit according to some embodiments of the present disclosure. The sequence of operations of method 1000 depicted in Figure 10 is for illustrative purposes only; the operations of method 1000 can be performed in a sequence different from that depicted in Figure 10. It should be understood that additional operations may be performed before, during, and / or after method 1000 depicted in Figure 10, and some other processes may be described only briefly herein.

[0074] In operation 1010, a reference voltage VREF is generated by compensating for a first voltage V1 provided by a first voltage source and a second voltage V2 provided by a second voltage source, wherein the first voltage V1 decreases monotonically with the absolute temperature of an integrated circuit (e.g., the voltage reference circuit 100 shown in FIG. 1), and the second voltage V2 increases monotonically with the absolute temperature of the integrated circuit. In some embodiments, the first voltage source 120 is a CTAT voltage source, and the first voltage V1 is CTAT. The second voltage source 130 is a PTAT voltage source, and the second voltage V2 is PTAT.

[0075] In operation 1020, a plurality of fine-tuning devices of a first fine-tuning circuit are used to fine-tune the first voltage to reduce the temperature coefficient of a reference voltage. In some embodiments, the first fine-tuning circuit may refer to the temperature coefficient fine-tuning circuit 140 shown in FIG. 1, one possible implementation of which is shown by the temperature coefficient fine-tuning circuit 340 in FIG. 3. In addition, with a properly designed fine-tuning code TC[x:0], the PTAT voltage-temperature curve of the second voltage V2 can be used to better compensate the CTAT voltage-temperature curve of the first voltage V1, thereby substantially reducing the temperature coefficient of the reference voltage VREF generated by the voltage reference circuit 100.

[0076] In operation 1030, a second fine-tuning circuit is used to multiply the reference voltage by a predetermined multiplication ratio to fine-tune a deviation of the reference voltage to generate an output reference voltage. In some embodiments, the second fine-tuning circuit may refer to the deviation fine-tuning circuit 150 shown in FIG1, one possible implementation of which is shown by the deviation fine-tuning circuit 350 in FIG3. Additionally, with a properly designed control signal C[5:0], the voltage level of the nominal (or average) voltage of the output reference voltage VREF_trimmed can be adjusted to a desired voltage level within the operating temperature range, such as in the TT case (e.g., an operating condition).

[0077] One aspect of this disclosure provides an integrated circuit comprising a first voltage source, a second voltage source, a first trimmer circuit, and a second trimmer circuit. The first voltage source is configured to generate a first voltage that decreases monotonically with an absolute temperature of the integrated circuit. The second voltage source is configured to generate a second voltage that increases monotonically with the absolute temperature of the integrated circuit. The first voltage is used to compensate the second voltage to generate a reference voltage. The first trimmer circuit includes a plurality of trimmers connected in parallel with the first voltage source and is configured to use the plurality of trimmers to adjust the first voltage to reduce a temperature coefficient of the reference voltage. The second trimmer circuit is configured to multiply the reference voltage by a predetermined multiplication ratio to adjust a deviation of the reference voltage to generate an output reference voltage at an output terminal of the integrated circuit.

[0078] Another aspect of this disclosure provides an integrated circuit comprising a first temperature sensing device, a second temperature sensing device, a first trimmer circuit, and a second trimmer circuit. The first temperature sensing device is configured to function as a first voltage source that varies with an absolute temperature of the integrated circuit. The second temperature sensing device is coupled to the first temperature sensing device and configured to function as a second voltage source that varies with the absolute temperature of the integrated circuit. The second voltage source compensates for the first voltage source to generate a reference voltage. The first trimmer circuit includes a plurality of trimmers connected in parallel with the first voltage source and is configured to use the plurality of trimmers to adjust a temperature coefficient of the reference voltage. The second trimmer circuit is configured to multiply the reference voltage by a predetermined multiplication ratio to adjust a deviation of the reference voltage to generate an output reference voltage at an output terminal of the integrated circuit having an inaccuracy level lower than the reference voltage.

[0079] Another aspect of this disclosure provides a method comprising generating a reference voltage using a first voltage and a second voltage. The method comprises the steps of: generating a reference voltage by compensating a first voltage provided by a first voltage source with a second voltage provided by a second voltage source. The first voltage is complementary to an absolute temperature of the integrated circuit, and the second voltage is proportional to the absolute temperature of the integrated circuit; fine-tuning the first voltage using a plurality of fine-tuning devices of a first fine-tuning circuit to reduce a temperature coefficient of the reference voltage; and multiplying the reference voltage by a predetermined multiplication ratio using a second fine-tuning circuit to fine-tune a deviation of the reference voltage to generate an output reference voltage.

[0080] The methods and components disclosed herein have been fully described in the examples and descriptions provided. It should be understood that any modifications or alterations that do not depart from the spirit of this disclosure are intended to be covered by the protection scope of this disclosure.

[0081] Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufacturing, and material compositions, means, methods, and steps described in the specification. Those skilled in the art will readily understand from this disclosure that currently existing or subsequently developed processes, machines, manufacturing, material compositions, means, methods, or steps that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein can be utilized based on this disclosure.

[0082] Therefore, the appended claims are intended to include processes, machines, manufacturing, material composition, means, methods, or steps within their scope. Furthermore, each claim constitutes an individual embodiment, and combinations of various claims and embodiments are within the scope of this disclosure. [Simplified Explanation of the Diagram]

[0006] The best understanding of this disclosure is achieved by reading it in conjunction with the accompanying drawings and the following detailed description. It should be emphasized that, in accordance with standard industry practice, various features are not drawn to scale. In fact, for clarity of expression, the dimensions of various components may be arbitrarily increased or decreased.

[0007] FIG1 is a block diagram of a voltage reference circuit according to some embodiments of the present disclosure.

[0008] Figure 2 is a schematic diagram illustrating a voltage-temperature curve resulting from compensation between a first voltage and a second voltage according to some embodiments of the present disclosure.

[0009] Figure 3 is a schematic diagram of one of the voltage reference circuits according to some embodiments of the present disclosure.

[0010] Figure 4A is a schematic diagram of one of the stacked gate devices according to some embodiments of the present disclosure.

[0011] Figure 4B is an equivalent circuit diagram of one of the stacked gate devices in Figure 4A.

[0012] Figure 4C is a schematic diagram of a stacked gate device having a plurality of finger structures according to some embodiments of the present disclosure.

[0013] Figure 4D is an equivalent circuit diagram of one of the stacked gate devices in Figure 4C.

[0014] Figure 5A is a schematic diagram of a stacked gate device in a diode connection configuration according to some embodiments of the present disclosure.

[0015] Figure 5B is a schematic diagram showing the change of the voltage-temperature curve of one of the stacked gate devices in Figure 5A.

[0016] Figures 6A to 6D are schematic diagrams of a stacked gate device with a different number of finger structures, according to some embodiments of the present disclosure.

[0017] Figure 7 is a schematic diagram of one of the deviation fine-tuning circuits according to the embodiment of Figure 3.

[0018] Figures 8A to 8C are schematic diagrams illustrating different voltage-temperature curves for different fine-tuning schemes of the reference voltage according to some embodiments of the present disclosure.

[0019] Figure 9 is a schematic diagram illustrating one of the voltage-temperature curves under different extreme conditions according to some embodiments of the present disclosure.

[0020] Figure 10 is a flowchart of one method for operating a voltage reference circuit according to some embodiments of the present disclosure.

Claims

1. An integrated circuit comprising: A first voltage source configured to generate a first voltage that decreases monotonically with an absolute temperature of the integrated circuit; and a second voltage source configured to generate a second voltage that increases monotonically with the absolute temperature of the integrated circuit, wherein the first voltage is used to compensate the second voltage to generate a reference voltage; a first trimmer circuit including a plurality of trimmers configured in parallel with the first voltage source and configured to use the plurality of trimmers to adjust the first voltage to reduce a temperature coefficient of the reference voltage; and a second trimmer circuit configured to multiply the reference voltage by a predetermined multiplication ratio to adjust a deviation of the reference voltage to generate an output reference voltage at an output terminal of the integrated circuit, wherein an inaccuracy level of the output reference voltage is lower than an inaccuracy level of the reference voltage, the first voltage source being an absolute temperature complementary (CTAT) voltage source implemented using a first temperature sensing device, and the second voltage source being an absolute temperature proportional (PTAT) voltage source implemented using a second temperature sensing device.

2. The integrated circuit of claim 1, wherein the first temperature-sensitive device includes a first stacked gate device, the first stacked gate device including one or more first finger structures configured in parallel, wherein each first finger structure includes a first number of field-effect transistors connected in series.

3. The integrated circuit of claim 2, wherein the plurality of fine-tuning devices are fine-tuning stacked gate devices, and the first fine-tuning circuit further includes: A plurality of buffer circuits are configured to be supplied with a voltage at one gate terminal of the first stacked gate device and a ground voltage. Each of the fine-tuning stacked gate devices is controlled by a bit of a fine-tuning code signal through one of the buffer circuits. Each of the fine-tuning stacked gate devices includes a different number of finger structures in powers of 2, and each finger structure in the fine-tuning stacked gate device includes the first number of field-effect transistors connected in series.

4. The integrated circuit of claim 3, wherein each of the fine-tuning stacked gate devices includes an equal number of finger structures, and each finger structure in the fine-tuning stacked gate device includes the first number of field-effect transistors connected in series.

5. The integrated circuit of claim 1, wherein the second trimming circuit comprises: An operational transconductance amplifier having a first input terminal for receiving a reference voltage, a second input terminal coupled to a first node, and an output terminal; a first transistor having a gate terminal coupled to the output terminal of the operational transconductance amplifier, a first terminal for receiving a power supply voltage, and a second terminal coupled to the first node; and a second transistor having a gate terminal coupled to the output terminal of the operational transconductance amplifier, a first terminal for receiving the power supply voltage, and a second terminal coupled to the output terminal of the integrated circuit.

6. As in request item 5, the integrated circuit, wherein: The first node is coupled to a ground via a first resistor, and the output terminal of the integrated circuit is coupled to the ground via a second resistor and a plurality of trimmer resistors; the first transistor and the first resistor constitute a first current path for a first current to flow from the power supply voltage through the first transistor and the first resistor to the ground; the second transistor, the second resistor, and the trimmer resistors constitute a second current path for a second current to flow from the power supply voltage through the second transistor, the second resistor, and the trimmer resistors to the ground; and the predetermined multiplication ratio is obtained by dividing the sum of the second resistor and one of the trimmer resistors by the first resistor, wherein each of the trimmer resistors is controlled by a bit of a control signal, and the trimmer resistors are configured using a binary encoding scheme, wherein the first resistor, the second resistor, and the trimmer resistors are manufactured in a back-end process (BEOL) of the integrated circuit.

7. An integrated circuit comprising: A first temperature-sensitive device configured to function as a first voltage source that varies with the absolute temperature of the integrated circuit; The integrated circuit includes: a second temperature-sensitive device coupled to the first temperature-sensitive device and configured to function as a second voltage source varying with the absolute temperature of the integrated circuit, wherein the second voltage source compensates the first voltage source to generate a reference voltage; a first trimmer circuit including a plurality of trimmers configured in parallel with the first temperature-sensitive device and configured to use the plurality of trimmers to adjust a temperature coefficient of the reference voltage; and a second trimmer circuit configured to multiply the reference voltage by a predetermined multiplication ratio to adjust a deviation of the reference voltage to generate an output reference voltage at an output terminal of the integrated circuit having an inaccuracy level lower than the reference voltage, wherein the second trimmer circuit includes: an operational transconductance amplifier having a first input terminal receiving the reference voltage, a second input terminal coupled to a first node, and an output terminal; A first transistor having a gate terminal coupled to the output terminal of the operational transconductance amplifier, a first terminal receiving a power supply voltage, and a second terminal coupled to the first node; and a second transistor having a gate terminal coupled to the output terminal of the operational transconductance amplifier, a first terminal receiving the power supply voltage, and a second terminal coupled to the output terminal of the integrated circuit.

8. A method of operating an integrated circuit, comprising: A reference voltage is generated by compensating a first voltage (V1) provided by a first voltage source with a second voltage provided by a second voltage source, wherein the first voltage is complementary to an absolute temperature of an integrated circuit, and the second voltage is proportional to the absolute temperature of the integrated circuit; the first voltage is fine-tuned by a plurality of fine-tuning devices of a first fine-tuning circuit to reduce a temperature coefficient of the reference voltage; and the reference voltage is multiplied by a predetermined multiplication ratio by a second fine-tuning circuit to fine-tune a deviation of the reference voltage to generate an output reference voltage, wherein an inaccuracy level of the output reference voltage is lower than the inaccuracy level of the reference voltage, wherein the first voltage source is an absolute temperature complementary (CTAT) voltage source implemented using a first temperature-sensitive device, and the second voltage source is an absolute temperature proportional (PTAT) voltage source implemented using a second temperature-sensitive device.

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