Display driver chip and display module

Abstract

This disclosure provides a display driver chip and a display module having the display driver chip. The display driver chip includes: a plurality of metal bumps disposed on a first boundary, and a data processing circuit for receiving multiple pieces of display data. The data processing circuit divides the multiple chip signal channels into multiple chip signal channel groups, connects them to the corresponding panel signal channel groups using opposite connection patterns, and controls the filling order of display data based on the connection patterns. Through this design, this disclosure achieves a narrow bezel effect, while avoiding the metal layer resource consumption problem of traditional recessed bump solutions, and simplifies part number management and improves production efficiency through standardized bump structure and configuration.

Claims

1. A display driver chip, suitable for driving a pixel array of a display module, the display driver chip comprising: A plurality of metal bumps are disposed on a first boundary of the display driver chip, wherein the plurality of metal bumps respectively correspond to a plurality of chip signal channels of the display driver chip, and the plurality of metal bumps are electrically connected to a plurality of panel signal channels of the pixel array through a plurality of source lines; a data processing circuit is used to receive a plurality of display data, wherein the data processing circuit is further used to divide the plurality of chip signal channels into at least a plurality of chip signal channel groups, the plurality of chip signal channel groups including at least one first chip signal channel group and at least one second chip signal channel group, wherein the at least one first chip signal channel group and the at least one second chip signal channel group each correspond to at least one first panel signal channel group and the at least one second panel signal channel group in the plurality of panel signal channel groups, wherein each panel signal channel group includes a plurality of panel signal channels, wherein the plurality of first chip signal channels of each first chip signal channel group are respectively connected to the plurality of first panel signal channels of the corresponding first panel signal channel group in a first connection state. Each second chip signal channel group has multiple second chip signal channels connected to a corresponding second panel signal channel group in a second connection pattern. The first connection pattern and the second connection pattern are opposite. The data processing circuit is further used to control the order in which the multiple display data are filled into the multiple chip signal channels based on the first connection pattern and the second connection pattern.

2. The display driver chip as claimed in claim 1, wherein the first connection state refers to the (i+1)th first chip signal channel in each first chip signal channel group being connected to the (i+1)th first panel signal channel in the corresponding first panel signal channel group, where i is an integer from 0 to N-1, and N is the total number of the plurality of first chip signal channels in the first chip signal channel group; wherein the second connection state refers to the (Mj)th second chip signal channel in each second chip signal channel group being connected to the (j+1)th second panel signal channel in the corresponding second panel signal channel group, where j is an integer from 0 to M-1, and M is the total number of the plurality of second chip signal channels in the second chip signal channel group.

3. The display driver chip as claimed in claim 2, wherein the data processing circuitry includes: A shift register is used to temporarily store the multiple display data; And a drive control circuit electrically connected to the shift register, for controlling the filling of the multiple display data from the shift register into the multiple chip signal channels based on the first connection state and the second connection state.

4. The display driver chip as claimed in claim 3, wherein the drive control circuit is further configured to: sequentially fill N pieces of first display data corresponding to each first chip signal channel group into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; and sequentially fill M pieces of second display data corresponding to each second chip signal channel group into the Mth second chip signal channel to the first second chip signal channel in the second chip signal channel group.

5. The display driver chip as claimed in claim 3, wherein the data processing circuitry further comprises: A timing controller, electrically connected to the drive control circuit, is used to: adjust the arrangement order of M second display data corresponding to each second chip signal channel group before the multiple display data are input to the multiple chip signal channels.

6. The display driver chip as claimed in claim 5, wherein the timing controller is further configured to: reverse-order the first to the Mth second display data in the M second display data corresponding to each second chip signal channel group, so as to obtain M adjusted second display data.

7. The display driver chip as claimed in claim 6, wherein the drive control circuit is further configured to: sequentially fill N pieces of first display data corresponding to each first chip signal channel group into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; and sequentially fill M pieces of adjusted second display data corresponding to each second chip signal channel group into the first second chip signal channel to the Mth second chip signal channel in the second chip signal channel group.

8. The display driver chip as claimed in claim 1, wherein the display module has a glass substrate, and the pixel array and the plurality of source lines are formed on the glass substrate.

9. The display driver chip as claimed in claim 3, wherein the drive control circuit is further configured to: apply a delay time to each first chip signal channel group such that the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group form a continuous drive timing sequence.

10. The display driver chip of claim 9, wherein the drive control circuit is further configured to: detect the signal drive time difference between the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group; and apply the delay time to multiple first display data output by multiple first chip signal channels of the first chip signal channel group according to the signal drive time difference, so that the delayed first signal drive time curve and the second signal drive time curve form a continuous drive timing sequence.

11. A display module, comprising: One-pixel array; Multiple panel signal channels are formed on a glass substrate, wherein the pixel array is electrically connected to the multiple panel signal channels; The display driver chip includes: a plurality of metal bumps disposed on a first boundary of the display driver chip, wherein each of the plurality of metal bumps corresponds to a plurality of chip signal channels of the display driver chip, and the plurality of metal bumps are electrically connected to the plurality of panel signal channels through a plurality of source lines; and a data processing circuit for receiving a plurality of display data, wherein the data processing circuit is further configured to divide the plurality of chip signal channels into at least a plurality of chip signal channel groups, the plurality of chip signal channel groups including at least one first chip signal channel group and at least one second chip signal channel group, wherein the at least one first chip signal channel group and the at least one second chip signal channel group each correspond to at least one first panel signal channel group and the at least one second panel signal channel group in the plurality of panel signal channel groups, wherein each panel signal channel group includes a plurality of panel signal channels, wherein the plurality of first chip signal channels of each first chip signal channel group are respectively connected to the plurality of first panel signal channels of the corresponding first panel signal channel group in a first connection configuration. Each second chip signal channel group has multiple second chip signal channels connected to a corresponding second panel signal channel group in a second connection pattern. The first connection pattern and the second connection pattern are opposite. The data processing circuit is further used to control the order in which the multiple display data are filled into the multiple chip signal channels based on the first connection pattern and the second connection pattern.

12. The display module as claimed in claim 11, wherein the first connection pattern refers to the (i+1)th first chip signal channel in each first chip signal channel group being connected to the (i+1)th first panel signal channel in the corresponding first panel signal channel group, where i is an integer from 0 to N-1, and N is the total number of the plurality of first chip signal channels in the first chip signal channel group, wherein the second connection pattern refers to the (Mj)th second chip signal channel in each second chip signal channel group being connected to the (j+1)th second panel signal channel in the corresponding second panel signal channel group, where j is an integer from 0 to M-1, and M is the total number of the plurality of second chip signal channels in the second chip signal channel group.

13. The display module as claimed in claim 12, wherein the data processing circuitry includes: A shift register is used to temporarily store the multiple display data; And a drive control circuit electrically connected to the shift register, for controlling the filling of the multiple display data from the shift register into the multiple chip signal channels based on the first connection state and the second connection state.

14. The display module as claimed in claim 13, wherein the drive control circuit is further configured to: sequentially fill N pieces of first display data corresponding to each first chip signal channel group into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; and sequentially fill M pieces of second display data corresponding to each second chip signal channel group into the Mth second chip signal channel to the first second chip signal channel in the second chip signal channel group.

15. The display module as claimed in claim 13, wherein the data processing circuitry further comprises: A timing controller, electrically connected to the drive control circuit, is used to: adjust the arrangement order of M second display data corresponding to each second chip signal channel group before the multiple display data are input to the multiple chip signal channels.

16. The display module as claimed in claim 15, wherein the timing controller is further configured to: reverse-order the first to the Mth second display data in the M second display data corresponding to each second chip signal channel group, so as to obtain M adjusted second display data.

17. The display module as claimed in claim 16, wherein the drive control circuit is further configured to: sequentially fill N pieces of first display data corresponding to each first chip signal channel group into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; and sequentially fill M pieces of adjusted second display data corresponding to each second chip signal channel group into the first second chip signal channel to the Mth second chip signal channel in the second chip signal channel group.

18. The display module as claimed in claim 11, wherein the plurality of source lines are formed on the glass substrate.

19. The display module as claimed in claim 13, wherein the drive control circuit is further configured to: apply a delay time to each first chip signal channel group such that the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group form a continuous drive timing sequence.

20. The display module of claim 19, wherein the drive control circuit is further configured to: detect the signal drive time difference between the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group; and apply the delay time to multiple first display data output by multiple first chip signal channels of the first chip signal channel group according to the signal drive time difference, so that the first signal drive time curve and the second signal drive time curve form a continuous drive timing sequence.

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